WO2015093212A1 - Electronic component, connector, connector production method, and electronic component connecting method - Google Patents

Electronic component, connector, connector production method, and electronic component connecting method Download PDF

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Publication number
WO2015093212A1
WO2015093212A1 PCT/JP2014/080406 JP2014080406W WO2015093212A1 WO 2015093212 A1 WO2015093212 A1 WO 2015093212A1 JP 2014080406 W JP2014080406 W JP 2014080406W WO 2015093212 A1 WO2015093212 A1 WO 2015093212A1
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WO
WIPO (PCT)
Prior art keywords
bump
side edge
area
output
electronic component
Prior art date
Application number
PCT/JP2014/080406
Other languages
French (fr)
Japanese (ja)
Inventor
堅一 平山
Original Assignee
デクセリアルズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2013264377A external-priority patent/JP6434210B2/en
Priority claimed from JP2014162480A external-priority patent/JP6457214B2/en
Application filed by デクセリアルズ株式会社 filed Critical デクセリアルズ株式会社
Priority to KR1020167015166A priority Critical patent/KR102373907B1/en
Priority to CN201910207728.4A priority patent/CN110246767B/en
Priority to CN201480069902.9A priority patent/CN105814675B/en
Priority to KR1020227024835A priority patent/KR102471283B1/en
Priority to KR1020227040690A priority patent/KR102514158B1/en
Priority to KR1020227007789A priority patent/KR102423319B1/en
Publication of WO2015093212A1 publication Critical patent/WO2015093212A1/en

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Definitions

  • the present invention relates to an electronic component connected to a circuit board via an adhesive, a connection body in which the electronic component is connected to the circuit board, a manufacturing method of the connection body, and a connection method of the electronic component, and more particularly to the circuit board.
  • the present invention relates to an electronic component in which a plurality of bump electrodes are arranged asymmetrically on the mounting surface, a connection body to which the electronic component is connected, a manufacturing method of the connection body, and a connection method of the electronic component.
  • connection body in which electronic components such as an IC chip and an LSI chip are connected to circuit boards of various electronic devices has been provided.
  • various electronic devices use IC chips or LSI chips in which bumps, which are protruding electrodes, are arranged on the mounting surface as electronic components from the viewpoints of fine pitch, light weight, and thinning.
  • So-called COB (chip-on-board) or COG (chip-on-glass) in which electronic components such as these are directly mounted on a circuit board are employed.
  • an IC chip is thermocompression-bonded on a terminal portion of a circuit board via an anisotropic conductive film.
  • An anisotropic conductive film is a film formed by mixing conductive particles in a thermosetting binder resin, and heat conduction is performed between two conductors so that electrical conduction between the conductors is achieved with the conductive particles. The mechanical connection between the conductors is maintained by the binder resin.
  • an adhesive constituting the anisotropic conductive film a highly reliable thermosetting adhesive is usually used.
  • connection using a photo-curable resin or a connection method using both thermosetting and photo-curing is also used. However, in the case of applying pressure with a tool, it is assumed that the same problems as thermosetting adhesives are included.
  • the bumped IC chip 50 has an input bump region 52 in which input bumps 51 are arranged in a line along one side edge 50a on the mounting surface of the circuit board.
  • An output bump area 54 in which output bumps 53 are arranged in two rows in a zigzag manner is provided along the other side edge 50b facing one side edge 50a.
  • the bump arrangement varies depending on the type of IC chip. In general, a conventional IC chip with bumps has a larger number of output bumps 53 than the number of input bumps 51, and an output bump area 54 than the area of the input bump area 52. And the shape of the input bump 51 is formed larger than the shape of the output bump 53.
  • the IC chip 50 is mounted on the electrode terminal 57 of the circuit board 56 via the anisotropic conductive film 55
  • the IC is performed by the thermocompression bonding head 58.
  • the chip 50 is heated and pressed from above.
  • the binder resin of the anisotropic conductive film 55 is melted and flows from between the input / output bumps 51 and 53 and the electrode terminals 57 of the circuit board 56, and each input / output.
  • Conductive particles are sandwiched between the bumps 51 and 53 and the electrode terminal 57 of the circuit board 56, and in this state, the binder resin is thermally cured.
  • the IC chip 50 is electrically and mechanically connected to the circuit board 56.
  • the bump arrangement and size of the input bump 51 and the output bump 53 formed on the mounting surface are different, and the input bump region 52 and the output bump are different. There is an area difference from the region 54.
  • the input bump area 52 and the output bump area 54 are asymmetrically arranged on the mounting surface.
  • the pressing force applied to the input bump 51 and the output bump 53 by the thermocompression bonding head 58 becomes non-uniform.
  • the output bump region 54 it is arranged on the other side edge 50b side.
  • the present invention provides an electronic component capable of eliminating the pressure difference caused by the thermocompression bonding head and improving the connection reliability in the electronic component in which the input bump region and the output bump region have an area difference and are disposed asymmetrically. It is an object of the present invention to provide a connection body, a manufacturing method of the connection body, and a connection method.
  • an electronic component according to the present invention is provided with an output bump area in which output bumps are arranged in proximity to one side of a pair of side edges facing each other.
  • An input bump area in which input bumps are arranged adjacent to the other side is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically, and the output bump area or the input bump area Of these, one having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges.
  • connection body according to the present invention is a connection body in which the electronic component is arranged on the circuit board via an adhesive and is pressed by a pressure tool so that the electronic component is connected to the circuit board.
  • the mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the other of the pair of side edges
  • An input bump area in which input bumps are arranged close to the side is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface, and the output bump area or the input bump
  • One of the bump areas having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. .
  • the manufacturing method of the connection body which concerns on this invention arrange
  • the mounting surface of the electronic component on the circuit board is provided with an output bump region in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the pair of side edges
  • An input bump area in which input bumps are arranged adjacent to the other side of the output bump area is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface.
  • One of the input bump regions having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. Is
  • connection method is an electronic component connection method in which an electronic component is arranged on a circuit board via an adhesive, and the electronic component is connected to the circuit board by applying pressure with a pressure tool.
  • the mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the other side of the pair of side edges.
  • An input bump area in which input bumps are arranged is provided adjacent to the output bump area, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface, and the output bump area or the input bump area.
  • One of the regions having a relatively large area is formed on the inner side from the one or the other side edge adjacent by a distance of 4% or more of the width between the pair of side edges.
  • an electronic component according to the present invention is opposed to a first bump region having a rectangular shape in which a bump row is formed along a first side edge, and the first side edge.
  • a rectangular second bump region in which a bump row is formed along the second side edge, and the distance in the width direction of the first bump region is the distance in the width direction of the second bump region.
  • a midpoint between the outer sides of the first bump regions and the outer sides of the second bump regions in the width direction is between the first side edges and the second bump regions. It exists in the said 2nd side edge side from the midpoint between side edges between side edges.
  • connection body includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side edge facing the first side edge.
  • a second bump region having a rectangular shape in which bump rows are formed, and a distance in the width direction of the first bump region is larger than a distance in the width direction of the second bump region,
  • a midpoint between the outer sides of the bump region and the outer side of the second bump region in the width direction is a side between the first side edge and the second side edge.
  • the method for manufacturing a connection body according to the present invention includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side facing the first side edge.
  • a midpoint between the outer sides of the first bump region and the outer side of the bump region between the outer side of the second bump region in the width direction is between the first side edge and the second side edge.
  • An electronic component existing on the second side edge side from the middle point between the side edges is disposed on the circuit board via an adhesive, and the electronic component is placed on the circuit board by pressing with a pressing tool. To connect to.
  • connection method includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side edge facing the first side edge.
  • a second bump region having a rectangular shape in which bump rows are formed, and a distance in the width direction of the first bump region is larger than a distance in the width direction of the second bump region,
  • a midpoint between the outer sides of the bump region and the outer side of the second bump region in the width direction is a side between the first side edge and the second side edge.
  • An electronic component existing on the second side edge side from the middle point between the edges is disposed on the circuit board via an adhesive, and the electronic component is connected to the circuit board by applying pressure with a pressure tool. Is.
  • the pressure gradient formed across the width direction of the bump region is formed by forming the large bump region from the side edge to the inside by a predetermined ratio with respect to the width of the mounting surface. It is gently leveled to prevent a situation where the pressing force by the thermocompression bonding head is insufficient on the side edge side.
  • the electronic component can reliably hold conductive particles between the bumps on the side edge side and the electrode terminals formed on the circuit board to ensure conductivity.
  • the midpoint between the bump region outer sides between the outer side in the width direction of the first bump region and the outer side in the width direction of the second bump region is the first side edge and the second side. Since it exists on the second side edge side from the midpoint between the side edges to the edge, the pressure gradient formed over the width direction of the bump area is gently leveled, and the pressing by the thermocompression bonding head on the side edge side. A situation where pressure is insufficient can be prevented. As a result, the conductive particles can be reliably sandwiched even in the bumps on the side edge side, and excellent conductivity can be obtained.
  • FIG. 1 is a plan view showing a mounting surface of an electronic component according to the present invention.
  • FIG. 2 is a cross-sectional view showing a connection body to which electronic components are connected.
  • FIG. 3 is a plan view showing a mounting surface of the electronic component according to the present invention provided with dummy bumps.
  • FIG. 4 is a cross-sectional view showing an anisotropic conductive film.
  • FIG. 5 is a cross-sectional view showing a mounting surface in the width direction of the electronic component according to the present invention.
  • 6A is a plan view showing a mounting surface of a conventional electronic component
  • FIG. 6B is a cross-sectional view showing a mounting state.
  • connection body a connection body, a method for manufacturing the connection body, and a connection method
  • connection method a connection method
  • An electronic component to which the present invention is applied is an electronic component that is arranged on a circuit board via an adhesive and is connected to the circuit board by being pressed by a thermocompression bonding head.
  • a driver IC or a system LSI Etc. are packaged electronic components.
  • the IC chip 1 will be described as an example of the electronic component.
  • the mounting surface 2 connected to the circuit board of the IC chip 1 has a substantially rectangular shape, and along the pair of side edges 2a and 2b facing each other in the length direction, output bumps are formed.
  • An output bump area 4 in which 3 is arranged and an input bump area 6 in which input bumps 5 are arranged are formed.
  • the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2
  • the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2.
  • the IC chip 1 is formed such that the output bump area 4 and the input bump area 6 are separated from each other in the width direction of the mounting surface 2.
  • the output bump area 4 for example, a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2.
  • the input bump area 6 for example, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2.
  • the input bump 5 is formed larger than the output bump 3.
  • the output bump region 4 and the input bump region 6 have an area difference and are disposed asymmetrically on the mounting surface 2.
  • the output bumps 3 arranged in the output bump region 4 are preferably formed with the same dimensions.
  • the input bumps 5 arranged in the input bump area 6 are preferably formed with the same dimensions.
  • the output bump region 4 is inward from the one side edge 2a by a predetermined ratio with respect to the IC width W extending between the one side edge 2a and the other side edge 2b. Is formed.
  • the thermocompression bonding head 17 applies pressure to the entire surface of the mounting surface 2.
  • the pressure gradient is such that the pressing force weakens toward one side edge 2a of the surface 2, and the pressing force against the output bumps 3 arranged on the one side edge 2a side is insufficient.
  • the conduction resistance of the output bump 3 is increased particularly in the outer edge region of the bump due to insufficient pushing of the conductive particles.
  • the IC chip 1 is formed across the width direction of the output bump region 4 by forming the output bump region 4 inward from the one side edge 2a by a predetermined ratio with respect to the width of the mounting surface 2.
  • the pressure gradient that is applied is gently leveled to prevent the pressing force by the thermocompression bonding head 17 from being insufficient on the one side edge 2a side.
  • the IC chip 1 reliably holds the conductive particles between the output bumps 3 on the one side edge 2a side and the electrode terminals 15 formed on the circuit board 14 to ensure conductivity. Can do.
  • the distance A from the one side edge 2a to the output bump region 4 is preferably 4% or more with respect to the IC width W between the opposing side edges 2a2b of the mounting surface 2.
  • the output bump region 4 and the input bump region 6 having an area difference are arranged asymmetrically. Even when the thermocompression bonding head 17 applies pressure evenly to the mounting surface 2, the pressing force is sufficiently transmitted to the output bumps 3 arranged on the first side edge 2 a side.
  • the pressing force by the thermocompression bonding head 17 is sufficient to the output bump 3 on the one side edge 2a side. There is a risk of poor conduction due to insufficient push-in of conductive particles.
  • the distance A is preferably within 30%, more preferably within 20%, and even more preferably within 15%.
  • the distance A from the one side edge 2 a of the output bump region 4 having a relatively large area is preferably longer than the distance B from the other side edge 2 b of the input bump region 6. That is, if the distance B from the other side edge 2b of the relatively small area input bump region 6 is longer than the distance A from the one side edge 2a of the large area output bump region 4, the width in the output bump region 4 The pressure gradient over the direction is increased, and obstruction of insufficient pressing of the conductive particles in the output bump 3 on the side edge 2a side is hindered.
  • the input bumps 5 are arranged in a line, in the input bump region 6 having a relatively small area, the pressing force by the thermocompression bonding head 17 is unevenly distributed due to an area difference from the output bump region 4 and an asymmetrical arrangement. Since the risk of insufficient push-in is small, there is no problem even if the distance B from the other side edge 2b of the mounting surface 2 is short.
  • the configuration of the input / output bumps on the mounting surface 2 can be appropriately designed.
  • the IC chip 1 forms the output bump region 4 having a relatively large area by arranging a plurality of output bumps 3 in the width direction.
  • a plurality of input bumps 5 are arranged in the width direction. By doing so, the input bump region 6 may be relatively enlarged.
  • the IC chip 1 determines that the input bump area 6 has a predetermined ratio to the IC width W, preferably a distance of 4% or more of the IC width W, It forms inside from the side edge 2b.
  • the distance B from the other side edge 2 b of the relatively large area input bump region 6 is preferably longer than the distance A from the one side edge 2 a of the output bump region 4.
  • the flexible substrate 16 is adjacent to the circuit substrate 14 on the anisotropic conductive film. 10
  • the connection position between the input bump 5 and the electrode terminal 15 is separated from the thermocompression bonding head 17 that heat-presses the flexible substrate 16. Therefore, it is possible to prevent deterioration in connectivity due to heat radiation from the thermocompression bonding head 17 after the IC chip 1 is connected.
  • the IC chip 1 appropriately includes a dummy bump area 19 in which so-called dummy bumps 18 that are not used for input / output of signals and the like are arranged between the output bump area 4 and the input bump area 6. May be.
  • an anisotropic conductive film 10 As an adhesive for connecting the IC chip 1 to the circuit board 14, an anisotropic conductive film 10 (ACF) can be suitably used.
  • the anisotropic conductive film 10 is generally formed by forming a binder resin layer (adhesive layer) 13 containing conductive particles 12 on a release film 11 serving as a base material.
  • the anisotropic conductive film 10 has the circuit board 14 and the IC chip 1 by interposing a binder resin layer 13 between the electrode terminal 15 formed on the circuit board 14 and the IC chip 1. Are used for connecting and conducting.
  • the adhesive composition of the binder resin layer 13 comprises a normal binder component containing, for example, a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, and the like.
  • the film-forming resin is preferably a resin having an average molecular weight of about 10,000 to 80,000, and various resins such as an epoxy resin, a modified epoxy resin, a urethane resin, and a phenoxy resin are particularly mentioned. Among these, phenoxy resin is preferable from the viewpoint of film formation state, connection reliability, and the like.
  • thermosetting resin is not particularly limited, and for example, a commercially available epoxy resin or acrylic resin can be used.
  • the epoxy resin is not particularly limited.
  • naphthalene type epoxy resin biphenyl type epoxy resin, phenol novolac type epoxy resin, bisphenol type epoxy resin, stilbene type epoxy resin, triphenolmethane type epoxy resin, phenol aralkyl type epoxy resin.
  • an acrylic compound, liquid acrylate, etc. can be selected suitably.
  • what made acrylate the methacrylate can also be selected from methyl acrylate, ethyl acrylate, isopropy
  • the latent curing agent is not particularly limited, but includes a heat curing type curing agent.
  • the latent curing agent does not normally react, but is activated by various triggers selected according to applications such as heat, light, and pressure, and starts the reaction.
  • the activation method of the thermal activation type latent curing agent includes a method of generating active species (cation, anion, radical) by a dissociation reaction by heating, etc., and it is stably dispersed in the epoxy resin near room temperature, and epoxy at high temperature
  • There are a method of initiating a curing reaction by dissolving and dissolving with a resin a method of initiating a curing reaction by eluting a molecular sieve encapsulated type curing agent at a high temperature, and an elution / curing method using microcapsules.
  • Thermally active latent curing agents include imidazole, hydrazide, boron trifluoride-amine complexes, sulfonium salts, amine imides, polyamine salts, dicyandiamide, etc., and modified products thereof.
  • the above mixture may be sufficient.
  • the radical polymerization initiator a known one can be used, and among them, an organic peroxide can be preferably used.
  • the silane coupling agent is not particularly limited, and examples thereof include an epoxy type, an amino type, a mercapto sulfide type, and a ureido type. By adding the silane coupling agent, the adhesion at the interface between the organic material and the inorganic material is improved.
  • Examples of the conductive particles 12 contained in the binder resin layer 13 include any known conductive particles used in anisotropic conductive films. That is, as the conductive particles, for example, particles of various metals and metal alloys such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, gold, metal oxide, carbon, graphite, glass, ceramic Examples thereof include those in which the surface of particles such as plastic is coated with metal, or those in which the surface of these particles is further coated with an insulating thin film.
  • examples of the resin particle include an epoxy resin, a phenol resin, an acrylic resin, an acrylonitrile / styrene (AS) resin, a benzoguanamine resin, a divinylbenzene resin, a styrene resin, and the like. Can be mentioned.
  • the adhesive composition constituting the binder resin layer 13 is not limited to the case where it contains a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, etc. You may make it comprise from any material used as an adhesive composition of a film.
  • the release film 11 that supports the binder resin layer 13 is made of, for example, a release agent such as silicone on PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), and the like. It is applied and prevents the anisotropic conductive film 10 from being dried, and maintains the shape of the anisotropic conductive film 10.
  • a release agent such as silicone on PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), and the like. It is applied and prevents the anisotropic conductive film 10 from being dried, and maintains the shape of the anisotropic conductive film 10.
  • the anisotropic conductive film 10 may be produced by any method, but can be produced, for example, by the following method.
  • An adhesive composition containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, conductive particles and the like is prepared.
  • the adhesive film obtained by forming a thermosetting resin composition appropriately containing the conductive particles 12 in the binder resin layer 13 as a film has been described as an example.
  • Such an adhesive is not limited to this, and may be, for example, an insulating adhesive film made of only the binder resin layer 13.
  • the adhesive according to the present invention has a configuration in which an insulating adhesive layer made of only the binder resin layer 13 and a conductive particle-containing layer made of the binder resin layer 13 containing the conductive particles 12 are laminated. it can.
  • the adhesive is not limited to such an adhesive film formed into a film, but an insulating adhesive consisting of a conductive adhesive paste in which conductive particles 12 are dispersed in a binder resin composition or a binder resin composition alone. It may be a paste.
  • the adhesive according to the present invention includes any of the forms described above.
  • connection process Next, a connection process for connecting the IC chip 1 to the circuit board 14 will be described.
  • the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 on which the electrode terminals 15 are formed.
  • the circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 via the anisotropic conductive film 10.
  • thermocompression bonding head 17 heated to a predetermined temperature for curing the binder resin layer 13 is hot-pressed from above the IC chip 1 at a predetermined pressure and time.
  • the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the conductive particles in the binder resin layer 13. 12 is sandwiched between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and is crushed.
  • the output bump region 4 is formed on the inner side from the one side edge 2a by a distance of 4% or more with respect to the IC width W.
  • the pressure gradient formed over the width direction 4 is leveled, the pressing force by the thermocompression bonding head 17 is applied substantially uniformly throughout the output bump region 4, and the pressing force is insufficient on the one side edge 2a side. Is prevented.
  • the conductive particles 12 that are not between the output bumps 3 and the input bumps 5 and the electrode terminals 15 are dispersed in the binder resin and maintain an electrically insulated state. Thereby, electrical conduction is achieved only between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14.
  • the binder resin can be rapidly cured even with a short heating time.
  • the anisotropic conductive film 10 is not limited to the thermosetting type, and may be a photo-curing type or a photo-heat combined type adhesive as long as it performs pressure connection.
  • a connected body sample is connected to a circuit board via an anisotropic conductive film using an IC chip having an area difference between the output bump area and the input bump area and asymmetrically arranged on the mounting surface.
  • the IC chips according to the example and the comparative example are different in the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region, and measure the conduction resistance values of the output bump and the input bump in the connection sample, respectively. ,evaluated.
  • the IC chip according to the example and the comparative example includes an output bump region 4 in which output bumps 3 are arranged along a pair of side edges 2a and 2b facing each other in the length direction of the substantially rectangular mounting surface 2.
  • An input bump area 6 in which the input bumps 5 are arranged is formed.
  • the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2
  • the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2.
  • the output bump region 4 and the input bump region 6 are formed apart from each other in the width direction of the mounting surface (see FIG. 1).
  • a plurality of output bumps 3 formed in the same shape are arranged in a staggered pattern in three rows along the longitudinal direction of the mounting surface 2.
  • the output bumps formed in the output bump area 4 are divided into columns, and are designated as output bump columns 3A, 3B, 3C in order from one side edge 2a side.
  • the output bumps 3 formed in each row have a rectangular shape (area: 1437.5 ⁇ m 2 , width: 12.5 ⁇ m, length: 115 ⁇ m), and 1276 output bump rows 3A, 3B, and 3C are arranged. Yes.
  • the total area of the output bump 3 in each bump row 3A, 3B, 3C is 1834250 ⁇ m 2 , respectively.
  • the total area of the output bump region 4 is 12919500 ⁇ m 2 (width: 31900 ⁇ m, length: 405 ⁇ m).
  • a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2.
  • One input bump row formed in the input bump area 6 is defined as an input bump row 5A.
  • the input bumps 5 arranged in the input bump row 5A have a rectangular shape (area: 3600 ⁇ m 2 , width: 45.0 ⁇ m, length: 80 ⁇ m), and 515 are arranged.
  • the total area of the input bumps 5 in the input bump row 5A is 1854000 ⁇ m 2 .
  • the total area of the input bump region 6 is 2553040 ⁇ m 2 (width: 31913 ⁇ m, length: 80 ⁇ m).
  • the IC width W between the opposing side edges 2a and 2b of the mounting surface 2 is 1.5 mm, and the IC length in the arrangement direction of the input / output bumps 3 and 5 is 32 mm. . Further, the distance A from one side edge 2a to the output bump region 4 is 150 ⁇ m, which is 10% of the IC width W (1.5 mm). In the IC chip according to the first embodiment, no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 ⁇ m. .
  • Example 2 The IC chip according to Example 2 was set to the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 100 ⁇ m.
  • the distance A in Example 2 is a distance of 6.6% with respect to the IC width W (1.5 mm).
  • Example 3 The IC chip according to Example 3 was set to the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 75 ⁇ m.
  • the distance A in Example 3 is 5.0% of the distance with respect to the IC width W (1.5 mm).
  • Example 4 The IC chip according to Example 4 was under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 62.5 ⁇ m.
  • the distance A in Example 4 is 4.2% of the IC width W (1.5 mm).
  • the IC chip according to the fifth embodiment has an IC width W of 2.0 mm between the opposing side edges 2a and 2b of the mounting surface 2 and an IC length of 32 mm in the arrangement direction of the input / output bumps 3 and 5. .
  • the distance A from one side edge 2a to the output bump region 4 is 83 ⁇ m, which is 4.2% of the IC width W (2.0 mm).
  • no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 ⁇ m. .
  • the IC chip according to Example 6 has an IC width W of 3.0 mm between the opposing side edges 2a and 2b of the mounting surface 2 and an IC length of 32 mm in the arrangement direction of the input / output bumps 3 and 5. .
  • the distance A from one side edge 2a to the output bump region 4 is 125 ⁇ m, which is 4.2% of the IC width W (3.0 mm).
  • no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 ⁇ m. .
  • Comparative Example 1 The IC chip according to Comparative Example 1 was the same as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 50 ⁇ m. The distance A in Comparative Example 1 is 3.3% of the IC width W (1.5 mm).
  • Comparative Example 2 The IC chip according to Comparative Example 2 was set to the same conditions as Comparative Example 1 except that a dummy bump region D was provided between the output bump region 4 and the input bump region 6.
  • dummy bump area D dummy bumps are arranged in a line in the length direction of the IC chip.
  • Each dummy bump has a rectangular shape (area: 1250 ⁇ m 2 , width: 12.5 ⁇ m, length: 100 ⁇ m), and 1276 are arranged.
  • the total area of the dummy bumps in the dummy bump row D is 1595000 ⁇ m 2 .
  • the total area of the dummy bump region D is 319000 ⁇ m 2 (width: 31900 ⁇ m, length: 100 ⁇ m).
  • the IC chips according to Examples 1 to 6 and Comparative Examples 1 to 2 are connected to a circuit board via an anisotropic conductive film (trade name CP36931-18AJ: manufactured by Dexerials Corporation) to manufacture a connected body sample. did.
  • the connection conditions are 150 ° C., 130 MPa, and 5 seconds.
  • column 5A was measured using the 4-terminal method.
  • the case where the conduction resistance was 1.0 ⁇ or less was determined as OK, and the case where the conduction resistance exceeded 1.0 ⁇ was determined as NG.
  • the measurement results are shown in Table 1.
  • the output bump rows 3A, 3B, and 3C and the input bump row 5A have a conduction resistance of 1.0 ⁇ or less, and are arranged on one side edge 2a side. It can be seen that each output bump 3 in the output bump row 3A could be pushed in with a sufficient pressing force.
  • the distance A from one side edge 2a to the output bump region 4 is set to 4% or more of the IC width W, so that the pressure gradient in the width direction of the output bump region 4 is increased. It depends on being averaged.
  • Comparative Example 1 the conduction resistance in the output bump rows 3A and 3B was high. This is because the distance A from one side edge 2a to the output bump region 4 is 3.3% of the IC width W, and therefore the pressure gradient at which the pressing force of the thermocompression bonding head decreases toward the outer output bump row. Because it became. From this, it can be seen that it is preferable to provide a distance A from one side edge 2a to the output bump region 4 of 4% or more of the IC width W.
  • the dummy bump region D was provided between the output bump region 4 and the input bump region 6, but the conduction resistance in the output bump rows 3A and 3B was high. Accordingly, when the distance A from the one side edge 2a to the output bump region 4 is 3.3% of the IC width W, the pressure that can improve the conductivity in the outer bump row may be formed by forming a dummy bump. It can be seen that it is difficult to obtain a gradient.
  • An electronic component to which the present invention is applied is an electronic component that is arranged on a circuit board via an adhesive and is connected to the circuit board by being pressed by a thermocompression bonding head.
  • a driver IC or a system LSI Etc. are packaged electronic components.
  • the IC chip 1 will be described as an example of the electronic component.
  • the mounting surface 2 connected to the circuit board of the IC chip 1 has a substantially rectangular shape, and along the pair of side edges 2a and 2b facing each other in the length direction, output bumps are formed.
  • An output bump area 4 in which 3 is arranged and an input bump area 6 in which input bumps 5 are arranged are formed.
  • the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2
  • the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2.
  • the IC chip 1 is formed such that the output bump area 4 and the input bump area 6 are separated from each other in the width direction of the mounting surface 2.
  • the output bump area 4 for example, a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2.
  • the input bump area 6 for example, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2.
  • the input bump 5 is formed larger than the output bump 3.
  • the output bump region 4 and the input bump region 6 have an area difference and are disposed asymmetrically on the mounting surface 2.
  • the output bumps 3 arranged in the output bump region 4 are preferably formed with the same dimensions.
  • the input bumps 5 arranged in the input bump area 6 are preferably formed with the same dimensions.
  • FIG. 5 is a sectional view showing a mounting surface in the width direction of the electronic component shown in FIG.
  • the IC chip as the electronic component includes an output bump area 4 as a first bump area having a rectangular shape in which a bump row is formed along the first side edge 2a, and a first side.
  • an input bump region 6 as a rectangular second bump region in which a bump row is formed along the second side edge 2b facing the edge 2a.
  • the distance ⁇ in the width direction of the first bump area is larger than the distance ⁇ in the width direction of the second bump area ( ⁇ > ⁇ ). Further, a distance ⁇ in the width direction of the first bump region and a distance ⁇ in the width direction of the second bump region with respect to the distance (IC width: W) between the first side edge 2a and the second side edge 2b.
  • the ratio of the bump area width difference ( ⁇ ) is preferably 5% to 30%, and more preferably 10% to 25%.
  • the midpoint between the outer sides of the bump region between the outer side in the width direction of the first bump region and the outer side in the width direction of the second bump region is the first side edge 2a. It exists on the second side edge 2b side from the midpoint between the side edges (W / 2) between the first side edge 2b and the second side edge 2b. That is, the relationship between the distance A from the first side edge 2a to the first bump area and the distance B from the second side edge 2b to the second bump area is A> B.
  • the configuration of the input / output bumps on the mounting surface 2 of the IC chip 1 can be designed as appropriate. As described above, the IC chip 1 forms the output bump region 4 having a relatively large area by arranging a plurality of output bumps 3 in the width direction. Conversely, a plurality of input bumps 5 are arranged in the width direction. By doing so, the input bump region 6 may be relatively enlarged.
  • the IC chip 1 appropriately includes a dummy bump area 19 in which so-called dummy bumps 18 that are not used for input / output of signals and the like are arranged between the output bump area 4 and the input bump area 6. May be.
  • ACF Anisotropic Conductive Film
  • connection method for connecting the IC chip 1 to the circuit board 14 will be described.
  • the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 on which the electrode terminals 15 are formed.
  • the circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 via the anisotropic conductive film 10.
  • thermocompression bonding head 17 heated to a predetermined temperature for curing the binder resin layer 13 is hot-pressed from above the IC chip 1 at a predetermined pressure and time.
  • the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the conductive particles in the binder resin layer 13. 12 is sandwiched between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and is crushed.
  • an IC chip having an output bump area and an input bump area as the second bump area is used as the first bump area, and connected to the circuit board through an anisotropic conductive film.
  • a connected sample was manufactured.
  • the IC chips according to the example and the comparative example are different in the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region, and measure the conduction resistance values of the output bump and the input bump in the connection sample, respectively. ,evaluated.
  • the IC chip has an output bump area 4 in which output bumps 3 are arranged and an input bump 5 are arranged along a pair of side edges 2a and 2b facing each other in the length direction of the substantially rectangular mounting surface 2.
  • An input bump area 6 is formed.
  • the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2
  • the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2.
  • the IC chip 1 is formed with the output bump area 4 and the input bump area 6 separated from each other in the width direction of the mounting surface (see FIGS. 1 and 5).
  • a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2.
  • the output bumps formed in the output bump area 4 are divided into columns, and are designated as output bump columns 3A, 3B, 3C in order from one side edge 2a side.
  • a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2.
  • One input bump row formed in the input bump area 6 is defined as an input bump row 5A.
  • the IC chip was connected to the circuit board via an anisotropic conductive film (trade name CP36931-18AJ: manufactured by Dexerials Corporation) to prepare a connected body sample.
  • the connection conditions were 150 ° C., 130 MPa, and 5 seconds.
  • column 5A was measured using the 4-terminal method.
  • the case where the conduction resistance of all the bump rows was 1.0 ⁇ or less was designated as “OK”, and the case where one or more bump rows exceeded 1.0 ⁇ was designated as NG.
  • Example 7 As shown in Table 2, the IC width W is 1500 ⁇ m, the distance A from one side edge 2a of the output bump region 4 is 60 ⁇ m, the width ⁇ of the output bump region 4 is 385 ⁇ m, and the other side edge 2b of the input bump region 6 An IC chip having a distance B of 50 ⁇ m, a width ⁇ of the input bump region 6 of 80 ⁇ m, and a ratio of the bump region width difference to the IC width W of 20.3% was prepared.
  • the distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 925 ⁇ m.
  • the distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1390 ⁇ m.
  • the distance ( ⁇ ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 5.0 ⁇ m, and the ratio to the IC width (W) was 0.33%. .
  • Example 8 As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 75 ⁇ m.
  • the distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 910 ⁇ m.
  • the distance (L2) between the bump area outsides between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1375 ⁇ m.
  • the distance ( ⁇ ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 12.5 ⁇ m, and the ratio to the IC width (W) was 0.83%. .
  • the measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection sample to which the IC chip of Example 8 was connected were 0.9 ⁇ , 0.8 ⁇ , 0.4 ⁇ , and 0.1 ⁇ , respectively. It was an OK evaluation.
  • Example 9 As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 150 ⁇ m.
  • the distance between inner bump regions (L1) between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 835 ⁇ m.
  • the distance (L2) between the bump regions outside between the outside in the width direction of the output bump region 4 and the outside in the width direction of the input bump region 6 was 1300 ⁇ m.
  • the distance ( ⁇ ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 50.0 ⁇ m, and the ratio to the IC width (W) was 3.33%. .
  • the measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 9 was connected were 0.9 ⁇ , 0.7 ⁇ , 0.5 ⁇ , and 0.1 ⁇ , respectively. It was an OK evaluation.
  • Example 10 As shown in Table 2, the IC width W is 2000 ⁇ m, the distance A from one side edge 2 a of the output bump region 4 is 63 ⁇ m, the width ⁇ of the output bump region 4 is 385 ⁇ m, and the other side edge 2 b of the input bump region 6.
  • An IC chip was prepared in which the distance B from the substrate was 50 ⁇ m, the width ⁇ of the input bump region 6 was 80 ⁇ m, and the ratio of the bump region width difference to the IC width W was 15.3%.
  • the distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 1422 ⁇ m.
  • the distance (L2) between the bump regions outside between the outside in the width direction of the output bump region 4 and the outside in the width direction of the input bump region 6 was 1887 ⁇ m.
  • the distance ( ⁇ ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 6.5 ⁇ m, and the ratio to the IC width (W) was 0.33%. .
  • the measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 10 was connected were 1.0 ⁇ , 0.9 ⁇ , 0.4 ⁇ , and 0.1 ⁇ , respectively. It was an OK evaluation.
  • Example 11 As shown in Table 2, the IC width W is 3000 ⁇ m, the distance A from one side edge 2a of the output bump region 4 is 70 ⁇ m, the width ⁇ of the output bump region 4 is 385 ⁇ m, and the other side edge 2b of the input bump region 6 An IC chip having a distance B of 50 ⁇ m, a width ⁇ of the input bump area 6 of 80 ⁇ m, and a ratio of the bump area width difference to the IC width W of 10.2% was prepared.
  • the distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 2415 ⁇ m.
  • the distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 2880 ⁇ m.
  • the distance ( ⁇ ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 10.0 ⁇ m, and the ratio to the IC width (W) was 0.33%. .
  • the measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 11 was connected were 1.0 ⁇ , 0.9 ⁇ , 0.4 ⁇ , and 0.1 ⁇ , respectively. It was an OK evaluation.
  • Example 3 As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was 50 ⁇ m and a dummy bump region was provided. The dummy bump area is provided between the output bump area 4 and the input bump area 6, and the dummy bumps are arranged in a line in the length direction of the IC chip. The dummy bump row is the same as the input bump row 5.
  • the distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 935 ⁇ m.
  • the distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1400 ⁇ m.
  • the distance ( ⁇ ) from the midpoint of the IC width (W / 2) to the midpoint between the bump area outsides (A + L2 / 2) was 0 ⁇ m, and the ratio to the IC width (W) was 0%.
  • the measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection sample to which the IC chip of Comparative Example 3 is connected are 2.3 ⁇ , 1.2 ⁇ , 0.5 ⁇ , and 0.1 ⁇ , respectively. It was NG evaluation.
  • Example 4 As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 50 ⁇ m.
  • the distance between inner bump regions (L1) between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 935 ⁇ m.
  • the distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1400 ⁇ m.
  • the distance ( ⁇ ) from the midpoint of the IC width (W / 2) to the midpoint between the bump area outsides (A + L2 / 2) was 0 ⁇ m, and the ratio to the IC width (W) was 0%.
  • the measurement results of the conduction resistances of the output bump arrays 3A, 3B, 3C and the input bump array 5A in the connection sample to which the IC chip of Comparative Example 4 is connected are 3.0 ⁇ , 1.7 ⁇ , 0.4 ⁇ , and 0.1 ⁇ , respectively. It was NG evaluation.
  • the distance ( ⁇ ) from the midpoint of the IC width (W / 2) to the midpoint between the bump areas outside (A + L2 / 2) is set to 0.3% to 3.3% of the IC width W.
  • the conduction resistance in all of the output bump rows 3A, 3B, 3C and the input bump row 5A was 1.0 ⁇ or less. This is because the pressure gradient in the width direction of the output bump region 4 is leveled, and each output bump 3 in the output bump row 3A can be pushed in with a sufficient pressing force.
  • thermocompression bonding head 1 IC chip, 2 mounting surface, 2a one side edge, 2b other side edge, 3 output bump, 4 output bump area, 5 input bump, 6 input bump area, 10 anisotropic conductive film, 11 release film, 12 Conductive particles, 13 binder resin layer, 14 circuit board, 15 electrode terminals, 17 thermocompression bonding head

Abstract

The purpose of the present invention is to cancel a pressure difference caused by a thermo-compression bonding head to improve the reliability of connections even in an electronic component wherein an input bump region and an output bump region have different surface areas and are disposed asymmetrically. On a side (2) for mounting onto a circuit board (14), an output bump region (4), in which output bumps (3) are arranged, is provided nearby one side (2a) among an opposing pair of edges, and an input bump region (6), in which input bumps (5) are arranged, is provided nearby the other side (2b) of the pair of edges. The output bump region (4) and the input bump region (6) have different surface areas and are disposed asymmetrically on the side (2) for mounting. Among the output bump region (4) and the input bump region (6), the region with a relatively large surface area is formed inward from the one or the other edge (2a, 2b) nearby, by a distance of at least 4% of a width W between the pair of edges.

Description

電子部品、接続体、接続体の製造方法及び電子部品の接続方法Electronic component, connecting body, manufacturing method of connecting body, and connecting method of electronic component
　本発明は、接着剤を介して回路基板上に接続される電子部品、回路基板上に電子部品が接続された接続体、接続体の製造方法及び電子部品の接続方法に関し、特に、回路基板への実装面に複数のバンプ電極が非対称に配置されている電子部品と、この電子部品が接続された接続体、接続体の製造方法及び電子部品の接続方法に関する。 The present invention relates to an electronic component connected to a circuit board via an adhesive, a connection body in which the electronic component is connected to the circuit board, a manufacturing method of the connection body, and a connection method of the electronic component, and more particularly to the circuit board. The present invention relates to an electronic component in which a plurality of bump electrodes are arranged asymmetrically on the mounting surface, a connection body to which the electronic component is connected, a manufacturing method of the connection body, and a connection method of the electronic component.
　本出願は、日本国において２０１３年１２月２０日に出願された日本特許出願番号特願２０１３－２６４３７７及び日本国において２０１４年８月８日に出願された日本特許出願番号特願２０１４－１６２４８０を基礎として優先権を主張するものであり、これらの出願は参照されることにより、本出願に援用される。 This application is filed with Japanese Patent Application No. 2013-264377 filed on December 20, 2013 in Japan and Japanese Patent Application No. 2014-162480 filed on August 8, 2014 in Japan. Claims priority as a basis and these applications are incorporated herein by reference.
　従来、各種電子機器の回路基板にＩＣチップやＬＳＩチップ等の電子部品が接続された接続体が提供されている。近年、各種電子機器においては、ファインピッチ化、軽量薄型化等の観点から、電子部品として、実装面に突起状の電極であるバンプが配列されたＩＣチップやＬＳＩチップを用いて、これらＩＣチップ等の電子部品を直接回路基板上に実装するいわゆるＣＯＢ（chip on board）や、ＣＯＧ（chip on glass）が採用されている。 Conventionally, a connection body in which electronic components such as an IC chip and an LSI chip are connected to circuit boards of various electronic devices has been provided. In recent years, various electronic devices use IC chips or LSI chips in which bumps, which are protruding electrodes, are arranged on the mounting surface as electronic components from the viewpoints of fine pitch, light weight, and thinning. So-called COB (chip-on-board) or COG (chip-on-glass) in which electronic components such as these are directly mounted on a circuit board are employed.
　ＣＯＢ接続やＣＯＧ接続においては、回路基板の端子部上に、異方性導電フィルムを介してＩＣチップが熱圧着されている。異方性導電フィルムは、熱硬化型のバインダー樹脂に導電性粒子を混ぜ込んでフィルム状としたもので、２つの導体間で加熱圧着されることにより導電粒子で導体間の電気的導通がとられ、バインダー樹脂にて導体間の機械的接続が保持される。異方性導電フィルムを構成する接着剤としては、通常、信頼性の高い熱硬化性の接着剤を用いるようになっている。また一方で、光硬化性樹脂による接続や、熱硬化と光硬化を併用した接続方法も用いられているが、ツールにより加圧する場合において、熱硬化性接着剤と同様の問題を含むと想定される。 In COB connection and COG connection, an IC chip is thermocompression-bonded on a terminal portion of a circuit board via an anisotropic conductive film. An anisotropic conductive film is a film formed by mixing conductive particles in a thermosetting binder resin, and heat conduction is performed between two conductors so that electrical conduction between the conductors is achieved with the conductive particles. The mechanical connection between the conductors is maintained by the binder resin. As an adhesive constituting the anisotropic conductive film, a highly reliable thermosetting adhesive is usually used. On the other hand, connection using a photo-curable resin or a connection method using both thermosetting and photo-curing is also used. However, in the case of applying pressure with a tool, it is assumed that the same problems as thermosetting adhesives are included. The
　バンプ付きＩＣチップ５０は、例えば図６（Ａ）に示すように、回路基板の実装面に、一方の側縁５０ａに沿って入力バンプ５１が一列で配列された入力バンプ領域５２が形成され、一方の側縁５０ａと対向する他方の側縁５０ｂに沿って出力バンプ５３が二列の千鳥状に配列された出力バンプ領域５４が設けられている。バンプ配列はＩＣチップの種類によって様々であるが、一般に、従来のバンプ付きＩＣチップは、入力バンプ５１の数よりも出力バンプ５３の数が多く、入力バンプ領域５２の面積よりも出力バンプ領域５４の面積が広くなり、また入力バンプ５１の形状が出力バンプ５３の形状よりも大きく形成されている。 For example, as shown in FIG. 6A, the bumped IC chip 50 has an input bump region 52 in which input bumps 51 are arranged in a line along one side edge 50a on the mounting surface of the circuit board. An output bump area 54 in which output bumps 53 are arranged in two rows in a zigzag manner is provided along the other side edge 50b facing one side edge 50a. The bump arrangement varies depending on the type of IC chip. In general, a conventional IC chip with bumps has a larger number of output bumps 53 than the number of input bumps 51, and an output bump area 54 than the area of the input bump area 52. And the shape of the input bump 51 is formed larger than the shape of the output bump 53.
　そして、ＣＯＧ実装では、例えば図６（Ｂ）に示すように、異方性導電フィルム５５を介して回路基板５６の電極端子５７上にＩＣチップ５０が搭載された後、熱圧着ヘッド５８によりＩＣチップ５０の上から加熱押圧する。この熱圧着ヘッド５８による熱加圧によって、異方性導電フィルム５５のバインダー樹脂が溶融して各入出力バンプ５１，５３と回路基板５６の電極端子５７との間から流動するとともに、各入出力バンプ５１，５３と回路基板５６の電極端子５７との間に導電性粒子が挟持され、この状態でバインダー樹脂が熱硬化する。これにより、ＩＣチップ５０は、回路基板５６上に電気的、機械的に接続される。 In the COG mounting, for example, as shown in FIG. 6B, after the IC chip 50 is mounted on the electrode terminal 57 of the circuit board 56 via the anisotropic conductive film 55, the IC is performed by the thermocompression bonding head 58. The chip 50 is heated and pressed from above. By the heat and pressure by the thermocompression bonding head 58, the binder resin of the anisotropic conductive film 55 is melted and flows from between the input / output bumps 51 and 53 and the electrode terminals 57 of the circuit board 56, and each input / output. Conductive particles are sandwiched between the bumps 51 and 53 and the electrode terminal 57 of the circuit board 56, and in this state, the binder resin is thermally cured. As a result, the IC chip 50 is electrically and mechanically connected to the circuit board 56.
特開２００４－２１４３７３号公報JP 2004-214373 A
　ここで、上述したように、バンプ付きＩＣチップ５０等の電子部品は、実装面に形成された入力バンプ５１と出力バンプ５３との各バンプ配列及び大きさが異なり、入力バンプ領域５２と出力バンプ領域５４とに面積差を有する。また、電子部品は、入力バンプ領域５２と出力バンプ領域５４とが実装面において非対称に配置されている。 Here, as described above, in the electronic component such as the IC chip 50 with bumps, the bump arrangement and size of the input bump 51 and the output bump 53 formed on the mounting surface are different, and the input bump region 52 and the output bump are different. There is an area difference from the region 54. In the electronic component, the input bump area 52 and the output bump area 54 are asymmetrically arranged on the mounting surface.
　そのため、従来のＣＯＢ接続やＣＯＧ接続においては、熱圧着ヘッド５８による入力バンプ５１と出力バンプ５３に掛かる押圧力が不均一となり、例えば出力バンプ領域５４においては、他方の側縁５０ｂ側に配列された出力バンプ５３と、実装面の内側に配列された出力バンプ５３とで、圧力差が生じ得る。 Therefore, in the conventional COB connection or COG connection, the pressing force applied to the input bump 51 and the output bump 53 by the thermocompression bonding head 58 becomes non-uniform. For example, in the output bump region 54, it is arranged on the other side edge 50b side. There may be a pressure difference between the output bump 53 and the output bump 53 arranged on the inner side of the mounting surface.
　また、熱圧着ヘッド５８による圧力が入力バンプ領域５２と出力バンプ領域５４との各内側縁に偏重することにより、出力バンプ領域５４においては、他方の側縁５０ｂ側に配列された出力バンプ５３への圧力が弱くなり、導電性粒子の押し込みが不足して導通不良を起こす恐れがある。 In addition, when the pressure by the thermocompression bonding head 58 is biased to the inner edges of the input bump area 52 and the output bump area 54, in the output bump area 54, the output bump 53 is arranged on the other side edge 50b side. There is a risk that the pressure of the electric field becomes weak and the conductive particles are insufficiently pushed to cause poor conduction.
　このような問題を解決するために、信号等の入出力には使用しないいわゆるダミーバンプを形成し、熱圧着ヘッドからＩＣチップ全面にかかる応力を分散させ均一化させることがなされている。しかし、この手法でも応力の支点が増えることで、技術的難易度は高くなる。また、ダミーバンプを形成するためには、電子部品の製造工数が増加し、また、よけいに材料コストも必要となってしまうため、ダミーバンプを使用しない構成が望まれる。 In order to solve such problems, so-called dummy bumps that are not used for signal input / output are formed, and the stress applied from the thermocompression bonding head to the entire surface of the IC chip is dispersed and made uniform. However, this technique also increases the technical difficulty by increasing the stress fulcrum. Further, in order to form dummy bumps, the number of man-hours for manufacturing electronic components increases, and material costs are also required. Therefore, a configuration that does not use dummy bumps is desired.
　そこで、本発明は、入力バンプ領域と出力バンプ領域とが面積差を有するとともに非対称に配置されている電子部品において、熱圧着ヘッドによる圧力差を解消し接続信頼性を向上することができる電子部品、接続体、接続体の製造方法及び接続方法を提供することを目的とする。 Therefore, the present invention provides an electronic component capable of eliminating the pressure difference caused by the thermocompression bonding head and improving the connection reliability in the electronic component in which the input bump region and the output bump region have an area difference and are disposed asymmetrically. It is an object of the present invention to provide a connection body, a manufacturing method of the connection body, and a connection method.
　上述した課題を解決するために、本発明に係る電子部品は、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ非対称に配置され、上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されているものである。 In order to solve the above-described problem, an electronic component according to the present invention is provided with an output bump area in which output bumps are arranged in proximity to one side of a pair of side edges facing each other. An input bump area in which input bumps are arranged adjacent to the other side is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically, and the output bump area or the input bump area Of these, one having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges.
　また、本発明に係る接続体は、電子部品が接着剤を介して回路基板上に配置され、加圧ツールで加圧されることにより、上記電子部品が上記回路基板上に接続された接続体において、上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されているものである。 In addition, the connection body according to the present invention is a connection body in which the electronic component is arranged on the circuit board via an adhesive and is pressed by a pressure tool so that the electronic component is connected to the circuit board. The mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the other of the pair of side edges An input bump area in which input bumps are arranged close to the side is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface, and the output bump area or the input bump One of the bump areas having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. .
　また、本発明に係る接続体の製造方法は、接着剤を介して回路基板上に電子部品を配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する接続体の製造方法において、上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されているものである。 Moreover, the manufacturing method of the connection body which concerns on this invention arrange | positions an electronic component on a circuit board via an adhesive agent, and connects the said electronic component on the said circuit board by pressurizing with a pressurization tool. In the manufacturing method, the mounting surface of the electronic component on the circuit board is provided with an output bump region in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the pair of side edges An input bump area in which input bumps are arranged adjacent to the other side of the output bump area is provided, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface. One of the input bump regions having a relatively large area is formed on the inner side from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. Is
　また、本発明に係る接続方法は、接着剤を介して回路基板上に電子部品を配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する電子部品の接続方法において、上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されているものである。 Further, the connection method according to the present invention is an electronic component connection method in which an electronic component is arranged on a circuit board via an adhesive, and the electronic component is connected to the circuit board by applying pressure with a pressure tool. The mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of the pair of side edges facing each other, and the other side of the pair of side edges. An input bump area in which input bumps are arranged is provided adjacent to the output bump area, and the output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface, and the output bump area or the input bump area. One of the regions having a relatively large area is formed on the inner side from the one or the other side edge adjacent by a distance of 4% or more of the width between the pair of side edges.
　上述した課題を解決するために、本発明に係る電子部品は、第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在するものである。 In order to solve the above-described problems, an electronic component according to the present invention is opposed to a first bump region having a rectangular shape in which a bump row is formed along a first side edge, and the first side edge. A rectangular second bump region in which a bump row is formed along the second side edge, and the distance in the width direction of the first bump region is the distance in the width direction of the second bump region. A midpoint between the outer sides of the first bump regions and the outer sides of the second bump regions in the width direction is between the first side edges and the second bump regions. It exists in the said 2nd side edge side from the midpoint between side edges between side edges.
　また、本発明に係る接続体は、第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品と、前記回路部品が接着剤を介して接続された回路基板とを備えるものである。 In addition, the connection body according to the present invention includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side edge facing the first side edge. A second bump region having a rectangular shape in which bump rows are formed, and a distance in the width direction of the first bump region is larger than a distance in the width direction of the second bump region, A midpoint between the outer sides of the bump region and the outer side of the second bump region in the width direction is a side between the first side edge and the second side edge. An electronic component present on the second side edge side from an inter-edge midpoint, and a circuit board to which the circuit component is connected via an adhesive.
　また、本発明に係る接続体の製造方法は、第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品を、接着剤を介して回路基板上に配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続するものである。 In addition, the method for manufacturing a connection body according to the present invention includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side facing the first side edge. A rectangular second bump region in which a bump row is formed along an edge, and the distance in the width direction of the first bump region is larger than the distance in the width direction of the second bump region, A midpoint between the outer sides of the first bump region and the outer side of the bump region between the outer side of the second bump region in the width direction is between the first side edge and the second side edge. An electronic component existing on the second side edge side from the middle point between the side edges is disposed on the circuit board via an adhesive, and the electronic component is placed on the circuit board by pressing with a pressing tool. To connect to.
　また、本発明に係る接続方法は、第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品を、接着剤を介して回路基板上に配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続するものである。 Further, the connection method according to the present invention includes a rectangular first bump region in which a bump row is formed along the first side edge, and a second side edge facing the first side edge. A second bump region having a rectangular shape in which bump rows are formed, and a distance in the width direction of the first bump region is larger than a distance in the width direction of the second bump region, A midpoint between the outer sides of the bump region and the outer side of the second bump region in the width direction is a side between the first side edge and the second side edge. An electronic component existing on the second side edge side from the middle point between the edges is disposed on the circuit board via an adhesive, and the electronic component is connected to the circuit board by applying pressure with a pressure tool. Is.
　本発明によれば、大面積のバンプ領域を実装面の幅に対して所定の割合だけ、側縁から内側に形成することにより、当該バンプ領域の幅方向に亘って形成されている圧力勾配が緩やかに均され、当該側縁側において熱圧着ヘッドによる押圧力が不足する事態を防止する。これにより、電子部品は、当該側縁側のバンプにおいても回路基板に形成された電極端子との間で確実に導電性粒子を挟持し、導通性を確保することができる。 According to the present invention, the pressure gradient formed across the width direction of the bump region is formed by forming the large bump region from the side edge to the inside by a predetermined ratio with respect to the width of the mounting surface. It is gently leveled to prevent a situation where the pressing force by the thermocompression bonding head is insufficient on the side edge side. As a result, the electronic component can reliably hold conductive particles between the bumps on the side edge side and the electrode terminals formed on the circuit board to ensure conductivity.
　本発明によれば、第１のバンプ領域の幅方向の外側と第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、第１の側縁と前記第２の側縁との間の側縁間中点より、第２の側縁側に存在するため、バンプ領域の幅方向に亘って形成されている圧力勾配が緩やかに均され、側縁側において熱圧着ヘッドによる押圧力が不足する事態を防止することができる。これにより、側縁側のバンプにおいても確実に導電性粒子を挟持することができ、優れた導通性を得ることができる。 According to the present invention, the midpoint between the bump region outer sides between the outer side in the width direction of the first bump region and the outer side in the width direction of the second bump region is the first side edge and the second side. Since it exists on the second side edge side from the midpoint between the side edges to the edge, the pressure gradient formed over the width direction of the bump area is gently leveled, and the pressing by the thermocompression bonding head on the side edge side. A situation where pressure is insufficient can be prevented. As a result, the conductive particles can be reliably sandwiched even in the bumps on the side edge side, and excellent conductivity can be obtained.
図１は、本発明に係る電子部品の実装面を示す平面図である。FIG. 1 is a plan view showing a mounting surface of an electronic component according to the present invention. 図２は、電子部品が接続された接続体を示す断面図である。FIG. 2 is a cross-sectional view showing a connection body to which electronic components are connected. 図３は、ダミーバンプを設けた本発明に係る電子部品の実装面を示す平面図である。FIG. 3 is a plan view showing a mounting surface of the electronic component according to the present invention provided with dummy bumps. 図４は、異方性導電フィルムを示す断面図である。FIG. 4 is a cross-sectional view showing an anisotropic conductive film. 図５は、本発明に係る電子部品の幅方向の実装面を示す断面図である。FIG. 5 is a cross-sectional view showing a mounting surface in the width direction of the electronic component according to the present invention. 図６（Ａ）は従来の電子部品の実装面を示す平面図であり、図６（Ｂ）は実装状態を示す断面図である。6A is a plan view showing a mounting surface of a conventional electronic component, and FIG. 6B is a cross-sectional view showing a mounting state.
　以下、本発明が適用された電子部品、接続体、接続体の製造方法及び接続方法について、図面を参照しながら詳細に説明する。なお、本発明は、以下の実施形態のみに限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々の変更が可能であることは勿論である。また、図面は模式的なものであり、各寸法の比率等は現実のものとは異なることがある。具体的な寸法等は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。 Hereinafter, an electronic component to which the present invention is applied, a connection body, a method for manufacturing the connection body, and a connection method will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and various modifications can be made without departing from the scope of the present invention. Further, the drawings are schematic, and the ratio of each dimension may be different from the actual one. Specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
　[第１の実施の形態]
　先ず、本発明の第１の実施の形態について説明する。本発明が適用された電子部品は、接着剤を介して回路基板上に配置され、熱圧着ヘッドで加圧されることにより回路基板上に接続される電子部品であり、例えばドライバＩＣやシステムＬＳＩ等のパッケージ化された電子部品である。以下では、電子部品として、ＩＣチップ１を例に説明する。 [First embodiment]
First, a first embodiment of the present invention will be described. An electronic component to which the present invention is applied is an electronic component that is arranged on a circuit board via an adhesive and is connected to the circuit board by being pressed by a thermocompression bonding head. For example, a driver IC or a system LSI Etc. are packaged electronic components. Hereinafter, the IC chip 1 will be described as an example of the electronic component.
　図１に示すように、ＩＣチップ１の回路基板上に接続される実装面２は、略矩形状をなし、長さ方向となる相対向する一対の側縁２ａ，２ｂに沿って、出力バンプ３が配列された出力バンプ領域４及び入力バンプ５が配列された入力バンプ領域６が形成されている。ＩＣチップ１は、出力バンプ領域４が実装面２の一方の側縁２ａ側に形成され、入力バンプ領域６が実装面２の他方の側縁２ｂ側に形成されている。これにより、ＩＣチップ１は、実装面２の幅方向に亘って出力バンプ領域４と入力バンプ領域６とが離間して形成されている。 As shown in FIG. 1, the mounting surface 2 connected to the circuit board of the IC chip 1 has a substantially rectangular shape, and along the pair of side edges 2a and 2b facing each other in the length direction, output bumps are formed. An output bump area 4 in which 3 is arranged and an input bump area 6 in which input bumps 5 are arranged are formed. In the IC chip 1, the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2. Thus, the IC chip 1 is formed such that the output bump area 4 and the input bump area 6 are separated from each other in the width direction of the mounting surface 2.
　出力バンプ領域４には、例えば同一形状に形成された複数の出力バンプ３が、実装面２の長手方向に沿って３列で千鳥状に配列されている。また、入力バンプ領域６には、例えば同一形状に形成された複数の入力バンプ５が、実装面２の長手方向に沿って１列で配列されている。なお、入力バンプ５は、出力バンプ３よりも大きく形成される。これにより、ＩＣチップ１は、出力バンプ領域４と入力バンプ領域６とが面積差を有するとともに、実装面２において非対称に配置されている。なお、出力バンプ領域４に配列されている各出力バンプ３は、それぞれ同一の寸法で形成されることが好ましい。同様に、入力バンプ領域６に配列されている各入力バンプ５は、それぞれ同一の寸法で形成されることが好ましい。 In the output bump area 4, for example, a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2. In the input bump area 6, for example, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2. The input bump 5 is formed larger than the output bump 3. Thus, in the IC chip 1, the output bump region 4 and the input bump region 6 have an area difference and are disposed asymmetrically on the mounting surface 2. The output bumps 3 arranged in the output bump region 4 are preferably formed with the same dimensions. Similarly, the input bumps 5 arranged in the input bump area 6 are preferably formed with the same dimensions.
　［大面積バンプ領域のオフセット］
　本発明に係るＩＣチップ１では、出力バンプ領域４が、一方の側縁２ａと他方の側縁２ｂとの間に亘るＩＣ幅Ｗに対して所定の割合だけ、一方の側縁２ａから内側に形成されている。これにより、ＩＣチップ１は、後述する熱圧着ヘッド１７によって回路基板１４上に加熱押圧された場合に、押圧力が出力バンプ領域４の内側に偏在することを防止し、一方の側縁２ａ側に配列されている出力パンプ３に対しても適正な押圧力を掛けることができる。 [Offset of large area bump area]
In the IC chip 1 according to the present invention, the output bump region 4 is inward from the one side edge 2a by a predetermined ratio with respect to the IC width W extending between the one side edge 2a and the other side edge 2b. Is formed. Thereby, when the IC chip 1 is heated and pressed on the circuit board 14 by a thermocompression bonding head 17 to be described later, the pressing force is prevented from being unevenly distributed inside the output bump region 4, and the one side edge 2a side It is possible to apply an appropriate pressing force to the output pumps 3 arranged in the above.
　すなわち、ＩＣチップ１は、出力バンプ領域４と入力バンプ領域６とに面積差を有するとともに実装面２において非対称に配置されているため、熱圧着ヘッド１７によって実装面２の全面に対して圧力を掛けられると、出力バンプ３が複数列で配列されることにより幅方向に亘って大面積に形成されている出力バンプ領域４においては、入力バンプ領域６と対峙する内側縁における押圧力が強まり実装面２の一方の側縁２ａ側にかけて押圧力が弱まる圧力勾配となり、一方の側縁２ａ側に配列されている出力バンプ３に対する押圧力が不足する。これにより、導電性粒子の押し込みが不足することにより、特にバンプの外縁領域において出力バンプ３の導通抵抗が高くなる恐れがあった。 That is, since the IC chip 1 has an area difference between the output bump region 4 and the input bump region 6 and is disposed asymmetrically on the mounting surface 2, the thermocompression bonding head 17 applies pressure to the entire surface of the mounting surface 2. When applied, in the output bump region 4 formed in a large area across the width direction by arranging the output bumps 3 in a plurality of rows, the pressing force at the inner edge facing the input bump region 6 is increased and mounting is performed. The pressure gradient is such that the pressing force weakens toward one side edge 2a of the surface 2, and the pressing force against the output bumps 3 arranged on the one side edge 2a side is insufficient. Thereby, there is a possibility that the conduction resistance of the output bump 3 is increased particularly in the outer edge region of the bump due to insufficient pushing of the conductive particles.
　そこで、ＩＣチップ１は、出力バンプ領域４を実装面２の幅に対して所定の割合だけ、一方の側縁２ａから内側に形成することにより、出力バンプ領域４の幅方向に亘って形成されている圧力勾配が緩やかに均され、当該一方の側縁２ａ側において熱圧着ヘッド１７による押圧力が不足する事態を防止する。これにより、ＩＣチップ１は、当該一方の側縁２ａ側の出力バンプ３においても回路基板１４に形成された電極端子１５との間で確実に導電性粒子を挟持し、導通性を確保することができる。 Therefore, the IC chip 1 is formed across the width direction of the output bump region 4 by forming the output bump region 4 inward from the one side edge 2a by a predetermined ratio with respect to the width of the mounting surface 2. The pressure gradient that is applied is gently leveled to prevent the pressing force by the thermocompression bonding head 17 from being insufficient on the one side edge 2a side. As a result, the IC chip 1 reliably holds the conductive particles between the output bumps 3 on the one side edge 2a side and the electrode terminals 15 formed on the circuit board 14 to ensure conductivity. Can do.
　この一方の側縁２ａから出力バンプ領域４までの距離Ａは、実装面２の相対向する側縁２ａ２ｂ間に亘るＩＣ幅Ｗに対して４％以上の距離とすることが好ましい。出力バンプ領域４を、ＩＣ幅Ｗに対して４％以上の距離だけ、一方の側縁２ａから内側に形成することにより、面積差を有する出力バンプ領域４と入力バンプ領域６とが非対称に配置されている実装面２に対して熱圧着ヘッド１７が均等に圧力を掛けた場合にも、第１の側縁２ａ側に配置された出力バンプ３まで十分に押圧力が伝わる。しかし、一方の側縁２ａから出力バンプ３までの距離Ａが、ＩＣ幅Ｗに対して４％未満であると、熱圧着ヘッド１７による押圧力が一方の側縁２ａ側の出力バンプ３まで十分に伝わらずに導電性粒子の押し込み不足による導通不良が起きる危険がある。 The distance A from the one side edge 2a to the output bump region 4 is preferably 4% or more with respect to the IC width W between the opposing side edges 2a2b of the mounting surface 2. By forming the output bump region 4 inward from one side edge 2a by a distance of 4% or more with respect to the IC width W, the output bump region 4 and the input bump region 6 having an area difference are arranged asymmetrically. Even when the thermocompression bonding head 17 applies pressure evenly to the mounting surface 2, the pressing force is sufficiently transmitted to the output bumps 3 arranged on the first side edge 2 a side. However, if the distance A from one side edge 2a to the output bump 3 is less than 4% of the IC width W, the pressing force by the thermocompression bonding head 17 is sufficient to the output bump 3 on the one side edge 2a side. There is a risk of poor conduction due to insufficient push-in of conductive particles.
　また、距離Ａが大きくなりすぎるとＩＣチップ１全面への圧力の均一化に齟齬をきたし、圧力の不均衡を別に誘発する恐れが生じる。そのため、距離Ａは３０％以内が好ましく、より好ましくは２０％以内であり、更により好ましくは１５％以内である。 Also, if the distance A becomes too large, the pressure on the entire surface of the IC chip 1 is made uniform, and there is a possibility that pressure imbalance is separately induced. Therefore, the distance A is preferably within 30%, more preferably within 20%, and even more preferably within 15%.
　［距離Ａ＞距離Ｂ］
　なお、ＩＣチップ１は、相対的に大面積の出力バンプ領域４の一方の側縁２ａからの距離Ａが、入力バンプ領域６の他方の側縁２ｂからの距離Ｂよりも長いことが好ましい。すなわち、比較的小面積の入力バンプ領域６の他方の側縁２ｂからの距離Ｂが大面積の出力バンプ領域４の一方の側縁２ａからの距離Ａよりも長いと、出力バンプ領域４における幅方向にわたる圧力勾配が大きくされ、一方の側縁２ａ側の出力バンプ３における導電性粒子の押し込み不足の解消を阻害してしまう。 [Distance A> Distance B]
In the IC chip 1, the distance A from the one side edge 2 a of the output bump region 4 having a relatively large area is preferably longer than the distance B from the other side edge 2 b of the input bump region 6. That is, if the distance B from the other side edge 2b of the relatively small area input bump region 6 is longer than the distance A from the one side edge 2a of the large area output bump region 4, the width in the output bump region 4 The pressure gradient over the direction is increased, and obstruction of insufficient pressing of the conductive particles in the output bump 3 on the side edge 2a side is hindered.
　また、入力バンプ５が一列で配列されることにより比較的小面積の入力バンプ領域６においては、出力バンプ領域４との面積差及び非対称配置によっても熱圧着ヘッド１７による押圧力が偏在することによる押し込み不足の危険が少ないことから、実装面２の他方の側縁２ｂからの距離Ｂが短くとも問題はない。 In addition, since the input bumps 5 are arranged in a line, in the input bump region 6 having a relatively small area, the pressing force by the thermocompression bonding head 17 is unevenly distributed due to an area difference from the output bump region 4 and an asymmetrical arrangement. Since the risk of insufficient push-in is small, there is no problem even if the distance B from the other side edge 2b of the mounting surface 2 is short.
　［大面積の入力バンプ領域６をオフセット］
　なお、ＩＣチップ１は、実装面２の入出力バンプの構成は適宜設計することができる。ＩＣチップ１は、上述したように出力バンプ３を幅方向に複数配列することにより相対的に大面積化させた出力バンプ領域４を形成したが、反対に、入力バンプ５を幅方向に複数配列することにより相対的に入力バンプ領域６を大面積化させてもよい。 [Offset large area input bump area 6]
In the IC chip 1, the configuration of the input / output bumps on the mounting surface 2 can be appropriately designed. As described above, the IC chip 1 forms the output bump region 4 having a relatively large area by arranging a plurality of output bumps 3 in the width direction. Conversely, a plurality of input bumps 5 are arranged in the width direction. By doing so, the input bump region 6 may be relatively enlarged.
　入力バンプ領域６を相対的に大面積化した場合は、ＩＣチップ１は、入力バンプ領域６を、ＩＣ幅Ｗに対して所定の割合、好ましくはＩＣ幅Ｗの４％以上の距離、他方の側縁２ｂから内側に形成させる。また、この場合、相対的に大面積の入力バンプ領域６の他方の側縁２ｂからの距離Ｂが、出力バンプ領域４の一方の側縁２ａからの距離Ａよりも長いことが好ましい。 When the input bump area 6 has a relatively large area, the IC chip 1 determines that the input bump area 6 has a predetermined ratio to the IC width W, preferably a distance of 4% or more of the IC width W, It forms inside from the side edge 2b. In this case, the distance B from the other side edge 2 b of the relatively large area input bump region 6 is preferably longer than the distance A from the one side edge 2 a of the output bump region 4.
　なお、入力バンプ領域６を他方の側縁２ｂからＩＣ幅Ｗの４％以上内側に形成した場合、図２に示すように、隣接して回路基板１４上にフレキシブル基板１６が異方性導電フィルム１０を介して接続される際に、入力バンプ５と電極端子１５との接続位置がフレキシブル基板１６を熱加圧する熱圧着ヘッド１７から離間される。したがって、ＩＣチップ１の接続後における熱圧着ヘッド１７からの放熱による接続性の悪化を防止することができる。 When the input bump region 6 is formed at least 4% of the IC width W from the other side edge 2b, as shown in FIG. 2, the flexible substrate 16 is adjacent to the circuit substrate 14 on the anisotropic conductive film. 10, the connection position between the input bump 5 and the electrode terminal 15 is separated from the thermocompression bonding head 17 that heat-presses the flexible substrate 16. Therefore, it is possible to prevent deterioration in connectivity due to heat radiation from the thermocompression bonding head 17 after the IC chip 1 is connected.
　［ダミーバンプ］
　なお、図３に示すように、ＩＣチップ１は、出力バンプ領域４と入力バンプ領域６との間に、信号等の入出力には使用しないいわゆるダミーバンプ１８が配列されたダミーバンプ領域１９を適宜設けてもよい。 [Dummy bump]
As shown in FIG. 3, the IC chip 1 appropriately includes a dummy bump area 19 in which so-called dummy bumps 18 that are not used for input / output of signals and the like are arranged between the output bump area 4 and the input bump area 6. May be.
　［接着剤］
　なお、ＩＣチップ１を回路基板１４に接続する接着剤としては、異方性導電フィルム１０（ＡＣＦ：Anisotropic Conductive Film）を好適に用いることができる。異方性導電フィルム１０は、図４に示すように、通常、基材となる剥離フィルム１１上に導電性粒子１２を含有するバインダー樹脂層（接着剤層）１３が形成されたものである。異方性導電フィルム１０は、図２に示すように、回路基板１４に形成された電極端子１５とＩＣチップ１との間にバインダー樹脂層１３を介在させることで、回路基板１４とＩＣチップ１とを接続し、導通させるために用いられる。 [adhesive]
As an adhesive for connecting the IC chip 1 to the circuit board 14, an anisotropic conductive film 10 (ACF) can be suitably used. As shown in FIG. 4, the anisotropic conductive film 10 is generally formed by forming a binder resin layer (adhesive layer) 13 containing conductive particles 12 on a release film 11 serving as a base material. As shown in FIG. 2, the anisotropic conductive film 10 has the circuit board 14 and the IC chip 1 by interposing a binder resin layer 13 between the electrode terminal 15 formed on the circuit board 14 and the IC chip 1. Are used for connecting and conducting.
　バインダー樹脂層１３の接着剤組成物は、例えば膜形成樹脂、熱硬化性樹脂、潜在性硬化剤、シランカップリング剤等を含有する通常のバインダー成分からなる。 The adhesive composition of the binder resin layer 13 comprises a normal binder component containing, for example, a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, and the like.
　膜形成樹脂としては、平均分子量が１００００～８００００程度の樹脂が好ましく、特にエポキシ樹脂、変形エポキシ樹脂、ウレタン樹脂、フェノキシ樹脂等の各種の樹脂が挙げられる。中でも、膜形成状態、接続信頼性等の観点からフェノキシ樹脂が好ましい。 The film-forming resin is preferably a resin having an average molecular weight of about 10,000 to 80,000, and various resins such as an epoxy resin, a modified epoxy resin, a urethane resin, and a phenoxy resin are particularly mentioned. Among these, phenoxy resin is preferable from the viewpoint of film formation state, connection reliability, and the like.
　熱硬化性樹脂としては特に限定されず、例えば市販のエポキシ樹脂やアクリル樹脂等を用いることができる。 The thermosetting resin is not particularly limited, and for example, a commercially available epoxy resin or acrylic resin can be used.
　エポキシ樹脂としては、特に限定されないが、例えば、ナフタレン型エポキシ樹脂、ビフェニル型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、ビスフェノール型エポキシ樹脂、スチルベン型エポキシ樹脂、トリフェノールメタン型エポキシ樹脂、フェノールアラルキル型エポキシ樹脂、ナフトール型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、トリフェニルメタン型エポキシ樹脂等が挙げられる。これらは単独でも、２種以上の組み合わせであってもよい。 The epoxy resin is not particularly limited. For example, naphthalene type epoxy resin, biphenyl type epoxy resin, phenol novolac type epoxy resin, bisphenol type epoxy resin, stilbene type epoxy resin, triphenolmethane type epoxy resin, phenol aralkyl type epoxy resin. Naphthol type epoxy resin, dicyclopentadiene type epoxy resin, triphenylmethane type epoxy resin and the like. These may be used alone or in combination of two or more.
　アクリル樹脂としては、特に制限はなく、目的に応じてアクリル化合物、液状アクリレート等を適宜選択することができる。例えば、メチルアクリレート、エチルアクリレート、イソプロピルアクリレート、イソブチルアクリレート、エポキシアクリレート、エチレングリコールジアクリレート、ジエチレングリコールジアクリレート、トリメチロールプロパントリアクリレート、ジメチロールトリシクロデカンジアクリレート、テトラメチレングリコールテトラアクリレート、２－ヒドロキシ－１，３－ジアクリロキシプロパン、２，２－ビス[４－（アクリロキシメトキシ）フェニル]プロパン、２，２－ビス[４－（アクリロキシエトキシ）フェニル]プロパン、ジシクロペンテニルアクリレート、トリシクロデカニルアクリレート、トリス（アクリロキシエチル）イソシアヌレート、ウレタンアクリレート、エポキシアクリレート等を挙げることができる。なお、アクリレートをメタクリレートにしたものを用いることもできる。これらは、１種単独で使用してもよいし、２種以上を併用してもよい。 There is no restriction | limiting in particular as an acrylic resin, According to the objective, an acrylic compound, liquid acrylate, etc. can be selected suitably. For example, methyl acrylate, ethyl acrylate, isopropyl acrylate, isobutyl acrylate, epoxy acrylate, ethylene glycol diacrylate, diethylene glycol diacrylate, trimethylolpropane triacrylate, dimethylol tricyclodecane diacrylate, tetramethylene glycol tetraacrylate, 2-hydroxy- 1,3-diacryloxypropane, 2,2-bis [4- (acryloxymethoxy) phenyl] propane, 2,2-bis [4- (acryloxyethoxy) phenyl] propane, dicyclopentenyl acrylate, tricyclo Examples include decanyl acrylate, tris (acryloxyethyl) isocyanurate, urethane acrylate, and epoxy acrylate. In addition, what made acrylate the methacrylate can also be used. These may be used individually by 1 type and may use 2 or more types together.
　潜在性硬化剤としては、特に限定されないが、加熱硬化型の硬化剤が挙げられる。潜在性硬化剤は、通常では反応せず、熱、光、加圧等の用途に応じて選択される各種のトリガにより活性化し、反応を開始する。熱活性型潜在性硬化剤の活性化方法には、加熱による解離反応などで活性種（カチオンやアニオン、ラジカル）を生成する方法、室温付近ではエポキシ樹脂中に安定に分散しており高温でエポキシ樹脂と相溶・溶解し、硬化反応を開始する方法、モレキュラーシーブ封入タイプの硬化剤を高温で溶出して硬化反応を開始する方法、マイクロカプセルによる溶出・硬化方法等が存在する。熱活性型潜在性硬化剤としては、イミダゾール系、ヒドラジド系、三フッ化ホウ素－アミン錯体、スルホニウム塩、アミンイミド、ポリアミン塩、ジシアンジアミド等や、これらの変性物があり、これらは単独でも、２種以上の混合体であってもよい。ラジカル重合開始剤としては、公知のものを使用することができ、中でも有機過酸化物を好ましく使用することができる。 The latent curing agent is not particularly limited, but includes a heat curing type curing agent. The latent curing agent does not normally react, but is activated by various triggers selected according to applications such as heat, light, and pressure, and starts the reaction. The activation method of the thermal activation type latent curing agent includes a method of generating active species (cation, anion, radical) by a dissociation reaction by heating, etc., and it is stably dispersed in the epoxy resin near room temperature, and epoxy at high temperature There are a method of initiating a curing reaction by dissolving and dissolving with a resin, a method of initiating a curing reaction by eluting a molecular sieve encapsulated type curing agent at a high temperature, and an elution / curing method using microcapsules. Thermally active latent curing agents include imidazole, hydrazide, boron trifluoride-amine complexes, sulfonium salts, amine imides, polyamine salts, dicyandiamide, etc., and modified products thereof. The above mixture may be sufficient. As the radical polymerization initiator, a known one can be used, and among them, an organic peroxide can be preferably used.
　シランカップリング剤としては、特に限定されないが、例えば、エポキシ系、アミノ系、メルカプト・スルフィド系、ウレイド系等を挙げることができる。シランカップリング剤を添加することにより、有機材料と無機材料との界面における接着性が向上される。 The silane coupling agent is not particularly limited, and examples thereof include an epoxy type, an amino type, a mercapto sulfide type, and a ureido type. By adding the silane coupling agent, the adhesion at the interface between the organic material and the inorganic material is improved.
　［導電性粒子］
　バインダー樹脂層１３に含有される導電性粒子１２としては、異方性導電フィルムにおいて使用されている公知の何れの導電性粒子を挙げることができる。すなわち、導電性粒子としては、例えば、ニッケル、鉄、銅、アルミニウム、錫、鉛、クロム、コバルト、銀、金等の各種金属や金属合金の粒子、金属酸化物、カーボン、グラファイト、ガラス、セラミック、プラスチック等の粒子の表面に金属をコートしたもの、或いは、これらの粒子の表面に更に絶縁薄膜をコートしたもの等が挙げられる。樹脂粒子の表面に金属をコートしたものである場合、樹脂粒子としては、例えば、エポキシ樹脂、フェノール樹脂、アクリル樹脂、アクリロニトリル・スチレン（ＡＳ）樹脂、ベンゾグアナミン樹脂、ジビニルベンゼン系樹脂、スチレン系樹脂等の粒子を挙げることができる。 [Conductive particles]
Examples of the conductive particles 12 contained in the binder resin layer 13 include any known conductive particles used in anisotropic conductive films. That is, as the conductive particles, for example, particles of various metals and metal alloys such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, gold, metal oxide, carbon, graphite, glass, ceramic Examples thereof include those in which the surface of particles such as plastic is coated with metal, or those in which the surface of these particles is further coated with an insulating thin film. In the case where the surface of the resin particle is coated with metal, examples of the resin particle include an epoxy resin, a phenol resin, an acrylic resin, an acrylonitrile / styrene (AS) resin, a benzoguanamine resin, a divinylbenzene resin, a styrene resin, and the like. Can be mentioned.
　バインダー樹脂層１３を構成する接着剤組成物は、このように膜形成樹脂、熱硬化性樹脂、潜在性硬化剤、シランカップリング剤等を含有する場合に限定されず、通常の異方性導電フィルムの接着剤組成物として用いられる何れの材料から構成されるようにしてもよい。 The adhesive composition constituting the binder resin layer 13 is not limited to the case where it contains a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, etc. You may make it comprise from any material used as an adhesive composition of a film.
　バインダー樹脂層１３を支持する剥離フィルム１１は、例えば、ＰＥＴ（Poly Ethylene Terephthalate）、ＯＰＰ（Oriented Polypropylene）、ＰＭＰ（Poly-4-methylpentene-1）、ＰＴＦＥ（Polytetrafluoroethylene）等にシリコーン等の剥離剤を塗布してなり、異方性導電フィルム１０の乾燥を防ぐとともに、異方性導電フィルム１０の形状を維持する。 The release film 11 that supports the binder resin layer 13 is made of, for example, a release agent such as silicone on PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), and the like. It is applied and prevents the anisotropic conductive film 10 from being dried, and maintains the shape of the anisotropic conductive film 10.
　異方性導電フィルム１０は、何れの方法で作製するようにしてもよいが、例えば以下の方法によって作製することができる。膜形成樹脂、熱硬化性樹脂、潜在性硬化剤、シランカップリング剤、導電性粒子等を含有する接着剤組成物を調整する。調整した接着剤組成物をバーコーター、塗布装置等を用いて剥離フィルム１１上に塗布し、オーブン等によって乾燥させることにより、剥離フィルム１１にバインダー樹脂層１３が支持された異方性導電フィルム１０を得る。 The anisotropic conductive film 10 may be produced by any method, but can be produced, for example, by the following method. An adhesive composition containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, conductive particles and the like is prepared. An anisotropic conductive film 10 in which the binder resin layer 13 is supported on the release film 11 by applying the adjusted adhesive composition on the release film 11 using a bar coater, a coating apparatus, and the like, and drying it by an oven or the like. Get.
　また、上述の実施の形態では、接着剤として、バインダー樹脂層１３に適宜導電性粒子１２を含有した熱硬化性樹脂組成物をフィルム状に成形した接着フィルムを例に説明したが、本発明に係る接着剤は、これに限定されず、例えばバインダー樹脂層１３のみからなる絶縁性接着フィルムでもよい。また、本発明に係る接着剤は、バインダー樹脂層１３のみからなる絶縁性接着剤層と導電性粒子１２を含有したバインダー樹脂層１３からなる導電性粒子含有層とを積層した構成とすることができる。また、接着剤は、このようなフィルム成形されてなる接着フィルムに限定されず、バインダー樹脂組成物に導電性粒子１２が分散された導電性接着ペースト、あるいはバインダー樹脂組成物のみからなる絶縁性接着ペーストとしてもよい。本発明に係る接着剤は、上述したいずれの形態をも包含するものである。 In the above-described embodiment, the adhesive film obtained by forming a thermosetting resin composition appropriately containing the conductive particles 12 in the binder resin layer 13 as a film has been described as an example. Such an adhesive is not limited to this, and may be, for example, an insulating adhesive film made of only the binder resin layer 13. In addition, the adhesive according to the present invention has a configuration in which an insulating adhesive layer made of only the binder resin layer 13 and a conductive particle-containing layer made of the binder resin layer 13 containing the conductive particles 12 are laminated. it can. Further, the adhesive is not limited to such an adhesive film formed into a film, but an insulating adhesive consisting of a conductive adhesive paste in which conductive particles 12 are dispersed in a binder resin composition or a binder resin composition alone. It may be a paste. The adhesive according to the present invention includes any of the forms described above.
　［接続工程］
　次いで、回路基板１４にＩＣチップ１を接続する接続工程について説明する。先ず、回路基板１４の電極端子１５が形成された実装部上に異方性導電フィルム１０を仮貼りする。次いで、この回路基板１４を接続装置のステージ上に載置し、回路基板１４の実装部上に異方性導電フィルム１０を介してＩＣチップ１を配置する。 [Connection process]
Next, a connection process for connecting the IC chip 1 to the circuit board 14 will be described. First, the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 on which the electrode terminals 15 are formed. Next, the circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 via the anisotropic conductive film 10.
　次いで、バインダー樹脂層１３を硬化させる所定の温度に加熱された熱圧着ヘッド１７によって、所定の圧力、時間でＩＣチップ１上から熱加圧する。これにより、異方性導電フィルム１０のバインダー樹脂層１３は流動性を示し、ＩＣチップ１の実装面２と回路基板１４の実装部の間から流出するとともに、バインダー樹脂層１３中の導電性粒子１２は、ＩＣチップ１の出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間に挟持されて押し潰される。 Next, the thermocompression bonding head 17 heated to a predetermined temperature for curing the binder resin layer 13 is hot-pressed from above the IC chip 1 at a predetermined pressure and time. Thereby, the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the conductive particles in the binder resin layer 13. 12 is sandwiched between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and is crushed.
　このとき、本発明が適用されたＩＣチップ１によれば、出力バンプ領域４をＩＣ幅Ｗに対して４％以上の距離だけ、一方の側縁２ａから内側に形成することにより、出力バンプ領域４の幅方向に亘って形成されている圧力勾配が均され、熱圧着ヘッド１７による押圧力が出力バンプ領域４全域において略均等に加わり、当該一方の側縁２ａ側において押圧力が不足する事態が防止されている。 At this time, according to the IC chip 1 to which the present invention is applied, the output bump region 4 is formed on the inner side from the one side edge 2a by a distance of 4% or more with respect to the IC width W. The pressure gradient formed over the width direction 4 is leveled, the pressing force by the thermocompression bonding head 17 is applied substantially uniformly throughout the output bump region 4, and the pressing force is insufficient on the one side edge 2a side. Is prevented.
　その結果、出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間で導電性粒子１２を挟持することにより電気的に接続され、この状態で熱圧着ヘッド１７によって加熱されたバインダー樹脂が硬化する。したがって、ＩＣチップ１は、当該一方の側縁２ａ側の出力バンプ３においても回路基板１４に形成された電極端子１５との間で確実に導通性を確保することができる。 As a result, the binder resin electrically connected by sandwiching the conductive particles 12 between the output bumps 3 and 5 and the electrode terminals 15 of the circuit board 14 and heated in this state by the thermocompression bonding head 17. Is cured. Therefore, the IC chip 1 can reliably ensure electrical continuity with the electrode terminal 15 formed on the circuit board 14 also in the output bump 3 on the one side edge 2a side.
　出力バンプ３及び入力バンプ５と電極端子１５との間にない導電性粒子１２は、バインダー樹脂に分散されており、電気的に絶縁した状態を維持している。これにより、ＩＣチップ１の出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間のみで電気的導通が図られる。なお、バインダー樹脂として、ラジカル重合反応系の速硬化タイプのものを用いることで、短い加熱時間によってもバインダー樹脂を速硬化させることができる。また、異方性導電フィルム１０としては、熱硬化型に限らず、加圧接続を行うものであれば、光硬化型もしくは光熱併用型の接着剤を用いてもよい。 The conductive particles 12 that are not between the output bumps 3 and the input bumps 5 and the electrode terminals 15 are dispersed in the binder resin and maintain an electrically insulated state. Thereby, electrical conduction is achieved only between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14. In addition, by using a fast curing type radical polymerization reaction system as the binder resin, the binder resin can be rapidly cured even with a short heating time. Further, the anisotropic conductive film 10 is not limited to the thermosetting type, and may be a photo-curing type or a photo-heat combined type adhesive as long as it performs pressure connection.
第１の実施例First embodiment
　次いで、本発明の第１の実施例について説明する。第１の実施例では、出力バンプ領域及び入力バンプ領域に面積差を有するとともに実装面に非対称に配置されたＩＣチップを用い、異方性導電フィルムを介して回路基板上に接続した接続体サンプルを製造した。実施例及び比較例に係るＩＣチップは、ＩＣ幅及び実装面の一方の側縁２ａから出力バンプ領域までの距離Ａを異ならせ、それぞれ接続体サンプルにおける出力バンプ及び入力バンプの導通抵抗値を測定、評価した。 Next, a first embodiment of the present invention will be described. In the first embodiment, a connected body sample is connected to a circuit board via an anisotropic conductive film using an IC chip having an area difference between the output bump area and the input bump area and asymmetrically arranged on the mounting surface. Manufactured. The IC chips according to the example and the comparative example are different in the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region, and measure the conduction resistance values of the output bump and the input bump in the connection sample, respectively. ,evaluated.
　実施例及び比較例に係るＩＣチップは、略矩形状の実装面２の長さ方向となる相対向する一対の側縁２ａ，２ｂに沿って、出力バンプ３が配列された出力バンプ領域４及び入力バンプ５が配列された入力バンプ領域６が形成されている。ＩＣチップ１は、出力バンプ領域４が実装面２の一方の側縁２ａ側に形成され、入力バンプ領域６が実装面２の他方の側縁２ｂ側に形成されている。これにより、ＩＣチップ１は、実装面の幅方向に亘って出力バンプ領域４と入力バンプ領域６とが離間して形成されている（図１参照）。 The IC chip according to the example and the comparative example includes an output bump region 4 in which output bumps 3 are arranged along a pair of side edges 2a and 2b facing each other in the length direction of the substantially rectangular mounting surface 2. An input bump area 6 in which the input bumps 5 are arranged is formed. In the IC chip 1, the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2. As a result, in the IC chip 1, the output bump region 4 and the input bump region 6 are formed apart from each other in the width direction of the mounting surface (see FIG. 1).
　出力バンプ領域４には、同一形状に形成された複数の出力バンプ３が、実装面２の長手方向に沿って３列で千鳥状に配列されている。出力バンプ領域４に形成されている出力バンプを列毎に分け、一方の側縁２ａ側から順に出力バンプ列３Ａ、３Ｂ、３Ｃとする。各列に形成されている出力バンプ３は矩形状をなし（面積：１４３７．５μｍ２、幅：１２．５μｍ、長さ：１１５μｍ）、出力バンプ列３Ａ、３Ｂ、３Ｃ毎に１２７６個配列されている。各バンプ列３Ａ、３Ｂ、３Ｃにおける出力バンプ３の全面積は、それぞれ１８３４２５０μｍ２である。出力バンプ領域４の全面積は、１２９１９５００μｍ２（幅：３１９００μｍ、長さ：４０５μｍ）である。 In the output bump area 4, a plurality of output bumps 3 formed in the same shape are arranged in a staggered pattern in three rows along the longitudinal direction of the mounting surface 2. The output bumps formed in the output bump area 4 are divided into columns, and are designated as output bump columns 3A, 3B, 3C in order from one side edge 2a side. The output bumps 3 formed in each row have a rectangular shape (area: 1437.5 μm 2 , width: 12.5 μm, length: 115 μm), and 1276 output bump rows 3A, 3B, and 3C are arranged. Yes. The total area of the output bump 3 in each bump row 3A, 3B, 3C is 1834250 μm 2 , respectively. The total area of the output bump region 4 is 12919500 μm 2 (width: 31900 μm, length: 405 μm).
　また、入力バンプ領域６には、同一形状に形成された複数の入力バンプ５が、実装面２の長手方向に沿って１列で配列されている。入力バンプ領域６に形成されている１列の入力バンプ列を、入力バンプ列５Ａとする。入力バンプ列５Ａに配列されている入力バンプ５は、矩形状をなし（面積：３６００μｍ２、幅：４５．０μｍ、長さ：８０μｍ）、５１５個配列されている。入力バンプ列５Ａにおける入力バンプ５の全面積は、１８５４０００μｍ２である。入力バンプ領域６の全面積は、２５５３０４０μｍ２（幅：３１９１３μｍ、長さ：８０μｍ）である。 In the input bump area 6, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2. One input bump row formed in the input bump area 6 is defined as an input bump row 5A. The input bumps 5 arranged in the input bump row 5A have a rectangular shape (area: 3600 μm 2 , width: 45.0 μm, length: 80 μm), and 515 are arranged. The total area of the input bumps 5 in the input bump row 5A is 1854000 μm 2 . The total area of the input bump region 6 is 2553040 μm 2 (width: 31913 μm, length: 80 μm).
　［実施例１］
　実施例１に係るＩＣチップは、実装面２の相対向する側縁２ａ，２ｂ間に亘るＩＣ幅Ｗが１．５ｍｍ、入出力バンプ３，５の配列方向となるＩＣ長さが３２ｍｍである。また、一方の側縁２ａから出力バンプ領域４までの距離Ａは１５０μｍであり、ＩＣ幅Ｗ（１．５ｍｍ）に対する１０％の距離である。また、実施例１に係るＩＣチップは、出力バンプ領域４と入力バンプ領域６との間にダミーバンプ領域は設けず、また、他方の側縁２ｂから入力バンプ領域６までの距離Ｂは５０μｍである。 [Example 1]
In the IC chip according to the first embodiment, the IC width W between the opposing side edges 2a and 2b of the mounting surface 2 is 1.5 mm, and the IC length in the arrangement direction of the input / output bumps 3 and 5 is 32 mm. . Further, the distance A from one side edge 2a to the output bump region 4 is 150 μm, which is 10% of the IC width W (1.5 mm). In the IC chip according to the first embodiment, no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 μm. .
　［実施例２］
　実施例２に係るＩＣチップは、一方の側縁２ａから出力バンプ領域４までの距離Ａを１００μｍとした他は実施例１と同じ条件とした。実施例２における距離Ａは、ＩＣ幅Ｗ（１．５ｍｍ）に対して６．６％の距離となる。 [Example 2]
The IC chip according to Example 2 was set to the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 100 μm. The distance A in Example 2 is a distance of 6.6% with respect to the IC width W (1.5 mm).
　［実施例３］
　実施例３に係るＩＣチップは、一方の側縁２ａから出力バンプ領域４までの距離Ａを７５μｍとした他は実施例１と同じ条件とした。実施例３における距離Ａは、ＩＣ幅Ｗ（１．５ｍｍ）に対して５．０％の距離となる。 [Example 3]
The IC chip according to Example 3 was set to the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 75 μm. The distance A in Example 3 is 5.0% of the distance with respect to the IC width W (1.5 mm).
　［実施例４］
　実施例４に係るＩＣチップは、一方の側縁２ａから出力バンプ領域４までの距離Ａを６２．５μｍとした他は実施例１と同じ条件とした。実施例４における距離Ａは、ＩＣ幅Ｗ（１．５ｍｍ）に対して４．２％の距離となる。 [Example 4]
The IC chip according to Example 4 was under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 62.5 μm. The distance A in Example 4 is 4.2% of the IC width W (1.5 mm).
　［実施例５］
　実施例５に係るＩＣチップは、実装面２の相対向する側縁２ａ，２ｂ間に亘るＩＣ幅Ｗが２．０ｍｍ、入出力バンプ３，５の配列方向となるＩＣ長さが３２ｍｍである。また、一方の側縁２ａから出力バンプ領域４までの距離Ａは８３μｍであり、ＩＣ幅Ｗ（２．０ｍｍ）に対する４．２％の距離である。また、実施例５に係るＩＣチップは、出力バンプ領域４と入力バンプ領域６との間にダミーバンプ領域は設けず、また、他方の側縁２ｂから入力バンプ領域６までの距離Ｂは５０μｍである。 [Example 5]
The IC chip according to the fifth embodiment has an IC width W of 2.0 mm between the opposing side edges 2a and 2b of the mounting surface 2 and an IC length of 32 mm in the arrangement direction of the input / output bumps 3 and 5. . The distance A from one side edge 2a to the output bump region 4 is 83 μm, which is 4.2% of the IC width W (2.0 mm). In the IC chip according to the fifth embodiment, no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 μm. .
　［実施例６］
　実施例６に係るＩＣチップは、実装面２の相対向する側縁２ａ，２ｂ間に亘るＩＣ幅Ｗが３．０ｍｍ、入出力バンプ３，５の配列方向となるＩＣ長さが３２ｍｍである。また、一方の側縁２ａから出力バンプ領域４までの距離Ａは１２５μｍであり、ＩＣ幅Ｗ（３．０ｍｍ）に対する４．２％の距離である。また、実施例６に係るＩＣチップは、出力バンプ領域４と入力バンプ領域６との間にダミーバンプ領域は設けず、また、他方の側縁２ｂから入力バンプ領域６までの距離Ｂは５０μｍである。 [Example 6]
The IC chip according to Example 6 has an IC width W of 3.0 mm between the opposing side edges 2a and 2b of the mounting surface 2 and an IC length of 32 mm in the arrangement direction of the input / output bumps 3 and 5. . The distance A from one side edge 2a to the output bump region 4 is 125 μm, which is 4.2% of the IC width W (3.0 mm). In the IC chip according to the sixth embodiment, no dummy bump area is provided between the output bump area 4 and the input bump area 6, and the distance B from the other side edge 2b to the input bump area 6 is 50 μm. .
　［比較例１］
　比較例１に係るＩＣチップは、一方の側縁２ａから出力バンプ領域４までの距離Ａを５０μｍとした他は実施例１と同じ条件とした。比較例１における距離Ａは、ＩＣ幅Ｗ（１．５ｍｍ）に対して３．３％の距離となる。 [Comparative Example 1]
The IC chip according to Comparative Example 1 was the same as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 50 μm. The distance A in Comparative Example 1 is 3.3% of the IC width W (1.5 mm).
　［比較例２］
　比較例２に係るＩＣチップは、出力バンプ領域４と入力バンプ領域６との間にダミーバンプ領域Ｄを設けた他は、比較例１と同じ条件とした。ダミーバンプ領域Ｄは、ダミーバンプがＩＣチップの長さ方向に１列に配列されている。各ダミーバンプは、矩形状をなし（面積：１２５０μｍ２、幅：１２．５μｍ、長さ：１００μｍ）、１２７６個配列されている。ダミーバンプ列Ｄにおけるダミーバンプの全面積は、１５９５０００μｍ２である。ダミーバンプ領域Ｄの全面積は、３１９００００μｍ２（幅：３１９００μｍ、長さ：１００μｍ）である。 [Comparative Example 2]
The IC chip according to Comparative Example 2 was set to the same conditions as Comparative Example 1 except that a dummy bump region D was provided between the output bump region 4 and the input bump region 6. In the dummy bump area D, dummy bumps are arranged in a line in the length direction of the IC chip. Each dummy bump has a rectangular shape (area: 1250 μm 2 , width: 12.5 μm, length: 100 μm), and 1276 are arranged. The total area of the dummy bumps in the dummy bump row D is 1595000 μm 2 . The total area of the dummy bump region D is 319000 μm 2 (width: 31900 μm, length: 100 μm).
　これら実施例１～６、及び比較例１～２に係るＩＣチップを、異方性導電フィルム（商品名ＣＰ３６９３１‐１８ＡＪ：デクセリアルズ株式会社製）を介して回路基板に接続し、接続体サンプルを製造した。接続条件は、１５０℃、１３０ＭＰａ、５ｓｅｃである。各接続体サンプルについて、４端子法を用いて、出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａにおける導通抵抗を測定した。測定の結果、導通抵抗が１．０Ω以下の場合をＯＫとし、１．０Ωを超える場合をＮＧとした。測定結果を表１に示す。 The IC chips according to Examples 1 to 6 and Comparative Examples 1 to 2 are connected to a circuit board via an anisotropic conductive film (trade name CP36931-18AJ: manufactured by Dexerials Corporation) to manufacture a connected body sample. did. The connection conditions are 150 ° C., 130 MPa, and 5 seconds. About each connection body sample, the conduction resistance in the output bump row | line | column 3A, 3B, 3C and the input bump row | line | column 5A was measured using the 4-terminal method. As a result of the measurement, the case where the conduction resistance was 1.0Ω or less was determined as OK, and the case where the conduction resistance exceeded 1.0Ω was determined as NG. The measurement results are shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１に示すように、実施例１～６においては、出力バンプ列３Ａ、３Ｂ、３Ｃ及び入力バンプ列５Ａの全てにおいて導通抵抗が１．０Ω以下となり、一方の側縁２ａ側に配列されている出力バンプ列３Ａの各出力バンプ３においても十分な押圧力で押し込むことができたことが分かる。これは、実施例１～６においては、一方の側縁２ａから出力バンプ領域４までの距離ＡをＩＣ幅Ｗの４％以上としたことから、出力バンプ領域４の幅方向に亘る圧力勾配が均されたことによる。 As shown in Table 1, in Examples 1 to 6, all of the output bump rows 3A, 3B, and 3C and the input bump row 5A have a conduction resistance of 1.0Ω or less, and are arranged on one side edge 2a side. It can be seen that each output bump 3 in the output bump row 3A could be pushed in with a sufficient pressing force. In the first to sixth embodiments, the distance A from one side edge 2a to the output bump region 4 is set to 4% or more of the IC width W, so that the pressure gradient in the width direction of the output bump region 4 is increased. It depends on being averaged.
　一方、比較例１では、出力バンプ列３Ａ、３Ｂにおける導通抵抗が高くなった。これは、一方の側縁２ａから出力バンプ領域４までの距離ＡがＩＣ幅Ｗの３．３％であったことから、外側の出力バンプ列にいくほど熱圧着ヘッドの押圧力が弱まる圧力勾配となったことによる。これより、一方の側縁２ａから出力バンプ領域４までの距離ＡをＩＣ幅Ｗの４％以上設けることが好ましいことがわかる。 On the other hand, in Comparative Example 1, the conduction resistance in the output bump rows 3A and 3B was high. This is because the distance A from one side edge 2a to the output bump region 4 is 3.3% of the IC width W, and therefore the pressure gradient at which the pressing force of the thermocompression bonding head decreases toward the outer output bump row. Because it became. From this, it can be seen that it is preferable to provide a distance A from one side edge 2a to the output bump region 4 of 4% or more of the IC width W.
　また、比較例２では、出力バンプ領域４と入力バンプ領域６との間にダミーバンプ領域Ｄを設けたが、出力バンプ列３Ａ、３Ｂにおける導通抵抗が高くなった。これより、一方の側縁２ａから出力バンプ領域４までの距離ＡがＩＣ幅Ｗの３．３％の場合、ダミーバンプを形成することによっては、外側のバンプ列における導通性を改善するほどの圧力勾配を得ることは困難であることが分かる。 In Comparative Example 2, the dummy bump region D was provided between the output bump region 4 and the input bump region 6, but the conduction resistance in the output bump rows 3A and 3B was high. Accordingly, when the distance A from the one side edge 2a to the output bump region 4 is 3.3% of the IC width W, the pressure that can improve the conductivity in the outer bump row may be formed by forming a dummy bump. It can be seen that it is difficult to obtain a gradient.
　なお、実施例５，６より、一方の側縁２ａから出力バンプ領域４までの距離ＡをＩＣ幅Ｗの４％以上とすることにより、ＩＣ幅が広がっても外側のバンプ列における導通性を改善できる圧力勾配が得られることが分かる。 From Examples 5 and 6, by setting the distance A from one side edge 2a to the output bump region 4 to be 4% or more of the IC width W, the continuity in the outer bump row is improved even if the IC width is widened. It can be seen that a pressure gradient that can be improved is obtained.
　[第２の実施の形態]
　次いで、本発明の第２の実施の形態について説明する。以下の説明において、上述した第１の実施の形態に係る部材と同じ部材については、同一の符号を付してその詳細を省略する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described. In the following description, the same members as those according to the first embodiment described above are denoted by the same reference numerals, and the details thereof are omitted.
　［電子部品、及び接続体］
　本発明が適用された電子部品は、接着剤を介して回路基板上に配置され、熱圧着ヘッドで加圧されることにより回路基板上に接続される電子部品であり、例えばドライバＩＣやシステムＬＳＩ等のパッケージ化された電子部品である。以下では、電子部品として、ＩＣチップ１を例に説明する。 [Electronic components and connectors]
An electronic component to which the present invention is applied is an electronic component that is arranged on a circuit board via an adhesive and is connected to the circuit board by being pressed by a thermocompression bonding head. For example, a driver IC or a system LSI Etc. are packaged electronic components. Hereinafter, the IC chip 1 will be described as an example of the electronic component.
　図１に示すように、ＩＣチップ１の回路基板上に接続される実装面２は、略矩形状をなし、長さ方向となる相対向する一対の側縁２ａ，２ｂに沿って、出力バンプ３が配列された出力バンプ領域４及び入力バンプ５が配列された入力バンプ領域６が形成されている。ＩＣチップ１は、出力バンプ領域４が実装面２の一方の側縁２ａ側に形成され、入力バンプ領域６が実装面２の他方の側縁２ｂ側に形成されている。これにより、ＩＣチップ１は、実装面２の幅方向に亘って出力バンプ領域４と入力バンプ領域６とが離間して形成されている。 As shown in FIG. 1, the mounting surface 2 connected to the circuit board of the IC chip 1 has a substantially rectangular shape, and along the pair of side edges 2a and 2b facing each other in the length direction, output bumps are formed. An output bump area 4 in which 3 is arranged and an input bump area 6 in which input bumps 5 are arranged are formed. In the IC chip 1, the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2. Thus, the IC chip 1 is formed such that the output bump area 4 and the input bump area 6 are separated from each other in the width direction of the mounting surface 2.
　出力バンプ領域４には、例えば同一形状に形成された複数の出力バンプ３が、実装面２の長手方向に沿って３列で千鳥状に配列されている。また、入力バンプ領域６には、例えば同一形状に形成された複数の入力バンプ５が、実装面２の長手方向に沿って１列で配列されている。なお、入力バンプ５は、出力バンプ３よりも大きく形成される。これにより、ＩＣチップ１は、出力バンプ領域４と入力バンプ領域６とが面積差を有するとともに、実装面２において非対称に配置されている。なお、出力バンプ領域４に配列されている各出力バンプ３は、それぞれ同一の寸法で形成されることが好ましい。同様に、入力バンプ領域６に配列されている各入力バンプ５は、それぞれ同一の寸法で形成されることが好ましい。 In the output bump area 4, for example, a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2. In the input bump area 6, for example, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2. The input bump 5 is formed larger than the output bump 3. Thus, in the IC chip 1, the output bump region 4 and the input bump region 6 have an area difference and are disposed asymmetrically on the mounting surface 2. The output bumps 3 arranged in the output bump region 4 are preferably formed with the same dimensions. Similarly, the input bumps 5 arranged in the input bump area 6 are preferably formed with the same dimensions.
　図５は、図１に示す電子部品の幅方向の実装面を示す断面図である。図５に示すように、電子部品としてのＩＣチップは、第１の側縁２ａに沿ってバンプ列が形成された矩形状の第１のバンプ領域としての出力バンプ領域４と、第１の側縁２ａに対向する第２の側縁２ｂに沿ってバンプ列が形成された矩形状の第２のバンプ領域としての入力バンプ領域６とを備える。 FIG. 5 is a sectional view showing a mounting surface in the width direction of the electronic component shown in FIG. As shown in FIG. 5, the IC chip as the electronic component includes an output bump area 4 as a first bump area having a rectangular shape in which a bump row is formed along the first side edge 2a, and a first side. And an input bump region 6 as a rectangular second bump region in which a bump row is formed along the second side edge 2b facing the edge 2a.
　ここで、第１のバンプ領域の幅方向の距離αは、第２のバンプ領域の幅方向の距離βよりも大きい（α＞β）。また、第１の側縁２ａと第２の側縁２ｂとの距離（ＩＣ幅：Ｗ）に対する第１のバンプ領域の幅方向の距離αと第２のバンプ領域の幅方向の距離βとのバンプ領域幅差（α－β）の割合は、５％～３０％であることが好ましく、１０％～２５％であることがより好ましい。バンプ領域幅差（α－β）が小さすぎる場合、バンプ領域外側間中点を移動させる必要性が低く、バンプ領域幅差（α－β）が大きすぎる場合、バンプ領域外側間中点の移動だけでは、熱圧着ヘッドによる圧力差を解消し接続信頼性を向上させることは困難となる。 Here, the distance α in the width direction of the first bump area is larger than the distance β in the width direction of the second bump area (α> β). Further, a distance α in the width direction of the first bump region and a distance β in the width direction of the second bump region with respect to the distance (IC width: W) between the first side edge 2a and the second side edge 2b. The ratio of the bump area width difference (α−β) is preferably 5% to 30%, and more preferably 10% to 25%. When the bump area width difference (α-β) is too small, it is not necessary to move the midpoint between the bump areas outside. When the bump area width difference (α-β) is too large, the midpoint between the bump areas outside is moved. It is difficult to eliminate the pressure difference due to the thermocompression bonding head and improve the connection reliability.
　また、第１のバンプ領域の幅方向の外側と第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点（Ａ＋Ｌ２／２　ｏｒ　Ｂ＋Ｌ２／２）は、第１の側縁２ａと第２の側縁２ｂとの間の側縁間中点（Ｗ／２）より、第２の側縁２ｂ側に存在する。すなわち、第１の側縁２ａから第１のバンプ領域までの距離Ａと、第２の側縁２ｂから第２のバンプ領域までの距離Ｂとの関係は、Ａ＞Ｂである。 In addition, the midpoint between the outer sides of the bump region between the outer side in the width direction of the first bump region and the outer side in the width direction of the second bump region (A + L2 / 2 or B + L2 / 2) is the first side edge 2a. It exists on the second side edge 2b side from the midpoint between the side edges (W / 2) between the first side edge 2b and the second side edge 2b. That is, the relationship between the distance A from the first side edge 2a to the first bump area and the distance B from the second side edge 2b to the second bump area is A> B.
　これにより、ＩＣチップ１は、図２に示すように熱圧着ヘッド１７によって回路基板１４上に加熱押圧された際に、押圧力が出力バンプ領域４の内側に偏在することを防止し、一方の側縁２ａ側に配列されている出力パンプ３に対しても適正な押圧力を掛けることができる。 Thereby, the IC chip 1 prevents the pressing force from being unevenly distributed inside the output bump region 4 when it is heated and pressed on the circuit board 14 by the thermocompression bonding head 17 as shown in FIG. Appropriate pressing force can be applied to the output pumps 3 arranged on the side edge 2a side.
　また、側縁間中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２　ｏｒ　Ｂ＋Ｌ２／２）までの距離（Δ）、すなわち（Ａ－Ｂ）／２が大きいほど、出力バンプ領域４の幅方向に亘って形成される圧力勾配が緩やかに均される。具体的な距離（Δ）としては、第１の側縁２ａと第２の側縁２ｂとの距離（Ｗ）の０．１％～５．０％であることが好ましく、０．３％～３．５％であることがより好ましい。これにより、図２に示すように熱圧着ヘッド１７によって実装面２の全面に対して圧力を掛けた際に、一方の側縁２ａ側において熱圧着ヘッド１７による押圧力が不足する事態を防止することができる。よって、ＩＣチップ１は、当該一方の側縁２ａ側の出力バンプ３においても回路基板１４に形成された電極端子１５との間で確実に導電性粒子を挟持し、導通性を確保することができる。 Also, the larger the distance (Δ) from the midpoint between the side edges (W / 2) to the midpoint between the bump areas outside (A + L2 / 2 or B + L2 / 2), that is, (AB) / 2, the larger the output bump area The pressure gradient formed over the width direction of 4 is gently leveled. The specific distance (Δ) is preferably 0.1% to 5.0% of the distance (W) between the first side edge 2a and the second side edge 2b, preferably 0.3% to More preferably, it is 3.5%. As a result, as shown in FIG. 2, when pressure is applied to the entire mounting surface 2 by the thermocompression bonding head 17, a situation in which the pressing force by the thermocompression bonding head 17 is insufficient on one side edge 2a side is prevented. be able to. Therefore, the IC chip 1 can reliably hold the conductive particles between the output bumps 3 on the one side edge 2a side and the electrode terminals 15 formed on the circuit board 14 to ensure conductivity. it can.
　なお、ＩＣチップ１の実装面２の入出力バンプの構成は、適宜設計することができる。ＩＣチップ１は、上述したように出力バンプ３を幅方向に複数配列することにより相対的に大面積化させた出力バンプ領域４を形成したが、反対に、入力バンプ５を幅方向に複数配列することにより相対的に入力バンプ領域６を大面積化させてもよい。 The configuration of the input / output bumps on the mounting surface 2 of the IC chip 1 can be designed as appropriate. As described above, the IC chip 1 forms the output bump region 4 having a relatively large area by arranging a plurality of output bumps 3 in the width direction. Conversely, a plurality of input bumps 5 are arranged in the width direction. By doing so, the input bump region 6 may be relatively enlarged.
　また、図３に示すように、ＩＣチップ１は、出力バンプ領域４と入力バンプ領域６との間に、信号等の入出力には使用しないいわゆるダミーバンプ１８が配列されたダミーバンプ領域１９を適宜設けてもよい。 As shown in FIG. 3, the IC chip 1 appropriately includes a dummy bump area 19 in which so-called dummy bumps 18 that are not used for input / output of signals and the like are arranged between the output bump area 4 and the input bump area 6. May be.
　［接着剤］
　ＩＣチップ１を回路基板１４に接続する接着剤としては、図４に示すように、上述した異方性導電フィルム１０（ＡＣＦ：Anisotropic Conductive Film）を好適に用いることができる。 [adhesive]
As an adhesive for connecting the IC chip 1 to the circuit board 14, the above-described anisotropic conductive film 10 (ACF: Anisotropic Conductive Film) can be suitably used as shown in FIG.
　［接続体の製造方法、及び接続方法］
　次いで、回路基板１４にＩＣチップ１を接続する接続方法について説明する。先ず、回路基板１４の電極端子１５が形成された実装部上に異方性導電フィルム１０を仮貼りする。次いで、この回路基板１４を接続装置のステージ上に載置し、回路基板１４の実装部上に異方性導電フィルム１０を介してＩＣチップ１を配置する。 [Manufacturing method of connecting body and connecting method]
Next, a connection method for connecting the IC chip 1 to the circuit board 14 will be described. First, the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 on which the electrode terminals 15 are formed. Next, the circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 via the anisotropic conductive film 10.
　次いで、バインダー樹脂層１３を硬化させる所定の温度に加熱された熱圧着ヘッド１７によって、所定の圧力、時間でＩＣチップ１上から熱加圧する。これにより、異方性導電フィルム１０のバインダー樹脂層１３は流動性を示し、ＩＣチップ１の実装面２と回路基板１４の実装部の間から流出するとともに、バインダー樹脂層１３中の導電性粒子１２は、ＩＣチップ１の出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間に挟持されて押し潰される。 Next, the thermocompression bonding head 17 heated to a predetermined temperature for curing the binder resin layer 13 is hot-pressed from above the IC chip 1 at a predetermined pressure and time. Thereby, the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the conductive particles in the binder resin layer 13. 12 is sandwiched between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and is crushed.
　その結果、出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間で導電性粒子１２を挟持することにより電気的に接続され、この状態で熱圧着ヘッド１７によって加熱されたバインダー樹脂が硬化する。したがって、ＩＣチップ１は、当該一方の側縁２ａ側の出力バンプ３においても回路基板１４に形成された電極端子１５との間で確実に導通性を確保することができる。 As a result, the binder resin electrically connected by sandwiching the conductive particles 12 between the output bumps 3 and 5 and the electrode terminals 15 of the circuit board 14 and heated in this state by the thermocompression bonding head 17. Is cured. Therefore, the IC chip 1 can reliably ensure electrical continuity with the electrode terminal 15 formed on the circuit board 14 also in the output bump 3 on the one side edge 2a side.
　出力バンプ３及び入力バンプ５と電極端子１５との間にない導電性粒子１２は、バインダー樹脂に分散されており、電気的に絶縁した状態を維持している。これにより、ＩＣチップ１の出力バンプ３及び入力バンプ５と回路基板１４の電極端子１５との間のみで電気的導通が図られる。なお、バインダー樹脂として、ラジカル重合反応系の速硬化タイプのものを用いることで、短い加熱時間によってもバインダー樹脂を速硬化させることができる。また、異方性導電フィルム１０としては、熱硬化型に限らず、加圧接続を行うものであれば、光硬化型もしくは光熱併用型の接着剤を用いてもよい。 The conductive particles 12 that are not between the output bumps 3 and the input bumps 5 and the electrode terminals 15 are dispersed in the binder resin and maintain an electrically insulated state. Thereby, electrical conduction is achieved only between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14. In addition, by using a fast curing type radical polymerization reaction system as the binder resin, the binder resin can be rapidly cured even with a short heating time. Further, the anisotropic conductive film 10 is not limited to the thermosetting type, and may be a photo-curing type or a photo-heat combined type adhesive as long as it performs pressure connection.
第２の実施例Second embodiment
　次いで、本発明の第２の実施例について説明する。第２の実施例では、第１のバンプ領域としても出力バンプ領域と、第２のバンプ領域としての入力バンプ領域とを有するＩＣチップを用い、異方性導電フィルムを介して回路基板上に接続した接続体サンプルを製造した。実施例及び比較例に係るＩＣチップは、ＩＣ幅及び実装面の一方の側縁２ａから出力バンプ領域までの距離Ａを異ならせ、それぞれ接続体サンプルにおける出力バンプ及び入力バンプの導通抵抗値を測定、評価した。 Next, a second embodiment of the present invention will be described. In the second embodiment, an IC chip having an output bump area and an input bump area as the second bump area is used as the first bump area, and connected to the circuit board through an anisotropic conductive film. A connected sample was manufactured. The IC chips according to the example and the comparative example are different in the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region, and measure the conduction resistance values of the output bump and the input bump in the connection sample, respectively. ,evaluated.
　［ＩＣチップ］
　ＩＣチップは、略矩形状の実装面２の長さ方向となる相対向する一対の側縁２ａ，２ｂに沿って、出力バンプ３が配列された出力バンプ領域４及び入力バンプ５が配列された入力バンプ領域６が形成されている。ＩＣチップ１は、出力バンプ領域４が実装面２の一方の側縁２ａ側に形成され、入力バンプ領域６が実装面２の他方の側縁２ｂ側に形成されている。これにより、ＩＣチップ１は、実装面の幅方向に亘って出力バンプ領域４と入力バンプ領域６とが離間して形成されている（図１、図５参照）。 [IC chip]
The IC chip has an output bump area 4 in which output bumps 3 are arranged and an input bump 5 are arranged along a pair of side edges 2a and 2b facing each other in the length direction of the substantially rectangular mounting surface 2. An input bump area 6 is formed. In the IC chip 1, the output bump region 4 is formed on the side edge 2 a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge 2 b side of the mounting surface 2. Thereby, the IC chip 1 is formed with the output bump area 4 and the input bump area 6 separated from each other in the width direction of the mounting surface (see FIGS. 1 and 5).
　出力バンプ領域４には、同一形状に形成された複数の出力バンプ３が、実装面２の長手方向に沿って３列で千鳥状に配列されている。出力バンプ領域４に形成されている出力バンプを列毎に分け、一方の側縁２ａ側から順に出力バンプ列３Ａ、３Ｂ、３Ｃとする。 In the output bump area 4, a plurality of output bumps 3 formed in the same shape are arranged in a staggered manner in three rows along the longitudinal direction of the mounting surface 2. The output bumps formed in the output bump area 4 are divided into columns, and are designated as output bump columns 3A, 3B, 3C in order from one side edge 2a side.
　また、入力バンプ領域６には、同一形状に形成された複数の入力バンプ５が、実装面２の長手方向に沿って１列で配列されている。入力バンプ領域６に形成されている１列の入力バンプ列を、入力バンプ列５Ａとする。 In the input bump area 6, a plurality of input bumps 5 formed in the same shape are arranged in a line along the longitudinal direction of the mounting surface 2. One input bump row formed in the input bump area 6 is defined as an input bump row 5A.
　［導通抵抗の評価］
　ＩＣチップを、異方性導電フィルム（商品名ＣＰ３６９３１‐１８ＡＪ：デクセリアルズ株式会社製）を介して回路基板に接続し、接続体サンプルを作製した。接続条件は、１５０℃、１３０ＭＰａ、５ｓｅｃとした。各接続体サンプルについて、４端子法を用いて、出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａにおける導通抵抗を測定した。測定の結果、全てのバンプ列の導通抵抗が１．０Ω以下の場合を「ＯＫ」とし、１以上のバンプ列が１．０Ωを超える場合をＮＧとした。 [Evaluation of conduction resistance]
The IC chip was connected to the circuit board via an anisotropic conductive film (trade name CP36931-18AJ: manufactured by Dexerials Corporation) to prepare a connected body sample. The connection conditions were 150 ° C., 130 MPa, and 5 seconds. About each connection body sample, the conduction resistance in the output bump row | line | column 3A, 3B, 3C and the input bump row | line | column 5A was measured using the 4-terminal method. As a result of the measurement, the case where the conduction resistance of all the bump rows was 1.0Ω or less was designated as “OK”, and the case where one or more bump rows exceeded 1.0Ω was designated as NG.
　［実施例７］
　表２に示すように、ＩＣ幅Ｗが１５００μｍ、出力バンプ領域４の一方の側縁２ａからの距離Ａが６０μｍ、出力バンプ領域４の幅αが３８５μｍ、入力バンプ領域６の他方の側縁２ｂからの距離Ｂが５０μｍ、入力バンプ領域６の幅βが８０μｍ、及びバンプ領域幅差のＩＣ幅Ｗに対する割合が２０．３％のＩＣチップを準備した。 [Example 7]
As shown in Table 2, the IC width W is 1500 μm, the distance A from one side edge 2a of the output bump region 4 is 60 μm, the width α of the output bump region 4 is 385 μm, and the other side edge 2b of the input bump region 6 An IC chip having a distance B of 50 μm, a width β of the input bump region 6 of 80 μm, and a ratio of the bump region width difference to the IC width W of 20.3% was prepared.
　出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は９２５μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１３９０μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、５．０μｍであり、ＩＣ幅（Ｗ）に対する割合は０．３３％であった。 The distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 925 μm. The distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1390 μm. The distance (Δ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 5.0 μm, and the ratio to the IC width (W) was 0.33%. .
　実施例７のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ１．０Ω、０．９Ω、０．４Ω、０．１Ωであり、ＯＫの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection sample to which the IC chip of Example 7 was connected were 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively. It was an OK evaluation.
　［実施例８］
　表２に示すように、出力バンプ領域４の一方の側縁２ａからの距離Ａを７５μｍとした以外は、実施例７と同様のＩＣチップを準備した。出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は９１０μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１３７５μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、１２．５μｍであり、ＩＣ幅（Ｗ）に対する割合は０．８３％であった。 [Example 8]
As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 75 μm. The distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 910 μm. The distance (L2) between the bump area outsides between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1375 μm. The distance (Δ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 12.5 μm, and the ratio to the IC width (W) was 0.83%. .
　実施例８のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ０．９Ω、０．８Ω、０．４Ω、０．１Ωであり、ＯＫの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection sample to which the IC chip of Example 8 was connected were 0.9Ω, 0.8Ω, 0.4Ω, and 0.1Ω, respectively. It was an OK evaluation.
　［実施例９］
　表２に示すように、出力バンプ領域４の一方の側縁２ａからの距離Ａを１５０μｍとした以外は、実施例７と同様のＩＣチップを準備した。出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は８３５μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１３００μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、５０．０μｍであり、ＩＣ幅（Ｗ）に対する割合は３．３３％であった。 [Example 9]
As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 150 μm. The distance between inner bump regions (L1) between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 835 μm. The distance (L2) between the bump regions outside between the outside in the width direction of the output bump region 4 and the outside in the width direction of the input bump region 6 was 1300 μm. The distance (Δ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 50.0 μm, and the ratio to the IC width (W) was 3.33%. .
　実施例９のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ０．９Ω、０．７Ω、０．５Ω、０．１Ωであり、ＯＫの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 9 was connected were 0.9Ω, 0.7Ω, 0.5Ω, and 0.1Ω, respectively. It was an OK evaluation.
　［実施例１０］
　表２に示すように、ＩＣ幅Ｗが２０００μｍ、出力バンプ領域４の一方の側縁２ａからの距離Ａが６３μｍ、出力バンプ領域４の幅αが３８５μｍ、入力バンプ領域６の他方の側縁２ｂからの距離Ｂが５０μｍ、入力バンプ領域６の幅βが８０μｍ、及びバンプ領域幅差のＩＣ幅Ｗに対する割合が１５．３％のＩＣチップを準備した。 [Example 10]
As shown in Table 2, the IC width W is 2000 μm, the distance A from one side edge 2 a of the output bump region 4 is 63 μm, the width α of the output bump region 4 is 385 μm, and the other side edge 2 b of the input bump region 6. An IC chip was prepared in which the distance B from the substrate was 50 μm, the width β of the input bump region 6 was 80 μm, and the ratio of the bump region width difference to the IC width W was 15.3%.
　出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は１４２２μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１８８７μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、６．５μｍであり、ＩＣ幅（Ｗ）に対する割合は０．３３％であった。 The distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 1422 μm. The distance (L2) between the bump regions outside between the outside in the width direction of the output bump region 4 and the outside in the width direction of the input bump region 6 was 1887 μm. The distance (Δ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 6.5 μm, and the ratio to the IC width (W) was 0.33%. .
　実施例１０のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ１．０Ω、０．９Ω、０．４Ω、０．１Ωであり、ＯＫの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 10 was connected were 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively. It was an OK evaluation.
　［実施例１１］
　表２に示すように、ＩＣ幅Ｗが３０００μｍ、出力バンプ領域４の一方の側縁２ａからの距離Ａが７０μｍ、出力バンプ領域４の幅αが３８５μｍ、入力バンプ領域６の他方の側縁２ｂからの距離Ｂが５０μｍ、入力バンプ領域６の幅βが８０μｍ、及びバンプ領域幅差のＩＣ幅Ｗに対する割合が１０．２％のＩＣチップを準備した。 [Example 11]
As shown in Table 2, the IC width W is 3000 μm, the distance A from one side edge 2a of the output bump region 4 is 70 μm, the width α of the output bump region 4 is 385 μm, and the other side edge 2b of the input bump region 6 An IC chip having a distance B of 50 μm, a width β of the input bump area 6 of 80 μm, and a ratio of the bump area width difference to the IC width W of 10.2% was prepared.
　出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は２４１５μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は２８８０μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、１０．０μｍであり、ＩＣ幅（Ｗ）に対する割合は０．３３％であった。 The distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 2415 μm. The distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 2880 μm. The distance (Δ) from the IC width midpoint (W / 2) to the midpoint between the bump area outside (A + L2 / 2) was 10.0 μm, and the ratio to the IC width (W) was 0.33%. .
　実施例１１のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ１．０Ω、０．９Ω、０．４Ω、０．１Ωであり、ＯＫの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection body sample to which the IC chip of Example 11 was connected were 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively. It was an OK evaluation.
　［比較例３］
　表２に示すように、出力バンプ領域４の一方の側縁２ａからの距離Ａを５０μｍとし、ダミーバンプ領域を設けた以外は、実施例７と同様のＩＣチップを準備した。ダミーバンプ領域は、出力バンプ領域４と入力バンプ領域６との間に設けられ、ダミーバンプがＩＣチップの長さ方向に１列に配列されている。なお、ダミーバンプ列は、入力バンプ列５と同様である。 [Comparative Example 3]
As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was 50 μm and a dummy bump region was provided. The dummy bump area is provided between the output bump area 4 and the input bump area 6, and the dummy bumps are arranged in a line in the length direction of the IC chip. The dummy bump row is the same as the input bump row 5.
　出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は９３５μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１４００μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、０μｍであり、ＩＣ幅（Ｗ）に対する割合は０％であった。 The distance (L1) between the bump region inner sides between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 935 μm. The distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1400 μm. The distance (Δ) from the midpoint of the IC width (W / 2) to the midpoint between the bump area outsides (A + L2 / 2) was 0 μm, and the ratio to the IC width (W) was 0%.
　比較例３のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ２．３Ω、１．２Ω、０．５Ω、０．１Ωであり、ＮＧの評価であった。 The measurement results of the conduction resistances of the output bump rows 3A, 3B, 3C and the input bump row 5A in the connection sample to which the IC chip of Comparative Example 3 is connected are 2.3Ω, 1.2Ω, 0.5Ω, and 0.1Ω, respectively. It was NG evaluation.
　［比較例４］
　表２に示すように、出力バンプ領域４の一方の側縁２ａからの距離Ａを５０μｍとした以外は、実施例７と同様のＩＣチップを準備した。出力バンプ領域４の幅方向の内側と入力バンプ領域６の幅方向の内側との間のバンプ領域内側間距離（Ｌ１）は９３５μｍであった。出力バンプ領域４の幅方向の外側と入力バンプ領域６の幅方向の外側との間のバンプ領域外側間距離（Ｌ２）は１４００μｍであった。ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）は、０μｍであり、ＩＣ幅（Ｗ）に対する割合は０％であった。 [Comparative Example 4]
As shown in Table 2, an IC chip similar to that of Example 7 was prepared except that the distance A from one side edge 2a of the output bump region 4 was set to 50 μm. The distance between inner bump regions (L1) between the inner side in the width direction of the output bump region 4 and the inner side in the width direction of the input bump region 6 was 935 μm. The distance (L2) between the bump areas outside between the outside in the width direction of the output bump area 4 and the outside in the width direction of the input bump area 6 was 1400 μm. The distance (Δ) from the midpoint of the IC width (W / 2) to the midpoint between the bump area outsides (A + L2 / 2) was 0 μm, and the ratio to the IC width (W) was 0%.
　比較例４のＩＣチップを接続した接続体サンプルにおける出力バンプ列３Ａ、３Ｂ、３Ｃ、入力バンプ列５Ａの導通抵抗の測定結果は、それぞれ３．０Ω、１．７Ω、０．４Ω、０．１Ωであり、ＮＧの評価であった。 The measurement results of the conduction resistances of the output bump arrays 3A, 3B, 3C and the input bump array 5A in the connection sample to which the IC chip of Comparative Example 4 is connected are 3.0Ω, 1.7Ω, 0.4Ω, and 0.1Ω, respectively. It was NG evaluation.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　比較例３のようにダミーバンプを設けた場合、出力バンプ列３Ａ、３Ｂにおける導通抵抗が高く、外側のバンプ列における導通性を改善するほどの圧力勾配を得ることは困難であった。また、比較例４のようにダミーバンプを設けなかった場合、出力バンプ列３Ａ、３Ｂにおける導通抵抗が比較例３よりも高くなってしまった。 When dummy bumps were provided as in Comparative Example 3, the conduction resistance in the output bump rows 3A and 3B was high, and it was difficult to obtain a pressure gradient that improved the conductivity in the outer bump row. Further, when no dummy bump was provided as in Comparative Example 4, the conduction resistance in the output bump rows 3A and 3B was higher than that in Comparative Example 3.
　一方、実施例７～１１のように、ＩＣ幅中点（Ｗ／２）からバンプ領域外側間中点（Ａ＋Ｌ２／２）までの距離（Δ）をＩＣ幅Ｗの０．３％～３．５％とした場合、出力バンプ列３Ａ、３Ｂ、３Ｃ及び入力バンプ列５Ａの全てにおいて導通抵抗が１．０Ω以下となった。これは、出力バンプ領域４の幅方向に亘る圧力勾配が均され、出力バンプ列３Ａの各出力バンプ３においても十分な押圧力で押し込むことができたからである。 On the other hand, as in Examples 7 to 11, the distance (Δ) from the midpoint of the IC width (W / 2) to the midpoint between the bump areas outside (A + L2 / 2) is set to 0.3% to 3.3% of the IC width W. In the case of 5%, the conduction resistance in all of the output bump rows 3A, 3B, 3C and the input bump row 5A was 1.0Ω or less. This is because the pressure gradient in the width direction of the output bump region 4 is leveled, and each output bump 3 in the output bump row 3A can be pushed in with a sufficient pressing force.
１　ＩＣチップ、２　実装面、２ａ　一方の側縁、２ｂ　他方の側縁、３　出力バンプ、４　出力バンプ領域、５　入力バンプ、６　入力バンプ領域、１０　異方性導電フィルム、１１　剥離フィルム、１２　導電性粒子、１３　バインダー樹脂層、１４　回路基板、１５　電極端子、１７　熱圧着ヘッド 1 IC chip, 2 mounting surface, 2a one side edge, 2b other side edge, 3 output bump, 4 output bump area, 5 input bump, 6 input bump area, 10 anisotropic conductive film, 11 release film, 12 Conductive particles, 13 binder resin layer, 14 circuit board, 15 electrode terminals, 17 thermocompression bonding head

Claims (18)

  1. 　相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、
    　上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ非対称に配置され、
    　上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されている電子部品。     An output bump area in which output bumps are arranged adjacent to one side of a pair of opposite side edges is provided, and an input bump area in which input bumps are arranged adjacent to the other side of the pair of side edges is provided. And
    The output bump area and the input bump area are arranged in different areas and asymmetrically,
    One of the output bump area or the input bump area, which has a relatively large area, is inward from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. Electronic components that are formed.
  2. 　出力バンプ領域が、上記一対の側縁間の幅に対して４％以上の距離だけ、上記一方の側縁から内側に形成されている請求項１記載の電子部品。 2. The electronic component according to claim 1, wherein the output bump region is formed inwardly from the one side edge by a distance of 4% or more with respect to the width between the pair of side edges.
  3. 　上記一方の側縁から上記出力バンプ領域までの距離が、上記他方の側縁から上記入力バンプ領域までの距離よりも長い請求項２記載の電子部品。 3. The electronic component according to claim 2, wherein a distance from the one side edge to the output bump area is longer than a distance from the other side edge to the input bump area.
  4. 　入力バンプ領域が、上記一対の側縁間の幅に対して４％以上の距離だけ、上記他方の側縁から内側に形成されている請求項１記載の電子部品。 2. The electronic component according to claim 1, wherein the input bump region is formed inward from the other side edge by a distance of 4% or more with respect to a width between the pair of side edges.
  5. 　上記他方の側縁から上記入力バンプ領域までの距離が、上記一方の側縁から上記出力バンプ領域までの距離よりも長い請求項４記載の電子部品。 5. The electronic component according to claim 4, wherein a distance from the other side edge to the input bump area is longer than a distance from the one side edge to the output bump area.
  6. 　上記電子部品の上記実装面には、上記入力バンプ領域及び上記出力バンプ領域の間に、ダミーバンプが形成されている請求項１～５のいずれか１項に記載の電子部品。 6. The electronic component according to claim 1, wherein dummy bumps are formed on the mounting surface of the electronic component between the input bump region and the output bump region.
  7. 　上記電子部品は、ＩＣチップである請求項１～６のいずれか１項に記載の電子部品。 The electronic component according to any one of claims 1 to 6, wherein the electronic component is an IC chip.
  8. 　電子部品が接着剤を介して回路基板上に配置され、加圧ツールで加圧されることにより、上記電子部品が上記回路基板上に接続された接続体において、
    　上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、
    　上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、
    　上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されている接続体。     In the connection body in which the electronic component is arranged on the circuit board via an adhesive and pressed by a pressure tool, the electronic component is connected to the circuit board.
    The mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of a pair of side edges facing each other, and on the other side of the pair of side edges. An input bump area in which input bumps are arranged adjacent to each other is provided,
    The output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface,
    One of the output bump area or the input bump area, which has a relatively large area, is inward from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. Connected body formed.
  9. 　接着剤を介して回路基板上に電子部品を配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する接続体の製造方法において、
    　上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、
    　上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、
    　上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されている接続体の製造方法。     In the method of manufacturing a connection body, in which an electronic component is arranged on a circuit board via an adhesive, and the electronic component is connected to the circuit board by applying pressure with a pressure tool.
    The mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of a pair of side edges facing each other, and on the other side of the pair of side edges. An input bump area in which input bumps are arranged adjacent to each other is provided,
    The output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface,
    One of the output bump area or the input bump area, which has a relatively large area, is inward from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. A method for manufacturing a formed connection body.
  10. 　接着剤を介して回路基板上に電子部品を配置し、加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する電子部品の接続方法において、
    　上記電子部品の上記回路基板への実装面には、相対向する一対の側縁の一方側に近接して出力バンプが配列された出力バンプ領域が設けられ、上記一対の側縁の他方側に近接して入力バンプが配列された入力バンプ領域が設けられ、
    　上記出力バンプ領域及び上記入力バンプ領域は、異なる面積で、かつ上記実装面において非対称に配置され、
    　上記出力バンプ領域又は上記入力バンプ領域のうち、相対的に大面積である一方は、上記一対の側縁間の幅の４％以上の距離だけ、近接する上記一方又は他方の側縁から内側に形成されている電子部品の接続方法。     In the electronic component connecting method of placing the electronic component on the circuit board via an adhesive and connecting the electronic component on the circuit board by applying pressure with a pressure tool,
    The mounting surface of the electronic component on the circuit board is provided with an output bump area in which output bumps are arranged adjacent to one side of a pair of side edges facing each other, and on the other side of the pair of side edges. An input bump area in which input bumps are arranged adjacent to each other is provided,
    The output bump area and the input bump area are arranged in different areas and asymmetrically on the mounting surface,
    One of the output bump area or the input bump area, which has a relatively large area, is inward from the adjacent one or other side edge by a distance of 4% or more of the width between the pair of side edges. A method for connecting formed electronic components.
  11. 　第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、
    　前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、
    　前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、
    　前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品。     A rectangular first bump area in which a bump row is formed along the first side edge;
    A rectangular second bump region in which a bump row is formed along a second side edge facing the first side edge;
    The distance in the width direction of the first bump region is larger than the distance in the width direction of the second bump region,
    A midpoint between the outer sides of the first bump region and the outer side of the bump region between the outer side of the second bump region in the width direction is between the first side edge and the second side edge. An electronic component that is present on the second side edge side from the midpoint between the side edges.
  12. 　前記側縁間中点から前記バンプ領域外側間中点までの距離が、前記第１の側縁と前記第２の側縁との距離の０．１％～５．０％である請求項１１記載の電子部品。 The distance from the midpoint between the side edges to the midpoint between the bump region outer sides is 0.1% to 5.0% of the distance between the first side edge and the second side edge. The electronic component described.
  13. 　前記第１の側縁と前記第２の側縁との距離に対する前記第１のバンプ領域の幅方向の距離と前記第２のバンプ領域の幅方向の距離とのバンプ領域幅差の割合が、５％～３０％である請求項１１又は１２記載の電子部品。 The ratio of the bump area width difference between the distance in the width direction of the first bump area and the distance in the width direction of the second bump area with respect to the distance between the first side edge and the second side edge, The electronic component according to claim 11 or 12, which is 5% to 30%.
  14. 　上記電子部品の上記実装面には、上記入力バンプ領域及び上記出力バンプ領域の間に、ダミーバンプが形成されている請求項１１～１３のいずれか１項に記載の電子部品。 14. The electronic component according to claim 11, wherein dummy bumps are formed between the input bump region and the output bump region on the mounting surface of the electronic component.
  15. 　上記電子部品は、ＩＣチップである請求項１１～１４のいずれか１項に記載の電子部品。 The electronic component according to any one of claims 11 to 14, wherein the electronic component is an IC chip.
  16. 　第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品と、
    　前記回路部品が接着剤を介して接続された回路基板と
    　を備える接続体。     A rectangular first bump region in which a bump row is formed along the first side edge, and a rectangular shape in which a bump row is formed along the second side edge opposite to the first side edge. A distance in the width direction of the first bump area is greater than a distance in the width direction of the second bump area, and the outer side in the width direction of the first bump area and the second bump area. The midpoint between the bump areas outside between the second bump areas in the width direction is more than the midpoint between the side edges between the first side edge and the second side edge. Electronic components present on the side edges,
    A connection body comprising: a circuit board to which the circuit component is connected via an adhesive.
  17. 　第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品を、接着剤を介して回路基板上に配置し、
    　加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する接続体の製造方法。     A rectangular first bump region in which a bump row is formed along the first side edge, and a rectangular shape in which a bump row is formed along the second side edge opposite to the first side edge. A distance in the width direction of the first bump area is greater than a distance in the width direction of the second bump area, and the outer side in the width direction of the first bump area and the second bump area. The midpoint between the bump areas outside between the second bump areas in the width direction is more than the midpoint between the side edges between the first side edge and the second side edge. Place electronic components on the side edge side on the circuit board via adhesive,
    A method for manufacturing a connection body in which the electronic component is connected to the circuit board by applying pressure with a pressing tool.
  18. 　第１の側縁に沿ってバンプ列が形成された矩形状の第１のバンプ領域と、前記第１の側縁に対向する第２の側縁に沿ってバンプ列が形成された矩形状の第２のバンプ領域とを備え、前記第１のバンプ領域の幅方向の距離が、前記第２のバンプ領域の幅方向の距離よりも大きく、前記第１のバンプ領域の幅方向の外側と前記第２のバンプ領域の幅方向の外側との間のバンプ領域外側間中点が、前記第１の側縁と前記第２の側縁との間の側縁間中点より、前記第２の側縁側に存在する電子部品を、接着剤を介して回路基板上に配置し、
    　加圧ツールで加圧することにより上記電子部品を上記回路基板上に接続する電子部品の接続方法。     A rectangular first bump region in which a bump row is formed along the first side edge, and a rectangular shape in which a bump row is formed along the second side edge opposite to the first side edge. A distance in the width direction of the first bump area is greater than a distance in the width direction of the second bump area, and the outer side in the width direction of the first bump area and the second bump area. The midpoint between the bump areas outside between the second bump areas in the width direction is more than the midpoint between the side edges between the first side edge and the second side edge. Place electronic components on the side edge side on the circuit board via adhesive,
    An electronic component connection method for connecting the electronic component onto the circuit board by applying pressure with a pressurizing tool.
PCT/JP2014/080406 2013-12-20 2014-11-17 Electronic component, connector, connector production method, and electronic component connecting method WO2015093212A1 (en)

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