KR102419196B1 - Display device and driving method thereof - Google Patents

Abstract

Deterioration of the switching element is determined through one or more dummy pixels provided in the display panel, and the level of the gate signal output to the display panel is increased accordingly, thereby reducing the charging failure of the data signal charged in the pixel due to deterioration of the switching element. A display device capable of preventing it is provided.

Description

Display device and driving method thereof

The present invention relates to a display device, and more particularly, to a display device capable of improving the occurrence of non-uniformity in charging of pixels due to deterioration of a switching element of a display panel, and a method of driving the same.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Flat panel displays include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among them, the liquid crystal display displays an image by using the electrical and optical characteristics of the liquid crystal. Liquid crystals have different anisotropic properties, such as refractive index and dielectric constant, depending on the molecular major axis and minor axis directions, and molecular arrangement and optical properties can be easily adjusted. The liquid crystal display using this changes the arrangement direction of liquid crystal molecules according to the magnitude of the electric field and displays an image by adjusting the transmittance of light passing through the polarizing plate.

1 is a diagram schematically showing a part of a conventional liquid crystal display device.

As shown in FIG. 1 , the conventional liquid crystal display 1 includes a liquid crystal panel 10 , a gate driver 20 , and a data driver 30 . In addition, a control circuit (not shown) for controlling the operations of the gate driver 20 and the data driver 30 is further included.

In the liquid crystal panel 10, a plurality of gate lines GL and data lines DL cross each other to define a pixel area, and a thin film transistor TFT, a liquid crystal capacitor Clc and a storage capacitor Cst for each pixel area. A pixel P provided with is configured.

The gate driver 20 sequentially outputs a gate signal to each gate line GL of the liquid crystal panel 10 to turn on the thin film transistor TFT of each pixel P.

The data driver 30 charges the pixel electrode of each pixel P by outputting a data signal through the data line DL while the thin film transistor TFT of each pixel P is turned on by the gate signal. .

On the other hand, the thin film transistor TFT provided for each pixel P of the liquid crystal panel 10 has a characteristic change in which the threshold voltage Vth is shifted due to a high temperature environment or long-term driving. This threshold voltage shift prevents the channel region of the thin film transistor (TFT) from being fully saturated, thereby causing poor charging of the data signal charged in each pixel (P).

2 is a diagram illustrating an operation change according to a threshold voltage shift of a thin film transistor.

As shown in FIG. 2 , when the conventional liquid crystal display 1 is driven in a high temperature environment or for a long time, the thin film transistor TFT of each pixel P in the liquid crystal panel 10 is deteriorated and the threshold voltage is shifted. phenomenon occurs. This threshold voltage shift causes a charging failure of the data signal charged in each pixel (P).

For example, as shown in FIG. 2 , if the threshold voltage shift phenomenon does not occur in the thin film transistor TFT (A), the gate signal output from the gate driver 20, that is, the current by the gate high voltage VGH ( Is), the channel region of the thin film transistor (TFT) is sufficiently activated and turned on. Accordingly, the data signal provided from the data driver 30 is fully charged in each pixel P through the turned-on thin film transistor TFT.

However, when a threshold voltage shift phenomenon occurs in the thin film transistor TFT (B), the current Is' by the gate high voltage VGH output from the gate driver 20 is reduced, so that the thin film transistor TFT is turned on in a state in which the channel region of the Accordingly, the data signal provided from the data driver 30 is incompletely charged in each pixel P, which appears as a stain in the liquid crystal display 1, and thus the display quality is deteriorated.

The present invention provides a display device and a driving method thereof, which can prevent a defective charging of a data signal charged in a pixel by a deteriorated switching element by increasing the level of the gate signal according to the deterioration of the pixel of the display panel. there is

A display device of the present invention for achieving the above object includes a display panel, a compensator, a voltage generator, and a gate driver.

The display panel is disposed adjacent to the pixel and includes at least one dummy pixel connected to a dummy line and a feedback line.

The compensator compares the dummy signal provided to the dummy pixel through the dummy line with the feedback signal output from the dummy pixel through the feedback line, and outputs a control signal according to the result.

The voltage generator increases and outputs the level of the gate high voltage among the gate voltages according to the control signal.

The gate driver generates a gate signal according to the increased gate high voltage and outputs the generated gate signal to the display panel.

According to a method of driving a display device of the present invention for achieving the above object, the level of the gate high voltage is increased to increase the level of the gate signal according to a result of determining deterioration from one or more dummy pixels disposed on a display panel.

To this end, the method includes outputting a comparison signal by comparing a dummy signal provided to the dummy pixel with a feedback signal output through the dummy pixel during the previous frame operation of the display panel.

Then, during a current frame operation of the display panel, outputting a gate high voltage whose level is increased according to the comparison signal, and thereby increasing the level of the gate signal.

In the display device of the present invention, deterioration of a switching element is determined from at least one dummy pixel disposed on the display panel, and the level of the gate signal outputted to the display panel is increased accordingly, so that each pixel of the display panel is provided. Even if the switching element is deteriorated, the channel region can be sufficiently activated. Accordingly, it is possible to prevent defective charging of the data signal charged in each pixel of the display panel by the deteriorated switching element.

1 is a diagram schematically showing a part of a conventional liquid crystal display device.
2 is a diagram illustrating an operation change according to a threshold voltage shift of a thin film transistor.
3 is a diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.
FIG. 4 is a diagram specifically illustrating part A of FIG. 3 .
5 is a diagram illustrating a configuration of a compensator according to an embodiment of the present invention.
6 is a view showing the configuration of a compensator according to another embodiment of the present invention.

Hereinafter, a display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating the configuration of a display device according to an embodiment of the present invention, and FIG. 4 is a diagram specifically illustrating a portion A of FIG. 3 .

Referring to FIG. 3 , the display device 100 according to the present embodiment may include a display panel 110 and a driving circuit for driving the display panel 110 .

The display panel 110 may be a liquid crystal panel in which a liquid crystal layer (not shown) is provided between two substrates (not shown), but is not limited thereto.

The display panel 110 may include a pixel P in each pixel area defined by crossing the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm.

Each pixel P may be arranged in a matrix form in the display area of the display panel 110 . Each pixel (P is a switching device (not shown) that charges a pixel electrode (not shown) with a data signal provided through the data lines DL1 to DLm in response to a gate signal provided through the gate lines GL1 to GLn may include

In addition, in the display panel 110 , at least one dummy pixel area defined by a plurality of dummy lines DDL1 and DDL2 formed to be parallel to the plurality of data lines DL1 to DLm and a plurality of feedback lines FL1 and FL2 , has one or more A dummy pixel DP may be provided.

One or more dummy pixels DP may be disposed in a non-display area of the display panel 110 , for example, may be disposed adjacent to the pixel P in at least one of four corner areas of the display panel 110 . have.

The plurality of dummy lines DDL1 and DDL2 includes a first dummy line DDL1 formed to be parallel to the first data line DL1 and a second dummy line DDL2 formed to be parallel to the m-th data line DLm. can do. The plurality of feedback lines FL1 and FL2 include a first feedback line FL1 formed to be parallel to a first data line DL1 and a first dummy line DDL1, an m-th data line DLm, and a second dummy line. A second feedback line FL2 formed to be parallel to the DDL2 may be included.

The plurality of dummy lines DDL1 and DDL2 and the plurality of feedback lines FL1 and FL2 may be formed to extend from the data driver 130 to the compensator 150 through the display panel 110 , which will be described later.

3 and 4 , the pixel P and the dummy pixel DP share the first gate line GL1 and may be disposed adjacent to each other in the horizontal direction with respect to the first data line DL1 .

The pixel P may include a switching element TFT connected to the first gate line GL1 and the first data line DL1, and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The switching element TFT of the pixel P is turned on according to a gate signal provided through the first gate line GL1 , and the data signal provided through the first data line DL1 may be charged to the pixel electrode. .

The dummy pixel DP may include a dummy switching device D_TFT connected to the first gate line GL1 , the first dummy line DDL1 , and the first feedback line FL1 . The dummy switching device D_TFT of the dummy pixel DP is turned on according to the gate signal provided through the first gate line GL1 and receives the dummy signal provided through the first dummy line DDL1 through the first feedback line ( It can be output through FL1).

The switching element TFT of the pixel P and the dummy switching element D_TFT of the dummy pixel DP may be formed of a thin film transistor (TFT) having the same structure. Also, the dummy signal provided to the dummy switching device D_TFT through the first dummy line DDL1 may be the same as the data signal provided to the switching device TFT through the first data line DL1.

That is, the display panel 110 of the present exemplary embodiment may include one or more dummy pixels DP disposed to be adjacent to the pixel P. Referring to FIG. Each dummy pixel DP may include a dummy switching device D_TFT connected to the gate lines GL1 to GLn, the dummy lines DDL1 and DDL2, and the feedback lines FL1 and FL2. The dummy switching element D_TFT of each dummy pixel DP may be turned on simultaneously with the switching element TFT of the adjacent pixel P according to a gate signal provided through the gate lines GL1 to GLn. In addition, the data signal provided through the dummy lines DDL1 and DDL2, that is, the dummy signal may be output to the outside through the feedback lines FL1 and FL2.

Since the above-described dummy pixel DP is disposed in a non-display area of the display panel 110 , it may be covered by a black matrix (not shown) provided in the display panel 110 . Accordingly, the dummy pixel DP is not viewed from the front of the display panel 110 .

Meanwhile, in FIG. 4 , an example in which the dummy pixel DP is disposed adjacent to the pixel P in the upper left region of the display panel 110 has been described. However, as described above, one or more dummy pixels DP may be disposed adjacent to the pixels P in four corner regions of the display panel 110 . That is, the plurality of dummy pixels DP may be disposed to be adjacent to the pixels P in upper left/right upper and lower regions of the display panel 110 . In this case, each dummy pixel DP and a pixel P adjacent thereto may share the gate lines GL1 to GLn.

Referring back to FIG. 3 , the gate driver 120 generates a gate signal according to the gate control signal GCS provided from the timing controller 140 , and uses the gate signal to generate the gate signal on the plurality of gate lines GL1 to GLn of the display panel 110 . can be output sequentially.

The gate driver 120 may generate a gate signal according to the gate voltage provided from the voltage generator 160 . The gate voltage may include a first gate high voltage VGH1 , a second gate high voltage VGH2 , and a gate low voltage VGL. The gate driver 120 generates a gate signal according to the first gate high voltage VGH1 and the gate low voltage VGL or generates a gate signal according to the second gate high voltage VGH2 and the gate low voltage VGL. can do.

The gate driver 120 may be configured and disposed on at least one side of the display panel 110 in the form of a Chip On Film (COF) or may be configured and disposed in the form of a Gate In Panel (GIP).

The data driver 130 generates a data signal and a dummy signal from the image data RGB according to the data control signal DCS provided from the timing controller 140 , and uses the data signal and the dummy signal on the plurality of data lines DL1 to DL1 of the display panel 110 . DLm) and the dummy lines DDL1 and DDL2, respectively.

The data driver 130 may output the same data signal to the data lines DL1 to DLm and the dummy lines DDL1 and DDL2 adjacent to each other. For example, when the first data line DL1 and the first dummy line DDL1 are adjacent to each other in the display panel 110 , the data driver 130 connects the first dummy line DDL1 to the first data line DL1 . The same signal as the data signal output to can be output as a dummy signal.

The timing controller 140 controls the gate control signal GCS and data from timing signals such as a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE provided from an external system (not shown). A signal DCS may be generated and output. Also, the timing controller 140 may convert an image signal provided from an external system into image data RGB in a format that the data driver 130 can process and output the converted image signal.

The compensator 150 may generate the control signal SS according to the dummy signal and the feedback signal provided from the display panel 110 , and output it to the voltage generator 160 . The compensator 150 may control the level of the gate voltage output from the voltage generator 160 according to the control signal SS.

The compensator 150 may be connected to a plurality of dummy lines DDL1 and DDL2 and a plurality of feedback lines FL1 and FL2 of the display panel 110 . The compensator 150 may receive a dummy signal through the plurality of dummy lines DDL1 and DDL2 and receive a feedback signal through the plurality of feedback lines FL1 and FL2. Here, the dummy signal is a signal provided to the dummy pixel DP of the display panel 110 through the plurality of dummy lines DDL1 and DDL2, and the feedback signal is provided to the display panel through the plurality of feedback lines FL1 and FL2. 110) is a signal output from the dummy pixel DP.

5 is a diagram illustrating a configuration of a compensator according to an embodiment of the present invention.

For convenience of explanation, in the present embodiment, a pair of dummy pixels DP are provided in the display panel 110 , and the pair of dummy pixels DP are a first dummy in the upper left area of the display panel 110 . A case in which the pixel and the second dummy pixel in the upper right region of the display panel 110 are included will be described as an example.

Here, the first dummy pixel is connected to the first dummy line DDL1 and the first feedback line FL1 of the display panel 110 , and the second dummy pixel is the second dummy line DDL2 of the display panel 110 . and a second feedback line FL2.

3 to 5 , the compensator 150 of the present embodiment may be connected to a plurality of dummy lines DDL1 and DDL2 and a plurality of feedback lines FL1 and FL2 of the display panel 110 .

The compensator 150 controls the control signal SS according to the dummy signals DDS1 and DDS2 provided from the plurality of dummy lines DDL1 and DDL2 and the feedback signals FS1 and FS2 provided from the plurality of feedback lines FL1 and FL2. can be created and printed.

The compensator 150 compares the dummy signals DDS1 and DDS2 with the feedback signals FS1 and FS2 and determines to output the control signal SS according to the comparison signal of the comparison unit 151 part 155 may be included.

The comparator 151 may include a first comparator 151_a and a second comparator 151_b.

The first comparator 151_a may be connected to the first dummy line DDL1 and the first feedback line FL1 of the display panel 110 to receive the first dummy signal DDS1 and the first feedback signal FS1 . have. The first dummy signal DDS1 is a signal provided to the first dummy pixel, and the first feedback signal FS1 is a signal output from the first dummy pixel.

The first comparator 151_a may output the first comparison signal CS1 according to a result of comparing the first dummy signal DDS1 with the first feedback signal FS1 . The first comparison signal CS1 has different levels depending on the level difference between the first dummy signal DDS1 and the first feedback signal FS1, for example, one of a high level signal and a low level signal. can be output as

The second comparator 151_b may be connected to the second dummy line DDL2 and the second feedback line FL2 of the display panel 110 to receive the second dummy signal DDS2 and the second feedback signal FS2 . have. The second dummy signal DDS2 is a signal provided to the second dummy pixel, and the second feedback signal FS2 is a signal output from the second dummy pixel.

The second comparator 151_b may output the second comparison signal CS2 according to a result of comparing the second dummy signal DDS2 with the second feedback signal FS2 . The second comparison signal CS2 may be output as one of a high level signal and a low level signal according to a level difference between the second dummy signal DDS2 and the second feedback signal FS2 .

The first comparator 151_a and the second comparator 151_b are the first gate signal GS1 , that is, the first gate signal GS1 provided from the gate driver 120 to the first gate line GL1 of the display panel 110 . It can be operated in response to GS1). This is because the dummy switching device D_TFT of the pair of dummy pixels DP of the display panel 110 connected to the first comparator 151_a and the second comparator 151_b, respectively, is in common to the first gate line GL1. This is because it is connected and turned on by the first gate signal GS1.

The determination unit 155 may output the control signal SS according to the first comparison signal CS1 and the second comparison signal CS2 output from the comparison unit 151 . The control signal SS may be output as one of a high level signal and a low level signal.

The determination unit 155 may output a high level control signal SS when at least one of the first comparison signal CS1 and the second comparison signal CS2 is output as a high level signal. Also, when both the first comparison signal CS1 and the second comparison signal CS2 are output as low-level signals, the determination unit 155 may output the low-level control signal SS. The control signal SS may control the level of the gate voltage output from the voltage generator 160 . The determination unit 155 may be formed of a logic circuit element such as an OR gate.

Referring back to FIG. 3 , the voltage generator 160 generates a plurality of voltages from the input power provided from the external system, for example, a first gate high voltage VGH1 , a second gate high voltage VGH2 , and a gate low voltage VGL. ) can be created.

The first gate high voltage VGH1 may have a lower level than the second gate high voltage VGH2 . For example, the first gate high voltage VGH1 may be generated at a level of approximately 25V, and the second gate high voltage VGH2 may be generated at a level of approximately 27V.

The voltage generator 160 may output at least two of the plurality of voltages as a gate voltage to the gate driver 120 according to the control signal SS provided from the compensator 150 .

For example, when the compensator 150 outputs the low-level control signal SS, the voltage generator 160 may output the first gate high voltage VGH1 and the gate low voltage VGL as gate voltages. . On the other hand, when the compensator 150 outputs the high level control signal SS, the voltage generator 160 may output the second gate high voltage VGH2 and the gate low voltage VGL as gate voltages. . That is, the voltage generator 160 may change the magnitude of the gate high voltage among the gate voltages according to the level of the control signal SS output from the compensator 150 .

As described above, in the display device 100 of this embodiment, at least one dummy pixel DP is provided on the display panel 110 , and signals from the dummy pixel DP through the compensator 150 , that is, The deterioration of the pixel may be determined according to the dummy signals DDS1 and DDS2 and the feedback signals FS1 and FS2. In addition, by controlling the level of the gate high voltage among the gate voltages output from the voltage generator 160 to increase according to the determination result, the deterioration of the switching element TFT in each pixel P of the display panel 110 is caused. It is possible to prevent the occurrence of a charging failure of the data signal.

Here, if it is determined that the dummy pixel DP is deteriorated by the compensator 150 , it may be determined that the pixel P adjacent to the dummy pixel DP is also deteriorated. Accordingly, in the display device 100 of the present invention, the level of the gate high voltage is increased and output from the voltage generator 160 according to the control of the compensator 150 , so that the level of the gate signal output from the gate driver 120 is increased. It can also be increased. This increase in the level of the gate signal can sufficiently activate the channel region of the switching element TFT provided in each pixel P of the display panel 110, and the deterioration of the switching element TFT causes the pixel P to be damaged. It is possible to solve the charging failure of the data signal being charged.

Hereinafter, an operation of the above-described display device 100 will be described in detail with reference to FIGS. 3 to 5 .

First, during the previous frame operation of the display panel 110 , that is, the (N-1)th frame operation of the display panel 110 , the voltage generator 160 generates the first gate high voltage VGH1 and the gate low voltage VGL. ) can be output as the gate voltage.

The gate driver 120 may generate a gate signal according to the gate voltage output from the voltage generator 160 , and sequentially output the gate signal to the plurality of gate lines GL1 to GLn of the display panel 110 .

The data driver 130 generates a data signal according to the image data RGB provided from the timing controller 140 , and uses the data signal to generate a plurality of data lines DL1 to DLm and dummy lines DDL1 and DDL2 of the display panel 110 . can be printed on

Meanwhile, as described above, a pair of dummy pixels DP may be provided in the display panel 110 , and a first dummy pixel and a second dummy pixel may be disposed in the upper left and right upper regions, respectively. The dummy switching element D_TFT of each of the first dummy pixel and the second dummy pixel may be turned on according to the first gate signal GS1 .

The first dummy pixel transmits the data signal provided from the data driver 130 through the first dummy line DDL1, that is, the first dummy signal DDS1, to the first feedback line FL1 according to the turned-on dummy switching device D_TFT. ) through the first feedback signal FS1.

The second dummy pixel transmits the data signal provided from the data driver 130 through the second dummy line DDL2, that is, the second dummy signal DDS2, to the second feedback line FL2 according to the turned-on dummy switching device D_TFT. ) through the second feedback signal FS2.

The comparator 151 of the compensator 150 may compare the first dummy signal DDS1 with the first feedback signal FS1 to output the first comparison signal CS1. Also, the compensator 150 may compare the second dummy signal DDS2 with the second feedback signal FS2 to output the second comparison signal CS2 .

Specifically, the first comparator 151_a of the comparator 151 operates in response to the first gate signal GS1, and compares the levels of the first dummy signal DDS1 with the first feedback signal FS1. 1 A comparison signal CS1 may be output.

In this case, when the first dummy signal DDS1 and the first feedback signal FS1 have the same level, the first comparator 151_a may output the first comparison signal CS1 of the low level. On the other hand, when the first dummy signal DDS1 has a higher level than the first feedback signal FS1 , the first comparator 151_a may output the first comparison signal CS1 having a high level. When the high-level first comparison signal CS1 is output from the first comparator 151_a, it may be determined that the first dummy pixel is deteriorated according to a characteristic change of the dummy switching element D_TFT.

In addition, the second comparator 151_b of the comparator 151 operates in response to the first gate signal GS1 and compares the levels of the second dummy signal DDS2 and the second feedback signal FS2 to obtain a second A comparison signal CS2 may be output.

In this case, when the second dummy signal DDS2 and the second feedback signal FS2 have the same level, the second comparator 151_b may output the second comparison signal CS2 of the low level. On the other hand, when the second dummy signal DDS2 has a higher level than the second feedback signal FS2 , the second comparator 151_b may output the second comparison signal CS2 of a high level. When the high-level second comparison signal CS2 is output from the second comparator 151_b, it may be determined that the second dummy pixel is deteriorated according to a characteristic change of the dummy switching element D_TFT.

Subsequently, the determination unit 155 of the compensator 150 generates and outputs the control signal SS according to the first comparison signal CS1 and the second comparison signal CS2 output from the comparison unit 151 . can

In this case, when at least one of the first comparison signal CS1 and the second comparison signal CS2 is output as a high level signal, the determination unit 155 may output the high level control signal SS. On the other hand, when both the first comparison signal CS1 and the second comparison signal CS2 are output as low-level signals, the determination unit 155 may output the low-level control signal SS.

Then, the compensator 150 may output the control signal SS to the voltage generator 160 to control the operation of the voltage generator 160 . The voltage generator 160 may adjust the level of the gate voltage output during the next frame operation, ie, the Nth frame operation of the display panel 110 , according to the control signal SS output from the compensator 150 .

Specifically, when the low-level control signal SS is output from the compensator 150 , the voltage generator 160 gates the first gate high voltage VGH1 and the gate low voltage VGL during the N-th frame operation. voltage can be output. On the other hand, when the high level control signal SS is output from the compensator 150 , the voltage generator 160 applies the second gate high voltage VGH2 and the gate low voltage VGL to the gate voltage during the Nth frame operation. can be output as In this case, the second gate high voltage VGH2 may be a voltage having a higher level than the first gate high voltage VGH1 .

As described above, the display device 100 of the present embodiment can determine the deterioration of at least one dummy pixel DP included in the display panel 110 to increase the level of the gate voltage output from the voltage generator 160 . have. Accordingly, in the display device 100 of the present invention, even if the switching element TFT provided in each pixel P of the display panel 110 is deteriorated, the deteriorated switching element as the level of the gate signal provided thereto is increased. Due to (TFT), it is possible to prevent a charging failure of the data signal charged in the pixel (P).

6 is a view showing the configuration of a compensator according to another embodiment of the present invention.

For convenience of explanation, in the present embodiment, a plurality of dummy pixels DP are provided in the display panel 110 , and the plurality of dummy pixels DP are first dummy in the upper left and lower regions of the display panel 110 . An example including the pixel and the third dummy pixel, and the second dummy pixel and the fourth dummy pixel in the upper right and lower regions of the display panel 110 will be described as an example.

Here, the first dummy pixel and the third dummy pixel are commonly connected to the first dummy line DDL1 of the display panel 110 , and the second dummy pixel and the fourth dummy pixel are the second dummy of the display panel 110 . It may be commonly connected to the line DDL2. In addition, the first dummy pixel and the third dummy pixel are respectively connected to the first feedback line FL1 and the third feedback line FL3 of the display panel 110 , and the second dummy pixel and the fourth dummy pixel are connected to the display panel It may be respectively connected to the second feedback line FL2 and the fourth feedback line FL4 of 110 . That is, the display panel 110 of the display device 100 including the compensator 150 ′ shown in FIG. 6 is adjacent to the first data line DL1 and the first dummy line DDL1 to be a first feedback line. FL1 and a third feedback line FL3 are configured, and a second feedback line FL2 and a fourth feedback line FL4 are configured adjacent to the m-th data line DLm and the second dummy line DDL2 can be

3 and 6 , the compensator 150 ′ according to the present exemplary embodiment may be connected to a plurality of dummy lines DDL1 and DDL2 and a plurality of feedback lines FL1 to FL4 of the display panel 110 . The compensator 150 ′ has a low level or a high level according to the dummy signals DDS1 and DDS2 provided from the plurality of dummy lines DDL1 and DDL2 and the feedback signals FS1 to FS4 provided from the plurality of feedback lines FL1 to FL4 . A level control signal SS may be generated and output.

The compensation unit 150 ′ may include a first comparison unit 152 , a second comparison unit 153 , and a determination unit 155 . The first comparator 152 may include a first comparator 152_a and a second comparator 152_b, and the second comparator 153 may include a third comparator 153_a and a fourth comparator 153_b. have.

The first comparator 152_a of the first comparator 152 includes a first dummy signal DDS1 provided through a first dummy line DDL1 and a first feedback signal FS1 provided through a first feedback line FL1. may be compared to output the first comparison signal CS1. The first comparison signal CS1 may be output as one of a low level signal or a high level signal according to a level difference between the first dummy signal DDS1 and the first feedback signal FS1 .

The second comparator 152_b of the first comparator 152 includes a second dummy signal DDS2 provided through the second dummy line DDL2 and a second feedback signal FS2 provided through the second feedback line FL2. may be compared to output the second comparison signal CS2. The second comparison signal CS2 may be output as one of a low level signal or a high level signal according to a level difference between the second dummy signal DDS2 and the second feedback signal FS2 .

The first comparator 152_a and the second comparator 152_b may be operated in response to the first gate signal GS1 provided to the first gate line GL1 of the display panel 110 . This is because the first and second dummy pixels 152_a and 152_b are connected in common to the first gate line GL1 in the upper left and right upper regions of the display panel 110, respectively. Because they are all connected.

The third comparator 153_a of the second comparator 153 includes the first dummy signal DDS1 provided through the first dummy line DDL1 and the third feedback signal FS3 provided through the third feedback line FL3. may be compared to output a third comparison signal CS3. The third comparison signal CS3 may be output as one of a low level signal or a high level signal according to a level difference between the first dummy signal DDS1 and the third feedback signal FS3 .

The fourth comparator 153_b of the second comparator 153 includes the second dummy signal DDS2 provided through the second dummy line DDL2 and the fourth feedback signal FS4 provided through the fourth feedback line FL4. may be compared to output a fourth comparison signal CS4. The fourth comparison signal CS4 may be output as one of a low level signal or a high level signal according to a level difference between the second dummy signal DDS2 and the fourth feedback signal FS4 .

The third comparator 153_a and the fourth comparator 153_b may be operated in response to the n-th gate signal GSn provided to the n-th gate line GLn of the display panel 110 . In this case, the third comparator 153_a and the fourth comparator 153_b are connected to the third dummy pixel and the fourth dummy pixel in common to the n-th gate line GLn in the lower left and right lower regions of the display panel 110 , respectively. Because they are all connected.

The determination unit 155 outputs the control signal SS according to the comparison signals output from the first comparison unit 152 and the second comparison unit 153, that is, the first to fourth comparison signals CS1 to CS4, respectively. can do. The control signal SS may be output as one of a low level signal or a high level signal according to the levels of the first to fourth comparison signals CS1 to CS4.

For example, if at least one of the first to fourth comparison signals CS1 to CS4 respectively output from the first comparison unit 152 and the second comparison unit 153 is at a high level, the determination unit 155 sets the high level. A control signal SS may be output. On the other hand, when all of the first to fourth comparison signals CS1 to CS4 output from the first comparison unit 152 and the second comparison unit 153 are low level, the determination unit 155 controls the low level control signal (SS) can be printed.

On the other hand, when a high level comparison signal is output from any one of the first comparator 152 and the second comparator 153 , each comparator of the first comparator 152 and the second comparator 153 . This is because deterioration occurs in one of the dummy pixels DP connected to any one of (152a to 153_b).

That is, the compensator 150 ′ is configured to generate deterioration in any one of the plurality of dummy pixels DP of the display panel 110 according to a comparison signal between the dummy signals DDS1 and DDS2 and the feedback signals FS1 to FS4 . is determined, and accordingly, the control signal SS having one of a low level and a high level may be output.

The determination unit 155 may output the control signal SS to the voltage generation unit 160 . The control signal SS may control the level of the gate voltage output from the voltage generator 160 . The determination unit 155 may be formed of a logic circuit element such as an OR gate.

As described above, the compensator 150 ′ of the present embodiment generates the control signal SS according to the signals provided from the plurality of dummy pixels DP provided in the four corner regions of the display panel 110 , and uses them to generate the control signal SS. The level of the gate voltage output from the voltage generator 160 may be controlled.

Specifically, when the low-level control signal SS is output from the compensator 150 ′, the voltage generator 160 outputs the first gate high voltage VGH1 and the gate low voltage VGL as gate voltages. can

On the other hand, when the high level control signal SS is output from the compensator 150 ′, the voltage generator 160 may output the second gate high voltage VGH2 and the gate low voltage VGL as gate voltages. have. In this case, the second gate high voltage VGH2 may have a higher level than the first gate high voltage VGH1 . Accordingly, the gate driver 120 may generate and output a gate signal whose level is increased according to the second gate high voltage VGH2 of the gate voltage output from the voltage generator 160 .

As described above, the display device 100 may determine the deterioration of at least one dummy pixel DP included in the display panel 110 to increase the level of the gate voltage output from the voltage generator 160 . . Accordingly, the display device 100 of the present invention increases the level of the gate signal provided thereto even if the switching element TFT provided in each pixel P of the display panel 110 is deteriorated, and thus the deteriorated switching element (TFT) is deteriorated. Due to the TFT), it is possible to prevent a charging failure of the data signal charged in the pixel P.

Meanwhile, in the display device 100 of the present invention, one or more dummy pixels DP are disposed in four corner regions of the display panel 110 as an example. This is because the region in which the dummy pixel DP is disposed is vulnerable to deterioration. However, the present invention is not limited thereto, and one or more dummy pixels DP may be disposed in a portion that does not interfere with the display area of the display panel 110 , that is, in any of the non-display areas of the display panel 110 . have.

Although many matters are specifically described in the above description, these should be construed as examples of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention should not be defined by the described embodiments, but should be defined by the claims and equivalents to the claims.

100: display device 110: display panel
120: gate driving unit 130: data driving unit
140: timing control unit 150: compensation unit
160: voltage generator

Claims (15)

at least one dummy pixel disposed adjacent to the pixel, each of the dummy pixels being connected to a dummy line and a feedback line;
a compensator for generating and outputting a control signal according to a dummy signal provided to the dummy pixel through the dummy line and a feedback signal output from the dummy pixel through the feedback line;
generating a first gate high voltage and a second gate high voltage having a level greater than the first gate high voltage, and selecting and outputting one of the first gate high voltage and the second gate high voltage according to the control signal voltage generator; and
and a gate driver generating a gate signal from one of the first gate high voltage and the second gate high voltage and outputting it to the display panel;
The compensation unit,
and outputting a control signal for outputting the second gate high voltage when the dummy signal and the feedback signal have different levels. According to claim 1,
the dummy pixel includes a first dummy pixel and a second dummy pixel commonly connected to a first gate line in upper left and right upper regions of the display panel;
The compensation unit,
a first comparator comparing a first dummy signal provided to the first dummy pixel with a first feedback signal output from the first dummy pixel and outputting a first comparison signal;
a second comparator comparing a second dummy signal provided to the second dummy pixel with a second feedback signal output from the second dummy pixel and outputting a second comparison signal; and
and a determination unit outputting the control signal according to the first comparison signal and the second comparison signal. 3. The method of claim 2,
the first comparator outputs the first comparison signal at one of a low level and a high level according to a level difference between the first dummy signal and the first feedback signal;
The second comparator outputs the second comparison signal at one of a low level and a high level according to a level difference between the second dummy signal and the second feedback signal. 4. The method of claim 3,
When at least one of the first comparison signal and the second comparison signal is at a high level, the determination unit outputs the control signal for outputting the second gate high voltage from the voltage generator. 3. The method of claim 2,
The first comparator and the second comparator are operated in response to a first gate signal provided to the first gate line. 3. The method of claim 2,
The determination unit is a display device composed of an OR gate. According to claim 1,
The dummy pixel includes a first dummy pixel and a second dummy pixel commonly connected to a first gate line in the upper left and right upper regions of the display panel, and a n-th gate line in the lower left and right lower regions of the display panel. including a connected third dummy pixel and a fourth dummy pixel;
The compensation unit,
A first comparison is made by comparing a first dummy signal provided to each of the first dummy pixel and the third dummy pixel with a first feedback signal and a third feedback signal outputted from each of the first dummy pixel and the third dummy pixel. a first comparator and a third comparator each outputting a signal and a third comparator;
A second comparison is performed by comparing a second dummy signal provided to each of the second dummy pixel and the fourth dummy pixel with a second feedback signal and a fourth feedback signal outputted from each of the second dummy pixel and the fourth dummy pixel. a second comparator and a fourth comparator each outputting a signal and a fourth comparator; and
and a determination unit outputting the control signal according to the first comparison signal to the fourth comparison signal. 8. The method of claim 7,
The first comparator outputs the first comparison signal at one of a low level and a high level according to a level difference between the first dummy signal and the first feedback signal, and the third comparator outputs the first dummy signal and outputting the third comparison signal at one of a low level and a high level according to a difference in level of the third feedback signal,
The second comparator outputs the second comparison signal at one of a low level and a high level according to a level difference between the second dummy signal and the second feedback signal, and the fourth comparator outputs the second dummy signal and a display device outputting the fourth comparison signal at one of a low level and a high level according to a level difference between the fourth feedback signal and the fourth feedback signal. 9. The method of claim 8,
When at least one of the first comparison signal to the fourth comparison signal is at a high level, the determination unit outputs the control signal for outputting the second gate high voltage from the voltage generator. 8. The method of claim 7,
The first comparator and the second comparator are operated in response to a first gate signal provided to the first gate line,
The third comparator and the fourth comparator are operated in response to an n-th gate signal provided to the n-th gate line. According to claim 1,
The dummy line and the feedback line are disposed parallel to a data line on at least one side of the display panel. One or more dummy pixels are disposed to be adjacent to the pixels, and each of the dummy pixels is transmitted through a dummy signal provided to the dummy pixel and the dummy pixel during an (N-1)th frame operation of the display panel connected to the dummy line and the feedback line. comparing the output feedback signals;
outputting a comparison signal at one of a low level and a high level according to a comparison result;
controlling one of a first gate high voltage and a second gate high voltage having a level greater than the first gate high voltage to be output according to the comparison signal; and
outputting a gate signal generated from one of the first gate high voltage and the second gate high voltage to the display panel during an Nth frame operation of the display panel;
The controlling step is
and controlling the second gate high voltage to be output when the dummy signal and the feedback signal are at different levels. 13. The method of claim 12,
Outputting the comparison signal comprises:
When the dummy signal and the feedback signal are at the same level, a low-level comparison signal is output,
A method of driving a display device for outputting a high level comparison signal when the dummy signal and the feedback signal have different levels. 14. The method of claim 13,
The controlling step is
When the comparison signal of the low level is output, the first gate high voltage is controlled to be output,
When the comparison signal of the high level is output, the method of driving a display device for controlling the output of the second gate high voltage. 13. The method of claim 12,
The dummy signal is the same signal as the data signal provided to the pixel adjacent to the dummy pixel.

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