KR101992885B1 - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, which can prevent a deterioration in picture quality due to a horizontal crosstalk phenomenon and reduce power consumption by optimizing a bias voltage level of a common voltage supply terminal for each display pattern of an image A liquid crystal panel having a plurality of pixel regions to display an image; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for analyzing image data input from outside to detect a display pattern of an image, outputting a bias voltage selection signal according to the detected image display pattern, and controlling the gate and the data driver; And a driving voltage generator for varying and applying a bias voltage level corresponding to the bias voltage selection signal to compensate and output a common voltage level supplied to the liquid crystal panel.

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can optimize a bias voltage level of a common voltage supply terminal for each display pattern of an image to prevent image quality deterioration due to a horizontal crosstalk phenomenon, And a driving method thereof.

A liquid crystal display device displays an image using electrical and optical characteristics of a liquid crystal. Liquid crystals can have different anisotropic properties depending on the molecular axis and minor axis direction, such as refractive index and dielectric constant, and can easily control the molecular arrangement and optical properties. A liquid crystal display device using the same displays an image by changing the alignment direction of liquid crystal molecules according to the electric field size and adjusting the light transmittance transmitted through the polarizing plate.

The liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the liquid crystal panel, and a data driver for driving the data lines of the liquid crystal panel.

In order to drive pixels of a liquid crystal panel, an inversion driving method such as a frame inversion system, a line inversion system, and a dot inversion system is used for a liquid crystal display .

However, in the case of displaying an image of a specific pattern, for example, an image pattern in which the contrast is kept constant or an image pattern in which the line pattern in which the contrast is large is maintained even if the image is displayed by various inversion driving methods, There arises a problem that the average level or the peak level is distorted. If the common voltage level is distorted, a horizontal cross-talk phenomenon occurs or a picture quality defect such as a greenish afterimage or a smear phenomenon occurs on the display screen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a liquid crystal display device capable of preventing a deterioration in image quality due to a horizontal crosstalk phenomenon, An object of the present invention is to provide a driving apparatus for a device and a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display, including: a liquid crystal panel having a plurality of pixel regions to display an image; A data driver for driving data lines of the liquid crystal panel; A gate driver for driving gate lines of the liquid crystal panel; A timing controller for analyzing image data input from outside to detect a display pattern of an image, outputting a bias voltage selection signal according to the detected image display pattern, and controlling the gate and the data driver; And a driving voltage generator for varying and applying a bias voltage level corresponding to the bias voltage selection signal to compensate and output a common voltage level supplied to the liquid crystal panel.

Wherein the timing controller comprises: a data alignment unit for aligning the image data from the outside in accordance with driving of the liquid crystal panel and supplying the image data to the data driver; and a comparison unit for comparing the aligned image data with predetermined defect display patterns A video display pattern corresponding to the defective display pattern and outputting a preset bias voltage selection signal corresponding to the detected video display pattern, respectively.

Wherein the common voltage supplier includes a digital-to-analog converter for selectively outputting at least one predetermined bias voltage corresponding to the bias voltage selection signal in response to the bias voltage selection signal, An at least one operational amplifier for compensating the feedback common voltage level to a reference common voltage level using at least one bias voltage selectively supplied from the analog converter and supplying the compensated common voltage to the common electrodes of the liquid crystal panel, And a second electrode.

The defective display patterns may include at least one of a size of the liquid crystal panel, a compensated common voltage level, a positive polarity and a negative driving voltage level, and a driving characteristic of the liquid crystal panel by measuring a distortion magnitude of a common voltage level supplied to the liquid crystal panel And is set and stored according to the degree of distortion of the compensated common voltage level.

Wherein the bias voltage selection signal includes a plurality of bias voltage selection signals each corresponding to the detected image display pattern so as to generate and compensate for a common voltage with a bias voltage of an optimum level for each of the detected image display patterns among a plurality of different levels of bias voltages, And is pre-set and stored according to the results of the experiment.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: detecting an image display pattern by analyzing image data input from the outside; Outputting a signal; And varying a bias voltage level corresponding to the bias voltage selection signal to compensate and output a common voltage level supplied to the liquid crystal panel.

Wherein the bias voltage selection signal output step includes the steps of: aligning the image data from the outside in accordance with driving of the liquid crystal panel; comparing the aligned image data with predetermined defective display patterns in units of at least one frame, And outputting the bias voltage selection signal set in advance to correspond to the detected video display pattern.

The common voltage level compensation output step may include selectively outputting at least one preset bias voltage corresponding to the bias voltage selection signal in response to the bias voltage selection signal, And compensating the feedback common voltage level to a reference common voltage level using at least one output bias voltage and supplying the compensated common voltage to the common electrodes of the liquid crystal panel.

The defective display patterns may include at least one of a size of the liquid crystal panel, a compensated common voltage level, a positive polarity and a negative driving voltage level, and a driving characteristic of the liquid crystal panel by measuring a distortion magnitude of a common voltage level supplied to the liquid crystal panel And is set and stored according to the degree of distortion of the compensated common voltage level.

Wherein the bias voltage selection signal includes a plurality of bias voltage selection signals each corresponding to the detected image display pattern so as to generate and compensate for a common voltage with a bias voltage of an optimum level for each of the detected image display patterns among a plurality of different levels of bias voltages, And is pre-set and stored according to the results of the experiment.

According to an embodiment of the present invention, there is provided a driving apparatus for a liquid crystal display device and a driving method thereof that optimize a bias voltage level of a common voltage supply terminal for each display pattern of an image, thereby lowering image quality due to a horizontal crosstalk phenomenon And reliability can be improved. In addition, the bias voltage level of the common voltage supply terminal can be reduced according to the display pattern of the image, so that the power consumption can be reduced.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a block diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention; FIG.
Fig. 2 is a block diagram specifically showing a timing controller in Fig. 1. Fig.
3 illustrates an example of bad image patterns that are set and stored in advance.
4 is a configuration diagram schematically showing a common voltage supply unit.
FIG. 5 is a waveform diagram showing a common voltage change waveform as a bias voltage is selectively applied to each defective image display pattern.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention.

The driving apparatus of the liquid crystal display shown in FIG. 1 includes a liquid crystal panel 2 having a plurality of pixel regions to display an image; A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2; (VSC) according to the detected image display pattern, and also controls the gate and data drivers (6, 4) by controlling the gate and data drivers A timing controller 8 for controlling the operation of the microcomputer; And a bias voltage level corresponding to the bias voltage selection signal VSC to compensate and output the common voltage Vcom level of the liquid crystal panel 2. The timing controller 8 arranges the input image data RGB in accordance with the driving of the liquid crystal panel 2 and supplies the image data RGB to the data driver 4 and outputs the synchronizing signals DCLK, Hsync, Vsync, The gate and data drivers GCS and DCS are generated by supplying the gate and data control signals GCS and DCS to the gate and data drivers 6 and 4, 6, 4).

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each sub-pixel (R, G, B) region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm ), And a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the reference common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage to implement the gradation . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the video signal charged in the liquid crystal capacitor Clc is maintained until the next video signal is supplied. The storage capacitor Cst may be formed by overlapping the pixel electrode with the previous gate line with the insulating film interposed therebetween, or the pixel electrode may be formed by overlapping the storage line with the insulating film interposed therebetween.

The data driver 4 receives the image data RGB from the timing controller 8 using the source start pulse SSP and the source shift clock SSC among the data control signal DCS from the timing controller 8. [ Into an analog voltage, that is, a video signal. Specifically, the data driver 4 latches the image data RGB input according to the source shift clock SSC of the data control signal DCS, and then, in response to the source output enable (SOE) signal, And supplies a video signal for one horizontal line to each of the data lines DL1 to DLm for every one horizontal period in which scan pulses are supplied to the data lines GL1 to GLn. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray level value of the input image data (RGB), and outputs the selected gamma voltage to each of the data lines DL1 to DLm as a video signal. .

The gate driver 6 sequentially generates scan pulses in response to a gate control signal GCS from the timing controller 8, for example, a gate start pulse GSP and a gate shift clock GSC, The pulse width of the scan pulses is controlled according to the GOE signal. Then, the scan pulses whose pulse widths are controlled are again supplied with the gate-on voltages sequentially to the gate lines GL1 to GLn. Specifically, the gate driver 6 sequentially shifts the gate start pulse GSP from the timing controller 8 in accordance with the gate shift clock GSC to generate a scan pulse sequentially. On the basis of the gate output enable (GOE) signal, the pulse width of the scan pulses is controlled to sequentially supply the gate-on voltages whose pulse widths are controlled to the gate lines GL1 to GLn. On the other hand, the gate-off voltage is supplied during the period when no gate-on voltage is supplied to the gate lines GL1 to GLn.

The timing controller 8 arranges the image data RGB from outside in accordance with the size and resolution of the liquid crystal panel 2 and supplies the image data RGB to the data driver 4. [ At this time, the timing controller 8 analyzes the aligned image data Data in real time and detects various bad display patterns that are likely to be distorted in the image display patterns previously set by the designer, that is, the common voltage Vcom level. Then, in accordance with the detection result of the defective display pattern, the bias voltage selection signal VSC corresponding thereto is supplied to the drive voltage generator 10. [ In other words, the timing controller 8 analyzes the image data (Data) in real time and outputs a common voltage (Vcom) such as an image pattern in which the contrast patterns are kept constant or the line patterns with high contrast are kept constant, And detects various bad display patterns in which the level is likely to be distorted. The timing controller 8 supplies the bias voltage selection signal VSC to the driving voltage generator 10 (FIG. 10) so as to generate and compensate the common voltage Vcom with the optimum level of the bias voltage corresponding to the detected image display pattern, ).

The timing controller 8 generates a gate control signal GCS and a data control signal DCS using synchronous signals DCLK, DE, Hsync and Vsync from the outside, And data control signals DCS to the gate driver 6 and the data driver 4, respectively. The structure and the driving method of the timing controller 8 of the present invention will be described more specifically with reference to the accompanying drawings.

The driving voltage generating unit 10 compensates the common voltage level fed back from the liquid crystal panel 2 and compensates the common voltage Vcom to the common electrodes of the liquid crystal panel 2. [ At this time, the driving voltage generator 10 controls the driving voltage generator 10 such that the level of the compensated common voltage Vcom_out is not distorted during the video display process of the specific defective pattern, or the common voltage Vcom_out level is distorted during the video display process of the specific defective pattern And compensates and supplies the common voltage Vcom. To this end, the driving voltage generator 10 generates and compensates the common voltage Vcom with the bias voltage of the optimum level for each image display pattern in accordance with the bias voltage selection signal VSC from the timing controller 8. In other words, the driving voltage generator 10 generates and compensates the common voltage Vcom with a bias voltage set to an optimum level according to the display image pattern even during a period of displaying a general image with a low possibility of distortion of the common voltage (Vcom) level. Can be output. Then, the common voltage Vcom can be generated and compensated for by the bias voltage set to the optimum level according to the video display pattern only when displaying the image of the bad display pattern in which the level of the common voltage Vcom is likely to be distorted.

In addition, the driving voltage generator 10 varies the voltage level of the input power supplied from the outside to generate a plurality of driving voltages VDD and GND for driving the liquid crystal display device. In other words, the driving voltage generating section 10 includes a positive polarity and negative polarity driving voltage (VDD, GND) of a constant voltage type in which the voltage level of the input power source is changed, a gate high voltage Divides the positive polarity and the negative polarity driving voltages VDD and GND into a plurality of gamma voltage levels to generate a reference gamma voltage divided into a plurality of levels and supplies them to the liquid crystal panel 2 and the gate and data drivers 6 and 4 Supply.

Fig. 2 is a block diagram specifically showing the timing controller in Fig.

The timing controller 8 shown in Fig. 2 includes a data arrangement unit 11 for arranging image data RGB from outside in accordance with driving of the liquid crystal panel 2 and supplying the data to the data driver 4, (VSC) which is set in advance so as to correspond to the detected video display pattern, and the video display pattern corresponding to the defective display pattern is detected by comparing the defective display pattern An image analyzing unit 12 for outputting an image; A gate control signal generator 14 for generating a gate control signal GCS by using at least one of synchronizing signals DCLK, DE, Hsync and Vsync from the outside and supplying it to the gate driver 6, And a data control signal generator 16 for generating a data control signal DCS using at least one of the synchronizing signals DCLK, Vsync, Hsync and DE and supplying the data control signal DCS to the data driver 4. [

The data sorting unit 11 arranges the image data RGB according to driving of the liquid crystal panel 2 using at least one of the synchronizing signals DCLK, Hsync, Vsync and DE, (Data) to the data driver 4.

The image analyzing unit 12 real-time analyzes the image data Data aligned from the data arranging unit 11 in units of at least one frame to detect an image display pattern corresponding to a predetermined failure display pattern, Generates a bias voltage selection signal VSC previously set to correspond to the display pattern, respectively, and supplies the generated bias voltage selection signal VSC to the driving voltage generator 10.

The image analyzing unit 12 compares the image data Data aligned with a plurality of bad display patterns stored in advance in the internal or external look-up table or memory in at least one frame unit. When the video data (Data) aligned with the defective display pattern match with the preset number of frames, a bias voltage selection signal VSC of a plurality of bits set to correspond to the defective display patterns that match each other is supplied to the drive voltage generator 10 Supply. The bias voltage selection signal VSC of a plurality of bits can be generated and output by using an internal or external oscillator. When a bad display pattern is not detected, a bias voltage selection signal VSC of a preset bit is generated, Can be supplied to the driving voltage generator (10).

3, various defective display patterns (image 1 to image n), in which the level of the common voltage Vcom of the liquid crystal panel 2 is likely to be distorted, are different from the size of the liquid crystal panel 2, the common voltage Vcom ) Level, the positive polarity, the negative driving voltage (VDD, GND) level, and the driving characteristic of the liquid crystal panel 2 according to various experimental results. Accordingly, patterns in which the level of the common voltage Vcom can be distorted to a relatively large width and patterns that can be distorted in a small width can be set and stored in stages. The bias voltage selection signal VSC is also set in advance so as to select at least one level of the bias voltage of the various levels of bias voltage. That is, the bias voltage selection signal VSC is set in advance so as to generate and compensate the common voltage Vcom with the bias voltage of the optimum level for each detected image display pattern. The image analysis unit 12 generates the bias voltage selection signal VSC to generate the driving voltage VSC so as to generate and compensate the common voltage Vcom with the optimum level of the bias voltage corresponding to the image display pattern detected in real time, (10).

The gate control signal generator 14 generates a gate control signal GOE using at least one of the input synchronizing signals DCLK, DE, Hsync and Vsync, for example, a data enable signal DE and a horizontal synchronizing signal Hsync, GSP and GSC including the signal are generated. Then, the generated gate control signal GCS is supplied to the gate driver 6. The gate control signal GCS is a signal for controlling the driving timing of the gate driver 6.

The data control signal generating unit 16 generates at least one of the input synchronizing signals DCLK, DE, Hsync and Vsync by using the data enable signal DE and the vertical synchronizing signal Vsync, SSC, SSP, and vertical and horizontal POL signals.

4 is a schematic diagram showing a common voltage supply unit.

The common voltage supply unit 26 of Figure 4 generates at least one bias voltage B_VDD1, B_GND1 to B_VDDn (B_VDD1, B_GND1 to B_VDDn) corresponding to the bias voltage selection signal VSC in response to the bias voltage selection signal VSC from the timing controller 8. [ Analog converter 30 that selectively receives the feedback common voltage FB_Vcom from the liquid crystal panel 2 and at least one bias voltage B_VDD1 selectively input from the digital- Which compensates the level of the feedback common voltage FB_Vcom to the level of the reference common voltage Vcom and supplies the compensated common voltage Vcom_out to the common electrodes of the liquid crystal panel 2 using at least the common voltage Vcc_out, B_GND1 to B_VDDn, and B_VDDn, And one operational amplifier unit Amp.

The digital-to-analog converter 30 selectively outputs bias voltages (B_VDD1, B_GND1 to B_VDDn, B_VDDn) of the optimum level for each image display pattern according to a bias voltage selection signal VSC from the timing controller 8, (B_VDD1, B_GND1 to B_VDDn, B_VDDn) of the optimum level for each image display pattern is supplied to the operational amplifier unit Amp of each pixel in units of at least one frame.

At least one operational amplifier unit Amp is connected between the feedback common voltage FB_Vcom from the liquid crystal panel 2 and at least one bias voltage B_VDD1, B_GND1 to B_VDDn, B_VDDn to compensate the level of the common voltage FB_Vcom fed back to the level of the reference common voltage Vcom and supply the compensated common voltage FB_Vcom to the liquid crystal panel 2. The feedback common voltage FB_Vcom level is compensated to the reference common voltage Vcom level by using the optimum bias voltages B_VDD1, B_GND1 to B_VDDn, and B_VDDn for each video display pattern, Level distortion of the common voltage Vcom_out supplied to the liquid crystal panel 2 can be minimized.

FIG. 5 is a waveform diagram showing a common voltage change waveform as a bias voltage is selectively applied to each defective image display pattern.

5, if the bias voltage (B_VDD1, B_GND1 to B_VDDn, B_VDDn) of the optimum level is selectively applied to each video display pattern, the peak voltage level of the compensated common voltage Vcom_out is set to at least the selected bias voltages B_VDD1, B_GND1, B_VDDn, B_VDDn) level. This minimizes the distortion of the level of the common voltage (Vcom_out) supplied to the liquid crystal panel 2 during the display period of the image of the defective pattern, thereby preventing the deterioration of image quality due to the defective display pattern. Even if the image is not a bad pattern, the power consumption can be reduced by optimizing the levels of the bias voltages B_VDD1, B_GND1 to B_VDDn, and B_VDDn according to the pattern of the display image. That is, when a general image is displayed, it is possible to reduce the load on the driving voltage generator 10 to prevent defects such as a heating phenomenon and an abnormal voltage generation phenomenon, and reduce power consumption.

As described above, the driving apparatus and the driving method of the liquid crystal display according to the present invention can stabilize the driving voltage level such as the common voltage corresponding to the display pattern of the image, thereby preventing the deterioration of the image quality of the display image, The reliability of the circuit for driving the panel 2 can be improved by preventing the heat generation or abnormal operation of the circuits.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Claims (10)

delete delete delete delete delete A common voltage level, a positive polarity, a negative polarity driving voltage level, and a driving characteristic of the liquid crystal panel, by measuring a magnitude of a distortion of a common voltage level supplied to the liquid crystal panel, And setting and storing bias voltage selection signals at various levels corresponding to the defective display patterns and the defective display patterns;
A display pattern of a corresponding video among a plurality of bad display patterns in which the common voltage level is likely to be distorted is analyzed by analyzing video data input from the outside in at least one frame unit, Outputting a bias voltage selection signal of an optimum level corresponding to the video display pattern; And
A feedback common voltage is compensated to a reference common voltage level by varying an optimal bias voltage level preset to correspond to the bias voltage selection signal in response to the bias voltage selection signal, Supplying a gate high voltage for driving the gate line of the liquid crystal panel to the gate driver, supplying a positive polarity and a negative polarity driving voltage (VDD, GND) of a constant voltage type obtained by converting the voltage level of the input power source to the liquid crystal panel, Dividing the positive polarity and negative polarity drive voltages (VDD, GND) to a plurality of gamma voltage levels to generate a reference gamma voltage divided into a plurality of levels, and outputting the generated reference gamma voltages to a data driver . delete delete The method according to claim 6,
Wherein the defective display patterns are set and stored in stages according to a degree of distortion of the compensated common voltage level. 10. The method of claim 9,
The bias voltage selection signal
And generating and outputting a common voltage with a bias voltage of an optimum level for each of the plurality of different levels of bias voltages according to the detected image display pattern, And wherein the driving signal is set and stored.

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