KR102396466B1 - Organic Light Emitting Display Device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display that achieves high resolution by reducing or omitting a distance between a data line and an adjacent wiring by changing the vertical positional relationship between data lines and lines arranged in the same direction, and to reference voltages arranged in the same direction. At least one of the line RL and the power supply voltage line VDL is located on a different layer from the data line and may contact or overlap the data line 111 in a plan view, thereby increasing the pixel density and the device. High resolution can be achieved.

Description

Organic Light Emitting Display Device {Organic Light Emitting Display Device}

The present invention relates to a display device, and more particularly, to an organic light emitting diode display having a high resolution by reducing or omitting a space between a data line and an adjacent wiring by changing the vertical positional relationship of lines arranged in the same direction as a data line.

With the development of various portable electronic devices such as mobile communication terminals and notebook computers, the demand for a flat panel display device applicable thereto is increasing.

Specific examples of the flat panel display device include a liquid crystal display device (LCD), an organic light emitting display device (organic emitting display device), a plasma display panel device (PDP), and a quantum dot display device (Quantum Dot Display Device). ), a field emission display device (FED), an electrophoretic display device (EPD), etc., which in common use a flat panel display panel that implements an image as an essential component, A flat panel display panel has a structure in which a pair of transparent insulating substrates are bonded to each other with a unique light emitting or polarized light or other optical material layer interposed therebetween.

An organic light emitting diode display includes an organic light emitting diode for emitting light for each pixel and a pixel circuit unit for controlling a current flowing through the organic light emitting diode, and the pixel circuit unit includes at least two thin film transistors and a storage capacitor.

On the other hand, the thin film transistor is divided into a top gate structure and a bottom gate structure according to the position of the gate electrode. And, such a gate structure is selected according to need.

The thin film transistor includes a semiconductor layer having a channel function between the source electrode and the drain electrode. A TFT (Thin Film Transistor) having a general top gate structure first forms an amorphous layer on a substrate, and crystallizes it using an excimer laser to make it poly-silicon. Then, a photosensitive film (not shown) is applied on the crystallized polycrystalline silicon, the photosensitive film is exposed and developed to form a photosensitive film pattern, and the polycrystalline silicon is etched using the photosensitive film pattern as a mask, It leaves an active layer. Then, a gate insulating layer is formed to cover the active layer, and a gate electrode is formed on the gate insulating layer to correspond to the upper portion of the active layer.

Hereinafter, a circuit configuration of one pixel in a conventional organic light emitting diode display will be described with reference to the drawings.

1 is a circuit diagram illustrating one pixel of a conventional organic light emitting diode display.

1 is a diagram illustrating the configuration of a pixel circuit of an organic light emitting diode display having a basic structure, including a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and a driving thin film transistor connected to the driving thin film transistor DT. It contains an organic light emitting diode (OLED).

The switching thin film transistor ST is formed in a region where the scan line SL and the data line DL intersect, and serves to select a pixel. In addition, the switching thin film transistor ST includes a switching gate electrode SG protruding from the gate line SL, a switching source electrode SS branched from the data line DL, a switching drain electrode SD, and a switching channel. and a first active layer in which a region is defined.

Here, in the first active layer, a switching channel region is defined in a portion overlapping with the switching gate electrode SG, and both periphery of the switching channel region are doped with impurities to function as a source region and a drain region. In addition, the source region and the drain region are respectively connected to the switching source electrode SS and the switching drain electrode SD of the switching thin film transistor ST.

In addition, the driving thin film transistor DT functions to drive the organic light emitting diode OLED of the pixel selected by the switching thin film transistor ST. The driving thin film transistor DT includes a driving gate electrode DG connected to the switching drain electrode SD of the switching thin film transistor ST, and a driving source included on the power supply voltage line VL for supplying the power voltage VDD. an electrode DS, a driving electrode pattern DD spaced apart from the driving source electrode DS, and a source region connected to the driving source electrode DS and the driving electrode pattern DD in and around the driving channel region; and a second active layer having a drain region. The driving electrode pattern DD of the driving thin film transistor DT is connected to the first electrode of the organic light emitting diode OLED.

In addition, electrical connection is made at the overlapping portion of the driving gate electrode DG and the switching drain electrode, so that the drain electrode of the switching thin film transistor ST and the gate electrode of the driving thin film transistor DT are connected.

In addition, a storage capacitor Cst may be defined at an overlapping portion between the driving gate electrode DG of the driving thin film transistor DT and the driving electrode pattern.

However, in the conventional organic light emitting diode display, referring to the illustrated circuit diagram, a driving circuit corresponding to one pixel of FIG. 1 is provided between the data line DL and the power supply voltage line VDL. . Accordingly, in the pixel adjacent to the illustrated pixel, the next data line DL may be disposed adjacent to the illustrated current driving line VDL.

The pixels of the conventional organic light emitting display device circuitly arrange signals applied in the same direction in the same direction, and form them on the same layer. Accordingly, the current driving line VDL and the data line DL are located on the same layer.

In this case, the current driving line VDL and the data line DL should be spaced apart from each other by a predetermined interval in order to avoid inter-line interference and to prevent a short circuit.

On the other hand, the application range of the organic light emitting display device is gradually expanding, and development of satisfying large area and high density specifications is accelerating. In particular, as the resolution increases, the size of the unit pixel gradually decreases. The reduction in the size of the unit pixel means that, in the above-described pixel structure, a spacing between the current driving line located on the same layer and the adjacent data line must exist, and this is in addition to the width of the data line or the power voltage line in the horizontal direction. The distance between them must be provided in the pixel, and when this condition is satisfied, it is difficult to integrate more than a certain level in the horizontal direction.

In the above-described conventional organic light emitting display device, when a sufficient separation between the data line and the power voltage line is ensured, there is a problem in that the size of the pixel increases, so there is a fundamental limitation in that it is difficult to arrange the pixels in the device with a high resolution. In an organic light emitting display device requiring ultra-high integration, efforts are required to solve this problem.

The present invention has been devised to solve the above-described problem, and the organic light emitting diode display achieves high resolution by reducing or omitting the space between the data line and the adjacent wiring by changing the vertical positional relationship of the lines arranged in the same direction as the data line. It aims to provide

According to an aspect of the present invention, in an organic light emitting diode display for achieving the above object, at least one of a reference voltage line RL and a power voltage line VDL arranged in the same direction is located on a different layer from the data line, The data line 111 may be in contact with or overlap with the data line 111 , so that high integration of pixels and high resolution of the device may be achieved.

For this purpose, the organic light emitting display device of the present invention includes a scan line and a sensing line disposed in a first direction on a substrate, a first active layer and a second active layer that intersect the scan line and the sensing line, respectively, and are spaced apart from each other; , a data line, a reference voltage line, and a power supply voltage line intersecting the first and second active layers, and receiving a first gate signal from the scan line; A first switching transistor positioned between a data line and a first node, a gate signal applied from the first node, a driving thin film transistor positioned between the power supply voltage line and a second node, and a second gate signal applied from the sensing line and a second switching thin film transistor positioned between the second node and the reference voltage line, wherein at least one of the reference voltage line and the power supply voltage line is located on a different layer from the data line, Lines can be tangent to or overlapped with.

In addition, the first active layer has first and second contacts, both ends of which are connected to the data line and the drain electrode of the first switching thin film transistor, and the second active layer has a gate electrode of the driving thin film transistor overlapped a third contact corresponding to both ends of one outer side of which one end is connected to a power supply voltage line, a fourth contact whose other end is connected to the source electrode of the second switching thin film transistor, and a fifth contact connected to the reference voltage line; can have

In addition, the reference voltage line is located on a different layer from the data line, is in planar contact with or overlaps the data line, is a region between the data line and the power voltage line, and may include a protrusion from the reference voltage line. there is. The fifth contact may have a shape in which a protrusion from the reference voltage line and a drain electrode of the second switching thin film transistor are connected.

Meanwhile, at the first node, a drain electrode of the switching thin film transistor and a gate electrode of the driving thin film transistor may be connected.

Meanwhile, as another example, the reference voltage line is located on a layer different from the data line, is in planar contact with or overlaps the data line, and is connected to a metal of a different layer from the data line and the reference voltage line in the fifth contact. Thus, the reference voltage line may be connected to the second active layer. In the fifth contact, a metal of a layer different from that of the data line and the reference voltage line, which is connected to the second active layer, may be an upper gate pattern provided on an upper side of the second active layer. In the fifth contact, a contact material electrically connecting the reference voltage line, the second active layer, and the upper gate pattern from the bottom. The first contact may be provided through the first active layer, and may be formed of a contact material filled between layers between the lower gate pattern under the first active layer and the data line.

Also, as another example, the power supply voltage line is positioned on a different layer from the data line, and is in contact with or overlaps the data line in a planar manner, and the data line and the power supply voltage line in the third contact are connected to the second active layer and the second active layer. It may be connected by a metal layer different from that of the data line and the power supply voltage line. In the third contact, a metal of a layer connected to the second active layer and different from the data line and the power voltage line may be an upper gate pattern provided on an upper side of the second active layer. The third contact is provided through the second active layer, and may include a contact material electrically connecting the power voltage line, the second active layer, and the upper gate pattern from a lower portion.

Meanwhile, the first contact is provided through the first active layer, and may be formed of a contact material filled between layers between the lower gate pattern under the first active layer and the data line.

In another example, the substrate includes a plurality of pixels, the scan lines and the sensing lines, the first active layer and the second active layer, the data line, the first switching thin film transistor in each pixel; A driving thin film transistor and a second switching thin film transistor may be provided, and at a boundary between adjacent pixels, the reference voltage line or the power voltage line may overlap the data lines of the adjacent pixels with the same width at both sides.

The organic light emitting diode display of the present invention has the following effects.

That is, at least one of the reference voltage line RL and the power voltage line VDL disposed in the same direction may be located on a different layer from the data line and may contact or overlap the data line 111 in a plan view. , it is possible to achieve high pixel integration and high resolution of the device.

In particular, when the reference voltage line or the power voltage line is disposed on a layer different from the data line when the reference voltage line or the power supply voltage line and the data line are overlapped or adjacent to each other, the pattern is formed on the same layer as the gate electrode provided in the pixel. Alternatively, by placing it on the same layer as the light blocking layer, it is possible to apply a high-resolution structure without adding a separate mask or material.

As a result, a design margin and a degree of freedom are increased by removing the wiring area and the space between the wirings, thereby realizing an ultra-high resolution.

1 is a circuit diagram of a conventional organic light emitting display device;
2 is a circuit diagram of an organic light emitting diode display according to the present invention;
3 is a plan view illustrating an organic light emitting diode display according to a first exemplary embodiment of the present invention;
4A and 4B are cross-sectional views taken along line I~I' and line II~II' of FIG.
5 is a plan view of a comparative example compared with FIGS. 3 and 4A;
6 is a plan view illustrating an organic light emitting diode display according to a second exemplary embodiment of the present invention;
7A and 7B are cross-sectional views taken along lines III to III' and IV to IV' of FIG. 6;
8 is a plan view illustrating an organic light emitting diode display according to a third exemplary embodiment of the present invention;
9A and 9B are cross-sectional views showing the line V-V' and the line VI-VI' of FIG. 8;
10 is a plan view illustrating an organic light emitting diode display according to a fourth exemplary embodiment of the present invention;
11 is a cross-sectional view taken along line VII to VII' of FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the part names of the actual product.

2 is a circuit diagram of an organic light emitting diode display according to the present invention.

First, if one pixel of the organic light emitting diode display of the present invention is expressed as a circuit, as shown in FIG. 2 , a first switching thin film transistor SW1 is formed between a scan line SL and a data line DL crossing each other, and the The driving thin film transistor D-TFT connected between the first switching thin film transistor SW1 and the power voltage line VDL, and a second switching connected between the driving thin film transistor D-TFT and the reference voltage line RL A thin film transistor SW2, a first node A that is a connection point between the first switching thin film transistor SW1 and the driving thin film transistor D-TFT, and a connection point between the driving thin film transistor and a second switching thin film transistor and a storage capacitor Cst connected to the second node B, and an organic light emitting diode OLED provided between the second node B and a ground terminal. Here, a pixel region is defined between the scan line SL and the data line DL crossing each other, and the pixel region is disposed on a substrate (see 100 of FIG. 4A ) in a matrix form.

Meanwhile, the switching drain electrode SD1 of the first switching thin film transistor SW1 and the driving gate electrode DG of the driving thin film transistor D-TFT are connected to the first node A, and the second node A driving electrode pattern DD of the driving thin film transistor and a second switching drain electrode SD2 of the second switching thin film transistor are connected to (B).

In addition, each of the gate electrodes SG1 and SG2 of the first switching thin film transistor SW1 and the second switching thin film transistor SW2 is connected to the scan line SL and the sensing line SSL.

The first switching thin film transistor SW1 selects a pixel driven according to a first gate signal applied to the scan line SL, and the driving thin film transistor D-TFT is the first switching thin film transistor SW1 connected to to control the driving current of the selected pixel and supply it to the organic light emitting diode (OLED). In addition, the storage capacitor Cst maintains the voltage provided from the first switching thin film transistor SW1 for one frame so that the driving thin film transistor D-TFT maintains a constant voltage. To this end, the storage capacitor Cst is positioned between the driving gate electrode DG and the driving electrode pattern DD of the driving thin film transistor D-TFT. Here, the storage capacitor Cst is connected to the second switching thin film transistor SW2 so that while the second switching thin film transistor SW is turned on when the sense signal of the sensing line SSL is supplied, the reference voltage line RL The initialization voltage (the second gate signal) provided from the is provided to the second node B, which means that initialization is performed according to the application of the sensing signal from the sensing line SSL in a specific section.

Hereinafter, a detailed shape of a pixel of an organic light emitting diode display of the present invention will be described with reference to the drawings. What will be described below will describe the four embodiments, but the present invention is not limited thereto. In common, at least one of the reference voltage line RL and the power supply voltage line VDL is located on a different layer from the data line DL, It is located in contact with or overlapping the data line on a plane.

*First embodiment*

3 is a plan view illustrating an organic light emitting diode display according to a first embodiment of the present invention, and FIGS. 4A and 4B are cross-sectional views taken along lines I to I' and II to II' of FIG. 2 .

In the organic light emitting diode display according to the first embodiment of the present invention, a substrate 100 includes a plurality of pixels in a matrix, and scan lines (SL) 101 are disposed on the substrate 100 in a first direction. and a sensing line (SSL) 102, and a first active layer 131 and a second active layer that intersect with the scan line (SL) 101 and the sensing line (SSL) 102, respectively, and are spaced apart from each other. 132 , a data line 111 (DL), a reference voltage line RL disposed in a second direction intersecting the first direction, and intersecting the first and second active layers 131 and 132 ( 121), a power voltage line (VDL) 112 , and a first switching transistor SW1 receiving a first gate signal from the scan line SL and positioned between the data line DL and the first node A ), a gate signal is applied from the first node, and a driving thin film transistor (D-TFT) positioned between the power supply voltage line (VDL) 112 and the second node B and the second from the sensing line SSL and a second switching thin film transistor SW2 receiving a second gate signal and positioned between the second node B and the reference voltage line RL 121 .

And, in the first embodiment, the reference voltage line (RL) 121 is located on a different layer from the data line (DL) 111 and is positioned to contact or overlap the data line 111 in a plan view. do.

That is, when the reference voltage line and the data line are located on the same layer, a spacing of about 2 μm must be maintained to prevent a short circuit between the wires. In the first embodiment of the present invention, the reference voltage line ( 121) and the data line 111 are positioned on different layers so that they can be in contact with or overlap each other in a plan view.

Here, the first active layer 131 in which the first switching thin film transistor SW1 is defined has both ends of the data line DL 111 and the drain electrode 113 of the first switching thin film transistor SW1 and It has first and second contacts CT1 and CT2 connected thereto, and the second active layer 132 corresponds to both ends of the overlapping outer side of the gate electrode 141 of the driving thin film transistor D-TFT, and the one end of the third contact CT3 connected to the power supply voltage line (VDL) 112, the other end of the fourth contact CT4 connected to the source electrode 114 of the second switching thin film transistor SW2; It has a fifth contact CT5 connected to the reference voltage line RL 121 .

In addition, the reference voltage line (RL) 121 is positioned on a different layer from the data line 111 , is in contact with or overlaps the data line 112 , and is in contact with the data line (DL) 111 . It is a region between the power voltage lines (VDL) 112 and includes a protrusion 121a from the reference voltage line (RL) 121 .

Here, the fifth contact CT5 may have a shape in which the protrusion 121a is connected from the reference voltage line RL 121 to the drain electrode 115 of the second switching thin film transistor SW2 . The fifth contact CT5 passes through the drain electrode 115 of the second switching thin film transistor SW2 and the second active layer 132 and is connected to the lower protrusion 121 of the reference voltage line.

On the other hand, the first node corresponds to the second contact CT2, which is the drain electrode 113 of the first switching thin film transistor SW1 and the gate electrode 141 of the driving thin film transistor D-TFT. It may be connected by the sixth contact CT6 .

In the organic light emitting diode display according to the first exemplary embodiment of the present invention, the pixel structure as illustrated in each pixel is repeated, and the reference voltage line 121 and the data line 111 are located in planar contact with or overlapping each other to form a flat surface. , it is possible to achieve high integration by reducing the horizontal width occupied by one pixel, and accordingly, it is possible to increase the number of pixels arranged in a horizontal line, thereby realizing a higher resolution.

In addition, if the protrusion 121a from the reference voltage line overlaps the second active layer 132 without overlapping the data line 111 , the length of the protrusion 121a can be freely determined. A fifth contact CT5 is provided below the through hole by filling a contact material between the protrusion 121a of the reference voltage line and the drain electrode 115 of the second switching thin film transistor.

Looking through the cross-sectional views of FIGS. 4A and 4B, it is as follows.

A buffer layer 105 is formed on the substrate 100 , and a plurality of reference voltage lines 121 in one direction and a protrusion 121a protruding for each pixel therefrom are formed on the buffer layer 105 . A first interlayer insulating layer 107 is deposited to cover the reference voltage line 121 and the protrusion 121a thereof.

Next, a first active layer spaced apart from each other on the first interlayer insulating layer 107 and defining the first switching thin film transistor SW1 , the driving thin film transistor D-TFT, and the second switching thin film transistor SW2 , respectively 131 and the second active layer 132 are formed.

Next, the gate insulating layer 109 is formed to cover the first and second active layers 131 and 132 .

Then, a scan line (SL) 101 and a sensing line 102 parallel to each other are formed for each pixel in a direction that covers the gate insulating layer 109 and intersects the reference voltage line, and at the same time has an island shape. to form the driving gate electrode 141 .

Here, the scan line 101 , the sensing line 102 , and the driving gate electrode 141 function as gate electrodes of each of the thin film transistors SW1 , SW2 , and D-TFT, and are located below each gate electrode. Channel regions 131a and 132a are provided in portions of the first and second active layers 131 and 132 . In addition, in the first and second active layers 131 and 132 immediately outside the scan line 101 , the sensing line 102 , and the driving gate electrode 141 , low-concentration impurity regions (LDDs) 131b and 132b, respectively. is provided, and high-concentration impurity regions 131c and 132c are provided on the outer side thereof. These are first formed by using the scan line 101, the sensing line 102, and the driving gate electrode 141 as masks to form the low-concentration impurity regions 131b and 132b, and then using a separate mask to form the low-concentration impurity regions ( The high-concentration impurity regions 131c and 132c may be formed by covering the 131b and 132b, or may be performed in the reverse order.

A second interlayer insulating layer 117 is provided to cover the scan line SL 101 and the sensing line 102 , and the reference voltage line RL ( A data line (DL) 111 and a power voltage line (VDL) 112 are provided in the same direction as the 121 .

Here, before forming the data line (DL) 111 and the power voltage line (VDL) 112 of the same layer, the lower second interlayer insulating layer 117 and the first and second active layers 131 and 132 are formed. , the gate insulating layer 109 and the first interlayer insulating layer 107 are selectively removed to form contact holes for the first to fifth contacts CT1, CT2, CT3, CT4, and CT5, and the data line and When the power voltage line is formed, a material forming the same is filled in the contact hole, and the second interlayer insulating layer 117 is selectively removed to form the data line DL and the power voltage line VDL 112 at the same time. , the drain electrode 113 of the first switching thin film transistor SW1 is formed, and the source electrode 114 and the drain electrode 115 of the second switching thin film transistor are formed.

Here, in the first to fifth contacts CT1 , CT2 , CT3 , CT4 , and CT5 , the material filled in each contact hole is of the same material as the data line 111 , and is located between the layers and is formed between the upper data line and the data line 111 . The metal of the same layer and the lower reference voltage line 121 and the material of the same layer are connected.

In addition, the reference voltage line 121 may be made of the same material as the light blocking layer closest to the buffer layer 105 , and in this case, a separate mask increase is not required.

Looking at the interlayer structure from the first contact CT1 to the fifth contact CT5, the first contact CT1 is connected to the first active layer 131 and the data line 111. In this case, two A second interlayer insulating layer 117 and a gate insulating layer 109 are sequentially provided between the layers from above, and the second interlayer insulating layer 117 and the gate insulating layer 109 are selectively removed from the first contact CT1 region. Also, the first active layer 131 in the region of the first contact CT1 is also removed, and the first active layer 131 is substantially over-etched to the first interlayer insulating layer 107 by the contact material in the removed contact hole. The layer 131 is connected between layers and is electrically connected to the data line 111 .

In addition, the second contact CT2 is the second interlayer insulating layer 117 and the gate insulating layer selectively removed from the top in the same manner as the first contact CT1 from the drain electrode 113 of the first switching thin film transistor. Interlayer connection with the first active layer 131 is performed by a contact material provided in the contact hole through the contact hole provided in the 109 and the first active layer 131 and the over-etched first interlayer insulating layer 107 .

In addition, the drain electrode 113 of the first switching thin film transistor SW1 and the gate electrode 141 of the driving thin film transistor are connected to each other through a sixth contact CT6 for connection to each other at the first node A. do. Although not shown in the cross-sectional view, the gate electrode 141 of the driving thin film transistor is made of the same layer of metal as the scan line 101 and the sensing line 102 , and thus the contact provided in the second interlayer insulating layer 117 . A connection between the gate electrode 141 of the driving thin film transistor and the drain electrode 113 of the first switching thin film transistor is possible through the hole.

The driving thin film transistor D-TFT is connected to the power supply voltage line 112 through a third contact CT3 , which is possible by a connection between the second active layer 132 and the power supply voltage line 112 . . Similarly, the first interlayer insulating layer 107 under the second active layer 132 is overetched, so that the power voltage line 112 is connected to the second interlayer insulating layer 117 , the gate insulating layer 109 , and the second active layer. Interlayer connection with the second active layer 132 may be achieved through a contact hole provided in the layer 132 and the first interlayer insulating layer 107 .

The fourth contact CT4 is provided in an island shape to be spaced apart from the gate electrode 141 of the driving thin film transistor D-TFT, and in the same manner as the drain electrode 113 of the first switching thin film transistor SW1 , the first The connection electrode 114 is a contact provided in the second interlayer insulating layer 117 , the gate insulating layer 109 and the second active layer 132 , and the overetched first interlayer insulating layer 107 which are selectively removed in order from the top. The second active layer 132 is interlayer-connected with the second active layer 132 by a contact material provided in the contact hole through the hole.

In the fifth contact CT5 , the second connection electrode 115 penetrates to the protrusion 121a of the reference voltage line on the buffer layer 105 . 109 , the second connection electrode 115 is connected to the protrusion 121a of the reference voltage line through a contact hole provided in the second active layer 132 and the first interlayer insulating layer 107 .

Meanwhile, the fourth contact CT4 is a connection portion to the first electrode (anode) of the organic light emitting diode OLED, and the organic light emitting diode is connected to the fourth contact CT4 for each pixel and provided in the pixel. The organic light emitting diode includes a first electrode connected to the fourth contact CT4, an organic light emitting layer provided on the first electrode, and a second electrode (cathode) on the organic light emitting layer, and a bank is provided at the boundary of each pixel. A region in which the organic light emitting layer is formed may be divided. In addition, the second electrode may be formed on the entire surface without being patterned, to which a ground voltage may be applied.

5 is a plan view of a comparative example compared with FIGS. 3 and 4A.

As shown in FIG. 5 , when the data line DL and the reference voltage line RL are positioned on the same layer, a gap 'a' is required to prevent a short between the two wires. In the industry, it was difficult to reduce this number to about 2㎛ or less due to the process margin and the prevention of parasitic caps between adjacent wirings.

In the organic light emitting diode display of the present invention, a reference voltage line or a power supply voltage line is arranged with a metal layer different from that of the data line, so that metals of different layers overlap or come into contact with each other in the same direction but in planar contact, which is required to provide a pixel. It is possible to reduce the unit pitch of pixels by reducing the spacing between the lines to be used, thereby increasing the number of pixels arranged on the same line to realize high resolution.

*Second embodiment*

6 is a plan view illustrating an organic light emitting diode display according to a second exemplary embodiment of the present invention, and FIGS. 7A and 7B are cross-sectional views taken along lines III to III′ and IV to IV′ of FIG. 6 .

6 to 7B , in the organic light emitting diode display according to the second exemplary embodiment of the present invention, the reference voltage line (RL) 221 is positioned on a different layer from the data line 211 , and the data line 211 ) and the reference voltage line 221 by a second connection electrode 216 that is a metal layer different from the data line 211 and the reference voltage line 221 in the fifth contact CT5 . ) is connected to the second active layer 232 , and the remaining second to fourth contacts CT2 to CT4 may have the same shape as in the above-described first embodiment.

Meanwhile, in the fifth contact CT5 , the second active layer 232 is connected to the second active layer 232 , and a metal of a layer different from that of the data line 211 and the reference voltage line 221 is formed in the second active layer 232 . ) is the second connection electrode 216 having an upper gate pattern provided on the upper side.

7B , in the fifth contact CT5 , a contact material electrically connecting the reference voltage line 221 , the second active layer 231 and the second connection electrode 216 from the bottom is included. do.

Meanwhile, considering that the first contact CT1 is over-etched in the process of forming the contact, the first active layer is used to prevent a short circuit with the reference voltage line 221 adjacent to the planar surface. A second interlayer insulating film 117 between the data line 211 and the lower gate pattern 214 through a lower gate pattern 241 below the reference voltage line 221 and above the reference voltage line 221 , a gate insulating film (109), a contact hole penetrating through the first active layer 231 and the third interlayer insulating film 227 is connected.

The second connection pattern 216 is the same layer as the scan line and the sensing line in the first embodiment described above, and a lower gate pattern 241 is further provided. The lower gate pattern 241 is provided on the 107 , and a third interlayer insulating layer 227 is further provided to cover the lower gate pattern 241 , and the first and second active layers 231 are formed on the third interlayer insulating layer 227 . , 232) are provided.

The advantage compared to the above-described first embodiment is that the storage capacitor generated between the first node A and the second node B does not have a separate area on the pixel, and the gate electrode 213 of the thin film transistor is driven as an interlayer. is formed as an upper gate pattern that is the same layer as the scan line and the sensing line, and the first storage electrode 242 is formed on the same layer as the lower gate pattern 241 in an overlapping form to overlap the first storage electrode 242 ) and the second storage electrode 222 on the same layer as the reference voltage line 221 overlapping the same on the lower side of the storage capacitor, sufficient storage capacitance may be secured without increasing the area of the pixel.

Here, in the second contact CT2, the drain electrode 242 of the first switching thin film transistor SW1 is connected at the first node A of the first active layer 231, and at the same time, the driving thin film transistor ( D-TFT) connected from the side to the gate electrode 213, the drain electrode 242, the first active layer 231, and the driving thin film of the first switching thin film transistor S1 sequentially from the bottom between the insulating films A gate electrode 213 of the transistor is connected.

Meanwhile, in the above-described second exemplary embodiment, the gate pattern is positioned at the upper and lower portions with respect to the active layer. However, the organic light emitting diode display of the present invention is a top emission method, and regardless of the position of the gate pattern, the fourth contact The light emitting area is determined by the first electrode of the organic light emitting diode connected at CT4 and the organic light emitting layer formed thereon, and the provision of the upper and lower gate patterns is not a factor affecting the aperture ratio.

On the other hand, in this structure, the gate structure is an example of forming the upper and lower portions together based on the active layer. In this case, the upper and lower gate electrodes do not need to overlap, and it is good if they can overlap in the storage capacitor region, and a single layer is formed in the remaining area. It can be used in the above contact configuration as needed.

*Third embodiment*

8 is a plan view illustrating an organic light emitting diode display according to a third exemplary embodiment of the present invention, and FIGS. 9A and 9B are cross-sectional views illustrating lines V to V' and VI to VI' of FIG. 8 .

8 to 9B , the organic light emitting diode display according to the third exemplary embodiment has a layered structure similar to that of the above second exemplary embodiment, and only overlaps or is adjacent to the data line 321 in plan. The difference is that is used as the power supply voltage line 312 .

In this case, the power supply voltage line (VDL) 312 is located on a different layer from the data line 321 , is in contact with or overlaps the data line 321 in a planar manner, and is located in the third contact CT3 . The data line 321 and the power supply voltage line 312 are connected to the second active layer 332 by a metal layer different from that of the data line 321 and the power supply voltage line 312 .

In the third contact CT3 , a metal of a layer different from that of the data line 321 and the power voltage line 312 and connected to the second active layer 332 is on an upper side of the second active layer 332 . The upper gate pattern 303 provided in the Here, the upper gate pattern 303 is on the same layer as the scan line 301 and the sensing line 302 . In addition, the third contact CT3 is provided through the second active layer 332 , and connects the power voltage line 312 , the second active layer 332 , and the upper gate pattern 303 from the bottom. It may include a contact material that electrically connects. Such a contact material is created by filling the contact hole with an upper gate material in the process of forming the upper gate pattern 303 after forming the contact hole of the insulating layers between the upper gate pattern 303 and the power voltage line 312, Accordingly, the upper gate pattern 303 and the contact material may be the same material.

In this third embodiment, the first contact CT1 is provided to pass through the first active layer 331 , the lower gate pattern 341 under the first active layer 331 , and the It may be formed of a contact material filled between layers between the data line 321 and the data line 321 .

Meanwhile, the organic light emitting diode display according to the above-described first to third exemplary embodiments shows a method of reducing the spacing between wirings passing in a vertical direction when each pixel has the same shape. However, by symmetrically configuring adjacent pixels, , it is also possible to obtain the same effect. This will be explained in the fourth embodiment.

*Fourth embodiment*

10 is a plan view illustrating an organic light emitting diode display according to a fourth exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line VII to VII' of FIG. 10 .

10 to 11 illustrate a fourth embodiment of the present invention, the power voltage line 411 is common to both adjacent pixels, and the data lines DL and DL' supplying image data of each pixel. ) shows a structure in which the power voltage line 411 is disposed to overlap with the same width on both sides of the power supply voltage line 411 .

In the structure of the fourth embodiment of the present invention, since one power supply voltage line 411 is shared in both pixels, there is an advantage of reducing wiring and simultaneously connecting the data lines of both pixels adjacent to the power supply voltage line 411. Due to the overlapping structure, it is possible to reduce the spacing between wirings by two times or more compared to the structure described with reference to FIGS. 4A to 4B .

The substrate 100 on which the fourth embodiment is implemented includes a plurality of pixels, and the scan line (SL) 401 and the sensing line (SSL) 402, a first active layer 421 and a second active layer 422, the data line DL or DL', the first switching thin film transistor SW1, a driving thin film transistor D-TFT, and a second switching thin film transistor SW2 are provided; At the boundary between adjacent pixels, the reference voltage line 441 or the power voltage line 411 may overlap the data lines DL and DL′ of the adjacent pixels with the same width at both sides.

In this fourth embodiment of the present invention, the first to second switching thin film transistors SW1 and SW2 and the driving thin film transistor D-TFT between the data line and the reference voltage line are formed in the first to third embodiments described above. See configuration according to example.

Meanwhile, in the present invention, the reference voltage line or the power supply voltage line overlapping or in planar contact with the data line is a wire to which a constant voltage is applied. With the raw data line on the upper side and the reference voltage line or the power supply voltage line on the lower side, the space between the layers is kept far to prevent overlapping or interference of adjacent parts.

In addition, interference between a reference voltage line and a power supply voltage line overlapping the data line in a planar manner can be prevented by using an interlayer insulating film having a high dielectric constant.

On the other hand, the reference voltage line or the power supply voltage line overlapping or in planar contact with the data line is formed below the data line and the active layer. may be limited, and in this case, it is preferable that a line to which a constant voltage is applied is provided below the active layer in order to have no abnormality in driving even when a high-resistance material is used as a limited metal.

However, this is a consideration from a manufacturing point of view, and even if the data line and the reference voltage line or the power voltage line are adjacent to each other in plan, three to four or more interlayer insulating films are interposed therebetween. In addition, even when the separation is considered to prevent the effect of interference, the level of the planar separation interval compared to the comparative example will be within 1 μm, and compared to the comparative example, the pitch between pixels can be significantly reduced proportionally, It is much more advantageous in terms of high resolution.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is understood that various substitutions, modifications and changes can be made without departing from the technical spirit of the present invention. It will be clear to those of ordinary skill in the art.

100: substrate 101: scan line
102: sensing line 105: buffer layer
107: first interlayer insulating film 109: gate insulating film
111: data line 112: driving voltage line
117: second interlayer insulating film 121: reference voltage line
131: first active layer 132: second active layer
141: driving gate electrode 227: third interlayer insulating film

Claims (15)

a scan line and a sensing line disposed in a first direction on the substrate; and
a data line, a reference voltage line, and a power supply voltage line disposed in a second direction intersecting the first direction and intersecting the first and second active layers;
At least one of the reference voltage line and the power supply voltage line is positioned on a different layer from the data line to contact or overlap the data line in a plan view. The method of claim 1,
a first active layer and a second active layer intersecting the scan line and the sensing line, respectively, and spaced apart from each other;
a first switching transistor receiving a first gate signal from the scan line and positioned between the data line and a first node;
a driving thin film transistor receiving a gate signal from the first node and positioned between the power supply voltage line and a second node; and
and a second switching thin film transistor receiving a second gate signal from the sensing line and positioned between the second node and the reference voltage line. 3. The method of claim 2,
the first active layer has first and second contacts, both ends of which are connected to the data line and a drain electrode of the first switching thin film transistor;
The second active layer corresponds to both ends of the outer side where the gate electrode of the driving thin film transistor overlaps, one end of which is connected to a third contact connected to a power supply voltage line, and the other end is connected to the source electrode of the second switching thin film transistor. An organic light emitting diode display having a fourth contact and a fifth contact connected to the reference voltage line. 4. The method of claim 3,
the reference voltage line is positioned on a different layer from the data line, and is in contact with or overlaps the data line in a planar manner;
An organic light emitting diode display having a protrusion from the reference voltage line as a region between the data line and the power voltage line. 5. The method of claim 4,
The fifth contact is an organic light emitting diode display connected to a protrusion from the reference voltage line and a drain electrode of the second switching thin film transistor. 4. The method of claim 3,
In the first node, a drain electrode of the switching thin film transistor and a gate electrode of the driving thin film transistor are connected to each other. 4. The method of claim 3,
the reference voltage line is positioned on a different layer from the data line, and is in contact with or overlaps the data line in a planar manner;
In the fifth contact, the reference voltage line is connected to the second active layer by a metal layer different from that of the data line and the reference voltage line. 8. The method of claim 7,
In the fifth contact, the organic light emitting diode display is connected to the second active layer, and a metal of a layer different from that of the data line and the reference voltage line is an upper gate pattern provided on an upper side of the second active layer. 9. The method of claim 8,
and a contact material electrically connecting the reference voltage line, the second active layer, and the upper gate pattern from a lower portion in the fifth contact. 8. The method of claim 7,
The first contact is provided through the first active layer,
An organic light emitting diode display comprising a contact material filled between layers between the lower gate pattern under the first active layer and the data line. 4. The method of claim 3,
the power supply voltage line is positioned on a different layer from the data line, and is in contact with or overlaps the data line in a planar manner;
In the third contact, the power supply voltage line is connected to the second active layer by a metal layer different from the data line. 12. The method of claim 11,
In the third contact, the organic light emitting diode display is connected to the second active layer, and a metal of a layer different from that of the data line and the power voltage line is an upper gate pattern provided on an upper side of the second active layer. 13. The method of claim 12,
The third contact is provided through the second active layer,
An organic light emitting diode display including a contact material electrically connecting the power voltage line, the second active layer, and the upper gate pattern from a bottom side. 12. The method of claim 11,
The first contact is provided through the first active layer,
An organic light emitting diode display comprising a contact material filled between layers between the lower gate pattern under the first active layer and the data line. 3. The method of claim 2,
The substrate includes a plurality of pixels,
The scan line and the sensing line, the first active layer and the second active layer, the data line, the first switching thin film transistor, a driving thin film transistor, and a second switching thin film transistor are provided in each pixel;
An organic light emitting diode display in which the reference voltage line or the power supply voltage line overlaps data lines of adjacent pixels with the same width at both sides at a boundary between adjacent pixels.

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