KR102059950B1 - Electroluminescent Display Device - Google Patents

Abstract

In the electroluminescent display device according to an embodiment of the present invention, the vertical lines of the data line / power line are disposed on the same layer as the light blocking layer of the lowermost layer, and the horizontal lines of the gate line are the same layer as the gate electrode or the source / drain electrode. By arrange | positioning to a layer, the short circuit defect which arises at the intersection of a vertical wiring and a horizontal wiring can be prevented.
In addition, an electroluminescent display device according to an embodiment of the present invention adds a transparent layer to an opaque wiring to apply a two-layer structure of a transparent layer and an opaque layer to a circuit, and at the same time, an opening is disposed only with a transparent layer or a transparent layer is disposed at an opening. The wiring of the circuit portion can be expanded in a layer different from that of the transparent layer of the opening. As a result, a design area can be secured, which is advantageous for improving the aperture ratio.

Description

Electroluminescent Display Device

The present invention relates to an electroluminescent display, and more particularly, to an electroluminescent display capable of realizing a high opening ratio in a high resolution model.

At the present time, the field of display devices for visually displaying electrical information signals has been rapidly developed, and researches for developing performances such as thinning, weight reduction, and low power consumption for various display devices continue.

Typical display devices include Liquid Crystal Display (LCD), Field Emission Display (FED), Electro-Wetting Display (EWD), and Organic Light Emitting Display (Organic). Light Emitting Display Device (OLED), etc. can be mentioned.

Among them, the electroluminescent display device, which is a display device including an organic light emitting display device, is a self-luminous display device. Unlike a liquid crystal display device, an electroluminescent display device does not need a separate light source, and thus, a light weight display device can be manufactured. In addition, the electroluminescent display is not only advantageous in terms of power consumption by low voltage driving, but also excellent in color implementation, response speed, viewing angle, contrast ratio (CR), and is expected to be used in various fields. It is becoming.

An electroluminescent display is constructed by disposing a light emitting layer using an organic material between two electrodes, referred to as an anode and a cathode. When holes are injected from the anode into the light emitting layer and electrons from the cathode are injected into the light emitting layer, the injected electrons and holes are recombined with each other to form excitons in the light emitting layer and emit light. do.

The light emitting layer includes a host material and a dopant material so that interaction between the two materials occurs. The host is responsible for generating excitons from electrons and holes and transferring energy to the dopant, and the dopant is a dye organic material to which a small amount is added, and receives energy from the host and converts it into light.

In order to increase the size of the display device and to realize high resolution, it is necessary to secure a high opening ratio, and there is a problem of a gate redundancy pattern for repairing a short circuit defect between the horizontal wiring of the gate line and the vertical wiring of the data line / power line. It is becoming.

This is because the intersection between the horizontal wiring and the vertical wiring has only an interlayer insulating layer interposed therebetween, causing electrostatic defects due to a short separation distance, short circuit caused by foreign matter between the wiring of the horizontal wiring and the vertical wiring, or insulation on the gate line. Defects may occur due to the state of the layer, and a structure for repair has to be designed in the pixel to improve the yield. As a result, the gate redundancy pattern is applied to the position where the horizontal wiring and the vertical wiring cross each other. As the gate redundancy pattern is formed to occupy a predetermined area above and below the gate line, the gate redundancy pattern becomes a factor of reducing the aperture ratio in the pixel, and it is difficult to design the pixel in the high resolution model due to the addition of the gate redundancy pattern in the pixel.

The inventors of the present invention are susceptible to short circuit defects because only the interlayer insulating layer is interposed between the horizontal wiring and the vertical wiring, and the short circuit failure is affected by the distance between the wirings, and the thickness of the interlayer insulating layer. It is difficult to increase the thickness because it depends on the capacitor capacity. However, the gate insulation layer can increase its thickness regardless of the capacitor capacity. An interlayer insulating layer and a buffer layer or two insulating layers of a gate insulating layer and a buffer layer are interposed between the and the horizontal wiring to prevent a short circuit failure.

Accordingly, an object of the present invention is to provide an electroluminescent display device capable of realizing a high opening ratio by preventing a short circuit defect occurring between a vertical wiring and a horizontal wiring without a gate redundancy pattern.

On the other hand, in the case of a bottom emission structure, the opening area should be transparent, and therefore, in order to secure a high opening ratio in a large screen electroluminescent display such as a TV, there should be no opaque electrodes or wirings in the opening.

In the past, it was difficult to secure the aperture ratio at the same time as securing the design area in the high-resolution model because the opening must be separated from the opaque wiring of the circuit part.

The inventors of the present invention, in view of the fact that when the transparent layer is applied to the electrode or the wiring adjacent to the opening can be expanded than before, by adding a transparent layer to the opaque wiring of the circuit portion, a two-layer structure of the transparent layer and the opaque layer in the circuit portion At the same time, the present invention invents a structure in which the aperture ratio can be improved by arranging only the transparent layer in the opening or by arranging the transparent layer in the opening and at the same time as the wiring of the circuit part in a layer different from the transparent layer of the opening. In this case, the gate line or the data line may be excluded as the wiring adjacent to the opening in consideration of the resistance. In addition, when the transparent wiring includes the gate line in the circuit part, a two-layer structure of a transparent layer and an opaque layer should be applied to reduce the resistance. To this end, the inventors of the present invention used a half-tone mask.

Accordingly, an object of the present invention is to provide an electroluminescent display device capable of realizing a high aperture ratio while securing a design area without increasing the number of masks in a high resolution model.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, an electroluminescent display device according to an exemplary embodiment of the present invention includes a data line disposed in a first direction on a substrate and a data line disposed in a second direction crossing the first direction. A gate line for dividing the pixel region, a thin film transistor disposed in a circuit portion of the pixel region, at least one wiring for transmitting various signals to the circuit portion, a light emitting element disposed in the light emitting portion of the pixel region, and a bank disposed to surround the light emitting portion The wiring may be disposed to pass through the light emitting part, and may be configured of a first layer of a transparent layer, and the bank may expose the first layer of the wiring.

In accordance with another aspect of the present invention, an electroluminescent display device includes a data line disposed in a first direction on a substrate, and a data line disposed in a second direction crossing the first direction. A gate line that partitions the pixel region together, a power line arranged in one or more pixel regions in a direction parallel to the first direction, a thin film transistor disposed in a circuit portion of the pixel region, and a thin film transistor connected to the power line to a neighboring pixel region And a light emitting element disposed in the light emitting portion of the pixel region, the bridge wiring transferring at least a power supply voltage, wherein the bridge wiring is disposed to pass through at least the light emitting portion, and comprises a first layer of a transparent layer in the light emitting portion to extend the pixel region. Can be.

Specific details of other embodiments are included in the detailed description and drawings.

The present invention provides a high-resolution model by adding a transparent layer to an existing opaque wiring using a half-tone mask to apply a two-layer structure of a transparent layer and an opaque layer to a circuit and simultaneously design a transparent layer in an opening. The area can be secured. Accordingly, in the high resolution and large screen model, the average aperture ratio is improved by 3% or more without increasing the number of masks.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a pixel included in an electroluminescent display device according to an exemplary embodiment of the present invention.
3 is a plan view schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.
4A and 4B are schematic views illustrating a cross-sectional structure of an electroluminescent display device according to an exemplary embodiment of the present invention shown in FIG. 3.
5 is a plan view schematically illustrating an electroluminescent display of a comparative example.
6 is a schematic cross-sectional view of an electroluminescent display device according to a comparative example illustrated in FIG. 5.
7A illustrates a cross-sectional structure of intersection points between lines in an electroluminescent display device according to a comparative example.
FIG. 7B is a diagram illustrating a cross-sectional structure of intersection points between lines in an electroluminescent display according to an exemplary embodiment of the present invention.
8 is a plan view schematically illustrating an electroluminescent display device according to another exemplary embodiment of the present invention.
9A and 9B are schematic views illustrating a cross-sectional structure of an electroluminescent display device according to another exemplary embodiment of the present invention illustrated in FIG. 8.

Advantages and features of the present invention, and methods for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated items. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'comprises', 'haves', 'consists of' and the like mentioned in the present specification, other parts may be added unless 'only' is used. In case of singular reference, the plural number includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upon', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

When an element or layer is referred to as another element or layer includes both instances of intervening another layer or element directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated configuration.

Each of the features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, various technically interlocking and driving as can be understood by those skilled in the art, each of the embodiments may be implemented independently of each other It may be possible to carry out together in an association.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an electroluminescent display device 100 according to an exemplary embodiment of the present invention may include a display panel 110, a data driver integrated circuit (IC) 130, a gate driver integrated circuit 150, The image processor 170 and the timing controller 180 may be configured to be included.

The display panel 110 may include a plurality of sub-pixels 160. The plurality of sub-pixels 160 may be arranged in a row direction and a column direction to be arranged in a matrix form. For example, as shown in FIG. 1, the plurality of sub-pixels 160 may be arranged in m rows and n columns. Hereinafter, for convenience of description, a group of sub-pixels 160 arranged in a row direction among the plurality of sub-pixels 160 is defined as a row sub-pixel, and a group of sub-pixels 160 arranged in a column direction is defined. Defined as column sub-pixels.

Each of the plurality of sub-pixels 160 may implement light of a specific color. For example, the plurality of sub-pixels 160 may be composed of a red sub-pixel that implements red, a green sub-pixel that implements green, and a blue sub-pixel that implements blue. In this case, a group of red sub-pixels, green sub-pixels, and blue sub-pixels may be referred to as one pixel.

The plurality of sub-pixels 160 of the display panel 110 may be connected to the gate lines GL1 to GLm and the data lines DL1 to DLn, respectively. For example, one row sub-pixel may be connected to the first gate line GL1 and one column sub-pixel may be connected to the first data line DL1. Also, the 2 to m row sub-pixels may be connected to the second to m th gate lines GL2 to GLm, respectively. The 2 to n column sub-pixels may be connected to the second to n th data lines DL2 to DLn, respectively. The plurality of sub-pixels 160 may be configured to operate based on gate voltages transferred from the gate lines GL1 to GLm and data voltages transferred from the data lines DL1 to DLn.

The image processor 170 may output a data enable signal DE together with a data signal (image data) DATA supplied from the outside. The image processor 170 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE.

The timing controller 180 may receive various timing signals including the vertical synchronization signal, the horizontal synchronization signal, the data enable signal DE, and the clock signal together with the data signal DATA from the image processor 170. The timing controller 180 receives the data signal DATA, that is, the input image data from the image processor 170, converts the data signal DATA into a data signal format that can be processed by the data driving integrated circuit 130, and then converts the data signal DATA, That is, in addition to outputting output image data, in order to control the data driver integrated circuit 130 and the gate driver integrated circuit 150, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal DE, a clock signal, and the like. In response to the timing signal, various control signals DCS and GCS may be generated and output to the data driver integrated circuit 130 and the gate driver integrated circuit 150.

For example, the timing controller 180 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal to control the gate driving integrated circuit 150. Various gate control signals GCS including a gate output enable (GOE) may be output.

Here, the gate start pulse may control operation start timing of one or more gate circuits constituting the gate driving integrated circuit 150. The gate shift clock is a clock signal commonly input to one or more gate circuits, and may control shift timing of a scan signal (gate pulse). The gate output enable signal specifies timing information of one or more gate circuits.

In addition, the timing controller 180 may control a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (Source SC) to control the data driving integrated circuit 130. Various data control signals DCS including an output enable (SOE) may be output.

Here, the source start pulse may control the data sampling start timing of one or more data circuits constituting the data driving integrated circuit 130. The source sampling clock is a clock signal that controls the sampling timing of data in each of the data circuits. The source output enable signal may control the output timing of the data driver integrated circuit 130.

The gate driving integrated circuit 150 sequentially supplies a scan signal of an on voltage or an off voltage to the gate lines GL1 to GLm according to the control of the timing controller 180, thereby providing a gate line GL1. To GLm) can be driven sequentially.

The gate driving integrated circuit 150 may be located on only one side of the display panel 110, or in some cases, on both sides of the gate driving integrated circuit 150.

The gate driving integrated circuit 150 may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) or chip on glass (COG) method, or may be a gate in panel (GIP). It may be implemented as a type and disposed directly on the display panel 110, and in some cases, may be integrated and disposed on the display panel 110.

The gate driving integrated circuit 150 may include a shift register, a level shifter, and the like.

When the specific gate line is opened, the data driving integrated circuit 130 converts the output image data DATA received from the timing controller 180 into an analog data voltage and supplies the data to the data lines DL1 to DLn. The lines DL1 to DLn can be driven.

The data driving integrated circuit 130 may be connected to the bonding pad of the display panel 110 by a tape automated bonding method or a chip on glass method, or may be disposed directly on the display panel 110. It may be integrated with the arrangement 110.

The data driving integrated circuit 130 may be implemented by a chip on film (COF) method. In this case, one end of the data driving integrated circuit 130 may be bonded to at least one source printed circuit board, and the other end may be bonded to the display panel 110.

The data driving integrated circuit 130 may include a logic unit including various circuits such as a level shifter and a latch unit, a digital analog converter (DAC), an output buffer, and the like.

The detailed structure of the pixel 160 will be described with reference to FIGS. 2 and 3.

2 is a circuit diagram of a pixel included in an electroluminescent display device according to an exemplary embodiment of the present invention. Hereinafter, for convenience of description, a structure and an operation thereof when the electroluminescent display device according to an embodiment of the present invention is a pixel circuit of 2T (Transistor) 1C (Capacitor) will be described, but the present invention is not limited thereto. .

Referring to FIG. 2, in the electroluminescent display device 100 according to an exemplary embodiment of the present invention, one pixel includes a switching transistor ST, a driving transistor DT, a compensation circuit (not shown), and the like. It may be configured to include a light emitting device (LE).

The light emitting device LE may operate to emit light according to a driving current formed by the driving transistor DT.

The switching transistor ST may perform a switching operation such that a data signal supplied through the data line 116 is stored as a data voltage in the capacitor C in response to a gate signal supplied through the gate line 117.

The driving transistor 113 may operate so that a constant driving current flows between the high potential power line VDD and the low potential power line VSS in response to the data voltage stored in the capacitor 112.

Here, the compensation circuit is a circuit for compensating the threshold voltage of the driving transistor DT and the like, and may include one or more thin film transistors and a capacitor. The configuration of the compensation circuit can vary greatly depending on the compensation method.

As described above, in the electroluminescent display device 100 according to an exemplary embodiment of the present invention, one pixel includes a switching transistor ST, a driving transistor DT, a capacitor C, and a light emitting device LE. 2T1C structure, but when the compensation circuit is added may be variously configured as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C and the like.

3 is a plan view schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention. 4A and 4B are schematic views illustrating a cross-sectional structure of an electroluminescent display device according to an exemplary embodiment of the present invention shown in FIG. 3.

3 illustrates a planar structure of one pixel in the electroluminescent display device 100 according to an exemplary embodiment of the present invention. For convenience of description, FIG. 3 illustrates a case in which a 2T1C structure including a switching transistor ST, a driving transistor DT, a capacitor C, and a light emitting element LE is illustrated as an example. As described above, when the compensation circuit is added, it may be variously configured as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.

4A illustrates a circuit part CA including a driving transistor DT and a capacitor, and a light emitting device LE in the electroluminescent display device 100 according to an exemplary embodiment of the present invention illustrated in FIG. 3. A portion of the light emitting portion EA and the intersection portion IA of the gate line 117 and the data line 116 are illustrated as an example. FIG. 4B illustrates a part of a circuit CA including a switching transistor ST in the electroluminescent display 100 according to the exemplary embodiment of FIG. 3.

3, 4A, and 4B, the electroluminescent display device 100 according to an exemplary embodiment of the present invention includes a gate line (or scan line) 117 and a data line 116 on the substrate 110. And the power line (or power voltage line) 119 may cross each other to partition the pixel area AA. In addition, a sensing control line and a reference line may be further disposed.

The data line 116 and the power line 119 may be disposed on the substrate 110 in a first direction. The gate line 117 may be disposed in a second direction crossing the first direction to partition the pixel area AA together with the data line 116 and the power line 119. For convenience, one pixel area AA may be divided into a light emitting unit EA in which the light emitting device LE emits light, and a circuit unit CA including a plurality of driving circuits for supplying a driving current to the light emitting device LE.

The power line 119 may be disposed in one or more pixel areas AA, but the present invention is not limited thereto.

In addition, the reference line may be disposed on the same layer as the data line 116 and the power line 119 along the data line 116 and the power line 119 in the first direction.

The plurality of pixel areas AA may be formed of a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. In FIG. 3, only one sub-pixel area AA is shown as an example, but the present invention is not limited thereto. Each of the red, green, blue, and white sub-pixel areas AA includes a light emitting element LE and a plurality of pixel driving circuits that independently drive the light emitting element LE. The pixel driving circuit may include a switching transistor ST, a driving transistor DT, a capacitor C, and a sensing transistor (not shown).

The switching transistor ST is turned on when a scan pulse is supplied to the gate line 117 to convert the data signal supplied to the data line 116 into the first gate of the capacitor C and the driving transistor DT. The electrode 121 may be supplied. The switching transistor ST may include the second gate electrode 121 ′ connected to the gate line 117, the second source electrode 122 ′ connected to the data line 116 through the seventh contact hole, and the eighth contact hole. The second drain electrode 123 ′ and the second active layer 124 ′ connected to the first gate electrode 121 may be included.

Next, the driving transistor DT controls the current supplied from the power line 119 according to the driving voltage charged in the capacitor C, and supplies a current proportional to the driving voltage to the light emitting element LE, thereby providing a light emitting element ( LE) emits light. The driving transistor DT includes a first gate electrode 121 connected to the second drain electrode 123 ′ through a seventh contact hole, and a first source electrode connected to the power line 119 through a ninth contact hole. 122) and a first drain electrode 123 and a first active layer 124 connected to the light emitting device LE through the fifth contact hole.

The power line 119 may be connected to the first source electrode 122 of the neighboring pixel area AA through the bridge line 119a. The bridge line 119a may extend to the neighboring pixel area AA in a direction parallel to the second direction. As such, the bridge wire 119a extending to the neighboring pixel region AA may be connected to the first source electrode 122 of the neighboring pixel region AA through the tenth contact hole. However, the present invention is not limited thereto.

One side of the bridge wiring 119a may be connected to the power line 119 below the sixth contact hole 140.

The thin film transistor illustrated in FIG. 4A is a driving transistor DT, and a thin film transistor having a top gate structure, particularly a coplanar structure, in which the first gate electrode 121 is disposed on the first active layer 124. I'm holding it as an example. In addition, the thin film transistor illustrated in FIG. 4B is a switching transistor ST, and a thin film having a top gate structure, particularly a coplanar structure, in which the second gate electrode 121 'is disposed on the second active layer 124'. The transistor is taken as an example. However, the present invention is not limited thereto, and a thin film transistor having a bottom gate structure in which the gate electrode is disposed under the active layer is also applicable.

The first gate electrode 121 of the driving transistor DT may be interposed with the first active layer 124 via the gate insulating layer 115b having substantially the same shape as the first gate electrode 121. The second gate electrode 121 ′ of the switching transistor ST may overlap the second active layer 124 ′ through the gate insulating layer 115 b having substantially the same shape as the second gate electrode 121 ′. Can be.

In detail, the first active layer 124 and the second active layer 124 ′ may be disposed on the substrate 110.

In this case, the light blocking layer 125 may be disposed below the first active layer 124, and the buffer layer 115a may be disposed between the first active layer 124 and the light blocking layer 125.

The light blocking layer 125 may serve to block the first active layer 124 from being affected by the light of an external or surrounding light emitting device, and may be disposed on the lowermost layer of the substrate 110.

The light blocking layer 125 may serve to block the first active layer 124 from being affected by the light of an external or surrounding light emitting device, and may be disposed on the lowermost layer of the substrate 110.

The data line 116 and the power line 119 of the present invention may be disposed on the same layer as the light blocking layer 125 in the first direction. That is, the data line 116 and the power line 119 of the present invention are disposed on the lowermost layer of the substrate 110 together with the light blocking layer 125.

This is because the vertical wiring of the data line 116 and the power line 119 is disposed on a different layer from the existing layer, so that the interlayer is formed between the vertical wiring of the data line 116 and the power line 119 and the horizontal wiring of the gate line 117. At least two insulating layers, for example, the buffer layer 115a and the interlayer insulating layer 115c, not one layer of the insulating layer 115c are interposed to prevent a short circuit failure.

The buffer layer 115a may be disposed on the substrate 110 to cover the light blocking layer 125, the data line 116, and the power line 119.

Each of the first active layer 124 and the second active layer 124 'is formed to overlap the first gate electrode 121 and the second gate electrode 121' on the gate insulating layer 115b, and thus, the first active layer 124 and the second active layer 124 'are formed to overlap each other. Channels may be formed between the source electrode 122 and the first drain electrode 123 and between the second source electrode 122 'and the second drain electrode 123'.

The first active layer 124 and the second active layer 124 'may be formed using an oxide semiconductor including at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. It may be composed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor.

4A illustrates a case in which the gate insulating layer 115b is formed to be limited to the lower portion of the first gate electrode 121, but the present invention is not limited thereto. 4B illustrates a case in which the gate insulating layer 115b is formed to be limited to the lower portion of the second gate electrode 121 ′, but the present invention is not limited thereto. The gate insulating layer 115b may be formed on the entire surface of the substrate 110 on which the first active layer 124 and the second active layer 124 'are formed. In this case, the gate insulating layer 115b may have a first source electrode ( A contact hole for connecting each of the 122 and first drain electrodes 123 to the source and drain regions of the first active layer 124 may be formed. The gate insulating layer 115b also includes contact holes for connecting the second source electrode 122 'and the second drain electrode 123' to the source and drain regions of the second active layer 124 ', respectively. Can be formed.

The gate insulating layer 115b may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

The first gate electrode 121 and the second gate electrode 121 ′ may be formed of various conductive materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), and nickel ( Ni), neodymium (Nd), and copper (Cu), or two or more alloys, or multiple layers thereof.

An interlayer insulating layer 115c may be disposed on the first gate electrode 121 and the second gate electrode 121 ′.

The interlayer insulating layer 115c may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIGS. 4A and 4B, the interlayer insulating layer 115c may be formed over the entire surface of the substrate 110 or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The first source electrode 122, the first drain electrode 123, and the second source electrode 122 ′ are disposed on the interlayer insulating layer 115c on the first active layer 124 and the second active layer 124 ′, respectively. And a second drain electrode 123 'may be disposed. Each of the first source electrode 122 and the second source electrode 122 ′ may have a first active layer 124 and a second active layer through a first contact hole and a third contact hole penetrating the interlayer insulating layer 115c. Each of the first drain electrode 123 and the second drain electrode 123 'may be connected to the source region 124', and each of the second and fourth contact holes penetrating through the interlayer insulating layer 115c. The first and second active layers 124 and 124 ′ may be connected to drain regions of the first and second active layers 124 and 124 ′.

The second drain electrode 123 ′ of the switching transistor ST may extend in one direction and be electrically connected to the first gate electrode 121 of the driving transistor DT through a predetermined contact hole.

In an exemplary embodiment of the present invention, a gate line in a second direction is formed on the same layer of the first source electrode 122, the second source electrode 122 ′, and the first drain electrode 123 and the second drain electrode 123 ′. 117 may be disposed.

As described above, in the electroluminescent display device 100 according to the exemplary embodiment of the present invention, vertical lines of the data line 116 and the power line 119 are disposed on the substrate 110 in the first direction, and the gate line ( The horizontal wiring of 117 is disposed in a second direction crossing the first direction to partition the pixel area AA together with the vertical wiring.

In the electroluminescent display device 100 according to an exemplary embodiment of the present invention, the vertical lines of the data line 116 and the power line 119 are disposed on the same layer as the light blocking layer 125 of the lowermost layer, By arranging the horizontal wiring on the same layer as the first source electrode 122 / the first drain electrode 123, at least the interlayer insulating layer 115c between the vertical wiring and the horizontal wiring instead of one layer of the existing interlayer insulating layer 115c. ) And two insulating layers of the buffer layer 115a are interposed. As a result, it is possible to prevent a short circuit failure occurring at the intersection of the vertical wiring and the horizontal wiring.

That is, conventionally, a gate redundancy pattern must be formed to repair a short circuit failure between the horizontal wiring of the gate line and the vertical wiring of the data line / power line, and the intersection of the horizontal wiring and the vertical wiring is Since only the interlayer insulating layer is interposed therebetween, the electrostatic defect may occur due to the short distance, the short circuit caused by the foreign matter between the wiring of the horizontal wiring and the vertical wiring, or the failure of the insulating layer on the gate line. In order to improve the yield, a structure for repair had to be designed in the pixel. As a result, the gate redundancy pattern is applied to the position where the horizontal wiring and the vertical wiring cross each other. As the gate redundancy pattern is formed to occupy a predetermined area above and below the gate line, the gate redundancy pattern becomes a factor of reducing the aperture ratio in the pixel, and it is difficult to design the pixel in the high resolution model due to the addition of the gate redundancy pattern in the pixel.

Therefore, in one embodiment of the present invention, the intersection of the horizontal wiring and the vertical wiring is susceptible to short circuit failure because only the interlayer insulating layer 115c is interposed therebetween, and the short circuit failure is affected by the distance between the wirings. In this regard, the data line 116 and the power line 119 are arranged in different layers from each other so that at least two insulating layers of the interlayer insulating layer 115c and the buffer layer 115a are interposed between the horizontal wiring and the vertical wiring. It is configured so as to prevent a short circuit failure.

Accordingly, the intra-pixel gate redundancy pattern can be eliminated, thereby facilitating the pixel design in the high-resolution model, improving the yield, and providing an additional aperture ratio.

On the other hand, in the case of a bottom emission structure, the opening area should be transparent, and therefore, in order to secure a high opening ratio in a large screen electroluminescent display such as a TV, there should be no opaque electrodes or wirings in the opening.

In the past, it was difficult to secure the aperture ratio at the same time as securing the design area in the high-resolution model because the opening must be separated from the opaque wiring of the circuit part.

Therefore, according to an exemplary embodiment of the present invention, when the transparent layer is applied to an electrode or a wire adjacent to the opening, for example, the bridge wiring 119a, the opening A is referred to the existing opening (A 'of FIGS. 5 and 6 to be described later). In view of the fact that it is possible to expand the circuit, the opaque wiring of the circuit part CA, for example, the first source electrode 122, the second source electrode 122 ′, the first drain electrode 123, and the second drain electrode An aperture ratio can be improved by adding a transparent layer at 123 ', applying a two-layer structure of a transparent layer and an opaque layer to the circuit portion CA, and simultaneously arranging only the transparent layer in the opening A. FIG. In this case, the gate line 117 or the data line 116 may be excluded from the wiring adjacent to the opening A in consideration of resistance. In addition, when the transparent wiring, that is, the bridge wiring 119a includes the gate line 117 in the circuit portion CA, a two-layer structure of a transparent layer and an opaque layer should be applied to reduce the resistance. half tone masks may be used.

In other words, by using a half-tone mask, a transparent layer is added to the existing opaque wiring to apply a two-layer structure of the transparent layer and the opaque layer to the circuit part CA, and the opening A is disposed only in the transparent layer, thereby designing the high resolution model. Area can be secured. As a result, it is advantageous to improve the aperture ratio.

That is, in the exemplary embodiment of the present invention, the first source electrode 122, the second source electrode 122 ′, the first drain electrode 123, and the second drain electrode 123 ′ are formed on the same layer in the second direction. The bridge wiring 119a may be arranged in a parallel direction. The bridge wiring 119a is disposed to pass through the light emitting part EA and may be configured as a first layer of the transparent layer. On the other hand, in the bridge wiring 119a, the second layer of the opaque layer is stacked on the first layer of the transparent layer in the circuit part CA, and thus may be composed of at least two layers.

In an exemplary embodiment of the present invention, the gate line 117 is formed on the same layer as the first source electrode 122, the second source electrode 122 ′, and the first drain electrode 123 and the second drain electrode 123 ′. ) May be arranged. The gate line 117 may be formed of at least two layers by laminating a second layer of an opaque layer on the first layer of the transparent layer. For example, the gate line 117 may include a gate line 117a of the first layer, which is a transparent layer, and a gate line 117b of the second layer, which is an opaque layer.

In addition, the first source electrode 122, the second source electrode 122 ', and the first drain electrode 123 and the second drain electrode 123' also have a second layer of an opaque layer stacked on the first layer of the transparent layer. It can be composed of at least two layers. For example, the first source electrode 122 may be configured of the first source electrode 122a of the first layer, which is a transparent layer, and the first source electrode 122b of the second layer, which is an opaque layer. The first drain electrode 123 may include a first drain electrode 123a of a first layer, which is a transparent layer, and a first drain electrode 123b of a second layer, which is an opaque layer. In addition, the second source electrode 122 ′ may include a second source electrode 122 a ′ of the first layer as a transparent layer and a second source electrode 122 b ′ of the second layer as an opaque layer. The second drain electrode 123 'may include a second drain electrode 123a' of the first layer as a transparent layer and a second drain electrode 123b 'of the second layer as an opaque layer.

As described above, in one embodiment of the present invention, the bridge wiring 119a passing through the light emitting portion EA is composed of the first layer of the transparent layer, and the other configuration in the circuit portion CA of the same layer as the bridge wiring 119a is provided. They are characterized in that the second layer of the opaque layer is laminated on the first layer of the transparent layer. In this case, the light emitting part can be extended toward the circuit part, thereby effecting the effect of the opening A being substantially expanded.

As described above, although the thin film transistor has been described as having a coplanar structure, the thin film transistor may be implemented in another structure such as a staggered structure.

Next, the passivation layer 115d and the planarization layer 115e may be disposed on the thin film transistor. The passivation layer 115d protects the gate driver and other wirings disposed in addition to the thin film transistor and the pixel area AA, and the planarization layer 115e smoothes the step on the substrate 110 to planarize the top of the substrate 110. Can be formed to

In this case, the color filter layer may be disposed on the passivation layer 115d of the light emitting unit EA.

The protective layer 115d may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The protective layer 115d may be formed over the entire surface of the substrate 110 as shown in FIG. 4, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The planarization layer 115e may be made of an organic insulating material.

The planarization layer 115e includes acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene and photoresist. It may be formed of any one, but is not limited thereto.

The first drain electrode 123 may be connected to the anode 126 of the light emitting device LE through a fifth contact hole penetrating through the passivation layer 115d and the planarization layer 115e.

Referring to FIG. 4A, a light emitting device LE may be disposed on the planarization layer 115e. For example, the organic light emitting element LE may be formed on the planarization layer 115e and disposed on the anode 126 and the anode 126 connected to the first drain electrode 123 of the driving transistor DT. The light emitting layer 127 and the cathode 128 formed on the organic light emitting layer 127 may be included.

The anode 126 is disposed on the planarization layer 115e and may be electrically connected to the first drain electrode 123 through a fifth contact hole formed in the planarization layer 115e. The anode 126 may be made of a conductive material having a high work function to supply holes to the organic light emitting layer 127. The anode 126 is made of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like. Can be.

3 and 4A, for example, the anode 126 is illustrated as being electrically connected to the first drain electrode 123 of the driving transistor DT. However, the present invention is not limited thereto, and the type and driving of the thin film transistor are not limited thereto. The anode 126 may be electrically connected to the first source electrode 122 of the driving transistor DT by a circuit design scheme or the like.

The organic emission layer 127 is an organic layer for emitting light of a specific color, and may include any one of a red organic emission layer, a green organic emission layer, a blue organic emission layer, and a white organic emission layer. In addition, the organic emission layer 127 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. 3 and 4A, the organic emission layer 127 is patterned for each pixel, but the present invention is not limited thereto, and the organic emission layer 127 may be a common layer formed in common with a plurality of pixels.

The cathode 128 may be disposed on the organic emission layer 127. The cathode 128 may supply electrons to the organic emission layer 127. The cathode 128 is made of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) and tin. It may be made of a tin oxide (TO) -based transparent conductive oxide or an ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

4A and 4B, a bank 115f may be disposed on the anode 126 and the planarization layer 115e. The bank 115f may cover a portion of the anode 126 of the organic light emitting diode. The bank 115f may be arranged to distinguish adjacent pixels in the pixel area AA.

The bank 115f may be made of an organic insulating material. For example, the bank 115f may be made of polyimide, acryl, or benzocyclobutene (BCB) -based resin, but the present invention is not limited thereto.

The bank 115f may be disposed to surround the light emitting unit EA on the planarization layer 115e, and the bank 115f may be a wiring, for example, a light emitting unit EA in which the first layer of the bridge wiring 119a is located. Can be removed. That is, the bank 115f is removed from the light emitting portion EA in which the first layer of the bridge wiring 119a is located, and may overlap with the second layer of the bridge wiring 119a.

An encapsulation part (not shown) may be formed on the organic light emitting device configured as described above to protect the organic light emitting device vulnerable to moisture from being exposed to moisture. For example, the encapsulation portion may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

As described above, the present invention adds a transparent layer to an existing opaque wiring using a half-tone mask to apply a two-layer structure of a transparent layer and an opaque layer to a circuit portion, and at the same time arranges the transparent layer in an opening, thereby designing a region. Can be secured. Accordingly, in the high resolution and large screen model, the average aperture ratio is improved by 3% or more without increasing the number of masks.

5 is a plan view schematically illustrating an electroluminescent display of a comparative example. 6 is a schematic cross-sectional view of the electroluminescent display of the comparative example shown in FIG. 5.

At this time, the electroluminescent display of the comparative example shown in FIGS. 5 and 6 is substantially the same as the electroluminescent display according to the exemplary embodiment of the present invention except for the vertical wiring, the horizontal wiring, the bridge wiring, and the source / drain electrodes. It consists of a composition. Therefore, for the sake of convenience, the same reference numerals are used except for the preceding seat, and the description of the same components will be omitted.

5 and 6, in the electroluminescent display 10 of the comparative example, since the wiring adjacent to the light emitting part EA is opaque, such as the bridge wiring 19a, the bank 15f covers the bridge wiring 19a. It must be formed so that. As the bank 15f extends into the light emitting portion EA in which the bridge wiring 19a is located, the opening A 'is inevitably reduced.

That is, the bridge wiring 19a of a comparative example is comprised from the opaque layer similarly to the light shielding layer 25. FIG. In this case, the bank 15f can extend into the light emitting portion EA where the bridge wiring 19a is located because the opening A 'must be separated from the opaque wiring of the circuit portion CA, like the bridge wiring 19a. There is nothing else. Therefore, the opening A 'is inevitably reduced, and it is difficult to secure the opening ratio simultaneously with securing the design area in the high resolution model.

On the other hand, as described above, when the transparent wiring is applied to the wiring adjacent to the light emitting portion, such as the bridge wiring 119a, the opening A may be expanded than the opening A 'of the comparative example. . That is, a transparent layer is added to the opaque wiring of the circuit part CA, for example, the first source electrode 122 and the second source electrode 122 ', and the first drain electrode 123 and the second drain electrode 123'. By applying a two-layer structure of a transparent layer and an opaque layer to the circuit portion CA, the opening portion A can be expanded by arranging only the transparent layer in the opening portion A.

7A illustrates a cross-sectional structure of intersection points between lines in an electroluminescent display device according to a comparative example. 7B is a diagram illustrating a cross-sectional structure of intersection points between lines in an electroluminescent display according to an exemplary embodiment of the present invention. Here, the above-mentioned line means between the gate line and the data line, but is not limited thereto. It may mean a gate line and a power line, or a gate line and a reference line.

Referring to FIG. 7A, in the electroluminescent display according to the comparative example, the buffer layer 15a is disposed on the substrate 10, and the gate insulating layer 15b and the gate line 17 are disposed on the buffer layer 15a. The data line 16 is disposed on the interlayer insulating layer 15c therebetween.

Under such a stacked structure, as only one interlayer insulating layer 15c is interposed between the gate line 17 and the data line 16, the distance between the lines g1 is relatively short, about 5,000 mW, resulting in electrostatic Poor sex may occur. Since the interlayer insulating layer 15c constitutes the dielectric layer of the capacitor, there is a limit to increasing the thickness thereof.

In contrast, referring to FIG. 7B, in the electroluminescent display according to the exemplary embodiment, the data line 116 is disposed on the substrate 110. The buffer layer 115a and the interlayer insulating layer 115c are stacked and disposed on the data line 116, and the gate line 117 is disposed on the interlayer insulating layer 115c.

The gate line 117 may include a gate line 117a of the first layer, which is a transparent layer, and a gate line 117b of the second layer, which is an opaque layer.

Under such a stacked structure, two insulating layers, a buffer layer 115a and an interlayer insulating layer 115c, are interposed between the gate line 117 and the data line 116, and the thickness of the buffer layer 115a is applied to another insulating layer. Compared with each other, the distance between the lines (g2) can be increased, thereby preventing electrostatic defects.

In addition, in the electroluminescent display device 100 according to an exemplary embodiment of the present invention, as the two insulating layers are interposed between the gate line 117 and the data line 116 as described above, the interlayer insulating layer 115c. ), The thickness of the capacitor can be reduced than before, thereby increasing the capacitor capacity.

On the other hand, unlike the above-described embodiment of the present invention, there is a structure that can improve the opening ratio by arranging the transparent layer in the opening and at the same time as the wiring of the circuit portion in a different layer than the transparent layer of the opening, It will be described in detail through another embodiment of the.

8 is a plan view schematically illustrating an electroluminescent display device according to another exemplary embodiment of the present invention. 9A and 9B are schematic views illustrating a cross-sectional structure of an electroluminescent display device according to another exemplary embodiment of the present invention illustrated in FIG. 8.

In this case, the electroluminescent display device according to another exemplary embodiment of the present invention illustrated in FIGS. 8, 9A, and 9B, except for the configuration of the source / drain electrode and the gate line, according to the exemplary embodiment of the present invention described above It has substantially the same configuration as the electroluminescent display.

FIG. 8 schematically illustrates a planar structure of one pixel in the electroluminescent display 200 according to another exemplary embodiment of the present invention. For convenience of description, FIG. 8 illustrates a case in which a pixel has a 2T1C structure including a switching transistor ST, a driving transistor DT, a capacitor C, and a light emitting device LE. As described above, when the compensation circuit is added, it may be variously configured as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.

In addition, FIG. 9A illustrates a circuit part CA including a driving transistor DT and a capacitor, and a light emitting device LE in the electroluminescent display 200 according to another exemplary embodiment of the present invention illustrated in FIG. 8. For example, a portion of the light emitting part EA and the intersection part IA of the gate line 217 and the data line 216 are illustrated. FIG. 9B illustrates a part of a circuit CA including a switching transistor ST in the electroluminescent display 200 according to another exemplary embodiment of the present invention illustrated in FIG. 8.

8, 9A, and 9B, the electroluminescent display 200 according to another exemplary embodiment of the present invention may include a gate line (or scan line) 217 and a data line 216 on the substrate 210. ) And the power line (or power voltage line) 219 may cross each other to partition the pixel area AA. In addition, a sensing control line and a reference line may be further disposed.

The data line 216 and the power line 219 may be disposed on the substrate 210 in the first direction. The gate line 217 may be arranged in a second direction crossing the first direction to partition the pixel area AA together with the data line 216 and the power line 219. For convenience, one pixel area AA may be divided into a light emitting unit EA in which the light emitting device LE emits light, and a circuit unit CA including a plurality of driving circuits for supplying a driving current to the light emitting device LE.

The power line 219 may be disposed in one or more pixel areas AA, but the present invention is not limited thereto.

The reference line may be arranged in the first direction on the same layer as the data line 216 and the power line 219 together with the data line 216 and the power line 219.

The plurality of pixel areas AA may be formed of a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. In FIG. 8, only one sub-pixel area AA is shown as an example, but the present invention is not limited thereto. Each of the red, green, blue, and white sub-pixel areas AA includes a light emitting element LE and a plurality of pixel driving circuits that independently drive the light emitting element LE. The pixel driving circuit may include a switching transistor ST, a driving transistor DT, a capacitor C, and a sensing transistor (not shown).

When the scan pulse is supplied to the gate line 217, the switching transistor ST is turned on to supply the data signal supplied to the data line 216 to the first gate of the capacitor C and the driving transistor DT. It may be supplied to the electrode 221. The switching transistor ST may include a second gate electrode 221 ′ connected to the gate line 217, a second source electrode 222 ′ connected to the data line 216 through a seventh contact hole, and an eighth contact hole. The second drain electrode 223 ′ and the second active layer 224 ′ connected to the first gate electrode 221 may be formed through the second gate electrode 221.

Next, the driving transistor DT controls the current supplied from the power line 219 according to the driving voltage charged in the capacitor C to supply a current proportional to the driving voltage to the light emitting element LE, thereby providing a light emitting element ( LE) emits light. The driving transistor DT includes a first gate electrode 221 connected to the second drain electrode 223 ′ through a seventh contact hole, and a first source electrode connected to the power line 219 through a ninth contact hole. 222, the first drain electrode 223 and the first active layer 224 connected to the light emitting device LE through the fifth contact hole.

The power line 219 may be connected to the first source electrode 222 of the neighboring pixel area AA through the bridge line 219a. The bridge line 219a may extend to the neighboring pixel area AA in a direction parallel to the second direction. As such, the bridge wire 219a extending to the neighboring pixel region AA may be connected to the first source electrode 222 of the neighboring pixel region AA through the tenth contact hole. However, the present invention is not limited thereto.

One side of the bridge wire 219a may be connected to the power line 219 below the sixth contact hole 240.

The thin film transistor illustrated in FIG. 9A is a driving transistor DT, and a thin film transistor having a top gate structure, particularly a coplanar structure, in which the first gate electrode 221 is disposed on the first active layer 224. I'm holding it as an example. In addition, the thin film transistor illustrated in FIG. 9B is a switching transistor ST, and a thin film having a top gate structure, particularly a coplanar structure, in which the second gate electrode 221 ′ is disposed on the second active layer 224 ′. The transistor is taken as an example. However, the present invention is not limited thereto, and a thin film transistor having a bottom gate structure in which the gate electrode is disposed under the active layer is also applicable.

The first gate electrode 221 of the driving transistor DT may be interposed with the first active layer 224 via the gate insulating layer 215b having substantially the same shape as the first gate electrode 221. The second gate electrode 221 ′ of the switching transistor ST may overlap the second active layer 224 ′ through the gate insulating layer 215 b having substantially the same shape as the second gate electrode 221 ′. Can be.

In detail, the first active layer 224 and the second active layer 224 ′ may be disposed on the substrate 210.

In this case, the light blocking layer 225 may be disposed below the first active layer 224, and the buffer layer 215a may be disposed between the first active layer 224 and the light blocking layer 225.

The light blocking layer 225 may serve to block the first active layer 224 from being affected by the light of an external or surrounding light emitting device, and may be disposed on the lowermost layer of the substrate 210.

The light blocking layer 225 may serve to block the first active layer 224 from being affected by the light of an external or surrounding light emitting device, and may be disposed on the lowermost layer of the substrate 210.

The data line 216 and the power line 219 of the present invention may be disposed on the same layer as the light blocking layer 225 in the first direction. That is, the data line 216 and the power line 219 of the present invention are disposed on the lowermost layer of the substrate 210 together with the light blocking layer 225.

This is because the vertical lines of the data line 216 and the power line 219 are arranged on a different layer from the existing ones, so that the interlayer is formed between the vertical lines of the data line 216 and the power line 219 and the horizontal lines of the gate line 217. The buffer layer 215a and the gate insulating layer 215b other than the insulating layer 215c are interposed to prevent a short circuit failure.

The buffer layer 215a may be disposed on the substrate 210 to cover the light blocking layer 225, the data line 216, and the power line 219.

Each of the first active layer 224 and the second active layer 224 ′ is formed to overlap the first gate electrode 221 and the second gate electrode 221 ′ on the gate insulating layer 215b to form a first first layer. A channel may be formed between the source electrode 222 and the first drain electrode 223 and between the second source electrode 222 ′ and the second drain electrode 223 ′.

The first active layer 224 and the second active layer 224 ′ may be configured using an oxide semiconductor including at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. It may be composed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor.

9A illustrates a case in which the gate insulating layer 215b is limited to the lower portion of the first gate electrode 221, but the present invention is not limited thereto. In addition, although FIG. 9B illustrates a case in which the gate insulating layer 215b is limited to the lower portion of the second gate electrode 221 ′, the present invention is not limited thereto. The gate insulating layer 215b may be formed on the entire surface of the substrate 210 on which the first active layer 224 and the second active layer 224 ′ are formed. In this case, the gate insulating layer 215b may have a first source electrode ( Contact holes may be formed to connect the 222 and the first drain electrode 223 to the source and drain regions of the first active layer 224, respectively. The gate insulating layer 215b includes contact holes for connecting the second source electrode 222 'and the second drain electrode 223' to the source and drain regions of the second active layer 224 ', respectively. Can be formed.

The gate insulating layer 215b may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

According to another exemplary embodiment of the present invention, the gate line 217 is disposed on the same layer as the first gate electrode 221 and the second gate electrode 221 ′. In this case, the gate insulating layer 215b may be formed under the gate line 217.

The first gate electrode 221, the second gate electrode 221 ′, and the gate line 217 may be formed of various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), It may be composed of any one of titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or two or more alloys thereof, or multiple layers thereof.

As described above, in the electroluminescent display 200 according to another exemplary embodiment of the present invention, vertical wires of the data line 216 and the power line 219 are disposed on the substrate 210 in the first direction, and the gate line A horizontal line 217 is disposed in a second direction crossing the first direction to partition the pixel area AA together with the vertical line.

In addition, the electroluminescent display 200 according to another exemplary embodiment of the present invention arranges the vertical lines of the data line 216 and the power line 219 on the same layer as the light blocking layer 225 of the lowermost layer. The horizontal wiring of 217 is disposed on the same layer as the first gate electrode 221 and the second gate electrode 221 'so that the gate insulating layer (215c) is replaced between the vertical wiring and the horizontal wiring instead of the existing interlayer insulating layer 215c. Two insulating layers, 215b) and a buffer layer 215a, are interposed. In particular, since the gate insulating layer 215b is independent of the capacitor capacitance, the short circuit defect occurring at the intersection of the vertical wiring and the horizontal wiring can be prevented by increasing the thickness of the gate insulating layer 215b.

Accordingly, the intra-pixel gate redundancy pattern can be eliminated, thereby facilitating the pixel design in the high-resolution model, improving the yield, and providing an additional aperture ratio.

An interlayer insulating layer 215c may be disposed on the first gate electrode 221, the second gate electrode 221 ′, and the gate line 217.

The interlayer insulating layer 215c may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As illustrated in FIGS. 9A and 9B, the interlayer insulating layer 215c may be formed over the entire surface of the substrate 210 or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The first source electrode 222, the first drain electrode 223, and the second source electrode 222 ′ on the interlayer insulating layer 215c on the first active layer 224 and the second active layer 224 ′, respectively. And a second drain electrode 223 ′ may be disposed. Each of the first source electrode 222 and the second source electrode 222 ′ may have a first active layer 224 and a second active layer through first and third contact holes penetrating the interlayer insulating layer 215c. Each of the first drain electrode 223 and the second drain electrode 223 ', which is connected to the source region 224', respectively and passes through the interlayer insulating layer 215c. The first and second active layers 224 and 224 ′ may be connected to drain regions of the first active layer 224 and the second active layer 224 ′.

The second drain electrode 221 ′ of the switching transistor ST may extend in one direction and be electrically connected to the first gate electrode 221 of the driving transistor DT through a predetermined contact hole.

Meanwhile, another embodiment of the present invention focuses on the fact that when the transparent layer is applied to an electrode or a wire adjacent to the opening, for example, the bridge wiring 219a, the opening A can be expanded than before. ) And the wiring of the circuit part CA, for example, the gate line 217 is disposed on a layer different from the bridge wiring 219a, and the wiring on the same layer as the bridge wiring 219a is considered. In the non-electrode, for example, the aperture ratio may be improved by forming the first source electrode 222, the first drain electrode 223, and the second source electrode 222 ′ and the second drain electrode 223 ′ as a transparent layer. It features.

That is, according to another exemplary embodiment of the present invention, the first direction electrode 222, the second source electrode 222 ′, and the same direction of the first drain electrode 223 and the second drain electrode 223 ′ in the second direction are provided. The bridge wiring 219a may be arranged in a direction parallel to the direction. The bridge wiring 219a may be disposed to pass through the light emitting part EA and may be configured as a first layer of the transparent layer. In addition, the first source electrode 222, the second source electrode 222 ′, the first drain electrode 223, and the second drain electrode 223 ′ may also be configured as the first layer of the transparent layer.

In another embodiment of the present invention, the gate line 217 may be disposed on the same layer as the first gate electrode 221 and the second gate electrode 221 ′. The gate line 217 may be made of the same conductive material as the first gate electrode 221 and the second gate electrode.

As described above, in another embodiment of the present invention, the bridge wiring 219a passing through the light emitting portion EA is formed of the first layer of the transparent layer, and the wiring of the circuit portion CA, for example, the gate line 217 It is disposed on a layer different from the bridge wiring 219a, and an electrode which is not a wiring on the same layer as the bridge wiring 219a, for example, the first source electrode 222, the first drain electrode 223, and the second source electrode ( 222 'and the second drain electrode 223' are formed as a transparent layer. In this case, the light emitting part EA may be extended toward the circuit part CA, and thus, the opening part A may be substantially expanded.

As described above, although the thin film transistor has been described as having a coplanar structure, the thin film transistor may be implemented in another structure such as a staggered structure.

Next, the protective layer 215d and the planarization layer 215e may be disposed on the thin film transistor. The passivation layer 215d protects the gate driver and other wirings disposed in addition to the thin film transistor and the pixel area AA, and the planarization layer 215e smoothes the step on the substrate 210 to planarize the top of the substrate 210. It can be formed to.

In this case, the color filter layer may be disposed on the passivation layer 215d of the light emitting unit EA.

The protective layer 215d may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The protective layer 215d may be formed over the entire surface of the substrate 210 as shown in FIGS. 9A and 9B, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The planarization layer 215e may be made of an organic insulating material.

The planarization layer 215e includes acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene and photoresist. It may be formed of any one, but is not limited thereto.

The first drain electrode 223 may be connected to the anode 226 of the light emitting device LE through a fifth contact hole penetrating through the passivation layer 215d and the planarization layer 215e.

Referring to FIG. 9A, a light emitting device LE may be disposed on the planarization layer 215e. For example, the organic light emitting diode LE is formed on the planarization layer 215e and is disposed on the anode 226 and the anode 226 connected to the first drain electrode 223 of the driving transistor DT. The light emitting layer 227 and the cathode 228 formed on the organic light emitting layer 227 may be included.

The anode 226 may be disposed on the planarization layer 215e and electrically connected to the first drain electrode 223 through a fifth contact hole formed in the planarization layer 215e. The anode 226 may be made of a conductive material having a high work function to supply holes to the organic light emitting layer 227. The anode 226 is made of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like. Can be.

8 and 9A, for example, the anode 226 is illustrated as being electrically connected to the first drain electrode 223 of the driving transistor DT. However, the present invention is not limited thereto, and the type and driving of the thin film transistor are not limited thereto. The anode 226 may be electrically connected to the first source electrode 222 of the driving transistor DT by a circuit design scheme or the like.

The organic emission layer 227 is an organic layer for emitting light of a specific color, and may include any one of a red organic emission layer, a green organic emission layer, a blue organic emission layer, and a white organic emission layer. In addition, the organic emission layer 227 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. 8 and 9A, the organic light emitting layer 227 is patterned for each pixel. However, the present invention is not limited thereto, and the organic light emitting layer 227 may be a common layer formed in common with a plurality of pixels.

The cathode 228 may be disposed on the organic emission layer 227. The cathode 228 may supply electrons to the organic emission layer 227. The cathode 228 is made of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) and tin. It may be made of a tin oxide (TO) -based transparent conductive oxide or an ytterbium (Yb) alloy. Alternatively, the cathode 228 may be made of a conductive material.

9A and 9B, a bank 215f may be disposed on the anode 226 and the planarization layer 215e. The bank 215f may cover a portion of the anode 226 of the organic light emitting diode. The bank 215f may be arranged to distinguish adjacent pixels in the pixel area AA.

The bank 215f may be made of an organic insulating material. For example, the bank 215f may be made of polyimide, acryl, or benzocyclobutene (BCB) -based resin, but the present invention is not limited thereto.

The bank 215f may be disposed to surround the light emitting unit EA on the planarization layer 215e, and the bank 215f may be a wiring, for example, a light emitting unit EA in which the first layer of the bridge wiring 219a is located. Can be removed.

An encapsulation part (not shown) may be formed on the organic light emitting device configured as described above to protect the organic light emitting device vulnerable to moisture from being exposed to moisture. For example, the encapsulation portion may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

Exemplary embodiments of the invention may be described as follows.

An electroluminescent display device according to an embodiment of the present invention includes a data line disposed in a first direction on a substrate, a gate line disposed in a second direction crossing the first direction, and partitioning the pixel region together with the data line, the pixel. A thin film transistor disposed in the circuit portion of the region, at least one wiring for transmitting various signals to the circuit portion, a light emitting element disposed in the light emitting portion of the pixel region, and a bank disposed to surround the light emitting portion, and the wiring is disposed to pass through the light emitting portion And a first layer of transparent layer, the bank may expose the first layer of wiring.

According to another feature of the invention, the wiring may be composed of at least two layers by laminating a second layer of an opaque layer on the first layer in the circuit portion.

According to another feature of the present invention, the electroluminescent display may further include a power line disposed on the same layer as the data line in a direction parallel to the first direction.

According to another feature of the invention, the wiring may include a bridge wiring connected to the power line to transfer the power supply voltage to the thin film transistor of the neighboring pixel region.

According to another feature of the present invention, the electroluminescent display further includes a light blocking layer disposed under the thin film transistor, and the data line may be disposed on the same layer as the light blocking layer.

According to another feature of the present invention, the source / drain electrodes of the thin film transistor may include at least two layers by laminating a second layer of an opaque layer on the first layer.

According to another feature of the invention, the gate line may be composed of at least two layers by laminating a second layer on the first layer.

According to another feature of the present invention, a buffer layer and an interlayer insulating layer may be stacked and interposed between the gate line and the data line.

According to another feature of the invention, the source / drain electrodes of the thin film transistor may be composed of a first layer.

According to another feature of the present invention, the electroluminescent display further includes an interlayer insulating layer disposed under the source / drain electrode, and the gate line may be disposed between the interlayer insulating layer and the buffer layer.

According to another feature of the present invention, at least a buffer layer and a gate insulating layer may be stacked and interposed between the gate line and the data line.

According to another feature of the invention, the banks may overlap the second layer of wiring, while exposing the first layer of wiring.

The electroluminescent display device according to another exemplary embodiment of the present invention includes a data line disposed in a first direction on a substrate and a gate arranged in a second direction crossing the first direction to partition a pixel region together with the data line. Line, parallel to the first direction, a power line arranged in each of the one or more pixel regions, a thin film transistor disposed in the circuit portion of the pixel region, and a bridge wiring connected to the power line to transfer the power voltage to the thin film transistor of a neighboring pixel region. And a light emitting element disposed in the light emitting portion of the pixel region, wherein the bridge wiring is disposed to pass through at least the light emitting portion, and the light emitting portion may include a first layer of a transparent layer to extend the pixel region.

According to another feature of the invention, the bridge wiring may be composed of at least two layers by laminating a second layer of an opaque layer on the first layer in the circuit portion.

According to another feature of the invention, the electroluminescent display further comprises a bank disposed to surround the light emitting portion, the bank exposing the first layer of the bridge wiring, while overlapping with the second layer of the bridge wiring. Can be.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100,200: electroluminescent display
115a, 215a: buffer layer
115b, 215b: gate insulating layer
115c, 215c: interlayer insulation layer
115d, 215d: protective layer
115e, 215e: planarization layer
115f, 215f: bank
116,216 data line
117,217: gate line
117a: gate line of the first layer
117b: gate line of the second layer
119,219 power line
119a, 219a: bridge wiring
125,225: Shading layer
126,226: anode
127,227: organic light emitting layer
128,228: cathode
140: sixth contact hole
150,250 connection electrode

Claims (15)

A data line disposed in a first direction on the substrate;
A gate line disposed on the data line in a second direction crossing the first direction to define a pixel area together with the data line;
A thin film transistor disposed in the circuit portion of the pixel region, the thin film transistor including a source electrode and a drain electrode disposed on the same layer as the gate line;
At least one wire which transmits various signals to the circuit unit and is disposed on the same layer as the gate line;
A light emitting element disposed in the light emitting portion of the pixel region; And
A bank disposed to surround the light emitting unit,
The wiring line is disposed to pass through the light emitting unit, and the light emitting unit includes a first layer of a transparent layer. The method of claim 1,
The wiring is an electroluminescent display device in which the second portion of the opaque layer is laminated on the first layer in the circuit portion, and is composed of at least two layers. The method of claim 1,
And a power line disposed on the same layer as the data line in a direction parallel to the first direction. The method of claim 3,
And the wirings include bridge wirings connected to the power lines to transfer power voltages to the thin film transistors in the neighboring pixel areas. The method of claim 1,
Further comprising a light blocking layer disposed on the lower portion of the thin film transistor,
And the data line is disposed on the same layer as the light blocking layer. The method of claim 2,
The source electrode and the drain electrode, the second layer is stacked on the first layer, the electroluminescent display device comprising at least two layers. The method of claim 6,
The gate line is an electroluminescent display device having at least two layers in which the second layer is stacked on the first layer. The method of claim 7, wherein
And a buffer layer and an interlayer insulating layer interposed between the gate line and the data line. delete delete delete The method of claim 2,
And the bank is removed from the light emitting portion where the first layer of the wiring is located and overlaps with the second layer of the wiring. A data line disposed in a first direction on the substrate;
A gate line disposed on the data line in a second direction crossing the first direction to define a pixel area together with the data line;
A power line disposed in a portion of the pixel area in a direction parallel to the first direction;
A thin film transistor disposed in the circuit portion of the pixel region, the thin film transistor including a source electrode and a drain electrode disposed on the same layer as the gate line;
A bridge wiring connected to the power line to transfer a power supply voltage to the thin film transistor in a neighboring pixel region, the bridge wiring being disposed on the same layer as the gate line; And
A light emitting element disposed in the light emitting portion of the pixel region;
And the bridge wirings are arranged to pass at least through the light emitting portion, and the light emitting portion includes a first layer of a transparent layer to extend the pixel region. The method of claim 13,
The bridge wiring is an electroluminescent display device in which the second portion of the opaque layer is laminated on the first layer in the circuit portion, and is composed of at least two layers. The method of claim 14,
Further comprising a bank disposed to surround the light emitting portion,
And the bank is removed from the light emitting portion in which the first layer of the bridge wiring is located and overlaps with the second layer of the bridge wiring.

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