KR102427516B1 - Eletroluminescence display device - Google Patents

Abstract

An electroluminescent display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area surrounding the display area, a plurality of thin film transistors disposed on the substrate in the display area, and disposed on the substrate in the non-display area a gate driver, a first planarization layer covering the plurality of thin film transistors and the gate driver, and a second planarization layer disposed on the first planarization layer only in the display area; and a plurality of light emitting devices disposed on the second planarization layer. By configuring the two-layer planarization layer only in the display area, the pitch between wirings and wiring resistance can be freely designed in the display area, and the gas component outgassed from the first planarization layer and the second planarization layer in the non-display area can be minimized. can

Description

Electroluminescent display device {ELETROLUMINESCENCE DISPLAY DEVICE}

The present invention relates to an electroluminescent display device, and more particularly, to an electroluminescent display device having improved reliability by minimizing gas that may be out-gassed in a planarization layer.

The electroluminescent display device is a self-luminous display device, and unlike a liquid crystal display device, it does not require a separate light source, so it can be manufactured in a lightweight and thin form. In addition, the electroluminescent display device is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent response speed, viewing angle, and contrast ratio, and thus is being studied as a next-generation display.

Recently, as the demand for a high-resolution electroluminescent display device increases, research has been conducted to densely arrange a plurality of wirings, thin film transistors, capacitors, and light emitting devices. Specifically, as a high resolution is required, a larger number of wires must be disposed in a predetermined space, and thus a problem in which a pitch between wires is insufficient occurred. In addition, when the width of the wiring is reduced to arrange a larger number of wirings, there is a problem in that the resistance of the wiring increases.

[Related technical literature]

1. Organic light emitting display device and manufacturing method thereof (Patent Application No. 10-2013-0167696).

Accordingly, the inventors of the present invention have invented a technique for applying two planarization layers to both the display area and the non-display area. That is, the inventors of the present invention applied two planarization layers to the display area and the non-display area to provide an additional space for arranging wirings and the like between the two planarization layers. Accordingly, by arranging the wirings that should have been arranged on one layer in two layers, the pitch between the wirings can be designed with a margin. resistance could be lowered.

Meanwhile, even if a curing process is performed in an oven to remove the gas component of the planarization layer, fine gases still remain in the planarization layer. When these fine gases are outgassed and move to the cathode of the light emitting device, the cathode may be oxidized, which may lead to poor pixel shrinkage.

The inventors of the present invention have recognized that the occurrence probability of the pixel shrinkage defect as described above increases as the volume of the planarization layer disposed in the non-display area increases. Accordingly, the inventors of the present invention have invented an electroluminescent display device having a new structure for securing a pitch between wirings, maintaining a low wiring resistance, and minimizing a gas that may be outgassed from a planarization layer.

Accordingly, the problem to be solved by the present invention is to provide an electroluminescent display device capable of minimizing a gas component outgassed from the planarization layer by applying two planarization layers to the display area while applying a single planarization layer to the non-display area will provide

In addition, another problem to be solved by the present invention is electroluminescence, which can minimize the outgassing gas component in the gate driver region by applying a planarization pattern to the non-display region and at the same time provide additional space for wiring. To provide a display device.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, an electroluminescent display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area surrounding the display area, and a plurality of thin film transistors disposed on the substrate in the display area. , a gate driver disposed on the substrate in the non-display area, a first planarization layer covering the plurality of thin film transistors and the gate driver, a second planarization layer disposed on the first planarization layer only in the display area, and on the second planarization layer It includes a plurality of light emitting devices disposed on the. By configuring the two-layer planarization layer only in the display area, the pitch between wirings and wiring resistance can be freely designed in the display area, and the gas component outgassed from the first planarization layer and the second planarization layer in the non-display area can be minimized. can

In order to solve the above problems, an electroluminescent display device according to another embodiment of the present invention includes a substrate in which a non-display area including a display area and a gate driver area in which the gate driver is disposed, the display area and the non-display area are defined. A planarization layer per unit area in the gate driver region to include a planarization layer disposed on the , and a light emitting device disposed on the planarization layer in the display area, and to suppress damage to the light emitting device by a gas discharged from the planarization layer. The volume may be smaller than the volume of the planarization layer per unit area in the display area. Accordingly, the volume of the planarization layer through which the gas component can be outgassed can be minimized by using the planarization layer having a two-layer structure, but using the planarization layer having a single layer structure in the non-display area.

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, since the two-layer planarization layer is formed only in the display area, the pitch between wirings and the wiring resistance in the display area can be freely designed.

Also, in the present invention, the volume of the planarization layer through which a gas component can be outgassed can be reduced by using the planarization layer having a two-layer structure, but using the planarization layer having a single layer structure in the non-display area.

In addition, according to the present invention, oxidation of the cathode of the light emitting device can be reduced by minimizing the gas component outgassed from the planarization layer, and thus, the reliability of the electroluminescent display can be improved.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic plan view of an electroluminescent display device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II-II' of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line III-III′ of FIG. 1 .
4 is a cross-sectional view of an electroluminescent display device according to another exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

When an element or layer is referred to as "on" another element or layer, it includes all cases with another layer or other element interposed therebetween or directly on the other element.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other, It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of an electroluminescent display device according to an embodiment of the present invention. Referring to FIG. 1 , the electroluminescence display 100 may include a substrate 110 , a gate driver 150 , a power supply line 160 , and a COF 170 .

The substrate 110 supports various components of the electroluminescent display device 100 . The substrate 110 may be made of a plastic material having flexibility, for example, polyimide (PI).

A display area AA and a non-display area NA surrounding the display area AA may be defined in the substrate 110 . The display area DA is an area where an image is actually displayed in the electroluminescent display device 100 , and a light emitting device to be described later and various driving devices for driving the light emitting device may be disposed in the display area AA. The non-display area NA is an area in which an image is not displayed and may be defined as an area surrounding the display area AA. Various components for driving the plurality of pixels PX disposed in the display area AA may be disposed in the non-display area NA. For example, as shown in FIG. 1 , various signal lines such as the gate line GL and the data line DL, the gate driver 150 , the power supply line 160 , etc. are not displayed on the substrate 110 . It may be disposed in the area NA.

A bending area BA is defined in the non-display area NA adjacent to the display area AA. As the bending area BA is bent, an external module bonded to the COF 170 , for example, a printed circuit board, etc. moves toward the back side of the substrate 110 , and when viewed from the top of the substrate 110 , the external module may not be admitted. In addition, as the bending area BA is bent, the size of the non-display area NA viewed from the upper portion of the substrate 110 may be reduced, so that a narrow bezel may be implemented.

The gate driver 150 outputs a gate signal and a light emission control signal under the control of the timing controller, selects a pixel PX charged with a data voltage through wiring such as the gate line GL and the light emission control signal line, and selects the light emission timing can be adjusted. The gate driver 150 may sequentially supply the gate signal and the emission control signals by shifting the scan signal and the emission control signal using a shift register. The gate driver 150 may be directly formed on the substrate 110 as shown in FIG. 1 in a gate-driver in panel (GIP) method, but is not limited thereto.

The power supply wiring 160 is a wiring for applying a common voltage to a cathode of a light emitting device to be described later. As shown in FIG. 1 , the power supply wiring 160 is formed outside the display area AA and the gate driver 150 and is disposed to surround the display area AA and the gate driver 150 .

Hereinafter, for a more detailed description of the components of the electroluminescent display device 100 according to an embodiment of the present invention, reference is made to FIGS. 2 to 3 together.

FIG. 2 is a cross-sectional view taken along line II-II' of FIG. 1 . In the electroluminescent display device 100 according to an embodiment of the present invention shown in FIG. 2 , the light emitted from the light emitting device 140 is emitted to the upper part of the electroluminescent display device 100 through the cathode 143 . It is an electroluminescent display device of the method.

Referring to FIG. 2 , the thin film transistor 120 for driving the light emitting device 140 is disposed in the display area AA on the substrate 110 . The thin film transistor 120 includes an active layer 121 , a gate electrode 122 , a source electrode 123 , and a drain electrode 124 . The thin film transistor 120 is a driving thin film transistor and has a top gate structure in which the gate electrode 122 is disposed on the active layer 121 .

Referring to FIG. 2 , the active layer 121 of the thin film transistor 120 is disposed on the substrate 110 . The active layer 121 is a region in which a channel is formed when the thin film transistor 120 is driven. The active layer 121 may be formed of an oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor. have.

Referring to FIG. 2 , a gate insulating layer 111 is disposed on the active layer 121 . The gate insulating layer 111 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). A contact hole is formed in the gate insulating layer 111 for the source electrode 123 and the drain electrode to respectively contact the source region and the drain region of the active layer 121 . The gate insulating layer may be formed over the entire substrate as shown in FIG. 2 or may be patterned to have the same width as the gate electrode 122 , but is not limited thereto.

Referring to FIG. 2 , a gate electrode 122 is disposed on the gate insulating layer 111 . The gate electrode 122 is disposed on the gate insulating layer 111 to overlap the channel region of the active layer 121 . The gate electrode 122 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be any one of copper (Cu), an alloy of two or more, or a multilayer thereof.

Referring to FIG. 2 , an interlayer insulating layer 112 is disposed on the gate electrode 122 . The interlayer insulating layer 112 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). In the interlayer insulating layer 112 , a contact hole is formed for the source electrode 123 and the drain electrode 124 to contact each of the source region and the drain region of the active layer 121 . The interlayer insulating layer may be formed over the entire substrate as shown in FIG. 2 or may be formed only in the display area, but is not limited thereto.

Referring to FIG. 2 , a source electrode 123 and a drain electrode 124 are disposed on the interlayer insulating layer 112 . The source electrode 123 and the drain electrode 124 are electrically connected to the active layer 121 through contact holes of the gate insulating layer 111 and the interlayer insulating layer 112 . The source electrode 123 and the drain electrode 124 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be made of any one of neodymium (Nd) and copper (Cu), an alloy of two or more, or a multilayer thereof.

2 shows only the driving thin film transistor among various thin film transistors that may be included in the electroluminescent display device 100 for convenience of explanation, but other thin film transistors such as switching thin film transistors may also be included in the electroluminescent display device 100 . have. In addition, although the thin film transistor 120 has been described as having a coplanar structure in this specification, the thin film transistor may be implemented in other structures such as a staggered structure.

Referring to FIG. 2 , the gate driver 150 and the wiring 129 are disposed in the non-display area NA on the substrate 110 . In FIG. 2 , the gate driver 150 is illustrated as a block for convenience of illustration, but in reality, the gate driver 150 may include various components such as thin film transistors and capacitors. Also, a wiring 129 for transmitting various signals may be disposed in the non-display area NA. In FIG. 2 , the wiring 129 is disposed in the gate driver area GA where the gate driver 150 is disposed. was assumed to be placed. The wiring 129 may be formed of the same material as the source electrode 123 and the drain electrode 124 , but is not limited thereto, and may be formed of the same material as the gate electrode 122 .

Referring to FIG. 2 , the power supply wiring 160 is disposed on the substrate 110 in the non-display area NA. As will be described later, the power supply wiring 160 is electrically connected to the cathode 143 to supply power to the cathode 143 . The power supply wiring 160 may be made of the same material as the source electrode 123 and the drain electrode 124 , but is not limited thereto, and may be made of the same material as the gate electrode 122 .

Referring to FIG. 2 , a first planarization layer 113 is disposed on the thin film transistor 120 and the gate driver 150 in the display area AA and the non-display area NA. The first planarization layer 113 is an insulating layer for protecting the thin film transistor 120 , the gate driver 150 , and the wiring 129 , and smoothing the step on the substrate 110 to planarize the upper portion of the substrate 110 . . The first planarization layer 113 may include an acrylic resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene-based resin, a polyphenylene sulfide-based resin, benzocyclobutene, and a photoresist. It can be formed with one of, but not limited to, a resist. does not

Referring to FIG. 2 , a connection electrode 139 is disposed on the first planarization layer 113 in the display area AA. The connection electrode 139 is an electrode for electrically connecting the thin film transistor 120 and the anode 141 . The connection electrode 139 is electrically connected to the drain electrode 124 of the thin film transistor 120 through a contact hole formed in the first planarization layer 113 . The connection electrode 139 may be made of the same material as the source electrode 123 and the drain electrode 124 of the thin film transistor 120 , or may be made of a material different from that of the anode 141 .

Next, referring to FIG. 2 , the second planarization layer 114 is disposed on the first planarization layer 113 only in the display area AA. The second planarization layer 114 is disposed only on the first planarization layer 113 and the connection electrode 139 in the display area AA. The second planarization layer 114 is an insulating layer for planarizing the first planarization layer 113 . The second planarization layer 114 includes an acrylic resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene-based resin, a polyphenylene sulfide-based resin, benzocyclobutene, and a photoresist. It may be formed of one of the resists, but is not limited thereto. The second planarization layer 114 may be formed of the same material as the first planarization layer 113 .

As the two planarization layers 113 and 114 are disposed between the thin film transistor 120 and the light emitting device 140 in the display area AA, the anode 141 and the thin film transistor 120 are formed through a single contact hole forming process. ) may be difficult to electrically connect. Accordingly, in the electroluminescent display device 100 according to an embodiment of the present invention, a connection electrode 139 electrically connected to the thin film transistor 120 is disposed on the first planarization layer 113 in the display area AA, , the anode 141 disposed on the second planarization layer 114 may be configured to be connected to the connection electrode 139 through a contact hole of the second planarization layer 114 .

Referring to FIG. 2 , the light emitting device 140 is disposed on the second planarization layer 114 . The light emitting device 140 includes an anode 141 formed on the second planarization layer 114 and electrically connected to the drain electrode 124 of the thin film transistor 120 , a light emitting layer 142 and a light emitting layer disposed on the anode 141 . and a cathode 143 formed on 142 .

The anode 141 is disposed on the second planarization layer 114 and is electrically connected to the connection electrode 139 through a contact hole formed in the second planarization layer 114 . The anode 141 may be made of a conductive material having a high work function in order to supply holes to the light emitting layer 142 . The anode 141 is made of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like. can be done

As described above, since the EL display device 100 is a top emission type EL display device, the anode 141 includes a reflective layer for reflecting the light emitted from the emission layer 142 toward the cathode 143 and the emission layer. A transparent conductive layer for supplying holes may be included. However, it may be defined that the anode 141 includes only a transparent conductive layer and the reflective layer is a separate component from the anode 141 .

In FIG. 2 , the anode 141 is electrically connected to the drain electrode 124 of the thin film transistor 120 through the connection electrode 139 , but depending on the type of the thin film transistor 120 , the design method of the driving circuit, etc. The anode 141 may be configured to be electrically connected to the source electrode 123 of the thin film transistor 120 through the connection electrode 139 .

The emission layer 142 is a layer for emitting light of a specific color, and may include one of a red emission layer, a green emission layer, a blue emission layer, and a white emission layer. In addition, the emission layer 142 may further include various layers such as a hole transport layer, a hole injection layer, an electron injection layer, an electron transport layer, and the like. Although FIG. 2 illustrates that the emission layer 142 is patterned for each pixel PX, the present invention is not limited thereto, and the emission layer 142 may be a common layer formed in common with the plurality of pixels PX.

The cathode 143 is disposed on the light emitting layer 142 . The cathode 143 supplies electrons to the light emitting layer 142 . The cathode 143 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (Zinc Oxide, ZnO), and tin. It may be made of a transparent conductive oxide (Tin Oxide, TO)-based oxide or a ytterbium (Yb) alloy. Alternatively, the cathode 143 may be made of a metal material.

Next, referring to FIG. 2 , a bank 115 is disposed on the anode 141 and the planarization layers 113 and 114 . The bank 115 may cover a portion of the anode 141 and a portion of the wiring 131 of the light emitting device 140 . The bank 115 is disposed to distinguish adjacent pixels PX in the display area AA. The bank 115 may be formed of an organic material. For example, the bank 115 may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

A wiring 131 is disposed on the first planarization layer 113 in the non-display area NA. The wiring 131 may be formed of the same material as the conductive element disposed in the display area AA. For example, as shown in FIG. 2 , the wiring 131 may be formed of the same material as the anode 141 , but is not limited thereto. The wiring 131 disposed in the non-display area NA may be connected in parallel with the wiring 129 to transmit the same signal or may transmit a signal separate from the wiring 129 .

A portion of the wiring 131 may be electrically connected to the cathode 143 and the power supply wiring 160 to supply power from the power supply wiring 160 to the cathode 143 . That is, the low potential voltage VSS transmitted from the COF 170 may sequentially pass through the power supply wiring 160 and the wiring 131 to be transmitted to the cathode 143 .

Although not shown in FIG. 2 , an encapsulation unit may be formed on the light emitting device 140 to protect the light emitting device 140 vulnerable to moisture from being exposed to moisture. For example, the encapsulation unit may have a structure in which inorganic layers and organic layers are alternately stacked.

For a more detailed description of the bending area BA of the substrate 110 in the electroluminescent display 100 according to an embodiment of the present invention, reference is also made to FIG. 3 .

FIG. 3 is a cross-sectional view taken along line III-III′ of FIG. 1 . Since the cross-sectional structure of the display area AA in FIG. 3 is substantially the same as that of the display area AA illustrated in FIG. 2 , a detailed description of the cross-sectional structure of the display area AA will be omitted.

Referring to FIG. 3 , in the bending area BA, the gate insulating layer 111 is disposed on the substrate 110 , and the interlayer insulating layer 112 is disposed on the gate insulating layer 111 . Also, the first planarization layer 113 is disposed in both the display area AA and the non-display area NA, but is patterned at the boundary of the bending area BA. Accordingly, the portion of the first planarization layer 113 disposed in the bending area BA and the first planarization layer 113 disposed in the display area AA and the area between the display area AA and the bending area BA. parts are separated from each other. Also, the second planarization layer 114 is disposed in the display area AA and the bending area BA, but is not disposed in the area between the display area AA and the bending area BA. Also, a portion of the second planarization layer 114 disposed in the display area AA and a portion of the second planarization layer 114 disposed in the bending area BA are separated from each other. Accordingly, the first planarization layer 113 and the second planarization layer 114 disposed in the bending area BA are formed with the first planarization layer 113 and the second planarization layer 114 disposed in the display area AA, and Since they are separated, the gas component outgassed from the first planarization layer 113 and the second planarization layer 114 disposed in the bending area BA is formed in the first planarization layer 113 disposed in the display area AA, and Since it is not transferred to the second planarization layer 114 , oxidation of the cathode 143 may be minimized.

In the electroluminescence display 100 according to an embodiment of the present invention, the first planarization layer 113 and the second planarization layer in the display area AA are planarization layers for planarizing the upper portion of the thin film transistor 120 in the display area AA. 2 The planarization layer 114 is used. Accordingly, an additional space in which various wirings used in the display area AA of the electroluminescence display 100 may be disposed may be provided.

That is, compared to a case where one planarization layer is used in the display area AA, the wiring is provided in the space between the first planarization layer 113 and the second planarization layer 114 , that is, on the upper surface of the first planarization layer 113 . Additional space may be provided for placing the . Accordingly, in the electroluminescent display device 100 according to an embodiment of the present invention, the degree of freedom in designing wiring arrangement can be increased. Accordingly, the electroluminescent display device 100 having a higher resolution can be provided, and the luminance unevenness problem that may occur due to the high resistance of the wiring disposed in the display area AA of the electroluminescent display 100 can be solved. have.

In addition, in the electroluminescent display device 100 according to an embodiment of the present invention, two planarization layers 113 and 114 are used in the display area AA and one planarization layer 113 is used in the non-display area NA. Accordingly, the volume of the planarization layer through which the gas component may be outgassed in the non-display area NA may be minimized. Accordingly, compared to the case of using two planarization layers in the non-display area NA, by reducing outgassing gas, a pixel shrinkage defect may be reduced, and the reliability of the electroluminescent display device 100 may be improved. .

In addition, in the electroluminescent display 100 according to an embodiment of the present invention, the first planarization layer 113 and the second planarization layer 114 disposed in the bending area BA and the display area AA are disposed in the display area AA. The first planarization layer 113 and the second planarization layer 114 are separated from each other. Accordingly, the gas component outgassed from the first planarization layer 113 and the second planarization layer 114 disposed in the bending area BA is disposed in the first planarization layer 113 and the second planarization layer 114 in the display area AA. Since it is not transferred to the planarization layer 114 , oxidation of the cathode 143 disposed in the display area AA may be minimized.

4 is a schematic cross-sectional view for explaining an electroluminescent display device according to another embodiment of the present invention. The electroluminescence display 400 shown in FIG. 4 has an additional planarization pattern 470 in the gate driver region GA of the non-display region NA, compared to the electroluminescence display 100 shown in FIGS. 1 to 3 . ) and the wiring 480 are substantially the same except that they are disposed, and thus a redundant description will be omitted.

Referring to FIG. 4 , a wiring 480 is disposed on the first planarization layer 113 in the gate driver area GA of the non-display area NA. The wiring 480 may be made of the same material as the connection electrode 139 , but is not limited thereto.

A plurality of planarization patterns 470 are disposed to cover the wiring 40 in the gate driver area GA of the non-display area NA. The plurality of planarization patterns 470 are disposed on the same plane as the second planarization layer 114 . That is, the planarization pattern 470 may be formed of the same material and the same thickness as the second planarization layer 114 in the same process.

Referring to FIG. 4 , a wiring 431 is disposed on the planarization pattern 470 and the first planarization layer 113 in the gate driver area GA of the non-display area NA. The wiring 431 and the wiring 131 disposed in the display area AA may be formed of the same material as the anode 141 .

The wirings 431 and 480 disposed in the non-display area NA may be connected in parallel with the wiring 129 to transmit the same signal or may transmit a signal separate from the wiring 129 .

Referring to FIG. 4 , a bank 115 is formed on the planarization pattern 470 of the non-display area NA and the second planarization layer 114 of the display area AA. In the display area AA, the bank 115 on the second planarization layer 114 is substantially the same as the bank 115 illustrated in FIG. 2 , and thus a redundant description thereof will be omitted. An opening is formed in the bank 115 on the planarization pattern 470 in the non-display area NA, so that a cathode formed on the bank 115 may be connected to the power driving line 160 through a contact hole.

In the electroluminescence display 400 according to another embodiment of the present invention, in the non-display area NA, the wiring 480 made of the same material as the connection electrode 139 and the wiring 431 made of the same material as the anode 141 . ) is disposed in the non-display area NA. Also, since the planarization pattern 470 is disposed to cover the wiring 480 , the wiring 480 and the wiring 431 may be electrically separated. Accordingly, in the electroluminescent display device 400 according to another embodiment of the present invention, a space is provided for wirings 129 , 431 , and 480 used to transmit various signals to the non-display area NA to be disposed. , the design freedom for wiring arrangement can be increased. Accordingly, the electroluminescent display device 400 having a higher resolution can be provided, and the number of wires 129 , 431 , and 480 that can be disposed in the non-display area NA of the electroluminescent display 400 may increase. and wiring resistance may be reduced. Accordingly, RC delay of various signals transmitted from the non-display area NA may be improved.

In addition, in the electroluminescence display 400 according to another embodiment of the present invention, a plurality of planarization patterns 470 covering the wiring 480 in the non-display area NA are formed over the entire non-display area NA. Instead, it is patterned and arranged to cover only the wiring 480 . Accordingly, while the wiring 480 made of the same material as the connection electrode 139 is additionally disposed on the first planarization layer 113 , the volume of the planarization pattern 470 covering the wiring 480 may be minimized. Accordingly, a gas component that may be outgassed from the planarization pattern 470 may be minimized, and oxidation of the cathode 143 may be reduced, thereby improving the reliability of the electroluminescent display 200 .

An exemplary embodiment of the present invention can be described as follows.

An electroluminescent display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area surrounding the display area, a plurality of thin film transistors disposed on the substrate in the display area, and disposed on the substrate in the non-display area a gate driver, a plurality of thin film transistors and a first planarization layer covering the gate driver, a second planarization layer disposed on the first planarization layer only in a display area, and a plurality of light emitting devices disposed on the second planarization layer do.

According to another feature of the present invention, the electroluminescent display device further includes a first wiring disposed on the gate driver and the first planarization layer in the non-display area, wherein the first wiring is made of the same material as the anodes of the plurality of light emitting devices. can be done

According to another aspect of the present invention, the electroluminescent display device further includes a connection electrode disposed on the first planarization layer in the display area and electrically connecting the plurality of thin film transistors and the anodes of the plurality of light emitting devices, The electrode may be made of a different material than the anode.

According to still another feature of the present invention, the electroluminescent display device further includes a power supply wiring disposed to surround the gate driver in the non-display area, and the power supply wiring is the first wiring through a wiring made of the same material as the connection electrode. can be connected with

According to another aspect of the present invention, the electroluminescent display device further includes a plurality of second wires disposed on the gate driver and the first planarization layer in the non-display area, and the plurality of second wires are made of the same material as the connection electrode. can be made with

According to another feature of the present invention, the electroluminescent display device may further include a plurality of planarization patterns covering the plurality of second wirings on the first planarization layer.

According to another feature of the present invention, the plurality of planarization patterns may be made of the same material as the second planarization layer and may have the same thickness.

According to another feature of the present invention, the electroluminescent display device may further include a bank that covers a portion of the anode of the plurality of light emitting devices and a portion of the first wiring.

According to another feature of the present invention, the non-display area may include a bending area in which the substrate is bent, and only the first planarization layer among the first planarization layer and the second planarization layer may be disposed between the display area and the bending area.

According to another feature of the present invention, in the electroluminescent display device, the first planarization layer and the second planarization layer are further disposed in the bending area, and the first planarization layer and the second planarization layer disposed in the bending area are disposed in the display area The first planarization layer and the second planarization layer may be separated.

An electroluminescent display device according to another embodiment of the present invention includes a substrate in which a non-display area including a display area and a gate driver area in which the gate driver is disposed is defined, a display area and a planarization layer disposed in the non-display area, and a display area to include the light emitting device disposed on the planarization layer in the present invention, and to suppress the light emitting device from being damaged by the gas discharged from the planarization layer, the volume of the planarization layer per unit area in the gate driver region per unit area in the display area It may be smaller than the volume of the planarization layer.

According to another feature of the present invention, the planarization layer may include a first planarization layer and a second planarization layer, and the second planarization layer may be disposed only in the display area among the display area and the non-display area.

According to another feature of the present invention, the first planarization layer in the non-display area may further include a plurality of planarization patterns disposed on the first in the non-display area.

According to another feature of the present invention, the electroluminescent display device may further include a wiring disposed between the plurality of planarization patterns and the first planarization layer.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

110: substrate
111: gate insulating layer
112: interlayer insulating layer
113: first planarization layer
114: second planarization layer
115: bank
120: thin film transistor
121: active layer
122: gate electrode
123: source electrode
124: drain electrode
129, 131, 480: wiring
139: connecting electrode
140: light emitting element
141: anode
142: light emitting layer
143: cathode
150: gate driver
160: power drive wiring
170: COF
171: base film
172: driving IC
100, 400: electroluminescent display device
470: flattening pattern
AA: display area
BA: bending area
NA: non-display area
GA: gate driver region

Claims (13)

a substrate including a display area and a non-display area;
a plurality of thin film transistors disposed on the substrate in the display area;
a gate driver disposed on the substrate in the non-display area;
a first planarization layer covering the plurality of thin film transistors and the gate driver;
a second planarization layer disposed on the first planarization layer in the display area; and
It is disposed on the second planarization layer and includes a plurality of light emitting devices including an anode electrode,
The non-display area includes a bending area in which the substrate is bent and a spaced area between the bending area and the display area,
The first planarization layer includes a spaced pattern at a boundary between a portion of the first planarization layer disposed in the bending region and a portion of the first planarization layer disposed in the separation region,
In the second planarization layer, a portion of the second planarization layer disposed in the bending area and a portion of the second planarization layer disposed in the display area are separated from each other by being spaced apart from each other in the separation area. The method of claim 1,
and a plurality of first wirings disposed on the gate driver and the first planarization layer in the non-display area. 3. The method of claim 2,
In the display area, further comprising a connection electrode disposed on the first planarization layer to electrically connect the anode electrode and the thin film transistor,
and the connection electrode is made of a material different from that of the anode electrode. 4. The method of claim 3,
In the non-display area, the display device further includes a power supply line disposed to surround the gate driver;
and the power supply wiring is made of the same material as the source electrode and the drain electrode of the thin film transistor. 5. The method of claim 4,
The power supply wiring is electrically connected to the cathode of the light emitting element in the non-display area. 5. The method of claim 4,
The power supply wiring is electrically connected to the first wiring through a wiring made of the same material as the connection electrode. 5. The method of claim 4,
in the non-display area, further comprising a plurality of second wirings disposed on the gate driver and the first planarization layer;
and the second wiring is made of the same material as the connection electrode. 8. The method of claim 7,
and a plurality of planarization patterns disposed on the first planarization layer and covering the plurality of second wires to separate the first wires and the second wires from each other. 9. The method of claim 8,
The plurality of planarization patterns are disposed on the same plane as the second planarization layer, and are formed of the same material in the same process as that of the second planarization layer. 5. The method of claim 4,
and a bank covering a portion of the anode electrode and a portion of the first wiring. 11. The method of claim 10,
In the non-display area, the cathode of the light emitting element and the power supply wiring are electrically connected through an opening provided in the bank. 9. The method of claim 8,
The planarization pattern is made of the same material as the second planarization layer and has the same thickness. The method of claim 1,
In the bending region, the second planarization layer is stacked on the first planarization layer.

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