KR102369260B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment includes a substrate; first and second semiconductor structures disposed on the substrate; an insulating reflective layer disposed on the first and second semiconductor structures; a first bonding pad disposed on the first semiconductor structure; a second bonding pad disposed on the second semiconductor structure; and a connection electrode disposed on the first semiconductor structure and the second semiconductor structure; may include
According to an embodiment, the connection electrode includes a first portion disposed on the first semiconductor layer of the first semiconductor structure, a second portion disposed on the fourth semiconductor layer of the second semiconductor structure, and the first portion and the second portion and a third portion connecting part, wherein the second part of the connection electrode includes a third electrode part that does not overlap the second bonding pad in a first direction, and a fourth electrode part that overlaps the second bonding pad, and the first electrode part includes a first semiconductor layer The area in contact with the substrate is provided in a size of 1.4% or more and 3.3% or less of the lower surface area of the substrate, and the area of the third electrode part in contact with the fourth semiconductor layer is 0.7% or more and 3.0% or less of the lower surface area of the substrate. can be provided as

Description

semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package.

A semiconductor device including a compound such as GaN or AlGaN has many advantages, such as having a wide and easily adjustable band gap energy, and thus can be used in various ways as a light emitting device, a light receiving device, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials have developed red, green, and It has the advantage of being able to implement light of various wavelength bands, such as blue and ultraviolet. In addition, a light emitting device such as a light emitting diode or a laser diode using a group 3-5 or group 2-6 compound semiconductor material may be implemented as a white light source with good efficiency by using a fluorescent material or combining colors. These light emitting devices have advantages of low power consumption, semi-permanent lifespan, fast response speed, safety, and environmental friendliness compared to conventional light sources such as fluorescent lamps and incandescent lamps.

In addition, when a light receiving device such as a photodetector or a solar cell is manufactured using a group 3-5 or group 2-6 compound semiconductor material, a photocurrent is generated by absorbing light in various wavelength ranges through the development of the device material. By doing so, light of various wavelength ranges from gamma rays to radio wavelength ranges can be used. In addition, such a light receiving element has advantages of fast response speed, safety, environmental friendliness, and easy adjustment of element materials, and thus can be easily used in power control or ultra-high frequency circuits or communication modules.

Therefore, the semiconductor device can replace a light emitting diode backlight, a fluorescent lamp or an incandescent light bulb that replaces a cold cathode fluorescence lamp (CCFL) constituting a transmission module of an optical communication means and a backlight of a liquid crystal display (LCD) display device. The application is expanding to white light emitting diode lighting devices, automobile headlights and traffic lights, and sensors that detect gas or fire. In addition, the application of the semiconductor device may be extended to high-frequency application circuits, other power control devices, and communication modules.

A light emitting device (Light Emitting Device) may be provided as a pn junction diode having a property of converting electrical energy into light energy by using, for example, a group 3-5 element or a group 2-6 element on the periodic table, Various wavelengths can be realized by adjusting the composition ratio.

For example, nitride semiconductors are receiving great attention in the field of developing optical devices and high-power electronic devices due to their high thermal stability and wide bandgap energy. In particular, a blue light emitting device, a green light emitting device, an ultraviolet (UV) light emitting device, and a red light emitting device using a nitride semiconductor have been commercialized and widely used.

For example, in the case of an ultraviolet light emitting device, it is a light emitting diode that emits light distributed in a wavelength range of 200 nm to 400 nm. can be used

Ultraviolet rays can be divided into UV-A (315nm~400nm), UV-B (280nm~315nm), and UV-C (200nm~280nm) in the order of the longest wavelength. The UV-A (315nm~400nm) area is applied in various fields such as industrial UV curing, printing ink curing, exposure machine, counterfeit detection, photocatalytic sterilization, special lighting (aquarium/agricultural use, etc.), and UV-B (280nm~315nm) ) area is used for medical purposes, and the UV-C (200nm~280nm) area is applied to air purification, water purification, and sterilization products.

Meanwhile, as a semiconductor device capable of providing a high output is requested, research on a semiconductor device capable of increasing the output by applying a high power is being conducted.

In addition, in a semiconductor device package, research is being conducted on a method for improving the light extraction efficiency of the semiconductor device and improving the luminous intensity at the package end.

The embodiment may provide a semiconductor device capable of improving optical output and reducing an operating voltage by supplying a high voltage, a semiconductor device manufacturing method, and a semiconductor device package.

Embodiments may provide a semiconductor device capable of preventing a package body from being deteriorated by light emitted from the semiconductor device, a method for manufacturing a semiconductor device, and a semiconductor device package.

Embodiments may provide a semiconductor device, a method of manufacturing a semiconductor device, and a semiconductor device package capable of improving the bonding bonding force between the package electrode and the semiconductor device.

Embodiments may provide a semiconductor device, a method of manufacturing a semiconductor device, and a semiconductor device package capable of improving reliability by preventing a current concentration phenomenon from occurring.

A semiconductor device according to an embodiment includes a substrate; first and second semiconductor structures disposed on the substrate; an insulating reflective layer disposed on the first and second semiconductor structures; a first bonding pad disposed on the first semiconductor structure; a second bonding pad disposed on the second semiconductor structure; and a connection electrode disposed on the first semiconductor structure and the second semiconductor structure. including, wherein the first semiconductor structure includes a first semiconductor layer disposed on the substrate, a first active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first active layer and the second semiconductor structure includes a third semiconductor layer disposed on the substrate, a second active layer disposed on the third semiconductor layer, and a fourth semiconductor layer disposed on the second active layer, The connection electrode includes a first portion disposed on the first semiconductor layer, a second portion disposed on the fourth semiconductor layer, and a third portion connecting the first portion and the second portion, The first portion of the connection electrode includes a first electrode portion not overlapping the first bonding pad and a second electrode portion overlapping the first bonding pad in a first direction perpendicular to the upper surface of the substrate, and The second part of the connection electrode includes a third electrode part that does not overlap the second bonding pad in the first direction and a fourth electrode part that overlaps the second bonding pad, and the first electrode part includes the first electrode part. The area in contact with the semiconductor layer is provided in a size of 1.4% or more and 3.3% or less of the area of the lower surface of the substrate, and the area of the third electrode part in contact with the fourth semiconductor layer is 0.7% or more compared to the area of the lower surface of the substrate and may be provided in a size of 3.0% or less.

In an embodiment, an area in which the first electrode part contacts the first semiconductor layer may be larger than an area in which the third electrode part contacts the fourth semiconductor layer.

According to an embodiment, the area in which the first electrode part contacts the first semiconductor layer may be 1.1 times to 2 times that of the area in which the third electrode part contacts the fourth semiconductor layer.

A semiconductor device according to an embodiment may include: a first electrode disposed between the first semiconductor structure and the first bonding pad; a second electrode disposed between the second semiconductor structure and the second bonding pad; It further includes, wherein the connection electrode may be disposed between the first electrode and the second electrode.

In an embodiment, the insulating reflective layer includes a first reflective layer, a second reflective layer, and a third reflective layer, the first reflective layer is disposed between the first semiconductor structure and the first electrode, and the second reflective layer includes the It may be disposed between a second semiconductor structure and the second electrode, and the third reflective layer may be disposed between the first reflective layer and the second reflective layer.

In example embodiments, the first reflective layer may include a plurality of first openings and a plurality of second openings provided to penetrate in the first direction, and the second reflective layer may include a plurality of third openings provided to penetrate in the first direction. The third reflective layer may include an opening and a plurality of fourth openings, and the third reflective layer may include a plurality of fifth and fifth openings, a plurality of sixth and sixth openings, and a line opening provided to penetrate in the first direction.

According to an embodiment, an area of the first electrode part in contact with the first semiconductor layer may be, in the region provided with the first semiconductor structure, the first electrode part on the upper surface of the first semiconductor layer through the plurality of 6a openings. It may correspond to an area obtained by adding an area in direct contact with an area in which the first electrode part directly contacts the upper surface of the first semiconductor layer through the line opening.

The semiconductor device according to the embodiment further includes a light-transmitting electrode layer disposed between the first and second semiconductor structures and the reflective layer, and an area in which the third electrode part contacts the fourth semiconductor layer is the second semiconductor structure In this provided region, the third electrode part may correspond to an area of a region in direct contact with the light-transmitting electrode layer disposed under the plurality of fifth openings.

The semiconductor device according to the embodiment further includes a protective layer disposed between the first and second electrodes and the first and second bonding pads, wherein the protective layer includes a first first electrode exposing an upper surface of the first electrode. a second contact portion exposing a contact portion and an upper surface of the second electrode, wherein the first bonding pad is disposed in direct contact with the upper surface of the first electrode through the first contact portion, and the second bonding pad includes The second contact portion may be disposed in direct contact with the upper surface of the second electrode.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, there is an advantage of improving the optical output and reducing the operating voltage.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, there is an advantage in that the package body can be prevented from being deteriorated by light emitted from the semiconductor device.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, there is an advantage in that bonding strength between the package electrode and the semiconductor device can be improved.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, there is an advantage in that it is possible to prevent a current concentration phenomenon from occurring and to improve reliability.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, the electrode, the reflective layer and the bonding pad are arranged to suit the flip-chip bonding method to facilitate the bonding process and increase the transmittance and reflectance of emitted light. There is an advantage of improving the light extraction efficiency.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA of the semiconductor device shown in FIG. 1 .
3A to 3C are views for explaining a step in which a semiconductor layer is formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
4A to 4C are views for explaining a step in which a light-transmitting electrode layer is formed by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
5A to 5C are views for explaining a step in which an isolation process is performed by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
6A to 6C are views for explaining a step in which a reflective layer is formed by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
7A to 7C are views for explaining the steps in which the first electrode, the second electrode, and the connection electrode are formed by the method for manufacturing a semiconductor device according to an embodiment of the present invention.
8A to 8C are views for explaining a step in which a protective layer is formed by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
9A to 9C are views for explaining a step in which a first bonding pad and a second bonding pad are formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
10 is a diagram illustrating a semiconductor device package according to an embodiment of the present invention.

Hereinafter, an embodiment will be described with reference to the accompanying drawings. In the description of embodiments, each layer (film), region, pattern or structure is “on/over” or “under” the substrate, each layer (film), region, pad or pattern. In the case of being described as being formed on, “on/over” and “under” include both “directly” or “indirectly” formed through another layer. do. In addition, the reference for the upper / upper or lower of each layer will be described with reference to the drawings, but the embodiment is not limited thereto.

Hereinafter, a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2 . 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of the semiconductor device shown in FIG. 1 .

Meanwhile, for better understanding, in FIG. 1 , the first electrode ( ) disposed under the first bonding pad 171 and the second bonding pad 172 , but electrically connected to the first bonding pad 171 . 141) and the second electrode 142 electrically connected to the second bonding pad 172 can be seen.

The semiconductor device 100 according to the embodiment may include a first semiconductor structure 110 and a second semiconductor structure 120 disposed on a substrate 105 as shown in FIGS. 1 and 2 .

The substrate 105 may be selected from a group including a sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge. For example, the substrate 105 may be provided as a patterned sapphire substrate (PSS) having a concave-convex pattern formed on an upper surface thereof.

The first semiconductor structure 110 may include a first semiconductor layer 111 of a first conductivity type, a first active layer 112 , and a second semiconductor layer 113 of a second conductivity type. The first active layer 112 may be disposed between the first semiconductor layer 111 and the second semiconductor layer 113 . For example, the first active layer 112 may be disposed on the first semiconductor layer 111 , and the second semiconductor layer 113 may be disposed on the first active layer 112 .

In addition, the second semiconductor structure 120 may include a third semiconductor layer 121 of a first conductivity type, a second active layer 122 , and a fourth semiconductor layer 123 of a second conductivity type. The second active layer 122 may be disposed between the third semiconductor layer 121 and the fourth semiconductor layer 123 . For example, the second active layer 122 may be disposed on the third semiconductor layer 121 , and the fourth semiconductor layer 123 may be disposed on the second active layer 122 .

According to an embodiment, the first semiconductor layer 111 and the third semiconductor layer 121 are provided as an n-type semiconductor layer, and the second semiconductor layer 113 and the fourth semiconductor layer 123 are p It may be provided as a type semiconductor layer. Of course, according to another embodiment, the first semiconductor layer 111 and the third semiconductor layer 121 are provided as p-type semiconductor layers, and the second semiconductor layer 113 and the fourth semiconductor layer 123 are provided. ) may be provided as an n-type semiconductor layer.

Hereinafter, for convenience of description, the first semiconductor layer 111 and the third semiconductor layer 121 are provided as n-type semiconductor layers, and the second semiconductor layer 113 and the fourth semiconductor layer 123 are A case in which the p-type semiconductor layer is provided will be described as a reference.

In addition, in the above description, a case in which the first semiconductor layer 111 and the third semiconductor layer 121 are disposed in contact with each other on the substrate 105 has been described. However, a buffer layer may be further disposed between the first semiconductor layer 111 and the substrate 105 and/or between the third semiconductor layer 121 and the substrate 105 . For example, the buffer layer may reduce a lattice constant difference between the substrate 105 and the first and second semiconductor structures 110 and 120 and provide a function of improving crystallinity.

The first and second semiconductor structures 110 and 120 may be formed of a compound semiconductor. The first and second semiconductor structures 110 and 120 may be formed of, for example, Group 2-6 or Group 3-5 compound semiconductors. For example, the first and second semiconductor structures 110 and 120 may include at least two selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), and nitrogen (N). It may be provided including more than one element.

The first and third semiconductor layers 111 and 121 may be formed of, for example, a Group 2-6 compound semiconductor or a Group 3-5 compound semiconductor. For example, the first and third semiconductor layers 111 and 121 have the composition formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). It may be provided as a semiconductor material having (Al _x Ga _{1 -x} ) _y In _1-y P (0≤x≤1, 0≤y≤1) as a semiconductor material having a compositional formula. For example, the first and third semiconductor layers 111 and 121 may be selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, and the like. may be selected, and an n-type dopant selected from a group including Si, Ge, Sn, Se, Te, and the like may be doped.

The first and second active layers 112 and 122 may be formed of, for example, a Group 2-6 compound semiconductor or a Group 3-5 compound semiconductor. For example, the first and second active layers 112 and 122 have the composition formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). It may be provided as a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _1-y P (0≤x≤1, 0≤y≤1). For example, the first and second active layers 112 and 122 are selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, and the like. can be For example, the first and second active layers 112 and 122 may be provided in a multi-well structure, and may include a plurality of barrier layers and a plurality of well layers.

The second and fourth semiconductor layers 113 and 123 may be formed of, for example, a group 2-6 compound semiconductor or a group 3-5 compound semiconductor. For example, the second and fourth semiconductor layers 113 and 123 have the composition formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). It may be provided as a semiconductor material having (Al _x Ga _{1 -x} ) _y In _1-y P (0≤x≤1, 0≤y≤1) as a semiconductor material having a compositional formula. For example, the second and fourth semiconductor layers 113 and 123 may include GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, and the like. may be selected, and a p-type dopant selected from the group including Mg, Zn, Ca, Sr, Ba, and the like may be doped.

The semiconductor device 100 according to the embodiment may include a light-transmitting electrode layer 230 as shown in FIG. 2 . The light-transmitting electrode layer 230 can improve the current injection efficiency between the second and fourth semiconductor layers 113 and 123 and the light-transmitting electrode layer 230 , and thus increase the light output of the semiconductor device 100 . can In addition, the light-transmitting electrode layer 230 may transmit light emitted from the active layer 122 . The effect thereof will be described later, and the arrangement position and shape of the light-transmitting electrode layer 230 will be further described while explaining the method of manufacturing a semiconductor device according to the embodiment.

For example, the light-transmitting electrode layer 230 may include at least one selected from the group consisting of a metal, a metal oxide, and a metal nitride.

The light-transmitting electrode layer 230 is, for example, indium tin oxide (ITO), indium zinc oxide (IZO), IZO nitride (IZON), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), or indium (IGZO). gallium zinc oxide), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx/ITO, Ni/IrOx/Au, Ni/ It may include at least one selected from the group including IrOx/Au/ITO, Pt, Ni, Au, Rh, and Pd.

The semiconductor device 100 according to the embodiment may include a reflective layer 160 as shown in FIGS. 1 and 2 . The reflective layer 160 may include a first reflective layer 161 , a second reflective layer 162 , and a third reflective layer 163 . The reflective layer 160 may be disposed on the light-transmitting electrode layer 230 .

As the reflective layer 160 is disposed on the light-transmitting electrode layer 230 , the light emitted from the active layer 123 may be reflected by the reflective layer 160 . Accordingly, it is possible to prevent light emitted from the active layer 123 from being absorbed and lost by the first electrode 141 , the second electrode 142 , and the connection electrode 143 that will be described later. ) of the light extraction efficiency can be improved.

That is, in this embodiment, the light-transmitting electrode layer 230 and the reflective layer 160 are provided in order to secure electrical characteristics. However, the present invention is not limited thereto, and according to another embodiment, an embodiment in which only the reflective layer 160 is provided without disposing the light-transmitting electrode layer 230 may be included to secure both electrical and optical characteristics.

The first reflective layer 161 may be disposed on the first semiconductor structure 110 . The second reflective layer 162 may be disposed on the second semiconductor structure 120 . The third reflective layer 163 may be disposed between the first reflective layer 161 and the second reflective layer 162 . The third reflective layer 163 may be disposed on the first semiconductor structure 110 and the second semiconductor structure 120 .

For example, the third reflective layer 163 may be connected to the first reflective layer 161 . Also, the third reflective layer 163 may be connected to the second reflective layer 162 . The third reflective layer 163 may be disposed in direct physical contact with the first reflective layer 161 and the second reflective layer 162 .

The first reflective layer 161 may include a plurality of openings. The first reflective layer 161 may include a plurality of first openings h1 provided to penetrate in a first direction that is perpendicular to the upper surface of the substrate 105 . Also, the first reflective layer 161 may include a plurality of second openings h2 provided to penetrate in the first direction.

The second reflective layer 162 may include a plurality of openings. The second reflective layer 162 may include a plurality of third openings h3 provided to penetrate in a first direction perpendicular to the upper surface of the substrate 105 . Also, the second reflective layer 162 may include a plurality of fourth openings h4 provided to penetrate in the first direction.

The third reflective layer 163 may include a plurality of openings. The third reflective layer 163 may include a plurality of fifth and fifth openings h5a and h5b provided to penetrate in a first direction perpendicular to the upper surface of the substrate 105 .

Also, the third reflective layer 163 may include a plurality of 6a and 6b openings h6a and h6b provided to penetrate in the first direction. Also, the third reflective layer 163 may include a line opening TH1 provided to penetrate in the first direction.

The line opening TH1 may extend in a second direction perpendicular to the first direction. The line opening TH1 is disposed between the first semiconductor structure 110 and the second semiconductor structure 120 to electrically connect the first and second semiconductor structures 110 and 120 in series. The first electrode of 110 and the second electrode of the second semiconductor structure 120 may be connected to each other.

In this case, in a structure in which the area of the first electrode is wider than that of the second electrode, it may be advantageous in terms of current spreading and current injection characteristics. Accordingly, the line opening TH1 is connected to the first electrode of the first semiconductor structure 110 and is disposed adjacent to the second semiconductor structure 120 , and a fifth opening TH1 facing the line opening TH1 ( TH1 ) h5b) may be disposed wider than the area.

For example, as shown in FIG. 2 , the third reflective layer 163 may include a line opening TH1 and a 5b opening h5b. The line opening TH1 may expose a top surface of the first semiconductor layer 111 . The 5b opening h5b may expose a top surface of the light-transmitting electrode layer 230 disposed on the fourth semiconductor layer 123 .

According to an embodiment, a current diffusion layer 220 may be further disposed under the fifth opening h5b. The current diffusion layer 220 may be disposed between the fourth semiconductor layer 123 and the light-transmitting electrode layer 230 .

The arrangement position and shape of the reflective layer 160 , the light-transmitting electrode layer 230 , and the current diffusion layer 220 according to the embodiment will be further described while describing the method of manufacturing a semiconductor device according to the embodiment.

The reflective layer 160 may be provided as an insulating reflective layer. For example, the reflective layer 160 may be provided as a distributed Bragg reflector (DBR) layer. In addition, the reflective layer 160 may be provided as an Omni Directional Reflector (ODR) layer. In addition, the reflective layer 160 may be provided by stacking a DBR layer and an ODR layer.

The semiconductor device 100 according to the embodiment may include a first electrode 141 , a second electrode 142 , and a connection electrode 143 as shown in FIGS. 1 and 2 .

According to an embodiment, the first electrode 141 and the second electrode 142 may be disposed to be spaced apart from each other. The connection electrode 143 may be disposed between the first electrode 141 and the second electrode 142 .

The first electrode 141 may be disposed on the first reflective layer 161 . A partial region of the first electrode 141 may be disposed on the third reflective layer 163 .

The first electrode 141 may be electrically connected to the second semiconductor layer 113 . The first electrode 141 may be electrically connected to the second semiconductor layer 113 through the plurality of first openings h1 . The first electrode 141 may be disposed in direct contact with the light-transmitting electrode layer 230 disposed under the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided. The first electrode 141 may be disposed in direct contact with the upper surface of the light-transmitting electrode layer 230 exposed by the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided.

The second electrode 142 may be disposed on the second reflective layer 162 . A partial region of the second electrode 142 may be disposed on the third reflective layer 163 .

The second electrode 142 may be electrically connected to the third semiconductor layer 121 . The second electrode 142 may be electrically connected to the third semiconductor layer 121 through the plurality of fourth openings h4 . The second electrode 142 may be disposed in direct contact with the third semiconductor layer 121 disposed under the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. The second electrode 142 may be disposed in direct contact with the upper surface of the third semiconductor layer 121 exposed by the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. there is.

The connection electrode 143 may be disposed on the third reflective layer 163 . A partial region of the connection electrode 143 may be disposed on the first reflective layer 161 . A partial region of the connection electrode 143 may be disposed on the second reflective layer 162 .

The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123 .

The connection electrode 143 includes a first portion 143a disposed on the first semiconductor layer 111 , a second portion 143b disposed on the fourth semiconductor layer 123 , and the first portion A third part 143c connecting the 143a and the second part 143b may be included.

The connection electrode 143 may include the first portion 143a disposed on the region in which the first semiconductor structure 110 is provided. The connection electrode 143 may include a second portion 143b disposed on the region in which the second semiconductor structure 120 is provided. The connection electrode 143 may include the third portion 143c disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120 .

According to an embodiment, the first part 143a may include a first electrode part 143aa and a second electrode part 143ab.

The first portion 143a may be electrically connected to the first semiconductor layer 111 through the plurality of second openings h2 , the plurality of sixtha openings h6a , and the line opening TH1 . .

The second electrode part 143ab of the first part 143a may have the first semiconductor layer 111 through the plurality of second openings h2 in the region provided with the first semiconductor structure 110 . It may be provided in direct contact with the upper surface.

The first electrode part 143aa of the first part 143a may have the first semiconductor layer 111 through the plurality of 6a openings h6a in the region where the first semiconductor structure 110 is provided. It may be provided in direct contact with the upper surface.

In addition, the first electrode part 143aa of the first part 143a may have a top surface of the first semiconductor layer 111 through the line opening TH1 in a region where the first semiconductor structure 110 is provided. may be provided in direct contact with

According to an embodiment, the second part 143b may include a third electrode part 143ba and a fourth electrode part 143bb.

The second portion 143b may be electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 and the plurality of fifth openings h5b.

The fourth electrode part 143bb of the second part 143b may have the fourth semiconductor layer 123 through the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be provided in contact with the upper surface.

The fourth electrode part 143bb of the second part 143b is disposed on the light-transmitting electrode layer 230 under the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact. The fourth electrode part 143bb of the second part 143b is a portion of the light-transmitting electrode layer 230 exposed by the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact with the upper surface.

The third electrode part 143ba of the second part 143b may have the fourth semiconductor layer 123 through the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be provided in contact with the upper surface.

The third electrode part 143ba of the second part 143b is provided on the light-transmitting electrode layer 230 under the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact. The third electrode part 143ba of the second part 143b is a light-transmitting electrode layer 230 exposed by the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact with the upper surface.

In an embodiment, the third portion 143c of the connection electrode 143 may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120 . The third part 143c of the connection electrode 143 may be electrically connected to the first part 143a and the second part 143b.

According to the semiconductor device according to the embodiment, the first electrode 141 may be electrically connected to the second semiconductor layer 113 . The second electrode 142 may be electrically connected to the third semiconductor layer 121 . Also, the connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123 .

Accordingly, according to an embodiment, as power is supplied to the first electrode 141 and the second electrode 142 , the first electrode 141 , the second semiconductor layer 113 , and the first The semiconductor layer 111 , the connection electrode 143 , the fourth semiconductor layer 123 , the third semiconductor layer 121 , and the second electrode 142 may be electrically connected in series.

According to an embodiment, an area in which the first electrode part 143ab contacts the first semiconductor layer 111 is larger than an area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 . can be provided.

An area of the first electrode part 143ab in contact with the first semiconductor layer 111 is an area in which the first semiconductor structure 110 is provided, wherein the first electrode part 143ab is formed through the plurality of 6a openings. The area in direct contact with the upper surface of the first semiconductor layer 111 through (h6a) and the first electrode part 143ab are in direct contact with the upper surface of the first semiconductor layer 111 through the line opening TH1. It may correspond to an area that is a sum of the areas.

In addition, an area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 is, in the region where the second semiconductor structure 120 is provided, the third electrode part 143ba It may correspond to an area of a region in direct contact with the light-transmitting electrode layer 230 disposed under the 5b opening h5b. An area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 is, in the region where the second semiconductor structure 120 is provided, the third electrode part 143ba is the plurality of fifth openings. It may correspond to the area of a region in direct contact with the upper surface of the light-transmitting electrode layer 230 exposed by (h5b).

For example, an area of the first electrode part 143ab in contact with the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of an area of the bottom surface of the substrate 105 . In addition, an area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of an area of the bottom surface of the substrate 105 .

According to an embodiment, the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is compared with the area in which the third electrode part 143ba contacts the fourth semiconductor layer 123, for example. It may be provided in the range of 1.1 times to 2 times.

In this way, the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is larger than the area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 is provided. , carriers can be smoothly diffused, and the operating voltage can be prevented from rising.

The first electrode 141 , the second electrode 142 , and the connection electrode 143 may be formed in a single-layer or multi-layer structure. For example, the first electrode 141 , the second electrode 142 , and the connection electrode 143 may be ohmic electrodes. For example, the first electrode 141 , the second electrode 142 , and the connection electrode 143 may include ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, and Ni/IrOx/ At least one of Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, and Hf, or an alloy of two or more of these materials.

The semiconductor device 100 according to the embodiment may include a protective layer 150 as shown in FIG. 2 .

Meanwhile, for better understanding, in FIG. 1 , the first electrode 141 , the second electrode 142 , the connection electrode 143 , and the reflective layer disposed under the protective layer 150 ( 160), the protective layer 150 is not shown in order to show the arrangement relationship.

The protective layer 150 may be disposed on the first electrode 141 , the second electrode, and the connection electrode 143 .

The protective layer 150 may be disposed on the reflective layer 160 . The protective layer 150 may be disposed on the first reflective layer 161 , the second reflective layer 162 , and the third reflective layer 163 .

The arrangement position and shape of the protective layer 150 will be further described while explaining the method of manufacturing a semiconductor device according to the embodiment.

For example, the protective layer 150 may be made of an insulating material. For example, the protective layer 150 is Si _x O _y , SiO _x N _y , Si _x N _y , Al _x O _y It may be formed of at least one material selected from the group comprising:

As shown in FIG. 1 , the semiconductor device 100 according to the embodiment may include a first bonding pad 171 and a second bonding pad 172 disposed on the protective layer 150 .

The first bonding pad 171 may be disposed on the first reflective layer 161 . Also, the second bonding pad 172 may be disposed on the second reflective layer 162 . The second bonding pad 172 may be disposed to be spaced apart from the first bonding pad 171 .

The first bonding pad 171 may be disposed on the first electrode 141 . The first bonding pad 171 may be electrically connected to the first electrode 141 .

The first bonding pad 171 may be disposed on the first semiconductor structure 110 . The first bonding pad 171 may be disposed on the second semiconductor layer 113 .

The first bonding pad 171 may be disposed on the connection electrode 143 . The first bonding pad 171 may be disposed on the first portion 143a of the connection electrode 143 . The first bonding pad 171 may be disposed on the second electrode part 143ab of the connection electrode 143 .

The second bonding pad 172 may be disposed on the second electrode 142 . The second bonding pad 172 may be electrically connected to the second electrode 142 .

The second bonding pad 172 may be disposed on the second semiconductor structure 120 . The second bonding pad 172 may be disposed on the fourth semiconductor layer 123 .

The second bonding pad 172 may be disposed on the connection electrode 143 . The second bonding pad 172 may be disposed on the second portion 143b of the connection electrode 143 . The second bonding pad 172 may be disposed on the fourth electrode part 143bb of the connection electrode 143 .

According to an embodiment, as shown in FIG. 1 , the connection electrode 143 is disposed on the first portion 143a disposed on the first semiconductor layer 111 and the fourth semiconductor layer 123 . It may include a second part 143b that is formed, and a third part 143c connecting the first part 143a and the second part 143b.

The first portion 143a of the connection electrode 143 includes a first electrode portion 143aa that does not overlap the first bonding pad 171 in a first direction perpendicular to the top surface of the substrate 105 and the A second electrode part 143ab overlapping the first bonding pad 171 may be included.

The second portion 143b of the connection electrode 143 overlaps a third electrode portion 143ba that does not overlap the second bonding pad 172 and the second bonding pad 172 in the first direction. and a fourth electrode part 143bb.

According to an embodiment, an area in which the first electrode part 143ab contacts the first semiconductor layer 111 is larger than an area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 . can be provided.

For example, an area of the first electrode part 143ab in contact with the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of an area of the bottom surface of the substrate 105 . In addition, an area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of an area of the bottom surface of the substrate 105 .

According to an embodiment, the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is compared with the area in which the third electrode part 143ba contacts the fourth semiconductor layer 123, for example. It may be provided in the range of 1.1 times to 2 times.

The first aspect is that the contact area between the first electrode part 143ab and the first semiconductor layer 111 is wider than the contact area between the third electrode part 143ba and the fourth semiconductor layer 123. In a structure in which the first semiconductor layer 111 and the fourth semiconductor layer 123 are connected in series, it may be advantageous in terms of current spreading and current injection characteristics.

In addition, since the contact area between the first electrode part 143ab and the first semiconductor layer 111 is 1.4% or more of the lower surface area of the substrate 105, the first semiconductor layer 111 is current spreading can be efficiently performed. The area in which the first electrode part 143ab and the first semiconductor layer 111 are in contact is provided in a size of 3.3% or less of the lower surface area of the substrate 105, so that the first electrode part 143ab The area of the first active layer 112 to be etched may be adjusted and the light extraction efficiency of the first semiconductor structure 110 may be improved.

An area in which the third electrode part 143ba and the fourth semiconductor layer 123 come in contact is 0.7% or more of the lower surface area of the substrate 105 , so that the current in the fourth semiconductor layer 213 is provided. Diffusion can be performed efficiently. The third electrode part 143ba and the fourth semiconductor layer 123 have a contact area of 3.0% or less compared to the lower surface area of the substrate 105, so that the third electrode part 143ba absorbs it. Thus, the amount of light lost may be reduced and the light extraction efficiency of the second semiconductor structure 120 may be improved.

According to an embodiment, as power is applied to the first bonding pad 171 and the second bonding pad 172 , the first and second semiconductor structures 110 and 120 may emit light.

As power is supplied to the first bonding pad 171 and the second bonding pad 172 , the first bonding pad 171 , the first electrode 141 , the second semiconductor layer 113 , The first semiconductor layer 111 , the connection electrode 143 , the fourth semiconductor layer 123 , the third semiconductor layer 121 , the second electrode 142 , and the second bonding pad 172 . can be electrically connected in series.

According to an embodiment, a high voltage may be applied between the first bonding pad 171 and the second bonding pad 172, and the applied high voltage is applied to the first electrode 141, the connection electrode 143, It can be distributed and supplied to the first and second semiconductor structures 110 and 120 through the second electrode 142 .

As described above, according to the semiconductor device 100 according to the embodiment, the first bonding pad 171 and the first electrode 141 may contact each other in a plurality of regions. Also, the second bonding pad 172 and the second electrode 142 may contact each other in a plurality of regions. Accordingly, according to the embodiment, since power can be supplied through a plurality of regions, there is an advantage that a current dispersion effect occurs and an operating voltage can be reduced according to an increase in the contact area and dispersion of the contact region.

In addition, when power is applied to the first bonding pad 171 and the second bonding pad 172 , the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is the third Since the electrode portion 143ba is provided to be larger than the area in contact with the fourth semiconductor layer 123 , carriers may be smoothly diffused and the operating voltage may be prevented from being increased.

The semiconductor device according to the embodiment may be connected to an external power source by a flip-chip bonding method. For example, in manufacturing a semiconductor device package, the upper surface of the first bonding pad 171 and the upper surface of the second bonding pad 172 may be disposed to be attached to a sub-mount, a lead frame, a circuit board, or the like. there is.

When the semiconductor device according to the embodiment is mounted in a flip-chip bonding method and implemented as a semiconductor device package, the light provided from the first and second semiconductor structures 110 and 120 may be emitted through the substrate 105 . there is. Light emitted from the first and second semiconductor structures 110 and 120 may be reflected by the first reflective layer 161 and the second reflective layer 162 to be emitted toward the substrate 105 .

In addition, light emitted from the first and second semiconductor structures 110 and 120 may also be emitted in a lateral direction of the first and second semiconductor structures 110 and 120 . In addition, light emitted from the first and second semiconductor structures 110 and 120 is emitted from the first bonding pad ( 171) and the second bonding pad 172 may be discharged to the outside through a region not provided.

Specifically, the light emitted from the first and second semiconductor structures 110 and 120 is emitted from the first reflective layer ( 161), the second reflective layer 162, and the third reflective layer 163 may be emitted to the outside through a region not provided.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the first and second semiconductor structures 110 and 120 , and the luminous intensity can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad 171 and the second bonding pad 172 having a large area can be directly bonded to a circuit board providing power, flip The chip bonding process can be easily and stably performed.

Meanwhile, according to the semiconductor device according to the embodiment, when viewed from the upper direction of the semiconductor device 100 , the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is, The pad 171 and the second bonding pad 172 may be provided equal to or smaller than 60% of the total area of the upper surface of the semiconductor device 100 on which the second bonding pad 172 is disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by the horizontal and vertical lengths of the lower surface of the substrate 105 .

In this way, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is provided to be equal to or smaller than 60% of the total area of the semiconductor device 100 , thereby providing the first bonding pad 172 . The amount of light emitted to the surface on which the pad 171 and the second bonding pad 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the direction of six surfaces of the semiconductor device 100 increases, light extraction efficiency is improved and the luminous intensity Po can be increased.

In addition, when viewed from the top of the semiconductor device, the sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is 30% of the total area of the semiconductor device 100 . The same or greater may be provided.

In this way, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is equal to or greater than 30% of the total area of the semiconductor device 100 , so that the first bonding pad 172 is provided. Stable mounting can be performed through the pad 171 and the second bonding pad 172 .

In the semiconductor device 100 according to the embodiment, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is the semiconductor device 100 in consideration of light extraction efficiency and securing stability of bonding. ) of 30% or more of the total area and may be selected as 60% or less.

That is, when the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is 30% or more to 100% or less of the total area of the semiconductor device 100 , the Stable mounting can be performed by securing electrical characteristics and securing bonding force to be mounted on the semiconductor device package.

In addition, when the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is greater than 0% to 60% or less of the total area of the semiconductor device 100 , the first bonding pad 171 is ) and the amount of light emitted to the surface on which the second bonding pad 172 is disposed increases, so that the light extraction efficiency of the semiconductor device 100 may be improved, and the luminous intensity Po may be increased.

In the embodiment, the area of the first bonding pad 171 and the second bonding pad 172 is to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package, and to increase the luminous intensity. The sum of is selected to be 30% or more to 60% or less of the total area of the semiconductor device 100 .

However, the present invention is not limited thereto, and in order to further secure the electrical characteristics and bonding force of the semiconductor device 100 , the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 60% or more. It may be composed of 100% or less, and in order to increase the luminosity more, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 may be configured to be more than 0% and less than 30%. there is.

Also, according to the semiconductor device 100 according to the embodiment, the third reflective layer 163 may be disposed between the first bonding pad 171 and the second bonding pad 172 . For example, a length of the third reflective layer 163 along the major axis of the semiconductor device 100 may be disposed to correspond to a gap between the first bonding pad 171 and the second bonding pad 172 . there is. In addition, the area of the third reflective layer 163 may be, for example, 10% or more and 25% or less of the entire upper surface of the semiconductor device 100 .

When the area of the third reflective layer 163 is 10% or more of the entire upper surface of the semiconductor device 100, discoloration or occurrence of cracks in the package body disposed under the semiconductor device can be prevented, and 25% or more In the following case, it is advantageous to secure light extraction efficiency to emit light on six surfaces of the semiconductor device.

However, the present invention is not limited thereto, and the area of the third reflective layer 163 may be disposed to be greater than 0% to less than 10% of the entire upper surface of the semiconductor device 100 in order to ensure a greater light extraction efficiency, and the If it is necessary to further secure conditions for preventing the occurrence of discoloration or cracks in the package body, the area of the third reflective layer 163 may be arranged to be greater than 25% to less than 100% of the entire upper surface of the semiconductor device 100 . can

As described above, according to the semiconductor device 100 according to the embodiment, the first and second semiconductor structures 110 and 120 are a first region provided between the first bonding pad 171 and the second bonding pad 172 . ) may be provided so that the light generated from it is transmitted and not emitted. In this case, the first region may be a region corresponding to a gap between the first bonding pad 171 and the second bonding pad 172 . Also, the first region may correspond to a length of the third reflective layer 163 disposed in the long axis direction of the semiconductor device.

In addition, the first and second semiconductor structures are a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the side surface disposed in the long axis direction of the semiconductor device 100 . Light generated at (110, 120) may be transmitted and emitted.

In addition, the first and second semiconductor structures are a third region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to a side surface disposed in the short axis direction of the semiconductor device 100 . Light generated at (110, 120) may be transmitted and emitted.

According to an embodiment, the size of the first reflective layer 161 may be several micrometers larger than the size of the first bonding pad 171 . For example, the area of the first reflective layer 161 may be large enough to completely cover the area of the first bonding pad 171 . In consideration of the process error, the length of one side of the first reflective layer 161 may be greater than the length of one side of the first bonding pad 171 by, for example, 4 micrometers to 10 micrometers.

In addition, the size of the second reflective layer 162 may be several micrometers larger than the size of the second bonding pad 172 . For example, the area of the second reflective layer 162 may be large enough to completely cover the area of the second bonding pad 172 . In consideration of the process error, the length of one side of the second reflective layer 162 may be greater than the length of one side of the second bonding pad 172 , for example, by about 4 micrometers to 10 micrometers.

According to an embodiment, by the first reflective layer 161 and the second reflective layer 162 , the light emitted from the first and second semiconductor structures 110 and 120 is transmitted to the first bonding pad 171 and It may be reflected without being incident on the second bonding pad 172 . Accordingly, according to the embodiment, the light generated and emitted from the first and second semiconductor structures 110 and 120 is incident on the first bonding pad 171 and the second bonding pad 172 and is lost. can be minimized

In addition, according to the semiconductor device 100 according to the embodiment, since the third reflective layer 163 is disposed between the first bonding pad 171 and the second bonding pad 172 , the first bonding pad ( 171) and the second bonding pad 172 may reduce light emission.

In addition, the minimum distance between the first bonding pad 171 and the second bonding pad 172 may be equal to or greater than 125 micrometers. The minimum interval between the first bonding pad 171 and the second bonding pad 172 may be selected in consideration of the interval between the first electrode pad and the second electrode pad of the package body on which the semiconductor device 100 is mounted. can

For example, the minimum distance between the first electrode pad and the second electrode pad of the package body may be provided as a minimum of 125 micrometers, and may be provided as a maximum of 200 micrometers. In this case, in consideration of the process error, the interval between the first bonding pad 171 and the second bonding pad 172 may be, for example, 125 micrometers or more and 300 micrometers or less.

In addition, the gap between the first bonding pad 171 and the second bonding pad 172 should be greater than 125 micrometers, and between the first bonding pad 171 and the second bonding pad 172 of the semiconductor device. A minimum space can be secured so that a short circuit does not occur in the , and a light emitting area for improving light extraction efficiency can be secured, so that the luminous intensity Po of the semiconductor device 100 can be increased.

In addition, when the distance between the first bonding pad 171 and the second bonding pad 172 is 300 micrometers or less, the first electrode pad and the second electrode pad of the semiconductor device package and the second electrode pad of the semiconductor device The first bonding pad 171 and the second bonding pad 172 may be bonded with sufficient bonding force, and electrical characteristics of the semiconductor device 100 may be secured.

The minimum distance between the first bonding pad 171 and the second bonding pad 172 is greater than 125 micrometers to secure optical properties, and 300 micrometers to secure reliability due to electrical properties and bonding force. It can be placed smaller than a meter.

In the embodiment, the interval between the first bonding pad 171 and the second bonding pad 172 is 125 micrometers or more and 300 micrometers or less. However, the present invention is not limited thereto, and the interval between the first bonding pad 171 and the second bonding pad 172 may be smaller than 125 micrometers in order to improve electrical characteristics or reliability of the semiconductor device package. , may be disposed larger than 300 micrometers to improve optical properties.

In addition, according to the semiconductor device 100 according to the embodiment, the first reflective layer 161 is disposed under the first electrode 141 , and the second reflective layer 162 is disposed under the second electrode 142 . is placed on Accordingly, the first reflective layer 161 and the second reflective layer 162 reflect light emitted from the first and second active layers 112 and 122 of the first and second semiconductor structures 110 and 120 . Thus, the light absorption at the first electrode 141 and the second electrode 142 can be minimized to improve the luminous intensity Po.

For example, the first reflective layer 161 and the second reflective layer 162 are made of an insulating material, and a material having high reflectivity, for example, a DBR structure, is used to reflect the light emitted from the active layer 114 . can be achieved

The first reflective layer 161 and the second reflective layer 162 may form a DBR structure in which materials having different refractive indices are repeatedly disposed. For example, the first reflective layer 161 and the second reflective layer 162 are TiO ₂ , SiO ₂ , Ta ₂ O ₅ , HfO ₂ . It may be arranged in a single-layer or multi-layer structure including at least one of them.

In addition, according to another embodiment, without being limited thereto, the first reflective layer 161 and the second reflective layer 162 may be formed according to the wavelength of light emitted from the first and second active layers 112 and 122 . The first and second active layers 112 and 122 may be freely selected so as to adjust the reflectivity of the light emitted from the active layers 112 and 122 .

Also, according to another embodiment, the first reflective layer 161 and the second reflective layer 162 may be provided as ODR layers. According to another embodiment, the first reflective layer 161 and the second reflective layer 162 may be provided in a hybrid form in which a DBR layer and an ODR layer are stacked.

For example, since the first bonding pad 171 and the second bonding pad 172 are formed of Au, AuTi, or the like, a mounting factory may be stably performed. In addition, the first bonding pad 171 and the second bonding pad 172 are Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Ge, Ag, Ag alloy, One or more materials or alloys from Au, Hf, Pt, Ru, Rh, ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, and Ni/IrOx/Au/ITO are used to form a single layer or multi-layer can be formed.

As described above, the semiconductor device 100 according to the embodiment may be mounted by, for example, a flip-chip bonding method and provided in the form of a semiconductor device package. At this time, when the package body on which the semiconductor device 100 is mounted is provided with a resin or the like, the package body is discolored by strong light of a short wavelength emitted from the semiconductor device 100 in the lower region of the semiconductor device 100 . or cracks may occur.

However, according to the semiconductor device 100 according to the embodiment, since it is possible to reduce the emission of light between the regions in which the first bonding pad 171 and the second bonding pad 172 are disposed, the semiconductor device 100 ) to prevent discoloration or cracking of the package body disposed in the lower region.

According to an embodiment, the first bonding pad 171 , the second bonding pad 172 , and the third reflective layer 163 are disposed in an area of 20% or more of the upper surface of the semiconductor device 100 . Light generated by the first and second semiconductor structures 110 and 120 may be transmitted and emitted.

Accordingly, according to the embodiment, since the amount of light emitted in the direction of six surfaces of the semiconductor device 100 increases, light extraction efficiency is improved and the luminous intensity Po can be increased. In addition, it is possible to prevent discoloration or cracking of the package body disposed close to the lower surface of the semiconductor device 100 .

Then, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to the accompanying drawings. In describing the method of manufacturing a semiconductor device according to the embodiment, descriptions of matters overlapping with those described with reference to FIGS. 1 and 2 may be omitted.

First, according to the method of manufacturing a semiconductor device according to an embodiment, a semiconductor structure may be formed on the substrate 105 as shown in FIGS. 3A to 3C .

3A is a plan view showing the shape of a semiconductor structure formed according to a method for manufacturing a semiconductor device according to an embodiment, FIG. 3B is a plan view showing a result of performing the unit process shown in FIG. 3A, and FIG. 3C is shown in FIG. 3A A cross-sectional view of the process taken along line AA of the semiconductor device is shown.

According to an embodiment, a semiconductor structure may be formed on the substrate 105 . For example, a first conductivity type semiconductor layer 101 , an active layer 102 , and a second conductivity type semiconductor layer 103 may be formed on the substrate 105 .

Also, according to an embodiment, the current diffusion layer 220 may be formed on the semiconductor structure. The current diffusion layer 220 may be formed on the second conductivity type semiconductor layer 103 . The current spreading layer 220 may be provided in plurality, and may be provided to be spaced apart from each other.

For example, the current diffusion layer 220 may be made of oxide or nitride.

Next, as shown in FIGS. 4A to 4C , a light-transmitting electrode layer 230 may be formed.

4A is a plan view showing the shape of a light-transmitting electrode layer formed according to a method for manufacturing a semiconductor device according to an embodiment, FIG. 4B is a plan view showing a result of the unit process shown in FIG. 4A, and FIG. 4C is a plan view shown in FIG. 4A A cross-sectional view of the process taken along line AA of the semiconductor device is shown.

In an embodiment, the light-transmitting electrode layer 230 may be formed on the semiconductor structure and mesa etching may be performed. The light-transmitting electrode layer 230 may be formed on the second conductivity-type semiconductor layer 103 , and a mesa etching process for exposing the first conductivity-type semiconductor layer 101 may be performed.

According to an embodiment, a partial region of the first conductivity-type semiconductor layer 101 may be exposed through a mesa etching process. A plurality of mesa recesses M exposing a portion of the first conductivity-type semiconductor layer 101 may be formed by the mesa etching process. In addition, a mesa recess line ML through which the semiconductor structure is separated into the first semiconductor structure 110 and the second semiconductor structure 120 may be formed by the mesa etching process.

The first semiconductor structure 110 may include a first semiconductor layer 111 of a first conductivity type, a first active layer 112 , and a second semiconductor layer 113 of a second conductivity type. In addition, the second semiconductor structure 120 may include a third semiconductor layer 121 of a first conductivity type, a second active layer 122 , and a fourth semiconductor layer 123 of a second conductivity type.

In example embodiments, the top surface of the first semiconductor layer 111 or the top surface of the third semiconductor layer 121 may be exposed in the plurality of mesa recesses M regions. Also, a boundary region between the first semiconductor layer 111 and the third semiconductor layer 121 may be exposed in the mesa recess line ML region.

For example, the mesa recess M may be provided in a plurality of circular shapes. The mesa recess M may be provided in various shapes, such as an oval or polygon, as well as a circular shape.

Also, the mesa recess line ML may be formed in a line shape having a predetermined width. For example, the mesa recess line ML may be formed to have different widths according to regions.

According to an embodiment, the light-transmitting electrode layer 230 may be formed on the second conductivity-type semiconductor layer 103 . The light-transmitting electrode layer 230 may include a plurality of openings provided in a region corresponding to the mesa recess M.

Also, the ohmic bonding layer 230 may include a line-shaped opening provided in a region corresponding to the mesa recess line ML.

Next, as shown in FIGS. 5A to 5C , an isolation process may be performed.

5A is a plan view showing the shape of a mask on which an isolation process is performed according to a method for manufacturing a semiconductor device according to an embodiment, FIG. 5B is a plan view showing a result of performing the unit process shown in FIG. 5A, and FIG. 5C is FIG. 5A A process cross-sectional view taken along line AA of the semiconductor device shown in FIG.

According to an embodiment, an isolation process for separating the first semiconductor structure 110 and the second semiconductor structure 120 may be performed.

An isolation line IL separating the first semiconductor structure 110 and the second semiconductor structure 120 may be formed by the isolation process. A top surface of the substrate 105 may be exposed in a region where the isolation line IL is formed.

The first semiconductor structure 110 and the second semiconductor structure 120 may be electrically separated. The first semiconductor layer 111 and the second semiconductor layer 121 may be provided separately from each other. The first semiconductor layer 111 and the second semiconductor layer 121 may be electrically isolated from each other.

Next, as shown in FIGS. 6A to 6C , a reflective layer 160 may be formed.

6A is a plan view illustrating a shape of a reflective layer formed according to a method of manufacturing a semiconductor device according to an embodiment, FIG. 6B is a plan view showing a result of the unit process shown in FIG. 6A, and FIG. 6C is a semiconductor shown in FIG. 6A A cross-sectional view of the process taken along line AA of the device is shown.

The reflective layer 160 may include a first reflective layer 161 , a second reflective layer 162 , and a third reflective layer 163 . The reflective layer 160 may be disposed on the light-transmitting electrode layer 230 . The reflective layer 160 may be disposed on the first semiconductor structure 110 and the second semiconductor structure 120 .

The first reflective layer 161 and the second reflective layer 162 may be disposed to be spaced apart from each other. The third reflective layer 163 may be disposed between the first reflective layer 161 and the second reflective layer 162 .

According to an embodiment, a transmissive part may be provided between the first reflective layer 161 and the third reflective layer 163 . In addition, a transmissive part may be provided between the second reflective layer 162 and the third reflective layer 163 .

The first reflective layer 161 may include a plurality of openings. The first reflective layer 161 may include a plurality of first openings h1 overlapping the current diffusion layer 220 in a first direction perpendicular to the top surface of the substrate 105 . Also, the first reflective layer 161 may include a plurality of second openings h2 overlapping the plurality of mesa recesses M in the first direction.

The light-transmitting electrode layer 230 disposed on the current diffusion layer 220 may be exposed through the plurality of first openings h1 . A top surface of the first semiconductor layer 111 of the first semiconductor structure 110 may be exposed through the plurality of second openings h2 .

For example, the plurality of first openings h1 may be arranged in a plurality of line shapes along the long axis direction of the substrate 105 . In addition, the plurality of second openings h2 may be arranged in a plurality of line shapes along the long axis direction of the substrate 105 . The plurality of first openings h1 and the plurality of second openings h2 may be sequentially arranged with each other in the minor axis direction of the substrate 105 .

The second reflective layer 162 may include a plurality of openings. The second reflective layer 162 may include a plurality of third openings h3 overlapping the current diffusion layer 220 in a first direction perpendicular to the top surface of the substrate 105 . Also, the second reflective layer 162 may include a plurality of fourth openings h4 overlapping the plurality of mesa recesses M in the first direction.

The light-transmitting electrode layer 230 disposed on the current diffusion layer 220 may be exposed through the plurality of third openings h3 . A top surface of the third semiconductor layer 121 of the second semiconductor structure 120 may be exposed through the plurality of fourth openings h4 .

For example, the plurality of third openings h3 may be arranged in a plurality of line shapes along the long axis direction of the substrate 105 . Also, the plurality of fourth openings h4 may be arranged in a plurality of line shapes along the long axis direction of the substrate 105 . The plurality of third openings h3 and the plurality of fourth openings h4 may be sequentially arranged with each other in the short axis direction of the substrate 105 to be provided.

The third reflective layer 163 may include a plurality of openings. The third reflective layer 163 may include a plurality of fifth openings h5 overlapping the current diffusion layer 220 in a first direction perpendicular to the top surface of the substrate 105 .

The plurality of fifth openings h5 may include a plurality of fifth openings h5a exposing the light-transmitting electrode layer 230 disposed on the current diffusion layer 220 in the region where the first semiconductor structure 110 is provided. can In addition, the plurality of fifth openings h5 includes a plurality of fifth openings h5b exposing the light-transmitting electrode layer 230 disposed on the current diffusion layer 220 in the region where the second semiconductor structure 120 is provided. may include

Also, the third reflective layer 163 may include a plurality of sixth openings h6 overlapping the plurality of mesa recesses M in the first direction. Also, the third reflective layer 163 may include a line opening TH1 overlapping the mesa recess line ML in the first direction.

The plurality of sixth openings h6 may include a plurality of sixth openings h6a exposing a top surface of the first semiconductor layer 111 of the first semiconductor structure 110 . In addition, the plurality of sixth openings h6 may include a plurality of 6b openings h6b exposing a top surface of the third semiconductor layer 121 of the second semiconductor structure 120 . The line opening TH1 may expose a top surface of the first semiconductor layer 111 of the first semiconductor structure 110 .

For example, the plurality of fifth openings h5 may be arranged in a plurality of line shapes along the minor axis direction of the substrate 105 . In addition, the plurality of sixth openings h6 may be arranged in a plurality of line shapes along the minor axis direction of the substrate 105 . The plurality of fifth openings h5 and the plurality of sixth openings h6 may be sequentially arranged with each other in the long axis direction of the substrate 105 to be provided.

Also, the line opening TH1 may be provided in a line shape along the minor axis direction of the substrate 105 . An area of the line opening TH1 may be larger than an area of one opening forming the plurality of fifth openings h5 .

For example, the area of the line opening TH1 may be 5 or more times larger than that of one opening forming the plurality of fifth openings h5 . An area of the line opening TH1 may be 9 times or more larger than an area of one opening forming the plurality of fifth openings h5 .

The effect according to the size of the area of the line opening TH1 will be described later.

Subsequently, as shown in FIGS. 7A to 7C , a first electrode 141 , a second electrode 142 , and a connection electrode 143 may be formed.

7A is a plan view showing the shapes of the first electrode, the second electrode, and the connection electrode formed according to the method for manufacturing a semiconductor device according to the embodiment, and FIG. 7B is a plan view showing the result of the unit process shown in FIG. 7A; 7C is a process cross-sectional view taken along line AA of the semiconductor device shown in FIG. 7A.

According to an embodiment, the first electrode 141 and the second electrode 142 may be disposed to be spaced apart from each other. The connection electrode 143 may be disposed between the first electrode 141 and the second electrode 142 .

The first electrode 141 may be disposed on the first reflective layer 161 . A partial region of the first electrode 141 may be disposed on the third reflective layer 163 .

The first electrode 141 may be electrically connected to the second semiconductor layer 113 . The first electrode 141 may be electrically connected to the second semiconductor layer 113 through the plurality of first openings h1 . The first electrode 141 may be disposed in direct contact with the light-transmitting electrode layer 230 disposed under the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided. The first electrode 141 may be disposed in direct contact with the upper surface of the light-transmitting electrode layer 230 exposed by the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided.

The second electrode 142 may be disposed on the second reflective layer 162 . A partial region of the second electrode 142 may be disposed on the third reflective layer 163 .

The second electrode 142 may be electrically connected to the third semiconductor layer 121 . The second electrode 142 may be electrically connected to the third semiconductor layer 121 through the plurality of fourth openings h4 . The second electrode 142 may be disposed in direct contact with the third semiconductor layer 121 disposed under the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. The second electrode 142 may be disposed in direct contact with the upper surface of the third semiconductor layer 121 exposed by the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. there is.

The connection electrode 143 may be disposed on the third reflective layer 163 . A partial region of the connection electrode 143 may be disposed on the first reflective layer 161 . A partial region of the connection electrode 143 may be disposed on the second reflective layer 162 .

The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123 .

The connection electrode 143 includes a first portion 143a disposed on the first semiconductor layer 111 , a second portion 143b disposed on the fourth semiconductor layer 123 , and the first portion A third part 143c connecting the 143a and the second part 143b may be included.

The connection electrode 143 may include the first portion 143a disposed on the region in which the first semiconductor structure 110 is provided. The connection electrode 143 may include a second portion 143b disposed on the region in which the second semiconductor structure 120 is provided. The connection electrode 143 may include the third portion 143c partially disposed on the area provided with the first semiconductor structure 110 and partially disposed over the area provided with the second semiconductor structure 120 . there is. Also, a partial region of the third portion 143c may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120 .

According to an embodiment, the first part 143a may include a first electrode part 143aa and a second electrode part 143ab.

The first portion 143a may be electrically connected to the first semiconductor layer 111 through the plurality of second openings h2 , the plurality of sixtha openings h6a , and the line opening TH1 . .

The second electrode part 143ab of the first part 143a may have the first semiconductor layer 111 through the plurality of second openings h2 in the region provided with the first semiconductor structure 110 . It may be provided in direct contact with the upper surface.

The first electrode part 143aa of the first part 143a may have the first semiconductor layer 111 through the plurality of 6a openings h6a in the region where the first semiconductor structure 110 is provided. It may be provided in direct contact with the upper surface.

In addition, the first electrode part 143aa of the first part 143a may have a top surface of the first semiconductor layer 111 through the line opening TH1 in a region where the first semiconductor structure 110 is provided. may be provided in direct contact with

According to an embodiment, the second part 143b may include a third electrode part 143ba and a fourth electrode part 143bb.

The second portion 143b may be electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 and the plurality of fifth openings h5b.

The fourth electrode part 143bb of the second part 143b may have the fourth semiconductor layer 123 through the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be provided in contact with the upper surface.

The fourth electrode part 143bb of the second part 143b is disposed on the light-transmitting electrode layer 230 under the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact. The fourth electrode part 143bb of the second part 143b is a portion of the light-transmitting electrode layer 230 exposed by the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact with the upper surface.

The third electrode part 143ba of the second part 143b may have the fourth semiconductor layer 123 through the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be provided in contact with the upper surface.

The third electrode part 143ba of the second part 143b is provided on the light-transmitting electrode layer 230 under the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact. The third electrode part 143ba of the second part 143b is a light-transmitting electrode layer 230 exposed by the plurality of 5b openings h5b in the region where the second semiconductor structure 120 is provided. It may be disposed in direct contact with the upper surface.

In an embodiment, the third portion 143c of the connection electrode 143 may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120 . The third part 143c of the connection electrode 143 may be electrically connected to the first part 143a and the second part 143b.

According to the semiconductor device according to the embodiment, the first electrode 141 may be electrically connected to the second semiconductor layer 113 . The second electrode 142 may be electrically connected to the third semiconductor layer 121 . Also, the connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123 .

Accordingly, according to an embodiment, as power is supplied to the first electrode 141 and the second electrode 142 , the first electrode 141 , the second semiconductor layer 113 , and the first The semiconductor layer 111 , the connection electrode 143 , the fourth semiconductor layer 123 , the third semiconductor layer 121 , and the second electrode 142 may be electrically connected in series.

Next, as shown in FIGS. 8A to 8C , a protective layer 150 may be formed.

8A is a plan view showing a shape of a protective layer formed according to a method for manufacturing a semiconductor device according to an embodiment, FIG. 8B is a plan view showing a result of the unit process shown in FIG. 8A, and FIG. 8C is a plan view shown in FIG. 8A A cross-sectional view of the process taken along line AA of the semiconductor device is shown.

The protective layer 150 may be disposed on the first electrode 141 and the second electrode 142 . The protective layer 150 may be disposed on the connection electrode 143 . The protective layer 150 may be disposed on the reflective layer 160 .

The protective layer 150 may include a first contact portion c1 exposing a top surface of the first electrode 141 . The protective layer 150 may include a plurality of first contact portions c1 exposing a top surface of the first electrode 141 . The plurality of first contact portions c1 may be provided on an area in which the first reflective layer 161 is disposed.

The protective layer 150 may include a second contact portion c2 exposing a top surface of the second electrode 142 . The protective layer 150 may include a plurality of second contact portions c2 exposing a plurality of upper surfaces of the second electrode 142 . The second contact portion c2 may be provided on an area in which the second reflective layer 162 is disposed.

Subsequently, as shown in FIGS. 9A to 9C , a first bonding pad 171 and a second bonding pad 172 may be formed.

9A is a plan view showing the shapes of first and second bonding pads formed according to a method for manufacturing a semiconductor device according to an embodiment, FIG. 9B is a plan view showing a result of the unit process shown in FIG. 9A, and FIG. 9C is It is a process cross-sectional view taken along line AA of the semiconductor device shown in FIG. 9A.

According to an embodiment, the first bonding pad 171 and the second bonding pad 172 may be formed in the shape shown in FIG. 9A . The first bonding pad 171 and the second bonding pad 172 may be disposed on the protective layer 150 .

The first bonding pad 171 may be disposed on the first reflective layer 161 . The second bonding pad 172 may be disposed on the second reflective layer 162 . The second bonding pad 172 may be disposed to be spaced apart from the first bonding pad 171 .

The first bonding pad 171 may be disposed on the first electrode 141 . The first bonding pad 171 may be electrically connected to the first electrode 141 .

The first bonding pad 171 may be electrically connected to the first electrode 141 through the first contact portion c1 provided on the protective layer 150 . The first bonding pad 171 may be disposed in direct contact with the upper surface of the first electrode 141 through the first contact portion c1 provided on the protective layer 150 .

The first bonding pad 171 may be disposed on the first semiconductor structure 110 . The first bonding pad 171 may be disposed on the second semiconductor layer 113 .

The first bonding pad 171 may be disposed on the connection electrode 143 . The first bonding pad 171 may be disposed on the first portion 143a of the connection electrode 143 . The first bonding pad 171 may be disposed on the second electrode part 143ab of the connection electrode 143 .

The second bonding pad 172 may be disposed on the second electrode 142 . The second bonding pad 172 may be electrically connected to the second electrode 142 .

The second bonding pad 172 may be disposed on the second semiconductor structure 120 . The second bonding pad 172 may be disposed on the fourth semiconductor layer 123 .

The second bonding pad 172 may be electrically connected to the second electrode 142 through the second contact portion c2 provided on the protective layer 150 . The second bonding pad 172 may be disposed in direct contact with the upper surface of the second electrode 142 through the second contact portion c2 provided on the protective layer 150 .

The second bonding pad 172 may be disposed on the connection electrode 143 . The second bonding pad 172 may be disposed on the second portion 143b of the connection electrode 143 . The second bonding pad 172 may be disposed on the fourth electrode part 143bb of the connection electrode 143 .

According to an embodiment, the connection electrode 143 may include a first portion 143a disposed on the first semiconductor layer 111 , a second portion 143b disposed on the fourth semiconductor layer 123 , and a third part 143c connecting the first part 143a and the second part 143b.

The first portion 143a of the connection electrode 143 includes a first electrode portion 143aa that does not overlap the first bonding pad 171 in a first direction perpendicular to the top surface of the substrate 105 and the A second electrode part 143ab overlapping the first bonding pad 171 may be included.

The second portion 143b of the connection electrode 143 overlaps the third electrode portion 143ba that does not overlap the second bonding pad 172 and the second bonding pad 172 in the first direction. and a fourth electrode part 143bb.

According to an embodiment, an area in which the first electrode part 143ab contacts the first semiconductor layer 111 is larger than an area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 . can be provided.

For example, an area of the first electrode part 143ab in contact with the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of an area of the bottom surface of the substrate 105 . In addition, an area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of an area of the bottom surface of the substrate 105 .

According to an embodiment, the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is compared with the area in which the third electrode part 143ba contacts the fourth semiconductor layer 123, for example. It may be provided in the range of 1.1 times to 2 times.

In this way, the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is larger than the area in which the third electrode part 143ba contacts the fourth semiconductor layer 123 is provided. , carriers can be smoothly diffused, and the operating voltage can be prevented from rising.

According to an embodiment, as power is applied to the first bonding pad 171 and the second bonding pad 172 , the first and second semiconductor structures 110 and 120 may emit light.

As power is supplied to the first bonding pad 171 and the second bonding pad 172 , the first bonding pad 171 , the first electrode 141 , the second semiconductor layer 113 , The first semiconductor layer 111 , the connection electrode 143 , the fourth semiconductor layer 123 , the third semiconductor layer 121 , the second electrode 142 , and the second bonding pad 172 . can be electrically connected in series.

According to an embodiment, a high voltage may be applied between the first bonding pad 171 and the second bonding pad 172, and the applied high voltage is applied to the first electrode 141, the connection electrode 143, It can be distributed and supplied to the first and second semiconductor structures 110 and 120 through the second electrode 142 .

As described above, according to the semiconductor device 100 according to the embodiment, the first bonding pad 171 and the first electrode 141 may contact each other in a plurality of regions. Also, the second bonding pad 172 and the second electrode 142 may contact each other in a plurality of regions. Accordingly, according to the embodiment, since power can be supplied through a plurality of regions, there is an advantage that a current dispersion effect is generated and an operating voltage can be reduced according to an increase in the contact area and dispersion of the contact region.

In addition, when power is applied to the first bonding pad 171 and the second bonding pad 172 , the area in which the first electrode part 143ab contacts the first semiconductor layer 111 is the third Since the electrode portion 143ba is provided to be larger than the area in contact with the fourth semiconductor layer 123 , carriers may be smoothly diffused and the operating voltage may be prevented from being increased.

The semiconductor device according to the embodiment may be connected to an external power source by a flip-chip bonding method. For example, in manufacturing a semiconductor device package, the upper surface of the first bonding pad 171 and the upper surface of the second bonding pad 172 may be disposed to be attached to a sub-mount, a lead frame, a circuit board, or the like. there is.

When the semiconductor device according to the embodiment is mounted in a flip-chip bonding method and implemented as a semiconductor device package, the light provided from the first and second semiconductor structures 110 and 120 may be emitted through the substrate 105 . there is. Light emitted from the first and second semiconductor structures 110 and 120 may be reflected by the first reflective layer 161 and the second reflective layer 162 to be emitted toward the substrate 105 .

In addition, light emitted from the first and second semiconductor structures 110 and 120 may also be emitted in a lateral direction of the first and second semiconductor structures 110 and 120 . In addition, light emitted from the first and second semiconductor structures 110 and 120 is emitted from the first bonding pad ( 171) and the second bonding pad 172 may be discharged to the outside through a region not provided.

Specifically, the light emitted from the first and second semiconductor structures 110 and 120 is emitted from the first reflective layer ( 161), the second reflective layer 162, and the third reflective layer 163 may be emitted to the outside through a region not provided.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the first and second semiconductor structures 110 and 120 , and the luminous intensity can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad 171 and the second bonding pad 172 having a large area can be directly bonded to a circuit board providing power, flip The chip bonding process can be easily and stably performed.

Meanwhile, according to the semiconductor device according to the embodiment, when viewed from the upper direction of the semiconductor device 100 , the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is, The pad 171 and the second bonding pad 172 may be provided equal to or smaller than 60% of the total area of the upper surface of the semiconductor device 100 on which the second bonding pad 172 is disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by the horizontal and vertical lengths of the lower surface of the substrate 105 .

In this way, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is provided to be equal to or smaller than 60% of the total area of the semiconductor device 100 , thereby providing the first bonding pad 172 . The amount of light emitted to the surface on which the pad 171 and the second bonding pad 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the direction of six surfaces of the semiconductor device 100 increases, light extraction efficiency is improved and the luminous intensity Po can be increased.

In addition, when viewed from the top of the semiconductor device, the sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is 30% of the total area of the semiconductor device 100 . The same or greater may be provided.

In this way, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is equal to or greater than 30% of the total area of the semiconductor device 100 , so that the first bonding pad 172 is provided. Stable mounting can be performed through the pad 171 and the second bonding pad 172 .

In the semiconductor device 100 according to the embodiment, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is the semiconductor device 100 in consideration of light extraction efficiency and securing stability of bonding. ) of 30% or more of the total area and may be selected as 60% or less.

That is, when the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is 30% or more to 100% or less of the total area of the semiconductor device 100 , the Stable mounting can be performed by securing electrical characteristics and securing bonding force to be mounted on the semiconductor device package.

In addition, when the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is greater than 0% to 60% or less of the total area of the semiconductor device 100 , the first bonding pad 171 is ) and the amount of light emitted to the surface on which the second bonding pad 172 is disposed increases, so that the light extraction efficiency of the semiconductor device 100 may be improved, and the luminous intensity Po may be increased.

In the embodiment, the area of the first bonding pad 171 and the second bonding pad 172 is to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package, and to increase the luminous intensity. The sum of is selected to be 30% or more to 60% or less of the total area of the semiconductor device 100 .

However, the present invention is not limited thereto, and the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is It may be composed of more than 60% to 100% or less, and in order to further increase the luminous intensity than in the present embodiment, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% and 30% It can be configured by selecting less than.

Also, according to the semiconductor device 100 according to the embodiment, the third reflective layer 163 may be disposed between the first bonding pad 171 and the second bonding pad 172 . For example, a length of the third reflective layer 163 along the major axis of the semiconductor device 100 may be disposed to correspond to a gap between the first bonding pad 171 and the second bonding pad 172 . there is. In addition, the area of the third reflective layer 163 may be, for example, 10% or more and 25% or less of the entire upper surface of the semiconductor device 100 .

When the area of the third reflective layer 163 is 10% or more of the entire upper surface of the semiconductor device 100, discoloration or occurrence of cracks in the package body disposed under the semiconductor device can be prevented, and 25% or more In the following case, it is advantageous to secure light extraction efficiency to emit light on six surfaces of the semiconductor device.

In addition, in another embodiment, the area of the third reflective layer 163 is arranged to be greater than 0% to less than 10% of the entire upper surface of the semiconductor device 100 in order to ensure a greater light extraction efficiency without being limited thereto. In order to prevent discoloration or cracking in the package body, the area of the third reflective layer 163 may be disposed to be greater than 25% to less than 100% of the entire upper surface of the semiconductor device 100 . .

As described above, according to the semiconductor device 100 according to the embodiment, the first and second semiconductor structures 110 and 120 are a first region provided between the first bonding pad 171 and the second bonding pad 172 . ) may be provided so that the light generated from it is transmitted and not emitted. In this case, the first region may be a region corresponding to a gap between the first bonding pad 171 and the second bonding pad 172 . Also, the first region may correspond to a length of the third reflective layer 163 disposed in the long axis direction of the semiconductor device.

In addition, the first and second semiconductor structures are a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the side surface disposed in the long axis direction of the semiconductor device 100 . Light generated at (110, 120) may be transmitted and emitted.

In addition, the first and second semiconductor structures are a third region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to a side surface disposed in the short axis direction of the semiconductor device 100 . Light generated at (110, 120) may be transmitted and emitted.

According to an embodiment, the size of the first reflective layer 161 may be several micrometers larger than the size of the first bonding pad 171 . For example, the area of the first reflective layer 161 may be large enough to completely cover the area of the first bonding pad 171 . In consideration of the process error, the length of one side of the first reflective layer 161 may be greater than the length of one side of the first bonding pad 171 by, for example, 4 micrometers to 10 micrometers.

In addition, the size of the second reflective layer 162 may be several micrometers larger than the size of the second bonding pad 172 . For example, the area of the second reflective layer 162 may be large enough to completely cover the area of the second bonding pad 172 . In consideration of the process error, the length of one side of the second reflective layer 162 may be greater than the length of one side of the second bonding pad 172 , for example, by about 4 micrometers to 10 micrometers.

According to an embodiment, by the first reflective layer 161 and the second reflective layer 162 , the light emitted from the first and second semiconductor structures 110 and 120 is transmitted to the first bonding pad 171 and It may be reflected without being incident on the second bonding pad 172 . Accordingly, according to the embodiment, the light generated and emitted from the first and second semiconductor structures 110 and 120 is incident on the first bonding pad 171 and the second bonding pad 172 and is lost. can be minimized

In addition, according to the semiconductor device 100 according to the embodiment, since the third reflective layer 163 is disposed between the first bonding pad 171 and the second bonding pad 172 , the first bonding pad ( 171) and the second bonding pad 172 may reduce light emission.

In addition, the minimum distance between the first bonding pad 171 and the second bonding pad 172 may be equal to or greater than 125 micrometers. The minimum interval between the first bonding pad 171 and the second bonding pad 172 may be selected in consideration of the interval between the first electrode pad and the second electrode pad of the package body on which the semiconductor device 100 is mounted. can

For example, the minimum distance between the first electrode pad and the second electrode pad of the package body may be provided as a minimum of 125 micrometers, and may be provided as a maximum of 200 micrometers. In this case, in consideration of the process error, the interval between the first bonding pad 171 and the second bonding pad 172 may be, for example, 125 micrometers or more and 300 micrometers or less.

In addition, the gap between the first bonding pad 171 and the second bonding pad 172 should be greater than 125 micrometers, and between the first bonding pad 171 and the second bonding pad 172 of the semiconductor device. A minimum space can be secured so that a short circuit does not occur in the , and a light emitting area for improving light extraction efficiency can be secured, so that the luminous intensity Po of the semiconductor device 100 can be increased.

In addition, when the distance between the first bonding pad 171 and the second bonding pad 172 is 300 micrometers or less, the first electrode pad and the second electrode pad of the semiconductor device package and the second electrode pad of the semiconductor device The first bonding pad 171 and the second bonding pad 172 may be bonded with sufficient bonding force, and electrical characteristics of the semiconductor device 100 may be secured.

The minimum distance between the first bonding pad 171 and the second bonding pad 172 is greater than 125 micrometers to secure optical properties, and 300 micrometers to secure reliability due to electrical properties and bonding force. It can be placed smaller than a meter.

In the embodiment, 125 micrometers or more and 300 micrometers or less are exemplified as the distance between the first bonding pad 171 and the second bonding pad 172 in order to secure reliability by the optical and electrical properties and bonding force. . However, without being limited thereto, the interval between the first bonding pad 171 and the second bonding pad 172 is greater than 125 micrometers in order to further improve the electrical characteristics or reliability of the semiconductor device package than in the present embodiment. It may be arranged to be small, or it may be arranged to be larger than 300 micrometers in order to further improve the optical properties than in the present embodiment.

According to an embodiment, by the first reflective layer 161 and the second reflective layer 162 , the light emitted from the first and second semiconductor structures 110 and 120 is transmitted to the first electrode 141 and the second reflective layer 162 . It may be reflected without being incident on the second electrode 142 . Accordingly, according to the embodiment, light generated and emitted from the first and second semiconductor structures 110 and 120 is incident on the first electrode 141 and the second electrode 142 to minimize loss. can do.

As described above, the semiconductor device 100 according to the embodiment may be mounted by, for example, a flip-chip bonding method and provided in the form of a semiconductor device package. At this time, when the package body on which the semiconductor device 100 is mounted is provided with a resin or the like, the package body is discolored by strong light of a short wavelength emitted from the semiconductor device 100 in the lower region of the semiconductor device 100 . or cracks may occur.

However, according to the semiconductor device 100 according to the embodiment, since it is possible to reduce the emission of light between the regions in which the first bonding pad 171 and the second bonding pad 172 are disposed, the semiconductor device 100 ) to prevent discoloration or cracking of the package body disposed in the lower region.

According to an embodiment, the first bonding pad 171 , the second bonding pad 172 , and the third reflective layer 163 are disposed in an area of 20% or more of the upper surface of the semiconductor device 100 . Light generated by the first and second semiconductor structures 110 may be transmitted and emitted.

Accordingly, according to the embodiment, since the amount of light emitted in the direction of six surfaces of the semiconductor device 100 increases, light extraction efficiency is improved and the luminous intensity Po can be increased. In addition, it is possible to prevent discoloration or cracking of the package body disposed close to the lower surface of the semiconductor device 100 .

Meanwhile, FIG. 10 is a diagram illustrating a semiconductor device package according to an embodiment. In describing the semiconductor device package according to the embodiment with reference to FIG. 10 , descriptions of items overlapping with those described above may be omitted.

The semiconductor device package according to the embodiment includes a package body 305 , a first package electrode 311 and a second package electrode 312 disposed on the package body 305 , and a semiconductor disposed on the package body 305 . The device 100 may include a molding part 230 provided with a phosphor disposed on the semiconductor device 100 . For example, the semiconductor device 100 may be a semiconductor device according to the embodiment described above with reference to the drawings.

For example, the package body 305 may include polyphthalamide (PPA), polychlorotriphenyl (PCT), liquid crystal polymer (LCP), polyamide9T (PA9T), silicone, and epoxy molding compound (EMC). , a material containing metal, ceramic, photo sensitive glass (PSG), sapphire (Al2O3), and a printed circuit board (PCB) may be formed of at least one. Also, the package body 305 may include a high refractive filler such as TiO ₂ and SiO ₂ .

The first package electrode 311 and the second package electrode 312 may include a conductive material. For example, the first package electrode 311 and the second package electrode 312 may include at least one of Ti, Cu, Ni, Au, Cr, Ta, Pt, Sn, Ag, P, Fe, Sn, Zn, and Al. It may include, and may be single-layered or multi-layered.

The semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312 . For example, the semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312 through predetermined first and second bumps 321 and 322 . A first bonding pad 171 and a second bonding pad 172 of the semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312 , respectively.

The first bump 321 and the second bump 322 are formed of a metal having a reflectivity of 80% or more, for example, at least one of Ag, Au, or Al, or an alloy thereof to prevent light absorption by the electrode to extract light efficiency can be improved. For example, the first bump 321 and the second bump 322 may include titanium (Ti), copper (Cu), nickel (Ni), gold (Au), chromium (Cr), and tantalum (Ta). , platinum (Pt), tin (Sn), silver (Ag), may be formed of at least one of phosphorus (P), or a selective alloy thereof.

Also, the semiconductor device 100 may be mounted on the first package electrode 311 and the second package electrode 312 by eutectic bonding without bumps. Also, the semiconductor device 100 may be mounted on the first package electrode 311 and the second package electrode 312 by a bonding layer without bumps.

As described above, the semiconductor device 100 according to the embodiment may emit light in six directions.

As described above with reference to the accompanying drawings, the semiconductor device 100 according to the embodiment provides sufficient bonding force between the first package electrode 311 and the second package electrode 312 . The area of the first bonding pad 171 and the area of the second bonding pad 172 were selected.

In addition, in the semiconductor device 100 according to the embodiment, light enters the region where the first bonding pad 171 and the second bonding pad 172 are disposed in order to improve the efficiency of emitting light in the downward direction as well as the bonding force. The area of the first bonding pad 171 and the area of the second bonding pad 172 were selected in consideration of the size of the transmittable region.

In addition, the light emitted from the first and second semiconductor structures 110 and 120 , among the surfaces on which the first bonding pad 171 and the second bonding pad 172 are disposed, is the first bonding pad 171 and the second bonding pad 172 . 2 The bonding pad 172 may be discharged to the outside through a region not provided. Specifically, the light emitted from the first and second semiconductor structures 110 and 120 is, among surfaces on which the first bonding pad 171 and the second bonding pad 172 are disposed, the reflective layer 160 is not provided. It can be emitted to the outside through the area.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the first and second semiconductor structures 110 and 120 , and the luminous intensity can be remarkably improved.

According to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad and the second bonding pad having a large area can be directly bonded to a circuit board providing power, the flip-chip bonding process can be performed easily and stably. can

Meanwhile, the light emitting device package according to the embodiment may be applied to a light source device.

In addition, the light source device may include a display device, a lighting device, a head lamp, etc. according to an industrial field.

As an example of the light source device, the display device includes a bottom cover, a reflecting plate disposed on the bottom cover, a light emitting module that emits light and includes a light emitting device, and is disposed in front of the reflecting plate and guides light emitted from the light emitting module to the front A light guide plate, an optical sheet including prism sheets disposed in front of the light guide plate, a display panel disposed in front of the optical sheet, an image signal output circuit connected to the display panel and supplying an image signal to the display panel; It may include a color filter disposed in front. Here, the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit. Also, the display device may have a structure in which light emitting devices emitting red, green, and blue light are respectively disposed without including a color filter.

As another example of the light source device, the head lamp is a light emitting module including a light emitting device package disposed on a substrate, a reflector that reflects light emitted from the light emitting module in a predetermined direction, for example, forward, and is reflected by the reflector It may include a lens that refracts light forward, and a shade that blocks or reflects a portion of light reflected by the reflector and directed to the lens to form a light distribution pattern desired by a designer.

A lighting device, which is another example of the light source device, may include a cover, a light source module, a heat sink, a power supply unit, an inner case, and a socket. Also, the light source device according to the embodiment may further include any one or more of a member and a holder. The light source module may include a light emitting device package according to an embodiment.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by a person skilled in the art to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

In the above, the embodiment has been mainly described, but this is only an example and not a limitation on the embodiment, and those of ordinary skill in the art to which the embodiment belongs are provided with several examples not illustrated above within the range that does not depart from the essential characteristics of the embodiment. It can be seen that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

100 semiconductor devices
101 first conductivity type semiconductor layer
102 active layer
103 second conductivity type semiconductor layer
105 board
110 first semiconductor structure
111 first semiconductor layer
112 first active layer
113 second semiconductor layer
120 second semiconductor structure
121 third semiconductor layer
122 second active layer
123 fourth semiconductor layer
220 current spreading layer
230 light-transmitting electrode layer
141 first electrode
142 second electrode
143 connecting electrode
143a first part
143aa first electrode part
143ab second electrode part
143b second part
143ba third electrode part
143bb fourth electrode part
143c third part
150 protective layer
160 reflective layer
161 first reflective layer
162 second reflective layer
163 third reflective layer
171 first bonding pad
172 second bonding pad

Claims (9)

Board;
first and second semiconductor structures disposed on the substrate;
an insulating reflective layer disposed on the first and second semiconductor structures;
a first bonding pad disposed on the first semiconductor structure;
a second bonding pad disposed on the second semiconductor structure; and
a connection electrode disposed on the first semiconductor structure and the second semiconductor structure;
including,
The first semiconductor structure includes a first semiconductor layer disposed on the substrate, a first active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first active layer,
The second semiconductor structure includes a third semiconductor layer disposed on the substrate, a second active layer disposed on the third semiconductor layer, and a fourth semiconductor layer disposed on the second active layer,
The connection electrode includes a first portion disposed on the first semiconductor layer, a second portion disposed on the fourth semiconductor layer, and a third portion connecting the first portion and the second portion,
The first portion of the connection electrode includes a first electrode portion not overlapping the first bonding pad and a second electrode portion overlapping the first bonding pad in a first direction perpendicular to the upper surface of the substrate,
The second portion of the connection electrode includes a third electrode portion that does not overlap the second bonding pad in the first direction and a fourth electrode portion that overlaps the second bonding pad,
The first electrode portion is provided with a size of 1.4% or more and 3.3% or less of the area of the lower surface of the substrate in contact with the first semiconductor layer,
A semiconductor device provided that an area of the third electrode in contact with the fourth semiconductor layer is 0.7% or more and 3.0% or less of an area of a lower surface of the substrate. According to claim 1,
A semiconductor device in which an area in which the first electrode part contacts the first semiconductor layer is larger than an area in which the third electrode part contacts the fourth semiconductor layer. delete According to claim 1,
a first electrode disposed between the first semiconductor structure and the first bonding pad;
a second electrode disposed between the second semiconductor structure and the second bonding pad; further comprising,
The connection electrode is a semiconductor device disposed between the first electrode and the second electrode. 5. The method of claim 4,
The insulating reflective layer includes a first reflective layer, a second reflective layer, and a third reflective layer,
The first reflective layer is disposed between the first semiconductor structure and the first electrode, the second reflective layer is disposed between the second semiconductor structure and the second electrode, and the third reflective layer includes the first reflective layer and A semiconductor device disposed between the second reflective layers. 6. The method of claim 5,
The first reflective layer and the second reflective layer are disposed to be spaced apart from each other,
The third reflective layer is disposed between the first reflective layer and the second reflective layer,
The first reflective layer includes a plurality of openings provided to penetrate in the first direction,
The second reflective layer includes a plurality of openings provided to penetrate in the first direction,
The third reflective layer may include a plurality of openings provided to penetrate in the first direction. delete delete delete

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