KR20190014321A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor device comprises: a substrate; first and second semiconductor structures disposed on the substrate; an insulating reflective layer disposed on the first and second semiconductor structures; a first bonding pad disposed on the first semiconductor structure; a second bonding pad disposed on the second semiconductor structure; and a connection electrode disposed on the first and second semiconductor structures. According to an embodiment of the present invention, the connection electrode includes a first portion disposed on a first semiconductor layer of the first semiconductor structure, a second portion disposed on a fourth semiconductor layer of the second semiconductor structure, and a third portion for connecting the first and second portions. The first portion of the connection electrode includes a first electrode portion which does not overlap the first bonding pad in a first direction perpendicular to an upper surface of the substrate, and a second electrode portion which overlaps the first bonding pad. The second portion of the connection electrode includes a third electrode portion which does not overlap the second bonding pad in the first direction, and a fourth electrode portion which overlaps the second bonding pad. An area of the first electrode portion being in contact with the first semiconductor layer is 1.4 to 3.3% as compared to that of a lower surface of the substrate. An area of the third electrode portion being in contact with the fourth semiconductor layer is 0.7 to 3.0% as compared to that of the bottom surface of the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The embodiment relates to a semiconductor element and a method of manufacturing a semiconductor element, and a semiconductor element package.

Semiconductor devices including compounds such as GaN and AlGaN have many merits such as wide and easy bandgap energy, and can be used variously as light emitting devices, light receiving devices, and various diodes.

Particularly, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group II-VI compound semiconductor material can be used for a variety of applications such as red, Blue and ultraviolet rays can be realized. In addition, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group-VI-VI compound semiconductor material can realize a white light source having high efficiency by using a fluorescent material or combining colors. Such a light emitting device has advantages of low power consumption, semi-permanent lifetime, fast response speed, safety, and environment friendliness compared with conventional light sources such as fluorescent lamps and incandescent lamps.

In addition, when a light-receiving element such as a photodetector or a solar cell is manufactured using a Group III-V or Group-VI-VI compound semiconducting material, development of a device material absorbs light of various wavelength regions to generate a photocurrent , It is possible to use light in various wavelength ranges from the gamma ray to the radio wave region. Further, such a light receiving element has advantages of fast response speed, safety, environmental friendliness and easy control of element materials, and can be easily used for power control or microwave circuit or communication module.

Accordingly, the semiconductor device can be replaced with a transmission module of an optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, White light emitting diode (LED) lighting devices, automotive headlights, traffic lights, and gas and fire sensors. In addition, semiconductor devices can be applied to high frequency application circuits, other power control devices, and communication modules.

The light emitting device can be provided as a pn junction diode having a characteristic in which electric energy is converted into light energy by using a group III-V element or a group II-VI element in the periodic table, Various wavelengths can be realized by adjusting the composition ratio.

For example, nitride semiconductors have received great interest in the development of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. Particularly, a blue light emitting element, a green light emitting element, an ultraviolet (UV) light emitting element, and a red (RED) light emitting element using a nitride semiconductor are commercially available and widely used.

For example, in the case of an ultraviolet light emitting device, it is a light emitting diode that generates light distributed in a wavelength range of 200 nm to 400 nm. It is used for sterilizing and purifying in the wavelength band, short wavelength, Can be used.

 Ultraviolet rays can be divided into UV-A (315nm ~ 400nm), UV-B (280nm ~ 315nm) and UV-C (200nm ~ 280nm) in the long wavelength order. UV-A (315nm ~ 400nm) is applied in various fields such as UV curing for industrial use, curing of printing ink, exposure machine, discrimination of counterfeit, photocatalytic disinfection and special illumination (aquarium / ) Area is used for medical use, and UV-C (200nm ~ 280nm) area is applied to air purification, water purification, sterilization products and the like.

On the other hand, a semiconductor device capable of providing a high output has been requested, and a semiconductor device capable of increasing a power by applying a high power source has been studied.

In addition, studies are being made on a method for improving the light extraction efficiency of a semiconductor device and improving the light intensity at a package end in a semiconductor device package.

Embodiments can provide a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package that can improve a light output and reduce an operating voltage by supplying a high voltage.

Embodiments can provide a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package that can prevent the package body from being deteriorated by light emitted from the semiconductor device.

The embodiment can provide a semiconductor element, a semiconductor element manufacturing method, and a semiconductor element package capable of improving bonding strength between a package electrode and a semiconductor element.

The embodiment can provide a semiconductor element, a semiconductor element manufacturing method, and a semiconductor element package which can prevent the current concentration phenomenon from occurring and improve the reliability.

A semiconductor device according to an embodiment includes: a substrate; First and second semiconductor structures disposed on the substrate; An insulating reflective layer disposed on the first and second semiconductor structures; A first bonding pad disposed on the first semiconductor structure; A second bonding pad disposed on the second semiconductor structure; And a connection electrode disposed on the first semiconductor structure and the second semiconductor structure; Wherein the first semiconductor structure includes a first semiconductor layer disposed on the substrate, a first active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first active layer Wherein the second semiconductor structure includes a third semiconductor layer disposed on the substrate, a second active layer disposed on the third semiconductor layer, and a fourth semiconductor layer disposed on the second active layer, The connecting electrode includes a first portion disposed on the first semiconductor layer, a second portion disposed on the fourth semiconductor layer, and a third portion connecting the first portion and the second portion, Wherein the first portion of the connection electrode includes a first electrode portion that does not overlap the first bonding pad in a first direction perpendicular to an upper surface of the substrate and a second electrode portion that overlaps the first bonding pad, Wherein the second portion of the connecting electrode A third electrode portion that does not overlap with the second bonding pad, and a fourth electrode portion that overlaps with the second bonding pad, wherein an area of the first electrode portion in contact with the first semiconductor layer is 1.4 And the third electrode part is provided in a size of 0.7% or more and 3.0% or less in area in contact with the fourth semiconductor layer, compared to the bottom area of the substrate.

According to the embodiment, an area of the first electrode portion contacting the first semiconductor layer may be larger than an area of the third electrode portion contacting the fourth semiconductor layer.

According to the embodiment, the area of the first electrode portion in contact with the first semiconductor layer may be in a range of 1.1 to 2 times the area of the third electrode portion in contact with the fourth semiconductor layer.

A semiconductor device according to an embodiment includes: a first electrode disposed between the first semiconductor structure and the first bonding pad; A second electrode disposed between the second semiconductor structure and the second bonding pad; And the connection electrode may be disposed between the first electrode and the second electrode.

According to an embodiment of the present invention, the insulating reflective layer includes a first reflective layer, a second reflective layer, and a third reflective layer, the first reflective layer being disposed between the first semiconductor structure and the first electrode, And the third reflective layer may be disposed between the first reflective layer and the second reflective layer.

According to an embodiment of the present invention, the first reflective layer includes a plurality of first openings and a plurality of second openings provided in the first direction, and the second reflective layer includes a plurality of third And the third reflective layer may include a plurality of fifth and a fifth opening portions provided in the first direction, a plurality of sixth and sixth opening portions, and a line opening portion.

According to an embodiment of the present invention, the area of the first electrode portion contacting the first semiconductor layer is larger than the area of the first semiconductor structure provided on the first semiconductor layer through the plurality of sixth opening portions And the area of the first electrode portion that is directly contacted with the upper surface of the first semiconductor layer through the line opening may correspond to an area that is directly contacted.

The semiconductor device according to the embodiment may further include a translucent electrode layer disposed between the first and second semiconductor structures and the reflective layer, and an area of the third electrode portion in contact with the fourth semiconductor layer, The third electrode portion may correspond to an area of an area directly in contact with the light transmitting electrode layer disposed below the plurality of fifth aperture portions.

The semiconductor device according to the embodiment may further include a protective layer disposed between the first and second electrodes and the first and second bonding pads, And a second contact portion exposing a contact portion and an upper surface of the second electrode, wherein the first bonding pad is disposed in direct contact with the upper surface of the first electrode via the first contact portion, And may be disposed in direct contact with the upper surface of the second electrode through the second contact portion.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, the light output can be improved and the operating voltage can be reduced.

According to the embodiments, there is an advantage that the package body can be prevented from being deteriorated by the light emitted from the semiconductor device according to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, the bonding strength between the package electrode and the semiconductor device can be improved.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, it is possible to prevent the current concentration phenomenon from occurring and improve the reliability.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiment, the bonding process is easily performed by arranging the electrode, the reflective layer, and the bonding pad so as to be suitable for the flip chip bonding method, and the transmittance and the reflectance of the emitted light are increased There is an advantage that the light extraction efficiency can be improved.

1 is a plan view of a semiconductor device according to an embodiment of the present invention.
2 is another cross-sectional view taken along the line AA of the semiconductor device shown in Fig.
3A to 3C are diagrams illustrating a step in which a semiconductor layer is formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
4A to 4C are views for explaining a step of forming a transparent electrode layer by a semiconductor device manufacturing method according to an embodiment of the present invention.
5A to 5C are views for explaining a step in which an isolation process is performed by a semiconductor device manufacturing method according to an embodiment of the present invention.
6A to 6C are views illustrating a step of forming a reflective layer by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 7A through 7C illustrate a step of forming a first electrode, a second electrode, and a connection electrode according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.
8A to 8C are diagrams illustrating a step of forming a protective layer by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 9A to 9C illustrate a step of forming a first bonding pad and a second bonding pad according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.
10 is a view showing a semiconductor device package according to an embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the accompanying drawings. In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under" the substrate, each layer Quot; on "and" under "are intended to include both" directly "or" indirectly " do. In addition, the criteria for the top, bottom, or bottom of each layer will be described with reference to drawings, but the embodiment is not limited thereto.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of the semiconductor device shown in FIG.

1, a first electrode (not shown) disposed under the first bonding pad 171 and the second bonding pad 172 but electrically connected to the first bonding pad 171 141 and the second electrode 142 electrically connected to the second bonding pad 172 can be seen.

A semiconductor device 100 according to an embodiment may include a first semiconductor structure 110 and a second semiconductor structure 120 disposed on a substrate 105 as shown in FIGS.

The substrate 105 may be selected from the group consisting of a sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge. For example, the substrate 105 may be provided as a patterned sapphire substrate (PSS) having a concavo-convex pattern formed on its upper surface.

The first semiconductor structure 110 may include a first semiconductor layer 111 of a first conductivity type, a first active layer 112, and a second semiconductor layer 113 of a second conductivity type. The first active layer 112 may be disposed between the first semiconductor layer 111 and the second semiconductor layer 113. For example, the first active layer 112 may be disposed on the first semiconductor layer 111, and the second semiconductor layer 113 may be disposed on the first active layer 112.

The second semiconductor structure 120 may include a third semiconductor layer 121 of a first conductivity type, a second active layer 122, and a fourth semiconductor layer 123 of a second conductivity type. The second active layer 122 may be disposed between the third semiconductor layer 121 and the fourth semiconductor layer 123. For example, the second active layer 122 may be disposed on the third semiconductor layer 121, and the fourth semiconductor layer 123 may be disposed on the second active layer 122.

The first semiconductor layer 111 and the third semiconductor layer 121 are provided as an n-type semiconductor layer, and the second semiconductor layer 113 and the fourth semiconductor layer 123 are formed of p Type semiconductor layer. The first semiconductor layer 111 and the third semiconductor layer 121 are provided as a p-type semiconductor layer and the second semiconductor layer 113 and the fourth semiconductor layer 123 ) May be provided as an n-type semiconductor layer.

The first semiconductor layer 111 and the third semiconductor layer 121 are provided as an n-type semiconductor layer and the second semiconductor layer 113 and the fourth semiconductor layer 123 are formed as an n- type semiconductor layer is provided as a p-type semiconductor layer.

In the above description, the case where the first semiconductor layer 111 and the third semiconductor layer 121 are disposed in contact with each other on the substrate 105 has been described. However, a buffer layer may be further disposed between the first semiconductor layer 111 and the substrate 105 and / or between the third semiconductor layer 121 and the substrate 105. For example, the buffer layer may reduce the difference in lattice constant between the substrate 105 and the first and second semiconductor structures 110 and 120, and may improve crystallinity.

The first and second semiconductor structures 110 and 120 may be formed of a compound semiconductor. The first and second semiconductor structures 110 and 120 may be formed of, for example, Group 2-VI-VI or Group III-V compound semiconductors. For example, the first and second semiconductor structures 110 and 120 may comprise at least two selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic More than two elements may be provided.

The first and third semiconductor layers 111 and 121 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3B-5 compound semiconductor. For example, the first and third semiconductor layers 111 and 121 may be formed of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Or a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _{1 -y} P (0? _X ? 1, 0? _Y? 1). For example, the first and third semiconductor layers 111 and 121 may be formed of a group including GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, And an n-type dopant selected from the group including Si, Ge, Sn, Se, Te and the like can be doped.

The first and second active layers 112 and 122 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3-V compound semiconductor. For example, the first and second active layers 112 and 122 may have a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Or a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _1-y P (0? _X ? 1, 0? _Y? 1). For example, the first and second active layers 112 and 122 may be selected from the group including GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, . For example, the first and second active layers 112 and 122 may be provided in a multi-well structure, and may include a plurality of barrier layers and a plurality of well layers.

The second and fourth semiconductor layers 113 and 123 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3-V compound semiconductor. For example, the second and fourth semiconductor layers 113 and 123 may be formed of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Or a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _{1 -y} P (0? _X ? 1, 0? _Y? 1). For example, the second and fourth semiconductor layers 113 and 123 may be formed of a group including GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, And may be doped with a p-type dopant selected from the group including Mg, Zn, Ca, Sr, Ba, and the like.

The semiconductor device 100 according to the embodiment may include a light-transmitting electrode layer 230, as shown in FIG. The transmissive electrode layer 230 can improve the current injection efficiency between the second and fourth semiconductor layers 113 and 123 and the transmissive electrode layer 230 and thus increase the light output of the semiconductor element 100 . The light transmitting electrode layer 230 may transmit light emitted from the active layer 122. The effect of this will be described later, and the arrangement position and shape of the transparent electrode layer 230 will be further described while explaining the semiconductor device manufacturing method according to the embodiment.

For example, the transparent electrode layer 230 may include at least one selected from the group consisting of a metal, a metal oxide, and a metal nitride.

The transmissive electrode layer 230 may be formed of a material such as ITO (indium tin oxide), IZO (indium zinc oxide), IZON (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO gallium zinc oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / ITO, Ni / IrOx / IrOx / Au / ITO, Pt, Ni, Au, Rh, and Pd.

The semiconductor device 100 according to the embodiment may include a reflective layer 160, as shown in FIGS. The reflective layer 160 may include a first reflective layer 161, a second reflective layer 162, and a third reflective layer 163. The reflective layer 160 may be disposed on the transmissive electrode layer 230.

The reflective layer 160 is disposed on the transparent electrode layer 230 so that light emitted from the active layer 123 can be reflected by the reflective layer 160. Since the light emitted from the active layer 123 can be prevented from being absorbed and lost by the first electrode 141, the second electrode 142 and the connection electrode 143 to be described later, Can be improved.

That is, in this embodiment, the transparent electrode layer 230 and the reflective layer 160 are provided to secure electrical characteristics. However, the present invention is not limited thereto. According to another embodiment, only the reflective layer 160 may be provided without disposing the light-transmitting electrode layer 230 to secure both electrical and optical characteristics.

The first reflective layer 161 may be disposed on the first semiconductor structure 110. The second reflective layer 162 may be disposed on the second semiconductor structure 120. The third reflective layer 163 may be disposed between the first reflective layer 161 and the second reflective layer 162. The third reflective layer 163 may be disposed on the first semiconductor structure 110 and the second semiconductor structure 120.

For example, the third reflective layer 163 may be connected to the first reflective layer 161. The third reflective layer 163 may be connected to the second reflective layer 162. The third reflective layer 163 may be physically in direct contact with the first reflective layer 161 and the second reflective layer 162.

The first reflective layer 161 may include a plurality of openings. The first reflective layer 161 may include a plurality of first openings h1 provided through the first reflective layer 161 in a first direction perpendicular to the upper surface of the substrate 105. [ In addition, the first reflective layer 161 may include a plurality of second openings h2 provided through the first reflective layer 161 in the first direction.

The second reflective layer 162 may include a plurality of openings. The second reflective layer 162 may include a plurality of third openings h3 provided through the substrate 105 in a first direction perpendicular to the upper surface of the substrate 105. [ In addition, the second reflective layer 162 may include a plurality of fourth openings h4 provided in the first direction.

The third reflective layer 163 may include a plurality of openings. The third reflective layer 163 may include a plurality of fifth and fifth openings h5a and h5b provided in a first direction perpendicular to the upper surface of the substrate 105. [

The third reflective layer 163 may include a plurality of sixth and sixth openings h6a and h6b provided through the first reflective layer 163 in the first direction. In addition, the third reflective layer 163 may include a line opening TH1 provided through the first reflective layer 163 in the first direction.

The line opening TH1 may extend in a second direction perpendicular to the first direction. The line opening TH1 is disposed between the first semiconductor structure 110 and the second semiconductor structure 120 to electrically connect the first and second semiconductor structures 110 and 120 to the first semiconductor structure 110 110 and the second electrode of the second semiconductor structure 120 are connected to each other.

At this time, it is advantageous in terms of current diffusion and current injection characteristics in a structure in which the area of the first electrode is wider than the area of the second electrode. The line opening TH1 is connected to the first electrode of the first semiconductor structure 110 and is disposed at a position adjacent to the second semiconductor structure 120. The line opening TH1 is opposed to the line opening TH1, h5b. < / RTI >

For example, the third reflective layer 163 may include a line opening TH1 and a fifth opening h5b, as shown in FIG. The line opening TH1 may expose the upper surface of the first semiconductor layer 111. [ The fifth opening h5b may expose the upper surface of the transparent electrode layer 230 disposed on the fourth semiconductor layer 123. [

According to the embodiment, the current diffusion layer 220 may be further disposed under the fifth opening h5b. The current diffusion layer 220 may be disposed between the fourth semiconductor layer 123 and the light transmitting electrode layer 230.

The arrangement position and shape of the reflective layer 160, the transparent electrode layer 230, and the current diffusion layer 220 according to the embodiment will be further described with reference to a method of manufacturing a semiconductor device according to an embodiment.

The reflective layer 160 may be provided as an insulating reflective layer. For example, the reflective layer 160 may be provided as a DBR (Distributed Bragg Reflector) layer. Also, the reflective layer 160 may be provided as an ODR (Omni Directional Reflector) layer. Also, the reflective layer 160 may be provided by stacking a DBR layer and an ODR layer.

The semiconductor device 100 according to the embodiment may include a first electrode 141, a second electrode 142, and a connection electrode 143, as shown in FIGS. 1 and 2.

According to the embodiment, the first electrode 141 and the second electrode 142 may be spaced apart from each other. The connection electrode 143 may be disposed between the first electrode 141 and the second electrode 142.

The first electrode 141 may be disposed on the first reflective layer 161. A portion of the first electrode 141 may be disposed on the third reflective layer 163.

The first electrode 141 may be electrically connected to the second semiconductor layer 113. The first electrode 141 may be electrically connected to the second semiconductor layer 113 through the plurality of first openings h1. The first electrode 141 may be disposed in direct contact with the transparent electrode layer 230 disposed below the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided. The first electrode 141 may be disposed in direct contact with the upper surface of the transparent electrode layer 230 exposed by the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided.

The second electrode 142 may be disposed on the second reflective layer 162. A portion of the second electrode 142 may be disposed on the third reflective layer 163.

The second electrode 142 may be electrically connected to the third semiconductor layer 121. The second electrode 142 may be electrically connected to the third semiconductor layer 121 through the plurality of fourth openings h4. The second electrode 142 may be disposed in direct contact with the third semiconductor layer 121 disposed below the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. The second electrode 142 may be disposed in direct contact with the upper surface of the third semiconductor layer 121 exposed by the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided have.

The connection electrode 143 may be disposed on the third reflective layer 163. A portion of the connection electrode 143 may be disposed on the first reflective layer 161. A portion of the connection electrode 143 may be disposed on the second reflective layer 162.

The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123.

The connection electrode 143 includes a first portion 143a disposed on the first semiconductor layer 111, a second portion 143b disposed on the fourth semiconductor layer 123, And a third portion 143c connecting the second portion 143a and the second portion 143b.

The connection electrode 143 may include the first portion 143a disposed above the region where the first semiconductor structure 110 is provided. The connection electrode 143 may include a second portion 143b disposed over an area where the second semiconductor structure 120 is provided. The connection electrode 143 may include the third portion 143c disposed on the boundary region between the first semiconductor structure 110 and the second semiconductor structure 120. [

According to the embodiment, the first portion 143a may include a first electrode portion 143aa and a second electrode portion 143ab.

The first portion 143a may be electrically connected to the first semiconductor layer 111 through the plurality of second openings h2, the plurality of sixth opening h6a, and the line opening TH1 .

The second electrode portion 143ab of the first portion 143a is electrically connected to the first semiconductor layer 111 through the plurality of second openings h2 in the region where the first semiconductor structure 110 is provided, And may be provided in direct contact with the upper surface.

The first electrode portion 143aa of the first portion 143a is electrically connected to the first semiconductor layer 111 through the plurality of sixth opening portions h6a in the region where the first semiconductor structure 110 is provided, And may be provided in direct contact with the upper surface.

The first electrode portion 143aa of the first portion 143a is electrically connected to the upper surface of the first semiconductor layer 111 through the line opening TH1 in the region where the first semiconductor structure 110 is provided, As shown in FIG.

According to the embodiment, the second portion 143b may include a third electrode portion 143ba and a fourth electrode portion 143bb.

The second portion 143b may be electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 and the plurality of fifth openings h5b.

The fourth electrode portion 143bb of the second portion 143b is electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. May be provided in contact with the upper surface.

The fourth electrode portion 143bb of the second portion 143b is electrically connected to the transparent electrode layer 230 disposed below the plurality of third openings h3 in the region provided with the second semiconductor structure 120 They can be placed in direct contact. The fourth electrode portion 143bb of the second portion 143b is electrically connected to the light-transmitting electrode layer 230 exposed by the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. And can be disposed in direct contact with the upper surface.

The third electrode portion 143ba of the second portion 143b is electrically connected to the fourth semiconductor layer 123 through the plurality of fifth opening portions h5b in the region where the second semiconductor structure 120 is provided. May be provided in contact with the upper surface.

The third electrode portion 143ba of the second portion 143b is electrically connected to the light transmitting electrode layer 230 disposed below the plurality of fifth opening portions h5b in the region provided with the second semiconductor structure 120 They can be placed in direct contact. The third electrode portion 143ba of the second portion 143b is electrically connected to the light-transmitting electrode layer 230 exposed by the plurality of fifth opening portions h5b in the region where the second semiconductor structure 120 is provided. And can be disposed in direct contact with the upper surface.

According to an embodiment, the third portion 143c of the connection electrode 143 may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120. The third portion 143c of the connection electrode 143 may be electrically connected to the first portion 143a and the second portion 143b.

According to the semiconductor device of the embodiment, the first electrode 141 may be electrically connected to the second semiconductor layer 113. The second electrode 142 may be electrically connected to the third semiconductor layer 121. The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123.

Accordingly, as power is supplied to the first electrode 141 and the second electrode 142, the first electrode 141, the second semiconductor layer 113, the first electrode 141, The semiconductor layer 111, the connection electrode 143, the fourth semiconductor layer 123, the third semiconductor layer 121, and the second electrode 142 can be electrically connected in series.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 Can be provided.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the first semiconductor part 110 in the area where the first semiconductor part 110 is provided, the first electrode portion 143ab is in direct contact with the upper surface of the first semiconductor layer 111 through the line opening TH1 through the contact hole h6a, The area can be matched to the sum of areas.

The area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 is larger than the area of the second semiconductor structure 120 in the area where the third electrode part 143ba is provided, 5b corresponding to the area of the region directly contacting the transparent electrode layer 230 disposed below the opening h5b. The area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 is larger than the area of the second semiconductor structure 120 provided in the third electrode part 143ba, may correspond to the area of an area directly in contact with the upper surface of the transparent electrode layer 230 exposed by the h5b.

For example, the area of the first electrode part 143ab contacting the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of the bottom area of the substrate 105. The area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of the bottom area of the substrate 105.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 May be provided in the range of 1.1 times to 2 times.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 , The carrier can be smoothly diffused, and the operating voltage can be prevented from rising.

The first electrode 141, the second electrode 142, and the connection electrode 143 may have a single-layer structure or a multi-layer structure. For example, the first electrode 141, the second electrode 142, and the connection electrode 143 may be ohmic electrodes. For example, the first electrode 141, the second electrode 142, and the connection electrode 143 may be formed of a metal such as ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, Or an alloy of at least one of Au, ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf.

The semiconductor device 100 according to the embodiment may include a protective layer 150, as shown in FIG.

1, the first electrode 141, the second electrode 142, the connection electrode 143, and the reflective layer (not shown) disposed under the protective layer 150 The protective layer 150 is not shown so that the arrangement relationship of the protective layer 150 and the protective layer 150 can be well shown.

The passivation layer 150 may be disposed on the first electrode 141, the second electrode, and the connection electrode 143.

The protective layer 150 may be disposed on the reflective layer 160. The protective layer 150 may be disposed on the first reflective layer 161, the second reflective layer 162, and the third reflective layer 163.

As for the arrangement position and shape of the protective layer 150, the semiconductor device manufacturing method according to the embodiment will be described in further detail.

For example, the protective layer 150 may be provided as an insulating material. For example, the passivation layer 150 may include at least one of Si _x O _y , SiO _x N _y , Si _x N _y , Al _x O _y And at least one material selected from the group consisting of:

The semiconductor device 100 according to the embodiment may include a first bonding pad 171 and a second bonding pad 172 disposed on the passivation layer 150 as shown in FIG.

The first bonding pad 171 may be disposed on the first reflective layer 161. The second bonding pad 172 may be disposed on the second reflective layer 162. The second bonding pad 172 may be spaced apart from the first bonding pad 171.

The first bonding pad 171 may be disposed on the first electrode 141. The first bonding pad 171 may be electrically connected to the first electrode 141.

The first bonding pad 171 may be disposed on the first semiconductor structure 110. The first bonding pad 171 may be disposed on the second semiconductor layer 113.

The first bonding pad 171 may be disposed on the connection electrode 143. The first bonding pad 171 may be disposed on the first portion 143a of the connection electrode 143. [ The first bonding pad 171 may be disposed on the second electrode portion 143ab of the connection electrode 143. [

The second bonding pad 172 may be disposed on the second electrode 142. The second bonding pad 172 may be electrically connected to the second electrode 142.

The second bonding pad 172 may be disposed on the second semiconductor structure 120. The second bonding pad 172 may be disposed on the fourth semiconductor layer 123.

The second bonding pad 172 may be disposed on the connection electrode 143. The second bonding pad 172 may be disposed on the second portion 143b of the connection electrode 143. [ The second bonding pad 172 may be disposed on the fourth electrode portion 143bb of the connection electrode 143. [

1, the connection electrode 143 may include a first portion 143a disposed on the first semiconductor layer 111, a second portion 143b disposed on the fourth semiconductor layer 123, And a third portion 143c connecting the first portion 143a and the second portion 143b to each other.

The first portion 143a of the connection electrode 143 may include a first electrode portion 143aa that does not overlap the first bonding pad 171 in a first direction perpendicular to the top surface of the substrate 105, And a second electrode part 143ab overlapping the first bonding pad 171. [

The second portion 143b of the connection electrode 143 may include a third electrode portion 143ba that does not overlap the second bonding pad 172 in the first direction and a third electrode portion 143ba that overlaps the second bonding pad 172 And a fourth electrode unit 143bb.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 Can be provided.

For example, the area of the first electrode part 143ab contacting the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of the bottom area of the substrate 105. The area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of the bottom area of the substrate 105.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 May be provided in the range of 1.1 times to 2 times.

It is preferable that an area where the first electrode part 143ab and the first semiconductor layer 111 are in contact with each other is wider than an area where the third electrode part 143ba and the fourth semiconductor layer 123 are in contact with each other, The first semiconductor layer 111 and the fourth semiconductor layer 123 may be connected in series, which is advantageous in terms of current diffusion and current injection characteristics.

The area of the first electrode part 143ab and the first semiconductor layer 111 which are in contact with each other is 1.4% or more of the area of the bottom surface of the substrate 105, Can be efficiently performed. The area of the first electrode part 143ab and the first semiconductor layer 111 that are in contact with each other is less than 3.3% of the bottom area of the substrate 105, The light extraction efficiency of the first semiconductor structure 110 can be improved by controlling the area of the first active layer 112 to be etched.

The area of the third electrode part 143ba that is in contact with the fourth semiconductor layer 123 is 0.7% or more of the area of the bottom surface of the substrate 105, Diffusion can be efficiently performed. The area of the third electrode part 143ba and the fourth semiconductor layer 123 that are in contact with each other is less than 3.0% of the area of the bottom surface of the substrate 105 so that the third electrode part 143ba absorbs And the light extraction efficiency of the second semiconductor structure 120 can be improved.

The first and second semiconductor structures 110 and 120 may emit light when power is applied to the first bonding pad 171 and the second bonding pad 172. In this case,

The first bonding pad 171, the first electrode 141, the second semiconductor layer 113, and the third semiconductor layer 113 are electrically connected to the first bonding pad 171 and the second bonding pad 172, The first semiconductor layer 111, the connection electrode 143, the fourth semiconductor layer 123, the third semiconductor layer 121, the second electrode 142, the second bonding pad 172, Can be electrically connected in series.

A high voltage may be applied between the first bonding pad 171 and the second bonding pad 172 and the applied high voltage may be applied to the first electrode 141, The first and second semiconductor structures 110 and 120 can be dispersed and supplied to the first and second semiconductor structures 110 and 120 through the second electrode 142.

As described above, according to the semiconductor device 100 of the embodiment, the first bonding pad 171 and the first electrode 141 can be contacted in a plurality of regions. Also, the second bonding pad 172 and the second electrode 142 may be in contact with each other in a plurality of regions. Thus, according to the embodiment, power can be supplied through a plurality of regions, so that current dispersion effect is generated according to increase of the contact area and dispersion of the contact region, and operation voltage can be reduced.

In addition, when power is applied to the first bonding pad 171 and the second bonding pad 172, the area of the first electrode part 143ab contacting the first semiconductor layer 111 is smaller than that of the third The electrode portion 143ba is provided to be larger than the area in contact with the fourth semiconductor layer 123, so that the carrier can be smoothly diffused and the operating voltage can be prevented from rising.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, in fabricating a semiconductor device package, the upper surface of the first bonding pad 171 and the upper surface of the second bonding pad 172 may be disposed to attach to a submount, leadframe, have.

The light provided by the first and second semiconductor structures 110 and 120 may be emitted through the substrate 105 when the semiconductor device according to the embodiment is mounted in a flip chip bonding manner to be implemented as a semiconductor device package have. Light emitted from the first and second semiconductor structures 110 and 120 may be reflected by the first reflective layer 161 and the second reflective layer 162 and may be emitted toward the substrate 105.

Also, the light emitted from the first and second semiconductor structures 110 and 120 may be emitted in the lateral direction of the first and second semiconductor structures 110 and 120. The light emitted from the first and second semiconductor structures 110 and 120 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the surface on which the first bonding pad 171 and the second bonding pad 172 are disposed. 171 and the region where the second bonding pad 172 is not provided.

Light emitted from the first and second semiconductor structures 110 and 120 may be transmitted through the first reflective layer 171 and the second reflective layer 172 from the surfaces on which the first bonding pad 171 and the second bonding pad 172 are disposed. 161, the second reflective layer 162, and the third reflective layer 163 are not provided.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions around the first and second semiconductor structures 110 and 120, and the lightness can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad 171 and the second bonding pad 172 having a large area can be directly bonded to the circuit board providing power, The chip bonding process can be performed easily and stably.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 in the upper direction of the semiconductor device 100 may be smaller than the sum of the areas of the first bonding pad 171 and the second bonding pad 172, May be equal to or smaller than 60% of the total area of the upper surface of the semiconductor element 100 on which the pads 171 and the second bonding pads 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to the area defined by the lateral length and the longitudinal length of the lower surface of the substrate 105.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or smaller than 60% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172.

The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be greater than the sum of the areas of the semiconductor devices 100 ) And not more than 60%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is more than 0% to 60% of the total area of the semiconductor device 100, the first bonding pads 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Is selected to be not less than 30% and not more than 60% of the total area of the semiconductor element 100.

However, the present invention is not limited thereto. In order to secure the electrical characteristics and the bonding strength of the semiconductor device 100, the sum of the areas of the first bonding pads 171 and the second bonding pads 172 exceeds 60% The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 may be selected to be more than 0% and less than 30%. have.

The third reflective layer 163 may be disposed between the first bonding pad 171 and the second bonding pad 172 according to the semiconductor device 100 of the embodiment. For example, the length of the third reflective layer 163 along the longitudinal axis of the semiconductor device 100 may be arranged corresponding to the distance between the first bonding pad 171 and the second bonding pad 172 have. The area of the third reflective layer 163 may be 10% or more and 25% or less of the entire upper surface of the semiconductor device 100, for example.

When the area of the third reflective layer 163 is 10% or more of the entire upper surface of the semiconductor element 100, the package body disposed under the semiconductor element may be discolored or cracked, , It is advantageous to secure the light extraction efficiency to emit light to the six surfaces of the semiconductor element.

However, the present invention is not limited thereto, and the area of the third reflective layer 163 may be set to more than 0% and less than 10% of the entire upper surface of the semiconductor element 100, The area of the third reflective layer 163 is set to be more than 25% to less than 100% of the entire upper surface of the semiconductor element 100, if it is necessary to further secure the condition for preventing discoloration or cracking in the package body .

The first and second semiconductor structures 110 and 120 are formed as a first region provided between the first bonding pad 171 and the second bonding pad 172. In this case, May be provided so as not to transmit and release the light generated in the light emitting device. At this time, the first region may be a region corresponding to the interval between the first bonding pad 171 and the second bonding pad 172. The first region may correspond to the length of the third reflective layer 163 disposed in the longitudinal direction of the semiconductor device.

The first and second bonding pads 171 and 172 may be formed on the semiconductor substrate 100. The first and second bonding pads 171 and 172 may be formed of the same material, The light generated in the light emitting devices 110 and 120 can be transmitted and emitted.

The first and second bonding pads 171 and 172 may be formed as a third region provided between the side surface of the semiconductor device 100 in the minor axis direction and the neighboring first bonding pad 171 or the second bonding pad 172, The light generated in the light emitting devices 110 and 120 can be transmitted and emitted.

According to the embodiment, the size of the first reflective layer 161 may be several micrometers larger than the size of the first bonding pad 171. For example, the area of the first reflective layer 161 may be sufficiently large to cover the area of the first bonding pad 171. The length of one side of the first reflective layer 161 may be greater than the length of one side of the first bonding pad 171 by about 4 micrometers to 10 micrometers, for example.

In addition, the size of the second reflective layer 162 may be several micrometers larger than the size of the second bonding pad 172. For example, the area of the second reflective layer 162 may be sufficiently large to cover the area of the second bonding pad 172. The length of one side of the second reflective layer 162 may be greater than the length of one side of the second bonding pad 172 by, for example, 4 micrometers to 10 micrometers.

Light emitted from the first and second semiconductor structures 110 and 120 may be transmitted to the first bonding pad 171 and the second bonding pad 171 by the first reflective layer 161 and the second reflective layer 162, And can be reflected without being incident on the second bonding pad 172. Accordingly, light generated and emitted from the first and second semiconductor structures 110 and 120 is incident on the first bonding pad 171 and the second bonding pad 172 to be lost Can be minimized.

According to the semiconductor device 100 of the embodiment, since the third reflective layer 163 is disposed between the first bonding pad 171 and the second bonding pad 172, 171 and the second bonding pads 172. In this case,

The minimum distance between the first bonding pad 171 and the second bonding pad 172 may be equal to or greater than 125 micrometers. The minimum gap between the first bonding pad 171 and the second bonding pad 172 is selected in consideration of the interval between the first electrode pad and the second electrode pad of the package body on which the semiconductor device 100 is mounted .

By way of example, the minimum spacing between the first and second electrode pads of the package body may be provided at a minimum of 125 micrometers and may be provided at a maximum of 200 micrometers. In this case, considering the process error, the interval between the first bonding pad 171 and the second bonding pad 172 may be 125 micrometers or more and 300 micrometers or less, for example.

The gap between the first bonding pad 171 and the second bonding pad 172 must be greater than 125 micrometers so that the distance between the first bonding pad 171 and the second bonding pad 172 A minimum space can be ensured so that a short circuit does not occur in the semiconductor device 100 and a light emitting area for improving the light extraction efficiency can be ensured so that the light intensity Po of the semiconductor device 100 can be increased.

If the distance between the first bonding pad 171 and the second bonding pad 172 is less than 300 micrometers, the first electrode pad and the second electrode pad of the semiconductor device package, The first bonding pad 171 and the second bonding pad 172 can be bonded with a sufficient bonding force and the electrical characteristics of the semiconductor device 100 can be secured.

The minimum distance between the first bonding pad 171 and the second bonding pad 172 is set to be larger than 125 micrometers in order to secure the optical characteristics. In order to secure the reliability by the electrical characteristic and the bonding force, Meter. ≪ / RTI >

The distance between the first bonding pad 171 and the second bonding pad 172 is 125 micrometers or more and 300 micrometers or less. However, the present invention is not limited thereto, and the interval between the first bonding pad 171 and the second bonding pad 172 may be less than 125 micrometers to improve the electrical characteristics or reliability of the semiconductor device package , And may be arranged larger than 300 micrometers to improve the optical characteristics.

The first reflective layer 161 is disposed under the first electrode 141 and the second reflective layer 162 is disposed under the second electrode 142. [ . The first reflective layer 161 and the second reflective layer 162 reflect light emitted from the first and second active layers 112 and 122 of the first and second semiconductor structures 110 and 120, Thereby minimizing the occurrence of light absorption at the first electrode 141 and the second electrode 142, thereby improving the luminous intensity Po.

For example, the first reflective layer 161 and the second reflective layer 162 may be made of an insulating material, and may be formed of a material having a high reflectance, for example, a DBR structure for reflecting light emitted from the active layer 114 Can be achieved.

The first reflective layer 161 and the second reflective layer 162 may have a DBR structure in which materials having different refractive indexes are repeatedly arranged. For example, the first reflective layer 161 and the second reflective layer 162 may be formed of TiO ₂ , SiO ₂ , Ta ₂ O ₅ , HfO ₂ Or a laminated structure including at least one of them.

The first reflective layer 161 and the second reflective layer 162 are formed on the first and second active layers 112 and 122 in accordance with the wavelength of the light emitted from the first and second active layers 112 and 122, The first and second active layers 112 and 122 may be freely selected so as to control reflectivity of light emitted from the first and second active layers 112 and 122.

According to another embodiment, the first reflective layer 161 and the second reflective layer 162 may be provided as an ODR layer. According to another embodiment, the first reflective layer 161 and the second reflective layer 162 may be provided as a hybrid type in which the DBR layer and the ODR layer are stacked.

For example, the first bonding pad 171 and the second bonding pad 172 are formed of Au, AuTi, or the like, so that the packaging factory can be stably operated. The first bonding pad 171 and the second bonding pad 172 may be formed of a metal such as Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Layer or multilayer structure using at least one material or alloy selected from Au, Hf, Pt, Ru, Rh, ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / .

As described above, the semiconductor device 100 according to the embodiment may be provided in the form of a semiconductor device package, for example, mounted in a flip chip bonding manner. At this time, when the package body on which the semiconductor element 100 is mounted is provided with resin or the like, strong light of a short wavelength emitted from the semiconductor element 100 in the lower region of the semiconductor element 100 causes discoloration Or cracks may occur.

However, according to the semiconductor device 100 according to the embodiment, light emission can be reduced between the regions where the first bonding pads 171 and the second bonding pads 172 are disposed, Can be prevented from being discolored or cracked.

The first bonding pad 171, the second bonding pad 172 and the third reflective layer 163 are formed on the upper surface of the upper surface of the semiconductor device 100. In this embodiment, 1 and the second semiconductor structures 110 and 120 can be transmitted and emitted.

Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased. In addition, it is possible to prevent the package body disposed close to the lower surface of the semiconductor device 100 from being discolored or cracked.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to the accompanying drawings. In explaining the semiconductor device manufacturing method according to the embodiment, description overlapping with those described with reference to FIGS. 1 and 2 may be omitted.

3A to 3C, a semiconductor structure may be formed on a substrate 105. In this case,

3A is a plan view showing the shape of a semiconductor structure formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 3B is a plan view showing the result of performing the unit process shown in FIG. 3A, and FIG. Sectional view of the semiconductor device according to the AA line.

According to an embodiment, a semiconductor structure may be formed on the substrate 105. For example, the first conductive semiconductor layer 101, the active layer 102, and the second conductive semiconductor layer 103 may be formed on the substrate 105.

In addition, according to the embodiment, the current diffusion layer 220 may be formed on the semiconductor structure. The current diffusion layer 220 may be formed on the second conductive semiconductor layer 103. The current diffusion layer 220 may be provided in plurality and may be provided separately from each other.

For example, the current diffusion layer 220 may be provided as an oxide or a nitride.

Next, as shown in FIGS. 4A to 4C, a transparent electrode layer 230 may be formed.

FIG. 4A is a plan view showing the shape of the transparent electrode layer formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 4B is a plan view showing the result of performing the unit process shown in FIG. Sectional view of the semiconductor device according to the AA line.

According to the embodiment, the light transmitting electrode layer 230 may be formed on the semiconductor structure and a mesa etching may be performed. The transmissive electrode layer 230 may be formed on the second conductive semiconductor layer 103 and a mesa etching process may be performed to expose the first conductive semiconductor layer 101.

According to the embodiment, a part of the first conductivity type semiconductor layer 101 may be exposed through a mesa etching process. A plurality of mesa recesses M exposing a part of the first conductivity type semiconductor layer 101 may be formed by the mesa etching process. In addition, a mesa recess line ML may be formed in which the semiconductor structure is divided into the first semiconductor structure 110 and the second semiconductor structure 120 by the mesa etching process.

The first semiconductor structure 110 may include a first semiconductor layer 111 of a first conductivity type, a first active layer 112, and a second semiconductor layer 113 of a second conductivity type. The second semiconductor structure 120 may include a third semiconductor layer 121 of a first conductivity type, a second active layer 122, and a fourth semiconductor layer 123 of a second conductivity type.

According to the embodiment, the upper surface of the first semiconductor layer 111 or the upper surface of the third semiconductor layer 121 may be exposed in the plurality of mesa recesses (M). In addition, a boundary region between the first semiconductor layer 111 and the third semiconductor layer 121 may be exposed in the mesa recess line ML.

As an example, the mesas (M) may be provided in a plurality of circular shapes. The mesa recesses M may be provided in various shapes such as an elliptical shape or a polygonal shape as well as a circular shape.

In addition, the mesa recess line ML may be formed in a line shape having a predetermined width. For example, the mesa recess lines ML may be formed to have different widths depending on regions.

According to the embodiment, the light transmitting electrode layer 230 may be formed on the second conductive semiconductor layer 103. The transmissive electrode layer 230 may include a plurality of openings provided in a region corresponding to the mesa recesses M.

In addition, the ohmic contact layer 230 may include a line-shaped opening provided in a region corresponding to the mesa recess line ML.

Next, as shown in Figs. 5A to 5C, an isolation process can be performed.

FIG. 5A is a plan view showing a shape of a mask in which an isolation process is performed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 5B is a plan view showing a result of performing the unit process shown in FIG. Sectional view of the semiconductor device shown in FIG.

According to the embodiment, an isolation process for separating the first semiconductor structure 110 and the second semiconductor structure 120 may be performed.

An isolation line IL for isolating the first semiconductor structure 110 and the second semiconductor structure 120 may be formed by the isolation process. An upper surface of the substrate 105 may be exposed in an area where the isolation line IL is formed.

The first semiconductor structure 110 and the second semiconductor structure 120 can be electrically separated from each other. The first semiconductor layer 111 and the second semiconductor layer 121 may be provided separately from each other. The first semiconductor layer 111 and the second semiconductor layer 121 may be electrically separated from each other.

Next, as shown in FIGS. 6A to 6C, a reflection layer 160 may be formed.

6A is a plan view showing the shape of a reflective layer formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 6B is a plan view showing a result of performing the unit process shown in FIG. 6A, FIG. Sectional view of the device according to the AA line.

The reflective layer 160 may include a first reflective layer 161, a second reflective layer 162, and a third reflective layer 163. The reflective layer 160 may be disposed on the transmissive electrode layer 230. The reflective layer 160 may be disposed on the first semiconductor structure 110 and the second semiconductor structure 120.

The first reflective layer 161 and the second reflective layer 162 may be spaced apart from each other. The third reflective layer 163 may be disposed between the first reflective layer 161 and the second reflective layer 162.

According to the embodiment, a transmission portion may be provided between the first reflective layer 161 and the third reflective layer 163. [ Also, a transmissive portion may be provided between the second reflective layer 162 and the third reflective layer 163.

The first reflective layer 161 may include a plurality of openings. The first reflective layer 161 may include a plurality of first openings h1 overlapping the current diffusion layer 220 in a first direction perpendicular to the upper surface of the substrate 105. [ The first reflective layer 161 may include a plurality of second openings h2 overlapping the mesa recesses M in the first direction.

The transparent electrode layer 230 disposed on the current diffusion layer 220 may be exposed through the plurality of first openings h1. The upper surface of the first semiconductor layer 111 of the first semiconductor structure 110 may be exposed through the plurality of second openings h2.

For example, the plurality of first openings h1 may be arranged in a plurality of line shapes along the major axis direction of the substrate 105. The plurality of second openings h2 may be arranged in a plurality of line shapes along the major axis direction of the substrate 105. [ The plurality of first openings h1 and the plurality of second openings h2 may be sequentially arranged in the direction of the minor axis of the substrate 105. [

The second reflective layer 162 may include a plurality of openings. The second reflective layer 162 may include a plurality of third openings h3 overlapping the current diffusion layer 220 in a first direction perpendicular to the upper surface of the substrate 105. [ The second reflective layer 162 may include a plurality of fourth openings h4 overlapping the mesa recesses M in the first direction.

The transparent electrode layer 230 disposed on the current diffusion layer 220 may be exposed through the plurality of third openings h3. The upper surface of the third semiconductor layer 121 of the second semiconductor structure 120 may be exposed through the plurality of fourth openings h4.

For example, the plurality of third openings h3 may be arranged in a plurality of line shapes along the major axis direction of the substrate 105. [ The plurality of fourth openings h4 may be arranged in a plurality of line shapes along the major axis direction of the substrate 105. The plurality of third openings h3 and the plurality of fourth openings h4 may be sequentially arranged in the direction of the minor axis of the substrate 105. [

The third reflective layer 163 may include a plurality of openings. The third reflective layer 163 may include a plurality of fifth openings h5 overlapping the current diffusion layer 220 in a first direction perpendicular to the upper surface of the substrate 105. [

The fifth openings h5 may include a plurality of fifth opening h5a exposing the transparent electrode layer 230 disposed on the current diffusion layer 220 in the region where the first semiconductor structure 110 is provided . The plurality of fifth openings h5 may include a plurality of fifth openings h5b exposing the transparent electrode layer 230 disposed on the current diffusion layer 220 in a region where the second semiconductor structure 120 is provided .

The third reflective layer 163 may include a plurality of sixth openings h6 overlapping the mesa recesses M in the first direction. In addition, the third reflective layer 163 may include a line opening TH1 overlapping the mesa recess line ML in the first direction.

The plurality of sixth openings h6 may include a plurality of sixth opening portions h6a exposing the upper surface of the first semiconductor layer 111 of the first semiconductor structure 110. [ The plurality of sixth openings h6 may include a plurality of sixth openings h6b exposing the upper surface of the third semiconductor layer 121 of the second semiconductor structure 120. [ The line opening TH1 may expose the upper surface of the first semiconductor layer 111 of the first semiconductor structure 110. [

For example, the plurality of fifth openings h5 may be arranged in a plurality of line shapes along the minor axis direction of the substrate 105. [ The plurality of sixth openings h6 may be provided in a plurality of line shapes along the minor axis direction of the substrate 105. [ The plurality of fifth openings h5 and the plurality of sixth openings h6 may be sequentially arranged in the longitudinal direction of the substrate 105.

In addition, the line opening TH1 may be provided in a line shape along the minor axis direction of the substrate 105. The area of the line opening TH1 may be larger than the area of one opening constituting the plurality of fifth openings h5.

For example, the area of the line opening TH1 may be 5 times or more larger than the area of one opening forming the fifth openings h5. The area of the line opening TH1 may be 9 times or more larger than the area of one opening constituting the plurality of fifth openings h5.

The effect of the area of the line opening TH1 will be further described later.

7A to 7C, a first electrode 141, a second electrode 142, and a connection electrode 143 may be formed.

FIG. 7A is a plan view showing shapes of a first electrode, a second electrode, and a connection electrode formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 7B is a plan view showing a result of performing the unit process shown in FIG. 7C is a sectional view of the semiconductor device shown in FIG. 7A according to the AA line.

According to the embodiment, the first electrode 141 and the second electrode 142 may be spaced apart from each other. The connection electrode 143 may be disposed between the first electrode 141 and the second electrode 142.

The first electrode 141 may be disposed on the first reflective layer 161. A portion of the first electrode 141 may be disposed on the third reflective layer 163.

The first electrode 141 may be electrically connected to the second semiconductor layer 113. The first electrode 141 may be electrically connected to the second semiconductor layer 113 through the plurality of first openings h1. The first electrode 141 may be disposed in direct contact with the transparent electrode layer 230 disposed below the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided. The first electrode 141 may be disposed in direct contact with the upper surface of the transparent electrode layer 230 exposed by the plurality of first openings h1 in the region where the first semiconductor structure 110 is provided.

The second electrode 142 may be disposed on the second reflective layer 162. A portion of the second electrode 142 may be disposed on the third reflective layer 163.

The second electrode 142 may be electrically connected to the third semiconductor layer 121. The second electrode 142 may be electrically connected to the third semiconductor layer 121 through the plurality of fourth openings h4. The second electrode 142 may be disposed in direct contact with the third semiconductor layer 121 disposed below the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided. The second electrode 142 may be disposed in direct contact with the upper surface of the third semiconductor layer 121 exposed by the plurality of fourth openings h4 in the region where the second semiconductor structure 120 is provided have.

The connection electrode 143 may be disposed on the third reflective layer 163. A portion of the connection electrode 143 may be disposed on the first reflective layer 161. A portion of the connection electrode 143 may be disposed on the second reflective layer 162.

The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123.

The connection electrode 143 includes a first portion 143a disposed on the first semiconductor layer 111, a second portion 143b disposed on the fourth semiconductor layer 123, And a third portion 143c connecting the second portion 143a and the second portion 143b.

The connection electrode 143 may include the first portion 143a disposed above the region where the first semiconductor structure 110 is provided. The connection electrode 143 may include a second portion 143b disposed over an area where the second semiconductor structure 120 is provided. The connecting electrode 143 may include the third portion 143c partially disposed over the region provided with the first semiconductor structure 110 and partially disposed over the region provided with the second semiconductor structure 120 have. A portion of the third portion 143c may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120.

According to the embodiment, the first portion 143a may include a first electrode portion 143aa and a second electrode portion 143ab.

The first portion 143a may be electrically connected to the first semiconductor layer 111 through the plurality of second openings h2, the plurality of sixth opening h6a, and the line opening TH1 .

The second electrode portion 143ab of the first portion 143a is electrically connected to the first semiconductor layer 111 through the plurality of second openings h2 in the region where the first semiconductor structure 110 is provided, And may be provided in direct contact with the upper surface.

The first electrode portion 143aa of the first portion 143a is electrically connected to the first semiconductor layer 111 through the plurality of sixth opening portions h6a in the region where the first semiconductor structure 110 is provided, And may be provided in direct contact with the upper surface.

The first electrode portion 143aa of the first portion 143a is electrically connected to the upper surface of the first semiconductor layer 111 through the line opening TH1 in the region where the first semiconductor structure 110 is provided, As shown in FIG.

According to the embodiment, the second portion 143b may include a third electrode portion 143ba and a fourth electrode portion 143bb.

The second portion 143b may be electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 and the plurality of fifth openings h5b.

The fourth electrode portion 143bb of the second portion 143b is electrically connected to the fourth semiconductor layer 123 through the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. May be provided in contact with the upper surface.

The fourth electrode portion 143bb of the second portion 143b is electrically connected to the transparent electrode layer 230 disposed below the plurality of third openings h3 in the region provided with the second semiconductor structure 120 They can be placed in direct contact. The fourth electrode portion 143bb of the second portion 143b is electrically connected to the light-transmitting electrode layer 230 exposed by the plurality of third openings h3 in the region where the second semiconductor structure 120 is provided. And can be disposed in direct contact with the upper surface.

The third electrode portion 143ba of the second portion 143b is electrically connected to the fourth semiconductor layer 123 through the plurality of fifth opening portions h5b in the region where the second semiconductor structure 120 is provided. May be provided in contact with the upper surface.

The third electrode portion 143ba of the second portion 143b is electrically connected to the light transmitting electrode layer 230 disposed below the plurality of fifth opening portions h5b in the region provided with the second semiconductor structure 120 They can be placed in direct contact. The third electrode portion 143ba of the second portion 143b is electrically connected to the light-transmitting electrode layer 230 exposed by the plurality of fifth opening portions h5b in the region where the second semiconductor structure 120 is provided. And can be disposed in direct contact with the upper surface.

According to an embodiment, the third portion 143c of the connection electrode 143 may be disposed on a boundary region between the first semiconductor structure 110 and the second semiconductor structure 120. The third portion 143c of the connection electrode 143 may be electrically connected to the first portion 143a and the second portion 143b.

According to the semiconductor device of the embodiment, the first electrode 141 may be electrically connected to the second semiconductor layer 113. The second electrode 142 may be electrically connected to the third semiconductor layer 121. The connection electrode 143 may be electrically connected to the first semiconductor layer 111 and the fourth semiconductor layer 123.

Accordingly, as power is supplied to the first electrode 141 and the second electrode 142, the first electrode 141, the second semiconductor layer 113, the first electrode 141, The semiconductor layer 111, the connection electrode 143, the fourth semiconductor layer 123, the third semiconductor layer 121, and the second electrode 142 can be electrically connected in series.

Next, as shown in FIGS. 8A to 8C, a protective layer 150 may be formed.

8A is a plan view showing the shape of a protective layer formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 8B is a plan view showing a result of performing the unit process shown in FIG. 8A, FIG. 8C is a cross- Sectional view of the semiconductor device according to the AA line.

The passivation layer 150 may be disposed on the first electrode 141 and the second electrode 142. The protective layer 150 may be disposed on the connection electrode 143. The protective layer 150 may be disposed on the reflective layer 160.

The passivation layer 150 may include a first contact c1 exposing the top surface of the first electrode 141. [ The passivation layer 150 may include a plurality of first contact portions c1 exposing the upper surface of the first electrode 141. [ The plurality of first contact portions c1 may be provided on a region where the first reflective layer 161 is disposed.

The passivation layer 150 may include a second contact c2 exposing an upper surface of the second electrode 142. [ The passivation layer 150 may include a plurality of second contact portions c2 exposing a plurality of upper surfaces of the second electrode 142. [ The second contact portion c2 may be provided on a region where the second reflective layer 162 is disposed.

Then, as shown in FIGS. 9A to 9C, a first bonding pad 171 and a second bonding pad 172 may be formed.

FIG. 9A is a plan view showing the shapes of the first and second bonding pads formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 9B is a plan view showing the result of performing the unit process shown in FIG. 9A is a sectional view of the semiconductor device according to the AA line.

According to the embodiment, the first bonding pad 171 and the second bonding pad 172 may be formed in the shape shown in FIG. 9A. The first bonding pad 171 and the second bonding pad 172 may be disposed on the passivation layer 150.

The first bonding pad 171 may be disposed on the first reflective layer 161. The second bonding pad 172 may be disposed on the second reflective layer 162. The second bonding pad 172 may be spaced apart from the first bonding pad 171.

The first bonding pad 171 may be disposed on the first electrode 141. The first bonding pad 171 may be electrically connected to the first electrode 141.

The first bonding pad 171 may be electrically connected to the first electrode 141 through the first contact portion c1 provided in the passivation layer 150. [ The first bonding pad 171 may be disposed in direct contact with the upper surface of the first electrode 141 through the first contact portion c1 provided in the passivation layer 150. [

The first bonding pad 171 may be disposed on the first semiconductor structure 110. The first bonding pad 171 may be disposed on the second semiconductor layer 113.

The first bonding pad 171 may be disposed on the connection electrode 143. The first bonding pad 171 may be disposed on the first portion 143a of the connection electrode 143. [ The first bonding pad 171 may be disposed on the second electrode portion 143ab of the connection electrode 143. [

The second bonding pad 172 may be disposed on the second electrode 142. The second bonding pad 172 may be electrically connected to the second electrode 142.

The second bonding pad 172 may be disposed on the second semiconductor structure 120. The second bonding pad 172 may be disposed on the fourth semiconductor layer 123.

The second bonding pad 172 may be electrically connected to the second electrode 142 through the second contact portion c2 provided on the passivation layer 150. [ The second bonding pad 172 may be disposed in direct contact with the upper surface of the second electrode 142 through the second contact portion c2 provided on the passivation layer 150. [

The second bonding pad 172 may be disposed on the connection electrode 143. The second bonding pad 172 may be disposed on the second portion 143b of the connection electrode 143. [ The second bonding pad 172 may be disposed on the fourth electrode portion 143bb of the connection electrode 143. [

The connection electrode 143 may include a first portion 143a disposed on the first semiconductor layer 111, a second portion 143b disposed on the fourth semiconductor layer 123, And a third portion 143c connecting the first portion 143a and the second portion 143b.

The first portion 143a of the connection electrode 143 may include a first electrode portion 143aa that does not overlap the first bonding pad 171 in a first direction perpendicular to the top surface of the substrate 105, And a second electrode part 143ab overlapping the first bonding pad 171. [

The second portion 143b of the connection electrode 143 may include a third electrode portion 143ba that does not overlap the second bonding pad 172 in the first direction and a third electrode portion 143ba that overlaps the second bonding pad 172 And a fourth electrode unit 143bb.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 Can be provided.

For example, the area of the first electrode part 143ab contacting the first semiconductor layer 111 may be 1.4% or more and 3.3% or less of the bottom area of the substrate 105. The area of the third electrode part 143ba in contact with the fourth semiconductor layer 123 may be 0.7% or more and 3.0% or less of the bottom area of the substrate 105.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 May be provided in the range of 1.1 times to 2 times.

The area of the first electrode part 143ab contacting the first semiconductor layer 111 is larger than the area of the third electrode part 143ba contacting the fourth semiconductor layer 123 , The carrier can be smoothly diffused, and the operating voltage can be prevented from rising.

The first and second semiconductor structures 110 and 120 may emit light when power is applied to the first bonding pad 171 and the second bonding pad 172. In this case,

The first bonding pad 171, the first electrode 141, the second semiconductor layer 113, and the third semiconductor layer 113 are electrically connected to the first bonding pad 171 and the second bonding pad 172, The first semiconductor layer 111, the connection electrode 143, the fourth semiconductor layer 123, the third semiconductor layer 121, the second electrode 142, the second bonding pad 172, Can be electrically connected in series.

A high voltage may be applied between the first bonding pad 171 and the second bonding pad 172 and the applied high voltage may be applied to the first electrode 141, The first and second semiconductor structures 110 and 120 can be dispersed and supplied to the first and second semiconductor structures 110 and 120 through the second electrode 142.

As described above, according to the semiconductor device 100 of the embodiment, the first bonding pad 171 and the first electrode 141 can be contacted in a plurality of regions. Also, the second bonding pad 172 and the second electrode 142 may be in contact with each other in a plurality of regions. Thus, according to the embodiment, power can be supplied through a plurality of regions, so that current dispersion effect is generated according to increase of the contact area and dispersion of the contact region, and operation voltage can be reduced.

In addition, when power is applied to the first bonding pad 171 and the second bonding pad 172, the area of the first electrode part 143ab contacting the first semiconductor layer 111 is smaller than that of the third The electrode portion 143ba is provided to be larger than the area in contact with the fourth semiconductor layer 123, so that the carrier can be smoothly diffused and the operating voltage can be prevented from rising.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, in fabricating a semiconductor device package, the upper surface of the first bonding pad 171 and the upper surface of the second bonding pad 172 may be disposed to attach to a submount, leadframe, have.

The light provided by the first and second semiconductor structures 110 and 120 may be emitted through the substrate 105 when the semiconductor device according to the embodiment is mounted in a flip chip bonding manner to be implemented as a semiconductor device package have. Light emitted from the first and second semiconductor structures 110 and 120 may be reflected by the first reflective layer 161 and the second reflective layer 162 and may be emitted toward the substrate 105.

Also, the light emitted from the first and second semiconductor structures 110 and 120 may be emitted in the lateral direction of the first and second semiconductor structures 110 and 120. The light emitted from the first and second semiconductor structures 110 and 120 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the surface on which the first bonding pad 171 and the second bonding pad 172 are disposed. 171 and the region where the second bonding pad 172 is not provided.

Light emitted from the first and second semiconductor structures 110 and 120 may be transmitted through the first reflective layer 171 and the second reflective layer 172 from the surfaces on which the first bonding pad 171 and the second bonding pad 172 are disposed. 161, the second reflective layer 162, and the third reflective layer 163 are not provided.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions around the first and second semiconductor structures 110 and 120, and the lightness can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad 171 and the second bonding pad 172 having a large area can be directly bonded to the circuit board providing power, The chip bonding process can be performed easily and stably.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 in the upper direction of the semiconductor device 100 may be smaller than the sum of the areas of the first bonding pad 171 and the second bonding pad 172, May be equal to or smaller than 60% of the total area of the upper surface of the semiconductor element 100 on which the pads 171 and the second bonding pads 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to the area defined by the lateral length and the longitudinal length of the lower surface of the substrate 105.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or smaller than 60% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172.

The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be greater than the sum of the areas of the semiconductor devices 100 ) And not more than 60%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is more than 0% to 60% of the total area of the semiconductor device 100, the first bonding pads 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Is selected to be not less than 30% and not more than 60% of the total area of the semiconductor element 100.

However, the present invention is not limited thereto. In order to secure the electrical characteristics and the bonding force of the semiconductor device 100 larger than that of the present embodiment, the sum of the areas of the first bonding pad 171 and the second bonding pad 172 The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be more than 0% and not more than 30% Or less.

The third reflective layer 163 may be disposed between the first bonding pad 171 and the second bonding pad 172 according to the semiconductor device 100 of the embodiment. For example, the length of the third reflective layer 163 along the longitudinal axis of the semiconductor device 100 may be arranged corresponding to the distance between the first bonding pad 171 and the second bonding pad 172 have. The area of the third reflective layer 163 may be 10% or more and 25% or less of the entire upper surface of the semiconductor device 100, for example.

When the area of the third reflective layer 163 is 10% or more of the entire upper surface of the semiconductor element 100, the package body disposed under the semiconductor element may be discolored or cracked, , It is advantageous to secure the light extraction efficiency to emit light to the six surfaces of the semiconductor element.

In other embodiments, the area of the third reflective layer 163 may be set to more than 0% and less than 10% of the entire upper surface of the semiconductor element 100 in order to secure a greater light extraction efficiency. And the area of the third reflective layer 163 may be set to more than 25% and less than 100% of the entire upper surface of the semiconductor element 100 in order to prevent discoloration or cracking in the package body .

The first and second semiconductor structures 110 and 120 are formed as a first region provided between the first bonding pad 171 and the second bonding pad 172. In this case, May be provided so as not to transmit and release the light generated in the light emitting device. At this time, the first region may be a region corresponding to the interval between the first bonding pad 171 and the second bonding pad 172. The first region may correspond to the length of the third reflective layer 163 disposed in the longitudinal direction of the semiconductor device.

The first and second bonding pads 171 and 172 may be formed on the semiconductor substrate 100. The first and second bonding pads 171 and 172 may be formed of the same material, The light generated in the light emitting devices 110 and 120 can be transmitted and emitted.

The first and second bonding pads 171 and 172 may be formed as a third region provided between the side surface of the semiconductor device 100 in the minor axis direction and the neighboring first bonding pad 171 or the second bonding pad 172, The light generated in the light emitting devices 110 and 120 can be transmitted and emitted.

According to the embodiment, the size of the first reflective layer 161 may be several micrometers larger than the size of the first bonding pad 171. For example, the area of the first reflective layer 161 may be sufficiently large to cover the area of the first bonding pad 171. The length of one side of the first reflective layer 161 may be greater than the length of one side of the first bonding pad 171 by about 4 micrometers to 10 micrometers, for example.

In addition, the size of the second reflective layer 162 may be several micrometers larger than the size of the second bonding pad 172. For example, the area of the second reflective layer 162 may be sufficiently large to cover the area of the second bonding pad 172. The length of one side of the second reflective layer 162 may be greater than the length of one side of the second bonding pad 172 by, for example, 4 micrometers to 10 micrometers.

Light emitted from the first and second semiconductor structures 110 and 120 may be transmitted to the first bonding pad 171 and the second bonding pad 171 by the first reflective layer 161 and the second reflective layer 162, And can be reflected without being incident on the second bonding pad 172. Accordingly, light generated and emitted from the first and second semiconductor structures 110 and 120 is incident on the first bonding pad 171 and the second bonding pad 172 to be lost Can be minimized.

According to the semiconductor device 100 of the embodiment, since the third reflective layer 163 is disposed between the first bonding pad 171 and the second bonding pad 172, 171 and the second bonding pads 172. In this case,

The minimum distance between the first bonding pad 171 and the second bonding pad 172 may be equal to or greater than 125 micrometers. The minimum gap between the first bonding pad 171 and the second bonding pad 172 is selected in consideration of the interval between the first electrode pad and the second electrode pad of the package body on which the semiconductor device 100 is mounted .

By way of example, the minimum spacing between the first and second electrode pads of the package body may be provided at a minimum of 125 micrometers and may be provided at a maximum of 200 micrometers. In this case, considering the process error, the interval between the first bonding pad 171 and the second bonding pad 172 may be 125 micrometers or more and 300 micrometers or less, for example.

The gap between the first bonding pad 171 and the second bonding pad 172 must be greater than 125 micrometers so that the distance between the first bonding pad 171 and the second bonding pad 172 A minimum space can be ensured so that a short circuit does not occur in the semiconductor device 100 and a light emitting area for improving the light extraction efficiency can be ensured so that the light intensity Po of the semiconductor device 100 can be increased.

If the distance between the first bonding pad 171 and the second bonding pad 172 is less than 300 micrometers, the first electrode pad and the second electrode pad of the semiconductor device package, The first bonding pad 171 and the second bonding pad 172 can be bonded with a sufficient bonding force and the electrical characteristics of the semiconductor device 100 can be secured.

The minimum distance between the first bonding pad 171 and the second bonding pad 172 is set to be larger than 125 micrometers in order to secure the optical characteristics. In order to secure the reliability by the electrical characteristic and the bonding force, Meter. ≪ / RTI >

In the embodiment, the distance between the first bonding pad 171 and the second bonding pad 172 is set to be 125 micrometers or more and 300 micrometers or less in order to secure the optical characteristics, the electrical characteristics, and the reliability by the bonding force . However, the present invention is not limited thereto, and the interval between the first bonding pad 171 and the second bonding pad 172 may be set to be greater than 125 micrometers in order to further improve the electrical characteristics or reliability of the semiconductor device package. Or may be arranged larger than 300 micrometers in order to further improve the optical characteristics than the present embodiment.

Light emitted from the first and second semiconductor structures 110 and 120 may be transmitted to the first electrode 141 and the second electrode 142 by the first reflective layer 161 and the second reflective layer 162, And can be reflected without being incident on the second electrode 142. Thus, according to the embodiment, light generated and emitted from the first and second semiconductor structures 110 and 120 is minimized by being incident on the first electrode 141 and the second electrode 142 can do.

As described above, the semiconductor device 100 according to the embodiment may be provided in the form of a semiconductor device package, for example, mounted in a flip chip bonding manner. At this time, when the package body on which the semiconductor element 100 is mounted is provided with resin or the like, strong light of a short wavelength emitted from the semiconductor element 100 in the lower region of the semiconductor element 100 causes discoloration Or cracks may occur.

However, according to the semiconductor device 100 according to the embodiment, light emission can be reduced between the regions where the first bonding pads 171 and the second bonding pads 172 are disposed, Can be prevented from being discolored or cracked.

The first bonding pad 171, the second bonding pad 172 and the third reflective layer 163 are formed on the upper surface of the upper surface of the semiconductor device 100. In this embodiment, 1 and the second semiconductor structure 110 can be transmitted and emitted.

Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased. In addition, it is possible to prevent the package body disposed close to the lower surface of the semiconductor device 100 from being discolored or cracked.

10 is a view showing a semiconductor device package according to an embodiment. In describing the semiconductor device package according to the embodiment with reference to FIG. 10, description of elements overlapping with those described above may be omitted.

The semiconductor device package according to the embodiment includes a package body 305, a first package electrode 311 and a second package electrode 312 disposed on the package body 305, a semiconductor package 305 disposed on the package body 305, A device 100, and a molding part 230 provided with a phosphor disposed on the semiconductor device 100. As an example, the semiconductor device 100 may be a semiconductor device according to the embodiment described above with reference to the drawings.

For example, the package body 305 may be formed of a material such as polyphthalamide (PPA), polychloro tri phenyl (PCT), liquid crystal polymer (LCP), polyamide 9T, silicone, epoxy molding compound (EMC) , A material including a metal, a ceramic, a photo sensitive glass (PSG), a sapphire (Al2O3), and a printed circuit board (PCB). In addition, the package body 305 may include a high refractive index filler such as TiO ₂ and SiO ₂ .

The first package electrode 311 and the second package electrode 312 may include a conductive material. For example, the first package electrode 311 and the second package electrode 312 may include at least one of Ti, Cu, Ni, Au, Cr, Ta, Pt, Sn, Ag, P, Fe, Sn, And may be a single layer or multiple layers.

The semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312. For example, the semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312 through the first bump 321 and the second bump 322. The first bonding pad 171 and the second bonding pad 172 of the semiconductor device 100 may be electrically connected to the first package electrode 311 and the second package electrode 312, respectively.

The first bump 321 and the second bump 322 may be formed of at least one of a high-reflectivity metal such as Ag, Au, or Al, or an alloy thereof, to prevent light absorption by the electrode, The efficiency can be improved. For example, the first bump 321 and the second bump 322 may be formed of one selected from the group consisting of Ti, Cu, Ni, Au, Cr, , At least one of platinum (Pt), tin (Sn), silver (Ag) and phosphorus (P) or a selective alloy thereof.

In addition, the semiconductor device 100 may be mounted on the first package electrode 311 and the second package electrode 312 by bending without eutectic bonding. In addition, the semiconductor device 100 may be mounted on the first package electrode 311 and the second package electrode 312 by a bonding layer without bumps.

As described above, the semiconductor device 100 according to the embodiment can emit light in six plane directions.

The semiconductor device 100 according to the embodiment may be formed to have a sufficient bonding force with the first package electrode 311 and the second package electrode 312 as described above with reference to the accompanying drawings The area of the first bonding pad 171 and the area of the second bonding pad 172 were selected.

In addition, in the semiconductor device 100 according to the embodiment, the first bonding pad 171 and the second bonding pad 172 are disposed to improve the efficiency of light emission in the downward direction as well as the bonding force. The area of the first bonding pad 171 and the area of the second bonding pad 172 were selected in consideration of the size of the transmissive region.

The light emitted from the first and second semiconductor structures 110 and 120 is emitted from the first bonding pad 171 and the second bonding pad 172 out of the surfaces on which the first bonding pad 171 and the second bonding pad 172 are disposed. 2 bonding pads 172 are not provided. The light emitted from the first and second semiconductor structures 110 and 120 may be transmitted through the first bonding pad 171 and the second bonding pad 172 without the reflective layer 160 And can be discharged to the outside through the region.

Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions around the first and second semiconductor structures 110 and 120, and the lightness can be remarkably improved.

According to the semiconductor device and the semiconductor device package according to the embodiment, since the first bonding pad and the second bonding pad having a large area can be directly bonded to the circuit board providing power, the flip chip bonding process can be easily and stably performed .

Meanwhile, the light emitting device package according to the embodiment can be applied to the light source device.

Further, the light source device may include a display device, a lighting device, a head lamp, and the like depending on an industrial field.

An example of the light source device includes a bottom cover, a reflector disposed on the bottom cover, a light emitting module that emits light and includes a light emitting element, a light emitting module disposed in front of the reflector, An optical sheet including a light guide plate, prism sheets disposed in front of the light guide plate, a display panel disposed in front of the optical sheet, an image signal output circuit connected to the display panel and supplying an image signal to the display panel, And may include a color filter disposed in front thereof. Here, the bottom cover, the reflection plate, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit. The display device may have a structure in which light emitting elements emitting red, green, and blue light are disposed, respectively, without including a color filter.

As another example of the light source device, the head lamp includes a light emitting module including a light emitting device package disposed on a substrate, a reflector that reflects light emitted from the light emitting module in a predetermined direction, for example, forward, A lens that refracts light forward, and a shade that reflects off a portion of the light that is reflected by the reflector and that is directed to the lens to provide the designer with a desired light distribution pattern.

The lighting device, which is another example of the light source device, may include a cover, a light source module, a heat sink, a power supply, an inner case, and a socket. Further, the light source device according to the embodiment may further include at least one of a member and a holder. The light source module may include the light emitting device package according to the embodiment.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention.

100 semiconductor device
101 First conductive type semiconductor layer
102 active layer
103 second conductive semiconductor layer
105 substrate
110 first semiconductor structure
111 first semiconductor layer
112 First active layer
113 second semiconductor layer
120 second semiconductor structure
121 third semiconductor layer
122 second active layer
123 fourth semiconductor layer
220 current diffusion layer
230 transparent electrode layer
141 First electrode
142 Second electrode
143 connecting electrode
143a first part
143aa < / RTI >
143ab second electrode portion
143b Second part
143ba Third electrode portion
143bb The fourth electrode portion
143c Third part
150 protective layer
160 reflective layer
161 First reflective layer
162 Second reflective layer
163 Third reflective layer
171 1st bonding pad
172 2nd bonding pad

Claims (9)

Board;
First and second semiconductor structures disposed on the substrate;
An insulating reflective layer disposed on the first and second semiconductor structures;
A first bonding pad disposed on the first semiconductor structure;
A second bonding pad disposed on the second semiconductor structure; And
A connection electrode disposed on the first semiconductor structure and the second semiconductor structure;
/ RTI >
Wherein the first semiconductor structure includes a first semiconductor layer disposed on the substrate, a first active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first active layer,
Wherein the second semiconductor structure includes a third semiconductor layer disposed on the substrate, a second active layer disposed on the third semiconductor layer, and a fourth semiconductor layer disposed on the second active layer,
The connecting electrode includes a first portion disposed on the first semiconductor layer, a second portion disposed on the fourth semiconductor layer, and a third portion connecting the first portion and the second portion,
The first portion of the connection electrode includes a first electrode portion that does not overlap the first bonding pad in a first direction perpendicular to the top surface of the substrate and a second electrode portion that overlaps the first bonding pad,
The second portion of the connection electrode includes a third electrode portion that does not overlap the second bonding pad in the first direction and a fourth electrode portion that overlaps the second bonding pad,
Wherein an area of the first electrode portion in contact with the first semiconductor layer is 1.4% or more and 3.3% or less of a bottom area of the substrate,
Wherein an area of the third electrode part in contact with the fourth semiconductor layer is 0.7% or more and 3.0% or less of a bottom area of the substrate. The method according to claim 1,
Wherein an area of the first electrode portion in contact with the first semiconductor layer is larger than an area of the third electrode portion in contact with the fourth semiconductor layer. The method according to claim 1,
Wherein an area of the first electrode portion in contact with the first semiconductor layer is in a range of 1.1 times to 2 times the area of the third electrode portion in contact with the fourth semiconductor layer. The method according to claim 1,
A first electrode disposed between the first semiconductor structure and the first bonding pad;
A second electrode disposed between the second semiconductor structure and the second bonding pad; Further comprising:
And the connection electrode is disposed between the first electrode and the second electrode. 5. The method of claim 4,
Wherein the insulating reflective layer includes a first reflective layer, a second reflective layer, and a third reflective layer,
Wherein the first reflective layer is disposed between the first semiconductor structure and the first electrode and the second reflective layer is disposed between the second semiconductor structure and the second electrode, And the second reflective layer. 6. The method of claim 5,
Wherein the first reflective layer includes a plurality of first openings and a plurality of second openings provided through the first reflective layer in the first direction,
Wherein the second reflective layer includes a plurality of third openings and a plurality of fourth openings provided in the first direction,
Wherein the third reflective layer includes a plurality of fifth and a fifth opening portions provided in the first direction, a plurality of sixth opening portions, and a line opening portion. The method according to claim 6,
Wherein the area of the first electrode portion in contact with the first semiconductor layer is larger than the area in which the first electrode portion is in direct contact with the upper surface of the first semiconductor layer through the plurality of the sixth aperture, Wherein the first electrode portion corresponds to an area obtained by adding an area directly in contact with the upper surface of the first semiconductor layer through the line opening. The method according to claim 6,
And a translucent electrode layer disposed between the first and second semiconductor structures and the reflective layer
Wherein an area of the third electrode portion in contact with the fourth semiconductor layer is larger than an area of a region in which the third electrode portion is in direct contact with the translucent electrode layer disposed below the plurality of fifthb opening portions in a region provided with the second semiconductor structure . The method according to claim 1,
Further comprising a protective layer disposed between the first and second electrodes and the first and second bonding pads,
Wherein the protective layer includes a first contact portion exposing an upper surface of the first electrode and a second contact portion exposing an upper surface of the second electrode,
Wherein the first bonding pad is disposed in direct contact with the upper surface of the first electrode through the first contact portion and the second bonding pad is disposed in direct contact with the upper surface of the second electrode through the second contact portion, device.

Images