KR102321668B1 - 언더필재 및 이것을 사용한 반도체 장치의 제조 방법 - Google Patents
언더필재 및 이것을 사용한 반도체 장치의 제조 방법 Download PDFInfo
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- KR102321668B1 KR102321668B1 KR1020157003774A KR20157003774A KR102321668B1 KR 102321668 B1 KR102321668 B1 KR 102321668B1 KR 1020157003774 A KR1020157003774 A KR 1020157003774A KR 20157003774 A KR20157003774 A KR 20157003774A KR 102321668 B1 KR102321668 B1 KR 102321668B1
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Abstract
본 발명은 보이드리스 실장 및 양호한 땜납 접합성을 실현하는 언더필재 및 이것을 사용한 반도체 장치의 제조 방법을 제공한다. 에폭시 수지 및 경화제를 함유하고, 시차 주사 열량계를 사용한 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 상기 반응률의 60%에 도달하는 시간이 3.0sec 이상인 언더필재를 사용한다. 이에 의해, 보이드리스 실장 및 양호한 땜납 접합성을 실현할 수 있다.
Description
본 발명은 반도체 칩의 실장에 사용되는 언더필재 및 이것을 사용한 반도체 장치의 제조 방법에 관한 것이다. 본 출원은 일본에 있어서 2013년 9월 27일에 출원된 일본 특허 출원 번호 특원 제2013-201613호를 기초로 하여 우선권을 주장하는 것이고, 이 출원은 참조로 본 출원에 원용된다.
최근, 반도체 칩의 실장 방법에 있어서, 공정 단축을 목적으로 반도체 IC(Integrated Circuit) 전극 상에 언더필 필름을 부착하는 「선공급형 언더필 필름(PUF:Pre-applied Underfill Film)」의 사용이 검토되고 있다.
이 선공급형 언더필 필름을 사용한 실장 방법은, 예를 들어 이하와 같이 행해진다(예를 들어, 특허문헌 1 참조).
공정 A: 웨이퍼에 언더필 필름을 부착하고 다이싱하여 반도체 칩을 얻는다.
공정 B: 언더필 필름이 접합된 상태에서 반도체 칩을 위치 정렬하여 탑재한다.
공정 C: 반도체 칩을 열 압착하고, 땜납 범프의 금속 결합에 의한 도통 확보 및 언더필 필름의 경화에 의한 접착을 행한다.
이와 같은 실장 방법에 있어서, 땜납 범프를 접합하는 접착제로서 에폭시 수지를 사용한 열경화 접착제가 고안되어 있다. 이 접착제에 있어서, 에폭시 수지의 경화제로서 페놀, 산 무수물, 아민계 경화제 등의 다양한 경화제를 사용한 배합 조성이 고안되어 있다(예를 들어, 특허문헌 2 참조).
고온 압착의 보이드 대책으로서, 경화제로서 과산화물 등을 사용하여 경화 속도를 빠르게 함으로써 보이드리스가 가능하지만, 땜납 접합성이 악화되어 버린다.
본 발명은 이와 같은 종래의 실정을 감안하여 제안된 것으로, 보이드리스 실장 및 양호한 땜납 접합성을 실현하는 언더필재 및 이것을 사용한 반도체 장치의 제조 방법을 제공한다.
본건 발명자는 예의 검토를 행한 결과, 제1 반응률에 이르기까지의 시간이 소정 시간 이하이고, 제1 반응률보다도 높은 제2 반응률에 이르기까지의 시간이 소정 시간 이상인 것에 의해, 보이드리스 실장 및 양호한 땜납 접합성이 얻어지는 것을 발견하여, 본 발명을 완성시키는 데 이르렀다.
즉, 본 발명은 납땜 전극이 형성된 반도체 칩을, 납땜 전극과 대향하는 대향 전극이 형성된 전자 부품에 탑재하기 전에, 반도체 칩에 미리 접합되는 언더필재이며, 에폭시 수지 및 경화제를 함유하고, 시차 주사 열량계를 사용한 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 상기 반응률의 60%에 도달하는 시간이 3.0sec 이상인 것을 특징으로 한다.
또한, 본 발명에 관한 반도체 장치의 제조 방법은 납땜 전극이 형성되고, 상기 전극면에 언더필재가 접합된 반도체 칩을, 상기 납땜 전극과 대향하는 대향 전극이 형성된 전자 부품에 탑재하는 탑재 공정, 및 상기 반도체 칩과 상기 전자 부품을 열 압착하는 열 압착 공정을 갖고, 상기 언더필재는 에폭시 수지 및 경화제를 함유하고, 시차 주사 열량계를 사용한 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 상기 반응률의 60%에 도달하는 시간이 3.0sec 이상인 것을 특징으로 한다.
본 발명에 따르면, 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고 반응률의 60%에 도달하는 시간이 3.0sec 이상인 것에 의해, 보이드리스 실장 및 양호한 땜납 접합성을 실현할 수 있다.
도 1은 탑재 전의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 2는 탑재 시의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 3은 열 압착 후의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 4는 본 실시형태에 있어서의 반도체 장치의 제조 방법을 도시하는 흐름도이다.
도 5는 웨이퍼 상에 언더필 필름을 부착하는 공정을 모식적으로 도시하는 사시도이다.
도 6은 웨이퍼를 다이싱하는 공정을 모식적으로 도시하는 사시도이다.
도 7은 반도체 칩을 픽업하는 공정을 모식적으로 도시하는 사시도이다.
도 8은 DSC-오자와법에 의해 산출된 반응 시간에 대한 언더필 필름의 반응률을 도시하는 그래프이다.
도 2는 탑재 시의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 3은 열 압착 후의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 4는 본 실시형태에 있어서의 반도체 장치의 제조 방법을 도시하는 흐름도이다.
도 5는 웨이퍼 상에 언더필 필름을 부착하는 공정을 모식적으로 도시하는 사시도이다.
도 6은 웨이퍼를 다이싱하는 공정을 모식적으로 도시하는 사시도이다.
도 7은 반도체 칩을 픽업하는 공정을 모식적으로 도시하는 사시도이다.
도 8은 DSC-오자와법에 의해 산출된 반응 시간에 대한 언더필 필름의 반응률을 도시하는 그래프이다.
이하, 본 발명의 실시형태에 대해, 하기 순서에 의해 상세하게 설명한다.
1. 언더필재
2. 반도체 장치의 제조 방법
3. 실시예
<1. 언더필재>
본 실시형태에 관한 언더필재는 납땜 전극이 형성된 반도체 칩을, 납땜 전극과 대향하는 대향 전극이 형성된 전자 부품에 탑재하기 전에 반도체 칩에 미리 접합시키는 것이다.
도 1은 탑재 전의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이고, 도 2는 탑재 시의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이고, 도 3은 열 압착 후의 반도체 칩과 회로 기판을 모식적으로 도시하는 단면도이다.
도 1 내지 도 3에 도시한 바와 같이, 본 실시형태에 있어서의 언더필재(20)는 납땜 전극이 형성된 반도체 칩(10)의 전극면에 미리 접합되어 사용되고, 언더필재(20)가 경화된 접착층(21)에 의해 반도체 칩(10)과, 납땜 전극과 대향하는 대향 전극이 형성된 회로 기판(30)을 접합한다.
반도체 칩(10)은 실리콘 등의 반도체(11) 표면에 집적 회로가 형성되고, 범프라고 불리는 접속용 납땜 전극을 갖는다. 납땜 전극은 구리 등을 포함하는 전극(12) 상에 땜납(13)을 접합한 것으로, 전극(12)의 두께와 땜납(13)의 두께를 합계한 두께를 갖는다.
땜납으로서는, Sn-37Pb 공정 땜납(융점 183℃), Sn-Bi 땜납(융점 139℃), Sn-3.5Ag(융점 221℃), Sn-3.0Ag-0.5Cu(융점 217℃), Sn-5.0Sb(융점 240℃) 등을 사용할 수 있다.
회로 기판(30)은, 예를 들어 리지드 기판, 플렉시블 기판 등의 기재(31)에 회로가 형성되어 있다. 또한, 반도체 칩(10)이 탑재되는 실장부에는 반도체 칩(10)의 납땜 전극과 대향하는 위치에 소정의 두께를 갖는 대향 전극(32)이 형성되어 있다.
언더필재(20)는 막 형성 수지, 에폭시 수지, 및 산 무수물을 함유한다. 막 형성 수지는, 중량 평균 분자량이 10×104 이상인 고분자량 수지에 상당하고, 필름 형성성의 관점에서, 10×104 내지 100×104의 중량 평균 분자량인 것이 바람직하다. 막 형성 수지로서는, 아크릴 고무 중합체, 페녹시 수지, 에폭시 수지, 변성 에폭시 수지, 우레탄 수지 등의 다양한 수지를 사용할 수 있다. 이들 막 형성 수지는 1종을 단독으로 사용해도 되고, 2종류 이상을 조합하여 사용해도 된다. 이들 중에서도, 본 실시형태에서는 막 강도 및 접착성의 관점에서, 페녹시 수지 및 글리시딜기를 갖는 아크릴 고무 중합체가 적절하게 사용된다. 또한, 아크릴 고무 중합체의 유리 전이 온도 Tg는 -30℃ 이상 20℃ 이하인 것이 바람직하다. 이에 의해, 언더필재(20)의 가요성을 향상시킬 수 있다.
에폭시 수지로서는, 예를 들어 디시클로펜타디엔형 에폭시 수지, 글리시딜에테르형 에폭시 수지, 글리시딜아민형 에폭시 수지, 비스페놀 A형 에폭시 수지, 비스페놀 F형 에폭시 수지, 비스페놀 S형 에폭시 수지, 스피로 환형 에폭시 수지, 나프탈렌형 에폭시 수지, 비페닐형 에폭시 수지, 테르펜형 에폭시 수지, 테트라브롬비스페놀 A형 에폭시 수지, 크레졸노볼락형 에폭시 수지, 페놀노볼락형 에폭시 수지, α-나프톨노볼락형 에폭시 수지, 브롬화페놀노볼락형 에폭시 수지 등을 들 수 있다. 이들 에폭시 수지는 1종을 단독으로 사용해도 되고, 2종류 이상을 조합하여 사용해도 된다. 이들 중에서도, 본 실시형태에서는 고접착성, 내열성의 점에서, 디시클로펜타디엔형 에폭시 수지를 사용하는 것이 바람직하다.
경화제로서는, 에폭시 화합물의 경화제로서 공지의 것을 사용할 수 있고, 잠재성이어도 된다. 예를 들어, 산 무수물계 경화제, 이미다졸계 경화제, 아민계 경화제 등을 사용할 수 있다.
산 무수물은 땜납 표면의 산화막을 제거하는 플럭스 기능을 가지므로, 우수한 접속 신뢰성을 얻을 수 있다. 산 무수물로서는, 예를 들어 테트라프로페닐무수숙신산, 도데세닐무수숙신산 등의 지방족 산 무수물, 헥사히드로무수프탈산, 메틸테트라히드로무수프탈산 등의 지환식 산 무수물, 무수프탈산, 무수트리멜리트산, 무수피로멜리트산 등의 방향족 산 무수물 등을 들 수 있다. 이들 에폭시 경화제는 1종을 단독으로 사용해도 되고, 2종류 이상을 조합하여 사용해도 된다. 이들 에폭시 경화제 중에서도 이들 중 땜납 접속성의 점에서, 지방족 산 무수물을 사용하는 것이 바람직하다.
또한, 경화 촉진제를 첨가하는 것이 바람직하다. 경화 촉진제의 구체예로서는, 2-메틸이미다졸, 2-에틸이미다졸, 2-에틸-4-메틸이미다졸 등의 이미다졸류, 1,8-디아자비시클로(5,4,0)운데센-7염(DBU염), 2-(디메틸아미노메틸)페놀 등의 제3급 아민류, 트리페닐포스핀 등의 포스핀류, 옥틸산주석 등의 금속 화합물 등을 들 수 있다.
또한, 언더필재(20)는 에폭시 수지 및 산 무수물을 더 함유한다. 아크릴 수지로서는, 단관능 (메트)아크릴레이트, 2관능 이상의 (메트)아크릴레이트를 사용 가능하다. 단관능 (메트)아크릴레이트로서는, 메틸(메트)아크릴레이트, 에틸(메트)아크릴레이트, n-프로필(메트)아크릴레이트, i-프로필(메트)아크릴레이트, n-부틸(메트)아크릴레이트 등을 들 수 있다. 2관능 이상의 (메트)아크릴레이트로서는, 비스페놀 F-EO 변성 디(메트)아크릴레이트, 비스페놀 A-EO 변성 디(메트)아크릴레이트, 트리메틸올프로판 PO 변성 (메트)아크릴레이트, 다관능 우레탄(메트)아크릴레이트 등을 들 수 있다. 이들 아크릴 수지는 단독으로 사용해도 되고, 2종 이상을 조합하여 사용해도 된다. 이들 중에서도, 본 실시형태에서는 2관능 (메트)아크릴레이트가 적절하게 사용된다.
유기 과산화물로서는, 예를 들어 퍼옥시에스테르, 퍼옥시케탈, 히드로퍼옥시드, 디알킬퍼옥시드, 디아실퍼옥시드, 퍼옥시디카르보네이트 등을 들 수 있다. 이들 유기 과산화물은 단독으로 사용해도 되고, 2종 이상을 조합하여 사용해도 된다. 이들 중에서도, 본 실시형태에서는 퍼옥시에스테르가 적절하게 사용된다.
또한, 그 밖의 첨가 조성물로서, 무기 필러를 함유하는 것이 바람직하다. 무기 필러를 함유함으로써, 압착 시에 있어서의 수지층의 유동성을 조정할 수 있다. 무기 필러로서는, 실리카, 탈크, 산화티타늄, 탄산칼슘, 산화마그네슘 등을 사용할 수 있다.
또한, 필요에 따라서 에폭시계, 아미노계, 머캅토ㆍ술피드계, 우레이드계 등의 실란 커플링제를 첨가해도 된다.
이와 같은 구성을 포함하는 언더필재(20)는 시차 주사 열량계(DSC:Differential Scanning Calorimeter)를 사용한 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 반응률의 60%에 도달하는 시간이 3.0sec 이상이다. 반응률의 20%에 도달하는 시간이 2.0sec 초과인 경우에는 보이드가 발생하고, 반응률의 60%에 도달하는 시간이 3.0sec 미만인 경우에는 양호한 땜납 접합이 얻어지지 않는다.
또한, 반응률이 20%일 때의 점도는 0.2×104㎩ㆍs 이상이고, 반응률이 60%일 때의 점도는 500×104㎩ㆍs 이하인 것이 바람직하다. 반응률이 20%일 때의 점도가 0.2×104㎩ㆍs 미만인 경우에는 보일이 남게 되고, 반응률이 60%일 때의 점도가 500×104㎩ㆍs 초과인 경우에는 양호한 땜납 접합이 얻어지지 않는다.
DSC-오자와법에 의한 반응률의 산출 방법은 다음과 같다. 우선, 샘플에 대한 등속 승온 데이터로부터 피크 전체의 열량, 피크 온도 및 피크 톱까지의 변화율을 산출한다. 다음에, 승온 속도의 상용 대수값을 종축에 취하고, 피크 온도의 역수값을 횡축에 취함으로써 오자와 플롯을 작성하고, 샘플에 대한 활성화 에너지, 빈도 인자 및 반응차수를 구한다. 그리고, 활성 에너지, 빈도 인자 및 반응차수로부터 반응 예측도를 작성함으로써, 소정 온도에서의 소정 반응률에 도달하는 시간을 산출할 수 있다.
다음에, 전술한 언더필재가 막 형상으로 형성된 선공급형 언더필 필름의 제조 방법에 대해 설명한다. 우선, 막 형성 수지, 에폭시 수지, 산 무수물, 아크릴 수지, 및 유기 과산화물을 함유하는 접착제 조성물을 용제에 용해시킨다. 용제로서는, 톨루엔, 아세트산에틸 등, 또는 이들의 혼합 용제를 사용할 수 있다. 수지 조성물을 조정 후, 바 코터, 도포 장치 등을 사용하여 박리 기재 상에 도포한다.
박리 기재는, 예를 들어 실리콘 등의 박리제를 PET(Poly Ethylene Terephthalate), OPP(Oriented Polypropylene), PMP(Poly-4-methylpentene-1), PTFE(Polytetrafluoroethylene) 등에 도포한 적층 구조를 포함하고, 조성물의 건조를 방지하면서 조성물의 형상을 유지하는 것이다.
다음에, 박리 기재 상에 도포된 수지 조성물을 열 오븐, 가열 건조 장치 등에 의해 건조시킨다. 이에 의해, 소정의 두께의 선공급형 언더필 필름을 얻을 수 있다.
<2. 반도체 장치의 제조 방법>
다음에, 전술한 선공급형 언더필 필름을 사용한 반도체 장치의 제조 방법에 대해 설명한다.
도 4는 본 실시형태에 있어서의 반도체 장치의 제조 방법을 도시하는 흐름도이다. 도 4에 도시한 바와 같이, 본 실시형태에 있어서의 반도체 장치의 제조 방법은 언더필 필름 부착 공정 S1과 다이싱 공정 S2와 반도체 칩 탑재 공정 S3과 열 압착 공정 S4를 갖는다.
도 5는 웨이퍼 상에 언더필 필름을 부착하는 공정을 모식적으로 도시하는 사시도이다. 도 6에 도시한 바와 같이, 언더필 필름 부착 공정 S1에서는, 웨이퍼(1)의 직경보다도 큰 직경을 갖는 링 형상 또는 테두리 형상의 프레임을 갖는 지그(3)에 의해 웨이퍼(1)를 고정하고, 웨이퍼(1) 상에 언더필 필름(2)을 부착한다. 언더필 필름(2)은 웨이퍼(1)의 다이싱 시에 웨이퍼(1)를 보호ㆍ고정하고, 픽업 시에 보유 지지하는 다이싱 테이프로서 기능한다. 또한, 웨이퍼(1)에는 다수의 IC(Integrated Circuit)가 조립되고, 웨이퍼(1)의 접착면에는, 도 1에 도시한 바와 같이 스크라이브 라인에 의해 구분되는 반도체 칩(10)마다 납땜 전극이 설치되어 있다.
도 6은 웨이퍼를 다이싱하는 공정을 모식적으로 도시하는 사시도이다. 도 6에 도시한 바와 같이, 다이싱 공정 S2에서는 블레이드(4)를 스크라이브 라인을 따라서 가압하여 웨이퍼(1)를 절삭하고, 개개의 반도체 칩으로 분할한다.
도 7은 반도체 칩을 픽업하는 공정을 모식적으로 도시하는 사시도이다. 도 7에 도시한 바와 같이, 각 언더필 필름이 부착된 반도체 칩(10)은 언더필 필름에 보유 지지되어 픽업된다.
반도체 칩 탑재 공정 S3에서는, 도 2에 도시한 바와 같이 언더필 필름이 부착된 반도체 칩(10)과 회로 기판(30)을 언더필 필름을 개재하여 배치한다. 또한, 언더필 필름이 부착된 반도체 칩(10)을 납땜 전극과 대향 전극(32)이 대향하도록 위치 정렬하여 배치한다. 그리고, 가열 본더에 의해, 언더필 필름에 유동성은 발생하지만, 본 경화는 발생하지 않을 정도의 소정의 온도, 압력, 시간의 조건으로 가열 가압하고 탑재한다.
탑재 시의 온도 조건은 30℃ 이상 155℃ 이하인 것이 바람직하다. 또한, 압력 조건은 50N 이하인 것이 바람직하고, 보다 바람직하게는 40N 이하이다. 또한, 시간 조건은 0.1초 이상 10초 이하인 것이 바람직하고, 보다 바람직하게는 0.1초 이상 1.0초 이하이다. 이에 의해, 납땜 전극이 용융되지 않고 회로 기판(30)측의 전극과 접하고 있는 상태로 할 수 있고, 언더필 필름이 완전 경화되어 있지 않은 상태로 할 수 있다. 또한, 낮은 온도에서 고정하기 때문에, 보이드의 발생을 억제하여, 반도체 칩(10)으로의 손상을 저감할 수 있다.
다음의 열 압착 공정 S4에서는, 예를 들어 제1 온도로부터 제2 온도까지 소정의 승온 속도로 승온시키는 본딩 조건으로, 납땜 전극의 땜납을 용융시켜 금속 결합을 형성시키면서 언더필 필름을 완전 경화시킨다.
제1 온도는 언더필재의 최저 용융 점도 도달 온도와 대략 동일한 것이 바람직하고, 50℃ 이상 150℃ 이하인 것이 바람직하다. 이에 의해 언더필재의 경화 거동을 본딩 조건에 합치시킬 수 있어, 보이드의 발생을 억제할 수 있다.
또한, 승온 속도는 50℃/sec 이상 150℃/sec 이하인 것이 바람직하다. 또한, 제2 온도는 땜납의 종류에 따라서 다르지만, 200℃ 이상 280℃ 이하인 것이 바람직하고, 보다 바람직하게는 220℃ 이상 260℃ 이하이다. 이에 의해, 납땜 전극과 기판 전극을 금속 결합시키면서 언더필 필름을 완전 경화시켜, 반도체 칩(10)의 전극과 회로 기판(30)의 전극을 전기적, 기계적으로 접속시킬 수 있다.
또한, 열 압착 공정 S4에 있어서, 본더 헤드는 탑재 후의 언더필 필름의 용융 개시 온도까지 수지의 탄성률에 의해 일정한 높이로 유지된 후, 승온에 수반하는 수지 용융에 의해 한 번에 하강하여, 헤드의 최하점에 도달한다. 이 최하점은 헤드의 하강 속도와 수지의 경화 속도의 관계에 의해 결정된다. 수지 경화가 더욱 진행된 후, 헤드의 높이는 수지와 헤드의 열팽창에 의해 서서히 상승한다. 이와 같이, 제1 온도로부터 제2 온도로 승온하는 시간 내에 본더 헤드를 최하점까지 하강시킴으로써, 수지 용융에 수반하는 보이드의 발생을 억제할 수 있다.
이와 같이 본 실시형태에 있어서의 반도체 장치의 제조 방법은 에폭시 수지 및 경화제를 함유하고, 시차 주사 열량계를 사용한 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 반응률의 60%에 도달하는 시간이 3.0sec 이상인 언더필재를, 납땜 전극이 형성된 반도체 칩에 미리 접합함으로써, 보이드리스 실장 및 양호한 땜납 접합성을 실현할 수 있다.
또한, 전술한 실시형태에서는 언더필 필름을 다이싱 테이프로서 기능시키는 것으로 하였지만, 이에 한정되는 것은 아니고, 다이싱 테이프를 별도로 사용하고, 다이싱 후에 언더필 필름을 사용하여 플립 칩 실장을 행해도 된다.
[다른 실시형태]
또한, 본 기술은 반도체 칩에 형성한 작은 구멍에 금속을 충전함으로써, 샌드위치 형상으로 적층한 복수의 칩 기판을 전기적으로 접속하는 TSV(Through Silicon Via) 기술에도 적용 가능하다.
즉, 납땜 전극이 형성된 제1 면과, 제1 면의 반대측에 납땜 전극과 대향하는 대향 전극이 형성된 제2 면을 갖는 복수의 칩 기판을 적층하는 반도체 장치의 제조 방법에도 적용 가능하다.
이 경우, 제1 칩 기판의 제1 면측에 언더필 필름을 부착한 상태에서, 제2 칩 기판의 제2 면에 탑재한다. 그 후, 제1 칩 기판의 제1 면과 제2 칩 기판의 제2 면을 납땜 전극의 땜납 융점 이상의 온도에서 열 압착함으로써, 복수의 칩 기판을 적층한 반도체 장치를 얻을 수 있다.
[실시예]
<3. 실시예>
이하, 본 발명의 실시예에 대해 설명한다. 본 실시예에서는 선공급형의 언더필 필름을 제작하여, DSC-오자와법에 의해 소정 반응률에 도달하는 시간을 산출하고, 소정 반응률의 점도를 산출하였다. 그리고, 언더필 필름을 사용하여 납땜 전극을 갖는 제1 IC 칩과, 이것에 대향하는 전극을 갖는 제2 IC 칩을 접속시켜 실장체를 제작하여, 보이드 및 땜납 접합성에 대해 평가하였다. 또한, 본 발명은 이들 실시예로 한정되는 것은 아니다.
실장체의 제작, 소정 반응률에 도달하는 시간의 산출, 소정 반응률의 점도 산출, 보이드의 평가 및 땜납 접합성의 평가는 다음과 같이 행하였다.
[실장체의 제작]
언더필 필름을 웨이퍼 상에 프레스기에 의해 50℃-0.5㎫의 조건으로 접합하고 다이싱하여 납땜 전극을 갖는 제1 IC 칩을 얻었다.
제1 IC 칩은 그 크기가 7㎜□, 두께 200㎛이고, 두께 10㎛의 Cu를 포함하는 전극의 선단에 두께 10㎛의 땜납(Sn-3.5Ag, 융점 221℃)이 형성된 주변 장치 배치의 범프(φ30㎛, 85㎛ 피치, 280 핀)를 갖는 것이었다.
또한, 이것에 대향하는 제2 IC 칩은 마찬가지로, 그 크기는 8㎜□, 두께 100㎛이고, 두께 10㎛의 Cu를 포함하는 전극의 선단에 두께 10㎛의 땜납(Sn-3.5Ag, 융점 221℃)이 형성된 주변 장치 배치의 범프(φ30㎛, 85㎛ 피치, 280 핀)를 갖는 것이었다.
다음에, 플립 칩 본더를 사용하여, 60℃-0.5초-30N의 조건으로 제2 IC 칩 상에 제1 IC 칩을 탑재하였다.
그 후, 플립 칩 본더를 사용하여, 10초 동안에 60℃로부터 250℃까지 온도를 올려 열 압착하였다(30N). 또한, 150℃-2시간의 조건으로 경화시켜 실장체를 얻었다. 또한, 플립 칩 본더 사용 시에 있어서의 온도는 열전대에 의해 샘플의 실온을 측정한 것이다.
[소정 반응률에 도달하는 시간의 산출]
소정 반응률에 도달하는 시간의 산출은 이하의 수순에 의해 산출하였다.
(1) 시차 주사 열량계(DSC)를 사용하여, 상기 장치에 첨부되어 있는 DSC 오자와법 소프트웨어의 매뉴얼 기술에 따라서, 각 시료에 대한 등속 승온 데이터(승온 속도 5℃/min, 10℃/min, 20℃/min)로부터 피크 전체의 열량, 피크 온도 및 피크 톱까지의 변화율을 구하였다. 변화율은 피크 온도까지의 열량을 피크 전체의 열량으로 나눈 값이다.
(2) 승온 속도의 상용 대수값을 종축에 취하고, 피크 온도의 역수값을 횡축에 취함으로써 오자와 플롯을 작성한 후, 각 시료에 대한 활성화 에너지, 빈도 인자, 반응차수를 구하였다.
(3) (2)에서 구한 활성 에너지, 빈도 인자 및 반응차수로부터 반응 예측도를 작성하여, 이 도면으로부터 240℃에서의 20%의 반응률 및 60%의 반응률에 도달하는 시간을 산출하였다.
[소정 반응률의 점도 산출]
각 언더필 필름에 대해, 레오미터(TA사제 ARES)를 사용하여, 5℃/min, 1㎐의 조건으로 용융 점도를 측정하였다. 또한, 시차 주사 열량계(DSC)를 사용하여, 5℃/min의 조건으로 피크 전체의 열량, 피크 온도 및 피크 톱까지의 변화율을 구하였다. 변화율은 피크 온도까지의 열량을 피크 전체의 열량으로 나눈 값이다. DSC 데이터로부터 20% 반응률에 대응하는 온도 및 60% 반응률에 대응하는 온도를 구하고, 그 온도에 대응하는 용융 점도를 레오미터 데이터로부터 구하고, 반응률 20%, 60%에 대응하는 용융 점도를 구하였다.
[보이드의 평가]
각 실장체에 대해, SAT(Scanning Acoustic Tomograph, 초음파 영상 장치)를 사용하여 관찰하고, 보이드가 IC 칩 면적의 5% 이하인 것을 ○, 보이드가 IC 칩 면적의 5% 초과인 것을 ×로 하였다.
[땜납 접합성의 평가]
각 실장체를 절단하여 단면 연마를 행하고, 전극간의 땜납의 접합 계면을 SEM(Scanning Electron Microscope) 관찰하였다. 땜납의 접합 계면이 없는 경우를 ○, 수지를 끼워 넣어 버려 땜납의 접합 계면이 있는 경우를 ×로 평가하였다.
<실시예 1>
표 1에 나타낸 바와 같이, 아크릴 고무 중합체(품명: 테이산 레진 SG-P3, 나가세 켐텍스사제)를 5.0질량부, 페녹시 수지(품명: PKHH, 유니언 카바이드사제)를 10.0질량부, 에폭시 수지(품명: HP7200H, 다이닛폰 잉크 카가쿠사제)를 15.0질량부, 산 무수물(품명: MH-700, 신닛폰 리카사제)을 9.0질량부, 이미다졸(품명: 2MZ-A, 시코쿠 카세이 고교사제)을 0.3질량부, 아크릴 수지(품명: DCP, 신나카무라 카가쿠사제)를 24.0질량부, 개시제(품명: 퍼부틸 Z, 닛폰 유시사제)를 0.3질량부, 필러 A(품명: SO-E5, 애드마텍스사제)를 31.5질량부 및 필러 B(품명: 에어로실 RY200, 닛폰 에어로실사제)를 5.0질량부 배합하여, 언더필 필름의 수지 조성물을 제조하였다. 이것을, 박리 처리된 PET(Polyethylene terephthalate)에 바 코터를 사용하여 도포하고 80℃의 오븐으로 3분간 건조시켜 두께 40㎛의 언더필 필름을 제작하였다[커버 박리 PET(25㎛)/언더필 필름(40㎛)/베이스 박리 PET(50㎛)].
도 8에 도시한 바와 같이, 실시예 1의 언더필 필름의 20%의 반응률에 도달하는 시간은 0.04sec이고, 60%의 반응률에 도달하는 시간은 4.83sec였다. 또한, 20%의 반응률의 용융 점도는 5.5E+04㎩ㆍs이고, 60%의 반응률의 용융 점도는 1.8E+06㎩ㆍs였다. 또한, 보이드의 평가는 ○이고, 땜납 접합성의 평가는 ○였다.
<실시예 2>
표 1에 나타낸 바와 같이, 아크릴 고무 중합체(품명: 테이산 레진 SG-P3, 나가세 켐텍스사제)를 5.0질량부, 페녹시 수지(품명: PKHH, 유니언 카바이드사제)를 10.0질량부, 에폭시 수지(품명: HP7200H, 다이닛폰 잉크 카가쿠사제)를 47.5질량부, 이미다졸(품명: 2MZ-A, 시코쿠 카세이 고교사제)을 1.0질량부, 필러 A(품명: SO-E5, 애드마텍스사제)를 31.5질량부 및 필러 B(품명: 에어로실 RY200, 닛폰 에어로실사제)를 5.0질량부 배합하여, 언더필 필름의 수지 조성물을 제조하였다. 이것을, 박리 처리된 PET(Polyethylene terephthalate)에 바 코터를 사용하여 도포하고 80℃의 오븐으로 3분간 건조시켜 두께 40㎛의 언더필 필름을 제작하였다[커버 박리 PET(25㎛)/언더필 필름(40㎛)/베이스 박리 PET(50㎛)].
도 8에 도시한 바와 같이, 실시예 2의 언더필 필름의 20%의 반응률에 도달하는 시간은 0.58sec이고, 60%의 반응률에 도달하는 시간은 4.80sec였다. 또한, 20%의 반응률의 용융 점도는 5.6E+04㎩ㆍs이고, 60%의 반응률의 용융 점도는 1.4E+06㎩ㆍs였다. 또한, 보이드의 평가는 ○이고, 땜납 접합성의 평가는 ○였다.
<실시예 3>
표 1에 나타낸 바와 같이, 아크릴 고무 중합체(품명: 테이산 레진 SG-P3, 나가세 켐텍스사제)를 5.0질량부, 페녹시 수지(품명: PKHH, 유니언 카바이드사제)를 10.0질량부, 에폭시 수지(품명: HP7200H, 다이닛폰 잉크 카가쿠사제)를 27.0질량부, 산 무수물(품명: MH-700, 신닛폰 리카사제)을 16.2질량부, 이미다졸(품명: 2MZ-A, 시코쿠 카세이 고교사제)을 0.5질량부, 아크릴 수지(품명: DCP, 신나카무라 카가쿠사제)를 4.8질량부, 개시제(품명: 퍼부틸 Z, 닛폰 유시사제)를 0.1질량부, 필러 A(품명: SO-E5, 애드마텍스사제)를 31.5질량부 및 필러 B(품명: 에어로실 RY200, 닛폰 에어로실사제)를 5.0질량부 배합하여, 언더필 필름의 수지 조성물을 제조하였다. 이것을, 박리 처리된 PET(Polyethylene terephthalate)에 바 코터를 사용하여 도포하고 80℃의 오븐으로 3분간 건조시켜 두께 40㎛의 언더필 필름을 제작하였다[커버 박리 PET(25㎛)/언더필 필름(40㎛)/베이스 박리 PET(50㎛)].
도 8에 도시한 바와 같이, 실시예 3의 언더필 필름의 20%의 반응률에 도달하는 시간은 1.71sec이고, 60%의 반응률에 도달하는 시간은 8.18sec였다. 또한, 20%의 반응률의 용융 점도는 6.3E+04㎩ㆍs이고, 60%의 반응률의 용융 점도는 1.6E+06㎩ㆍs였다. 또한, 보이드의 평가는 ○이고, 땜납 접합성의 평가는 ○였다.
<비교예 1>
표 1에 나타낸 바와 같이, 아크릴 고무 중합체(품명: 테이산 레진 SG-P3, 나가세 켐텍스사제)를 5.0질량부, 페녹시 수지(품명: PKHH, 유니언 카바이드사제)를 10.0질량부, 에폭시 수지(품명: HP7200H, 다이닛폰 잉크 카가쿠사제)를 30.0질량부, 산 무수물(품명: MH-700, 신닛폰 리카사제)을 18.0질량부, 이미다졸(품명: 2MZ-A, 시코쿠 카세이 고교사제)을 0.5질량부, 필러 A(품명: SO-E5, 애드마텍스사제)를 31.5질량부 및 필러 B(품명: 에어로실 RY200, 닛폰 에어로실사제)를 5.0질량부 배합하여, 언더필 필름의 수지 조성물을 제조하였다. 이것을, 박리 처리된 PET(Polyethylene terephthalate)에 바 코터를 사용하여 도포하고 80℃의 오븐으로 3분간 건조시켜 두께 40㎛의 언더필 필름을 제작하였다[커버 박리 PET(25㎛)/언더필 필름(40㎛)/베이스 박리 PET(50㎛)].
도 8에 도시한 바와 같이, 비교예 1의 언더필 필름의 20%의 반응률에 도달하는 시간은 2.45sec이고, 60%의 반응률에 도달하는 시간은 6.48sec였다. 또한, 20%의 반응률의 용융 점도는 1.0E+03㎩ㆍs이고, 60%의 반응률의 용융 점도는 2.3E+05㎩ㆍs였다. 또한, 보이드의 평가는 ×이고, 땜납 접합성의 평가는 ○였다.
<비교예 2>
표 1에 나타낸 바와 같이, 아크릴 고무 중합체(품명: 테이산 레진 SG-P3, 나가세 켐텍스사제)를 5.0질량부, 페녹시 수지(품명: PKHH, 유니언 카바이드사제)를 10.0질량부, 아크릴 수지(품명: DCP, 신나카무라 카가쿠사제)를 48.0질량부, 개시제(품명: 퍼부틸 Z, 닛폰 유시사제)를 0.5질량부, 필러 A(품명: SO-E5, 애드마텍스사제)를 31.5질량부 및 필러 B(품명: 에어로실 RY200, 닛폰 에어로실사제)를 5.0질량부 배합하여, 언더필 필름의 수지 조성물을 제조하였다. 이것을, 박리 처리된 PET(Polyethylene terephthalate)에 바 코터를 사용하여 도포하고 80℃의 오븐으로 3분간 건조시켜 두께 40㎛의 언더필 필름을 제작하였다[커버 박리 PET(25㎛)/언더필 필름(40㎛)/베이스 박리 PET(50㎛)].
도 8에 도시한 바와 같이, 비교예 2의 언더필 필름의 20%의 반응률에 도달하는 시간은 0.02sec이고, 60%의 반응률에 도달하는 시간은 0.07sec였다. 또한, 20%의 반응률의 용융 점도는 1.1E+06㎩ㆍs이고, 60%의 반응률의 용융 점도는 1.0E+07㎩ㆍs 이상이었다. 또한, 보이드의 평가는 ○이고, 땜납 접합성의 평가는 ×였다.
비교예 1은 반응률의 20%에 도달하는 시간이 2.0sec 초과이므로 보이드가 발생했다. 또한, 비교예 1은 반응률이 20%일 때의 점도가 0.2×104㎩ㆍs 미만이므로 보일이 남아 있었다.
또한, 비교예 2는 반응률의 60%에 도달하는 시간이 3.0sec 미만이므로 양호한 땜납 접합이 얻어지지 않았다. 또한, 비교예 2는 반응률이 60%일 때의 점도가 500×104㎩ㆍs 초과이므로 양호한 땜납 접합이 얻어지지 않았다.
한편, 실시예 1 내지 3은 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고 반응률의 60%에 도달하는 시간이 3.0sec 이상이므로, 보이드리스 실장 및 양호한 땜납 접합성을 실현할 수 있었다.
1 : 웨이퍼
2 : 언더필 필름
3 : 지그
4 : 블레이드
10 : 반도체 칩
11 : 반도체
12 : 전극
13 : 땜납
20 : 언더필재
21 : 제1 접착제층
22 : 제2 접착제층
30 : 회로 기판
31 : 기재
32 : 대향 전극
2 : 언더필 필름
3 : 지그
4 : 블레이드
10 : 반도체 칩
11 : 반도체
12 : 전극
13 : 땜납
20 : 언더필재
21 : 제1 접착제층
22 : 제2 접착제층
30 : 회로 기판
31 : 기재
32 : 대향 전극
Claims (8)
- 납땜 전극이 형성된 반도체 칩을, 납땜 전극과 대향하는 대향 전극이 형성된 전자 부품에 탑재하기 전에, 반도체 칩에 미리 접합되는 언더필재이며,
에폭시 수지 및 경화제를 함유하고,
시차 주사 열량계를 사용하여 얻어진 승온 속도 5℃/min, 10℃/min, 20℃/min에서의 등속 승온 데이터를 사용하여 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 상기 반응률의 60%에 도달하는 시간이 3.0sec 이상인 언더필재. - 제1항에 있어서, 상기 반응률이 20%일 때의 점도가 0.2×104㎩ㆍs 이상이고, 상기 반응률이 60%일 때의 점도가 500×104㎩ㆍs 이하인 언더필재.
- 제1항 또는 제2항에 있어서, 상기 에폭시 수지가 디시클로펜타디엔형 에폭시 수지이고, 상기 경화제가 지방족 산 무수물 또는 이미다졸계 경화제인 언더필재.
- 제1항 또는 제2항에 있어서, 아크릴 수지 및 유기 과산화물을 더 함유하는 언더필재.
- 제3항에 있어서, 아크릴 수지 및 유기 과산화물을 더 함유하는 언더필재.
- 제4항에 있어서, 상기 아크릴 수지가 2관능 (메트)아크릴레이트이고, 상기 유기 과산화물이 퍼옥시에스테르인 언더필재.
- 제5항에 있어서, 상기 아크릴 수지가 2관능 (메트)아크릴레이트이고, 상기 유기 과산화물이 퍼옥시에스테르인 언더필재.
- 납땜 전극이 형성되고, 상기 전극면에 언더필재가 접합된 반도체 칩을, 상기 납땜 전극과 대향하는 대향 전극이 형성된 전자 부품에 탑재하는 탑재 공정, 및
상기 반도체 칩과 상기 전자 부품을 열 압착하는 열 압착 공정
을 갖고, 상기 언더필재는 에폭시 수지 및 산 무수물을 함유하고, 시차 주사 열량계를 사용하여 얻어진 승온 속도 5℃/min, 10℃/min, 20℃/min에서의 등속 승온 데이터를 사용하여 오자와법에 의해 산출된 240℃에서의 반응률의 20%에 도달하는 시간이 2.0sec 이하이고, 상기 반응률의 60%에 도달하는 시간이 3.0sec 이상인 반도체 장치의 제조 방법.
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