KR102295212B1 - Display device and power supply - Google Patents

Abstract

In the present exemplary embodiments, a scan signal is generated based on high-level and low-level gate voltages supplied through a display panel in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of sub-pixels are disposed, and a gate voltage line. The present invention relates to a display device and a power supply unit including a gate driver supplied to the gate line and a power supply unit for supplying a high-level gate voltage including a rising voltage higher than the high-level voltage for a first period to the gate driver.

Description

Display device and its power supply

The present embodiments relate to a display device for displaying an image.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device, a plasma display device, and an organic light emitting display device ( Various display devices such as Organic Light Emitting Display Device) are being used.

Such a display device controls a display panel in which data lines and gate lines are disposed and subpixels are disposed, a data driver driving the data lines, a gate driver sequentially driving the gate lines, and a data driver and a gate driver timing controller, etc.

Meanwhile, the gate driver receives the high-level gate voltage VGH and the low-level gate voltage VGL as input, generates a scan signal using the input, and sequentially drives the gate lines using the generated scan signal.

At this time, for some reason, a gate current may be generated through the gate voltage line or the gate line.

The gate current generated in the gate voltage wiring or the gate line may cause a drop in the gate voltage.

SUMMARY OF THE INVENTION An object of the present embodiments is to provide a power supply and a display device having improved lowering of a high-level gate voltage.

Another object of the present exemplary embodiments is to provide a power supply and a display device having improved waveform distortion of the scan signal at the rising timing of the scan signal SCAN.

It is an object of the present embodiments to provide a display device in which a scan signal is sufficiently secured by improving waveform distortion of a scan signal, and a display device thereof.

It is an object of the present embodiments to provide a power supply that accurately transmits data to pixels of a high-resolution large-area display device and a display device thereof.

SUMMARY OF THE INVENTION An object of the present embodiments is to provide a power supply and a display device having improved image quality uniformity of a high-resolution, large-area display device.

In an exemplary embodiment, based on high-level and low-level gate voltages supplied through a display panel in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of sub-pixels are disposed, and a gate voltage line A display device comprising: a gate driver that generates a scan signal and supplies it to the gate line; and a power supply unit that supplies the gate driver with a high-level gate voltage including a rising voltage higher than the high-level voltage for a first period. have.

In another aspect, another embodiment provides a high-level high-level signal for a first period to a gate driver that generates a scan signal based on high-level and low-level gate voltages supplied through the gate voltage line and supplies it to the gate line of the display panel. It is possible to provide a power supply for supplying a high-level gate voltage including a rising voltage higher than the voltage of .

According to the present embodiments as described above, it is possible to improve the drop of the high-level gate voltage.

Also, according to the present exemplary embodiments, it is possible to improve the waveform distortion of the scan signal at the rising timing of the scan signal SCAN.

In addition, according to the present embodiments, since the waveform distortion of the scan signal is improved, the scan signal can be sufficiently secured.

Also, according to the present exemplary embodiments, data can be accurately transmitted to pixels of a display device having a high resolution and a large area.

Also, according to the present embodiments, it is possible to improve the uniformity of the image quality of the high-resolution, large-area display device.

1 is a schematic system configuration diagram of a display device according to the present exemplary embodiment.
2 is a structural diagram of the display device 100 according to the present exemplary embodiment.
3 is a diagram illustrating voltage/current states of a power supply unit and a gate driver of FIG. 2 .
4 shows that the gate driver generates and outputs two scan signals at the same time.
5 shows the output voltage and current when the gate driver generates and outputs two scan signals at the same time.
6 illustrates that the gate driver generates and simultaneously outputs four scan signals.
7 shows the output voltage and current when the gate driver generates and outputs four scan signals at the same time.
8 illustrates that distortion of the scan signal of the display device occurs.
9 is a block diagram of a display device according to an exemplary embodiment.
FIG. 10 is a circuit diagram of the power supply unit of FIG. 9 .
11 is a timing diagram of a display device according to an exemplary embodiment when four scan signals are simultaneously applied.
12 is a timing diagram of a display device according to an exemplary embodiment when two scan signals are simultaneously applied.
13 is a simulation result of an operation of a display device according to an exemplary embodiment. 14 illustrates that distortion of a scan signal of a display device according to an exemplary embodiment is improved.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 according to the present exemplary embodiment.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiments, a display panel in which a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of subpixels are disposed in a matrix type. 110 , a data driver 120 driving a plurality of data lines DL, a gate driver 130 driving a plurality of gate lines, and controlling the data driver 120 and the gate driver 130 . and a timing controller 140 and the like.

The data driver 120 drives the plurality of data lines by supplying data voltages to the plurality of data lines. Here, the data driver 120 is also referred to as a source driver.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying scan signals to the plurality of gate lines. Here, the gate driver 130 is also referred to as a scan driver.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

The timing controller 140 starts scanning according to the timing implemented in each frame, converts externally input image data to match the data signal format used by the data driver 120 , and outputs the converted image data. and control the data operation at an appropriate time according to the scan.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying a scan signal of an on voltage or an off voltage to the plurality of gate lines under the control of the timing controller 140 . .

The gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1 or, in some cases, on both sides, according to a driving method.

Also, the gate driver 130 may include one or more gate driver integrated circuits (GDICs).

In addition, the one or more gate driver integrated circuits included in the gate driver 130 may include bonding pads of the display panel 110 using a tape automated bonding (TAB) method or a chip-on-glass (COG) method. .

Each of the one or more gate driver integrated circuits GDIC included in the gate driver 130 may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies it to the data lines, thereby driving a plurality of data lines.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

At least one source driver integrated circuit (SDIC) included in the data driver 120 may be configured as a bonding pad ( It may be connected to the bonding pad) or directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each source driver integrated circuit (SDIC) included in the data driver 120 may include a logic unit including a shift register, a latch circuit, and the like, a digital analog converter (DAC), an output butter, and the like. In some cases, a sensing unit for sensing the characteristics of the sub-pixel (e.g., the threshold voltage and mobility of the driving transistor, the threshold voltage of the organic light emitting diode, the luminance of the sub-pixel, etc.) For example, an analog-to-digital converter (ADC) may be further included.

In addition, each source driver integrated circuit SDIC included in the data driver 120 may be implemented in a Chip On Film (COF) method.

In this case, one end of each source driver integrated circuit SDIC is bonded to at least one source printed circuit board (S-PCB) 150 , and the other end is bonded to the display panel 110 .

Meanwhile, the timing controller 140 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), etc. together with the input image data. Receives various timing signals from an external (eg, host system).

The timing controller 140 converts the input image data input from the outside to match the data signal format used by the data driver 120 and outputs the converted image data, as well as the data driver 120 and the gate driver 130 . ), the data driver 120 and the gate driver 130 receive timing signals such as a vertical sync signal (Vsync), a horizontal sync signal (Hsync), an input DE signal, and a clock signal to generate various control signals. ) is output.

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable).

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Various data control signals (DCS: Data Control Signal) including output enable) are output.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120 .

Referring to FIG. 1 , the timing controller 140 includes a source printed circuit board 150 to which a source driver integrated circuit (SDIC) is bonded and a flexible flat cable (FFC) or flexible printed circuit (FPC). Circuit) may be disposed on a control printed circuit board (C-PCB: Control Printed Circuit Board, 160) connected through a connection medium 170 such as.

In the control printed circuit board 160 , a power supply unit (see FIG. 2 ) for supplying various voltages or currents to the display panel 110 , the data driver 120 , and the gate driver 130 , or controlling various voltages or currents to be supplied. 200 (300 in FIG. 9) may be further disposed. Such a power supply is also referred to as a power management integrated circuit (PMIC).

The above-mentioned source printed circuit board 150 and control printed circuit board 170 may be a single printed circuit board.

The display device 100 according to the present embodiments may be, for example, one of a liquid crystal display device, a plasma display device, an organic light emitting display device, and the like. can

In the display device 100 , circuit elements such as a transistor and a capacitor may be disposed in each of the plurality of sub-pixels (SP) disposed on the display panel 110 .

For example, when the display panel 110 is an organic light emitting display panel, each sub-pixel SP is a circuit element such as an organic light emitting diode (OLED), two or more transistors, and at least one capacitor. can be configured.

The type and number of circuit elements constituting each sub-pixel may be variously determined according to a provided function and a design method.

2 is a structural diagram of the display device 100 according to the present exemplary embodiment. 3 is a diagram illustrating voltage/current states of a power supply unit and a gate driver of FIG. 2 .

Referring to FIG. 2 , in the display device 100 according to the present exemplary embodiments, each gate driver integrated circuit GDIC includes a gate voltage VGH supplied from the power supply 200 through a gate voltage line 201 , VGL), a scan signal SCAN having a high level voltage VGH or a low level voltage VGL may be generated and sequentially supplied to the plurality of gate lines GL.

When the display device 100 according to the present exemplary embodiment is an organic light emitting display device, each subpixel SP includes an organic light emitting diode OLED, two or more transistors T1 and T2 , one or more capacitors Cst, etc. This can be placed T1 is a driving transistor for driving an organic light emitting diode (OLED). T2 is electrically connected between the gate node of T1 and the data line DL, and may be controlled by a scan signal SCAN output from each gate driver integrated circuit GDIC. The T2 is a switching transistor that is controlled by the scan signal SCAN and transfers the data voltage Vdata supplied from the data line DL to the gate node of T1. Cst is electrically connected between the gate node and the source node (or drain node) of T1, and serves to maintain a constant voltage for one frame.

Referring to FIG. 2 , currents IVGH and IVGL flowing through the gate voltage line 201 or the gate line GL may be generated. Here, IVGH means a current flowing through the gate voltage line 201 or the gate line GL in relation to the high-level gate voltage VGH supplied to the gate driving integrated circuit GDIC or in the scan signal SCAN. do. IVGL refers to a current supplied to the gate driving integrated circuit GDIC or flowing through the gate voltage line 201 or the gate line GL in relation to the low-level gate voltage VGL in the scan signal SCAN.

Meanwhile, the voltage output from the power supply unit 200 may include a high level voltage (gate voltage) and a low level voltage (gate voltage).

In order to generate the scan signal SCAN, the gate voltage transmitted to each gate driver integrated circuit GDIC may be a voltage in which the voltage output from the power supply 200 is a voltage drop or a voltage rise, and a high level It may include a gate voltage and a low-level gate voltage.

Below, the high-level voltage (gate voltage) and the low-level voltage (gate voltage) output from the power supply unit 200 and the high-level gate voltage and low-level voltage transmitted to each gate driver integrated circuit GDIC are shown below. In order to distinguish the gate voltages, the high-level voltage (gate voltage) and the low-level voltage (gate voltage) output from the power supply unit 200 are denoted by “VGH_IN” and “VGL_IN”. In addition, the high-level gate voltage and the low-level gate voltage transmitted to each gate driver integrated circuit GDIC are denoted by “VGH_OUT” and “VGL_OUT”.

The high-level voltage VGH_IN and the low-level voltage VGL_IN output from the power supply 200 are fixed voltages.

The high-level gate voltage VGH_OUT and the low-level gate voltage VGL_OUT transmitted to each gate driver integrated circuit GDIC are voltages that change when a current is generated.

Referring to FIG. 3 , the wiring resistance R such as the log resistance of the display panel 110 on the path of the high level gate voltage VGH between the power supply 200 and the gate driver integrated circuit GDIC is exist. In other words, the wiring resistor R has one end connected to the gate voltage wiring part electrically connected to the power supply 200 and the other end connected to the gate voltage wiring part electrically connected to the gate driver integrated circuit (GDIC). do.

The gate voltage VGH_IN output from the power supply 200 is dropped to the gate voltage VGH_OUT by the wiring resistor R. In this regard, it will be exemplarily described below with reference to FIGS. 4 to 8 .

4 shows that the gate driver generates and outputs two scan signals at the same time. 5 shows the output voltage and current when the gate driver generates and outputs two scan signals at the same time. 6 illustrates that the gate driver generates and simultaneously outputs four scan signals. 7 shows the output voltage and current when the gate driver generates and outputs four scan signals at the same time.

4 to 8 , one gate driver integrated circuit GDIC receives a high-level gate voltage VGH_OUT and a low-level gate voltage VGL_OUT, and as shown in FIG. 4 , two scan signals For example, generating (SCAN 1, SCAN 2) and simultaneously outputting, or generating and simultaneously outputting four scan signals (SCAN 1, SCAN 2, SCAN 3, SCAN 4) as shown in FIG. 6 .

Referring to FIG. 5 , a temporary peak current occurs in IVGH at the rising timing of the two scan signals SCAN 1 and SCAN 2 . Accordingly, a drop of the high-level gate voltage VGH_OUT occurs. As a result, waveform distortion occurs when the scan signals SCAN 1 and SCAN 2 rise. Referring to FIG. 7 , at the rising timing of the four scan signals SCAN 1 , SCAN 2 , SCAN 3 , and SCAN 4 , a peak current is temporarily generated in the IVGH. At this time, it is IVGH than when the two scan signals SCAN 1 and SCAN 2 are simultaneously applied to the gate lines at the same time than when the four scan signals SCAN 1, SCAN 2, SCAN 3, and SCAN 4 are simultaneously applied to the gate lines. has a larger peak current. Accordingly, the drop of the high-level gate voltage VGH_OUT becomes larger.

As the display device 100 goes to a large area/high resolution, a drop of the high-level gate voltage VGH for driving the gate of the pixel occurs, which causes waveform distortion when the scan signal SCAN rises. do. Conventionally, it is not a big problem due to an adequate scan time, but when scan signals are simultaneously driven to several gate lines for compensation in the large-area high-resolution display device 100, the data of the pixel is not transmitted properly due to the lack of scan time. Otherwise, it may affect the burn.

The large-area/high-resolution display panel 110 has a large log resistance, and when several scan signals are applied at the same time, the high-level gate voltage falls and distortion occurs in the waveform when the scan signal rises when the scan signal rises, It doesn't deliver the voltage that opens the pixel's gate properly.

A high level caused by an increase in the gate current IVGH due to an increase in the load on the display panel 110 and a wiring resistance such as a log resistance of the display panel 110 that is a resistance on the path of the high level gate voltage VGH A drop in the gate voltage VGH occurs. In order to improve the drop of the high-level gate voltage VGH, it is necessary to lower the log resistance of the display panel 110 , which is difficult for a narrow bezel, and when the gate current is reduced, the display panel 110 . may affect the behavior of

Hereinafter, a configuration and operation of a display device according to an exemplary embodiment will be described with reference to FIGS. 9 to 14 .

9 is a block diagram of a display device according to an exemplary embodiment. FIG. 10 is a circuit diagram of the power supply unit of FIG. 9 .

Referring to FIG. 9 , in the display device according to an exemplary embodiment, a display panel 110 in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of sub-pixels are disposed, and a high level and a low level supplied through a gate voltage line. A rising voltage Vover higher than the high level voltage VGH during the first period T1 to the gate driver GDIC and the gate driver GDIC that generates a scan signal based on the gate voltages of the level and supplies it to the gate line ) includes a power supply unit 300 for supplying a high-level gate voltage including In addition, the display device according to an exemplary embodiment includes a timing controller 140 that controls the gate driver GDIC and the power supply 300 . The display panel 110 , the gate driver GDIC, and the timing controller 140 are the same as described with reference to FIG. 1 .

9 and 10 , in the display device according to an exemplary embodiment, the power supply unit 300 includes a boost converter or a charge pump that generates a high-level gate voltage VGH_IN from an input voltage Vin. Charge Pump) or a DC/DC converter 310 for similar feedback control. The DC/DC converter 310 divides the output voltage VGH_IN by resistors and compares it with a reference voltage V_REF for feedback control. When the feedback voltage is lowered, the output voltage VGH_OUT of the DC/DC converter 310 rises. By connecting a resistor and a switch to this feedback terminal, the timing controller 140 turns on the switch before the scan time to lower the feedback voltage V_FB, and the drop of the high-level gate voltage VGH_IN is At the end, the switch is turned off.

The power supply unit 300 includes a first resistor (R1) and a second resistor (R2) in series for dividing the output voltage at the output terminal, and the voltage is divided between the first resistor (R1) and the second term (R2). The feedback unit 320 feeds back the feedback voltage V_FB of the first node N1 and the feedback voltage to the first node N1 between the first resistor R1 and the second resistor R2 of the feedback unit 320 . A third resistor R3 for lowering (VGH_FB) and the switch SW include a rising voltage generator 330 connected in series. The switch SW may be a device that performs a similar operation, such as an FET, a BJT, or the like.

The resistance value of the third resistor R3 is set to a value for matching the corresponding feedback voltage VGH_FB to raise it to a specific voltage. The third resistor R3 is connected to the node between the first resistor R1 and the second resistor R2, and the opposite side is connected to the switch SW. The switch SW is connected to a ground voltage, for example, a ground voltage GND. The gate of the switch SW is connected to the timing controller 140 to receive the power control signal PCS.

The timing controller 140 raises the high-level gate voltage VGH_IN in advance by turning on the switch SW before the scan time opens, that is, before the gate current IVGH reaches the peak current. At a time when the gate current IVGH decreases to some extent after the scan signal is turned on, the timing controller 140 turns the switch SW into an off state to return to the original high-level gate voltage VGH_IN.

11 is a timing diagram of a display device according to an exemplary embodiment when four scan signals are simultaneously applied. 12 is a timing diagram of a display device according to an exemplary embodiment when two scan signals are simultaneously applied.

11 and 12 , the power control signal PCS is applied to the switch SW of the rising voltage generator 330 for a first period t1 to be turned on during the first period t1, and the remaining It is turned off during the period to generate an over voltage during the first period t1. The first period t1 includes a predetermined period t11 before the rising timing of the scan signal. In particular, the first period t1 may be a predetermined period t11 before the rising timing of the scan signal and a predetermined period t12 after the rising timing.

The gate driver GDIC simultaneously transmits two or more scan signals SCAN 1, .., k (k is an integer greater than or equal to 2) of the display panel 110 as shown in FIGS. 4, 6, and 9 . It can be supplied to gate lines.

In other words, in the display device according to an exemplary embodiment, a control signal, for example, a power control signal (PCS) from the timing controller 140 before the high-level gate voltage VGH_OUT input to the gate driver GDIC falls. ) is supplied and the switch (SW) is turned on.

13 is a simulation result of an operation of a display device according to an exemplary embodiment. 14 illustrates that distortion of a scan signal of a display device according to an exemplary embodiment is improved.

Parallel resistors R1 and R3 are connected to the feedback terminal of the DC/DC converter 310 to instantaneously increase the high-level gate voltage VGH_IN, and the high-level gate voltage VGH_IN becomes high in a stable period. Lower the level of the gate voltage (VGH_IN). Over driving the high-level gate voltage VGH_IN output from the power supply 300 before the scan time starts, that is, before the gate current IVGH reaches the peak current as shown in FIG. 13 . Accordingly, as shown in FIG. 14 , the drop of the high-level gate voltage VGH_OUT input to the gate driver GDIC is improved. Accordingly, according to embodiments, even when a temporary peak current occurs in IVGH at the rising timing of the scan signal SCAN, it is possible to improve the waveform distortion of the scan signal.

As shown in FIGS. 4 and 6 for compensation in a large-area high-resolution display device, even when scan signals are simultaneously driven to two or more gate lines, as shown in FIG. 13, the gate current IVGH does not reach the peak current. By over-driving the high-level gate voltage VGH_IN output from the power supply unit 300 before, the waveform distortion of the scan signal is improved to secure a scan time sufficiently, and the pixel data is accurately transferred to improve the image. can do.

According to embodiments, uniformity of image quality of a high-resolution large-area display device may be improved.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driver
130: gate driver
140: timing controller
200, 300: power supply

Claims (10)

a display panel in which a plurality of data lines and a plurality of gate lines are disposed and a plurality of sub-pixels are disposed;
a gate driver generating a scan signal based on high-level and low-level gate voltages supplied through a gate voltage line and supplying the scan signal to the gate line; and
A rising voltage higher than the high-level voltage is maintained for a first period from a point in time preceding the rising timing of the scan signal to a point in time later than the rising timing of the scan signal by a predetermined period, and in a section other than the first period A power supply unit for supplying the gate voltage of the high level maintaining the high level to the gate driver,
The power supply unit,
a feedback unit including a first resistor and a second resistor in series at an output terminal and feeding back a voltage of a first node between the first resistor and the second resistor;
a rising voltage generator connecting a third resistor and a switch in parallel with the first resistor to the first node between the first resistor and the second resistor of the feedback part;
The display device is configured to apply a power control signal to the switch of the rising voltage generator during the first period to be in an on state during the first period and be turned off during the remaining period to generate the rising voltage during the first period. delete delete delete According to claim 1,
The gate driver simultaneously supplies two or more scan signals to two or more gate lines of the display panel. The scan signal is generated based on the high-level and low-level gate voltages supplied through the gate voltage line and is supplied to the gate driver for supplying the scan signal to the gate line of the display panel from a point in time that precedes the rising timing of the scan signal by a certain period of time. Maintaining a rising voltage higher than the high-level voltage for a first period up to a time point after a certain period from the rising timing of , and supplying the high-level gate voltage maintaining the high level in a section other than the first period ,
a feedback unit including a first resistor and a second resistor in series at an output terminal and feeding back a voltage of a first node between the first resistor and the second resistor;
a rising voltage generator connecting a third resistor and a switch in parallel with the first resistor to the first node between the first resistor and the second resistor of the feedback part;
A power supply unit for applying a power control signal to the switch of the rising voltage generator during the first period to be in an on state during the first period and in an off state for the remaining period to generate the rising voltage during the first period. delete delete delete 7. The method of claim 6,
The gate driver is a power supply that simultaneously supplies two or more scan signals to two or more gate lines of the display panel.

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