KR102244545B1 - Organic light emitting display panel, organic light emitting display device, and the method for driving the organic light emitting display device - Google Patents

Abstract

The present embodiments relate to an organic light emitting display panel, an organic light emitting display device, and a driving method thereof, which can shorten a threshold voltage sensing time and increase threshold voltage sensing accuracy.

Description

Organic light emitting display panel, organic light emitting display device and its driving method {ORGANIC LIGHT EMITTING DISPLAY PANEL, ORGANIC LIGHT EMITTING DISPLAY DEVICE, AND THE METHOD FOR DRIVING THE ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present embodiments relate to an organic light emitting display panel, an organic light emitting display device, and a driving method thereof.

Recently, organic light emitting display devices that are in the spotlight as display devices use organic light emitting diodes (OLEDs) that emit light by themselves, so that the response speed is fast, and the contrast ratio, luminous efficiency, luminance, and viewing angle are large. There is an advantage.

Each sub-pixel disposed on the organic light-emitting display panel of such an organic light-emitting display device basically includes an organic light-emitting diode and a driving transistor that drives the organic light-emitting diode.

Such an organic light emitting display device displays an image by controlling the brightness of an organic light emitting diode with a driving current of a driving transistor determined based on a data voltage output from a data driver.

Meanwhile, the driving transistors in each subpixel on the organic light emitting display panel have unique characteristic values such as a threshold voltage. As the driving time increases, the driving transistor is degraded and the threshold voltage changes.

Such deterioration of the driving transistor may cause a threshold voltage deviation between the driving transistors in each subpixel, resulting in a luminance deviation between the subpixels, thereby deteriorating the image quality.

Accordingly, a technique for compensating for luminance deviation between subpixels, that is, a technique for compensating for a threshold voltage deviation between driving transistors, has been proposed.

However, in order to compensate for the threshold voltage deviation of the driving transistor, a sensing process of making the voltage of the source node or the gate node of the driving transistor into a state in which threshold voltage sensing is possible, and then sensing the voltage of the source node or drain node of the driving transistor. I need this.

Conventionally, during such a sensing process, there has been a problem in that it takes a very long sensing time to make the voltage of a source node or a gate node of a driving transistor into a state in which threshold voltage sensing is possible.

In relation to this problem, when the size of the driving transistor is reduced according to the recent trend of gradually decreasing the pixel size for high resolution implementation, when the current driving capability of the driving transistor is deteriorated, the threshold voltage sensing time may be longer.

Meanwhile, the driving transistors on the organic light-emitting display panel deteriorate as the driving time increases, so that the distribution of threshold voltages for the driving transistors changes as a whole. In this case, due to a constant limited sensing time, etc., the threshold voltage sensing accuracy is likely to be lowered.

An object of the present embodiments is to provide an organic light emitting display panel, an organic light emitting display device, and a driving method thereof capable of shortening a threshold voltage sensing time.

Another object of the present embodiments is to provide an organic light-emitting display panel, an organic light-emitting display device, and a driving method thereof capable of improving the accuracy of sensing threshold voltage.

In one embodiment, a plurality of data lines and a plurality of gate lines are disposed, a plurality of subpixels are disposed, an organic light emitting display panel, a data driver driving a plurality of data lines, and a gate driving a plurality of gate lines An organic light emitting display device including a driving unit and a timing controller that controls the data driving unit and the gate driving unit may be provided.

In such an organic light emitting display device, each of the plurality of subpixels may include an organic light emitting diode, a driving transistor that drives the organic light emitting diode, and a switching transistor that transmits a data voltage to a gate node of the driving transistor.

In addition, in such an organic light emitting display device, in the N-th sensing period, the reference voltage applied to the source node or the drain node of the driving transistor of each of the plurality of subpixels is greater than the initial reference voltage and the Vgs of the driving transistor is greater than the threshold voltage. It can be set to an optimum reference voltage that is large and Vgs is the minimum.

Another embodiment includes a plurality of data lines and a plurality of gate lines disposed in a direction crossing each other, and a plurality of subpixels disposed in a matrix type, each of the plurality of subpixels, an organic light emitting diode, and the An organic light emitting display panel including a driving transistor driving the organic light emitting diode and a switching transistor transmitting a data voltage to a gate node of the driving transistor may be provided.

In such an organic light emitting display panel, in an Nth sensing period, a reference voltage applied to a source node or a drain node of the driving transistor of each of the plurality of subpixels is greater than an initial reference voltage, and Vgs of the driving transistor is a threshold voltage. It may be set to an optimum reference voltage that is larger and the Vgs is the minimum.

In another embodiment, an organic light-emitting display comprising a plurality of subpixels each including an organic light-emitting diode, a driving transistor for driving the organic light-emitting diode, and a switching transistor for transmitting a data voltage to a gate node of the driving transistor A method of driving a device can be provided.

The driving method of the organic light emitting display device includes applying a data voltage to a gate node of a driving transistor and an initial reference voltage to a source node or a drain node of the driving transistor in an NN-th sensing period, a source node of the driving transistor, or In the step of sensing the sensing voltage of the drain node, determining whether the sensing voltage is increased, or determining whether the sensing voltage is increased, when the sensing voltages of the driving transistors of a plurality of subpixels are all increased, the source node of the driving transistor or In the step of returning to the step of sensing the sensing voltage after applying the reference voltage to the drain node by raising it by one step and determining whether the sensing voltage is increased, the sensing voltage of more than a predetermined number among the driving transistors of the subpixels does not rise. Otherwise, a step of lowering the reference voltage to the source node or the drain node of the driving transistor by one step to set the optimum reference voltage applied to the source or drain of the driving transistors of the subpixels may be provided.

According to the exemplary embodiments described above, an organic light emitting display panel, an organic light emitting display device, and a driving method thereof capable of shortening the threshold voltage sensing time can be provided.

According to the present embodiments, it is possible to provide an organic light-emitting display panel, an organic light-emitting display device, and a driving method thereof capable of improving the accuracy of sensing a threshold voltage.

1 is a schematic system configuration diagram of an organic light emitting display device according to exemplary embodiments.
2 is an exemplary diagram of a subpixel structure of an organic light emitting display device according to the present embodiments.
3 is a timing diagram for sensing a threshold voltage of a driving transistor in a subpixel of an organic light emitting display device according to the present exemplary embodiments.
4 is a diagram illustrating a distribution of threshold voltages of driving transistors and a change thereof in the organic light emitting display device according to the present exemplary embodiments.
5 is a diagram illustrating a voltage change at a sensing point according to a change in a threshold voltage distribution of driving transistors in the organic light emitting display device according to the present embodiments.
6 is a diagram illustrating a reference voltage tracking technique of an organic light emitting display device according to the present embodiments.
7A is a diagram illustrating an example of a reference voltage tracking technique for tracking a reference voltage in an N-th sensing section in the organic light emitting display device according to the present embodiments.
7B is a diagram illustrating another example of a reference voltage tracking technique for tracking a reference voltage in an N-th sensing section in the organic light emitting display device according to the present embodiments.
8 is a timing diagram illustrating a threshold voltage sensing of a driving transistor DRT in a subpixel of the organic light emitting display device 100 according to the present exemplary embodiments.
9 is a flowchart of a driving method for sensing a threshold voltage of the organic light emitting display device 100 according to another exemplary embodiment.
10 is a diagram illustrating a variable precharge voltage in a sensing line capacitor according to a reference voltage tracking technique of an organic light emitting display device according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, the detailed description may be omitted.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a) and (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but other components between each component It should be understood that "interposed" or that each component may be "connected", "coupled" or "connected" through other components.

1 is a schematic system configuration diagram of an organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 1, the organic light emitting display device 100 according to the present embodiments includes an organic light emitting display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like. .

In the organic light emitting display panel 110, a plurality of data lines (DL) are disposed in a first direction, a plurality of gate lines (GL) are disposed in a second direction crossing the first direction, and , A plurality of sub-pixels (SP: Sub Pixels) are arranged in a matrix type. The data driver 120 drives data lines by supplying data voltages to the data lines. The gate driver 130 sequentially drives the gate lines by sequentially supplying scan signals to the gate lines. The timing controller 140 supplies control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The timing controller 140 starts scanning according to the timing implemented in each frame, and converts or compensates image data input from the host system 160 according to the data signal format used by the data driver 120. It converts according to the processing and outputs the converted image data (Data'), and controls data driving at an appropriate time according to the scan.

The gate driver 130 sequentially drives the gate lines by sequentially supplying scan signals of an on voltage or an off voltage to the gate lines under the control of the timing controller 140.

The gate driver 130 may be positioned only on one side of the organic light emitting display panel 110, or in some cases, may be positioned on both sides, as shown in FIG. 1, depending on the driving method.

In addition, the gate driver 130 may include one or a plurality of gate driver integrated circuits (Gate Driver IC, GDIC #1, ..., GDIC #n, n is a natural number of 1 or more).

In addition, the gate driver integrated circuits (GDIC #1, ..., GDIC #n) included in the gate driver 130 are a tape automated bonding (TAB) method or a chip on glass (COG) method. As a result, it may be connected to a bonding pad of the organic light-emitting display panel 110 or implemented in a GIP (Gate In Panel) type and directly disposed on the organic light-emitting display panel 110. In some cases, the organic light-emitting display It may be integrated and disposed on the panel 110.

Each of the gate driver integrated circuits GDIC #1, ..., GDIC #n may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driver 120 drives the data lines by converting the image data received from the timing controller 140 into analog data voltages and supplying them to the data lines.

The data driver 120 may include one or a plurality of source driver integrated circuits (Source Driver IC, SDIC #1, ..., SDIC #m, m is a natural number greater than or equal to 1). This source driver integrated circuit is also referred to as a data driver integrated circuit (Data Driver IC),

The source driver integrated circuits (SDIC #1, ..., SDIC #m) included in the data driver 120 are organic by a tape automated bonding (TAB) method or a chip on glass (COG) method. It may be connected to a bonding pad of the light-emitting display panel 110 or directly disposed on the organic light-emitting display panel 110, or may be integrated and disposed on the organic light-emitting display panel 110 in some cases.

Each of the source driver integrated circuits (SDIC #1, ..., SDIC #m) includes a shift register, a latch, a digital analog converter (DAC), an output butter, etc., and in some cases, a subpixel For compensation, an analog digital converter (ADC) for sensing an analog voltage value, converting it to a digital value, and generating and outputting the sensing data may be further included.

In addition, each of the source driver integrated circuits (SDIC #1, ..., SDIC #m) may be implemented in a Chip On Film (COF) method. In each of the source driver integrated circuits (SDIC #1, ..., SDIC #m), one end is bonded to at least one source printed circuit board, and the other end is an organic light emitting display panel 110 ) Is bonded to.

The timing controller 140 is a control printed circuit board connected to at least one source printed circuit board through a flexible flat cable (FFC) or a flexible printed circuit (FPC). It can be placed on the (Control Printed Circuit Board).

On a control printed circuit board on which the timing controller 140 is disposed, various voltages or currents are supplied or supplied to the organic light emitting display panel 110, the data driving unit 120, the gate driving unit 130, etc. A power controller 150 for controlling voltage or current may be further disposed. The power controller 150 is also referred to as a power management integrated circuit (PMIC).

The control printed circuit board and the source printed circuit board may be integrated into one printed circuit board.

In addition, the host system 160 and the timing controller 140 may be configured separately, but may be integrated into one controller.

On the other hand, the timing controller 140, together with the image data of the input image from the external host system 160, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), input data enable (DE: Data Enable) signal , And receive various timing signals including a clock signal CLK and the like.

The timing controller 140 converts the image data input from the host system 160 according to the data signal format used by the data driver 120 and outputs the converted image data. In order to control the driving unit 130, timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal are received, and various control signals are generated to generate the data driving unit 120 and the gate. Output to the driving unit 130.

For example, in order to control the gate driver 130, the timing controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS) including Gate Output Enable). The gate start pulse GSP controls operation start timing of the gate driver integrated circuits GDIC #1, ..., GDIC #n constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuits GDIC #1, ..., GDIC #n, and controls shift timing of the scan signal (gate pulse). The gate output enable signal GOE designates timing information of the gate driver integrated circuits GDIC #1, ..., GDIC #n.

In order to control the data driver 120, the timing controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). Outputs various data control signals (DCS) including ). The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits (SDIC #1, ..., SDIC #m) constituting the data driver 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits (SDIC #1, ..., SDIC #m). The source output enable signal SOE controls the output timing of the data driver 120.

Each subpixel SP disposed on the organic light emitting display panel 110 according to the present embodiments includes an organic light emitting diode (OLED), two or more transistors, and one or more capacitors. A circuit made of etc. is formed.

Each subpixel SP of the organic light emitting display panel 110 may be most basically configured to include two transistors and one capacitor in addition to the organic light emitting diode OLED.

That is, the most basic sub-pixel structure is an organic light-emitting diode (OLED), a driving transistor (DRT) that drives it, and a switching transistor (SWT) that transmits a data voltage to the gate node of the driving transistor (DRT). ), a storage capacitor (Cstg) that is electrically connected between a source node or a drain node and a gate node of the driving transistor DRT to maintain a constant voltage for one frame time.

In this most basic subpixel structure, one or more transistors may be added or one or more capacitors may be added, depending on the additional function.

Meanwhile, the driving transistor DRT in each subpixel has intrinsic characteristic values such as a threshold voltage (Vth) and mobility.

As the driving time of the driving transistor DRT increases, degradation proceeds, and intrinsic characteristic values such as threshold voltage and mobility also change.

Accordingly, a variation in the intrinsic characteristic value between the driving transistors DRT in each subpixel may be greater, and thus, a luminance variation between each subpixel may be caused to be greater.

The luminance deviation between each sub-pixel may cause a luminance non-uniformity phenomenon in the organic light emitting display panel 110, and thus image quality may be greatly degraded.

Accordingly, the organic light emitting display device 100 according to the present exemplary embodiments provides a technology for detecting a characteristic characteristic value difference by sensing a characteristic characteristic value between the driving transistors DRT in each subpixel, and compensating for the characteristic characteristic value deviation. can do.

In order to compensate for the deviation of the unique characteristic value, the structure of each subpixel may also be changed. 2 shows an example of a subpixel structure for compensating for a deviation of an intrinsic characteristic value.

In FIG. 2, as an example, a case of a 3T (Transistor) 1C (Capacitor) structure including one organic light-emitting diode (OLED), three transistors (DRT, SWT, SENT), and one capacitor (Cstg) is taken as an example. Explain.

2 is an exemplary diagram of a subpixel structure of the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 2, each subpixel includes, in addition to one organic light emitting diode (OLED), three transistors including a driving transistor (DRT), a switching transistor (SWT), and a sensing transistor (SENT), and one storage. It has a 3T (Transistor) 1C (Capacitor) structure including a capacitor (Cstg).

The subpixel structure illustrated in FIG. 2 is an exemplary diagram of a structure to which a sensing and compensation function is applied to compensate for a deviation in characteristic values (eg, threshold voltage and mobility) of the driving transistor DRT.

An organic light-emitting diode (OLED) includes a first electrode (eg, an anode electrode or a cathode electrode), an organic layer, and a second electrode (eg, a cathode electrode or an anode electrode). Here, as an example, the first electrode may be electrically connected to a second node (N2 node) of the driving transistor DRT, and the second electrode may be electrically connected to a node to which the base voltage EVSS is supplied.

Intrinsic characteristic value deviation compensation of the driving transistor (DRT) is used in the same meaning as the luminance deviation compensation of the subpixel, and since the data to be supplied to the subpixel must be changed to compensate for the luminance deviation, it is also used in the same meaning as "data compensation". do. That is, transistor characteristic value deviation compensation, luminance deviation compensation, data compensation, and pixel compensation are all used interchangeably.

A driving transistor (DRT) is a transistor that drives an organic light emitting diode (OLED), between the first electrode (eg, anode or drain electrode) of the organic light emitting diode (OLED) and a driving voltage line (DVL). It is electrically connected.

The driving transistor DRT includes a first node (N1 node) corresponding to a gate node, and a second node (N2 node) electrically connected to the first electrode of the organic light emitting diode (OLED), e.g., a source node or a drain node. ) And a third node (N3 node, for example, a drain node or a source node) electrically connected to the driving voltage line DVL for supplying the driving voltage EVDD.

The switching transistor SWT is a transistor for transmitting a data voltage Vdata to an N1 node corresponding to a gate node of the driving transistor DRT, and the N1 node and a data line corresponding to the gate node of the driving transistor DRT ( DL) is electrically connected.

The switching transistor SWT is controlled by the scan signal SCAN applied to the gate node through the corresponding gate line GL, and when turned on, the data voltage supplied through the data line DL is applied to the driving transistor ( DRT) to the N1 node corresponding to the gate node.

A storage capacitor (Cstg: Storage Capacitor) is electrically connected between the N1 node (gate node) and the N2 node (source node or drain node) of the driving transistor (DRT) to maintain a constant voltage for one frame time. do.

The sensing transistor (SENT) is controlled by a sense signal (SENSE), a type of scan signal applied to the gate node from the corresponding gate line (GL'), and is a reference for supplying a reference voltage (VREF). It is electrically connected between the voltage line (RVL: Reference Voltage Line) and the N2 node of the driving transistor (DRT).

Meanwhile, referring to FIG. 2, the organic light emitting display device 100 is supplied with a reference voltage Vref according to a switching operation of the first switch SPRE connected to one side or the other side of the reference voltage line RVL. The node and the reference voltage line RVL may be connected. That is, when the first switch SPRE is turned on, the reference voltage Vref may be supplied to the reference voltage line RVL.

In addition, referring to FIG. 2, the organic light emitting display device 100 includes a second switch SAM connected to one side of the reference voltage line RVL and a reference according to the switching operation of the second switch SAM. It may further include an analog-to-digital converter (ADC) electrically connectable to the voltage line (RVL).

When the second switch (SAM) is turned on (On), the reference voltage line (RVL) and the analog-to-digital converter (ADC) are connected, and when the second switch (SAM) is off (Off), the reference voltage line (RVL) And the analog-to-digital converter (ADC) is disconnected.

When the second switch SAM is turned on and is electrically connected to the reference voltage line RVL, the analog-to-digital converter ADC senses the voltage of the reference voltage line RVL.

At this time, the sensed voltage of the reference voltage RVL is the same as the voltage of the N2 node of the driving transistor DRT when the sensing transistor SENT is turned on and the resistance component of the sensing transistor SENT is ignored.

In addition, the sensed voltage Vsen of the N2 node of the driving transistor DRT may be expressed by including a threshold voltage Vth component of the driving transistor DRT (Vsen=Vdata-Vth). Accordingly, it is possible to determine the threshold voltage of the driving transistor DRT or a deviation thereof from the sensed sensing voltage of the N2 node of the driving transistor DRT. This will be described again later.

The analog-to-digital converter (ADC) converts the sensed sensing voltage into a digital value, generates sensing data, and transmits the sensing data to the timing controller 140.

When the above-described analog-to-digital converter (ADC) is used, the timing controller 140 may sense information (eg, threshold voltage, threshold voltage deviation, etc.) necessary on a digital basis and perform data compensation processing.

More specifically, the timing controller 140 receives the sensing data and, based on the received sensing data, finds out the threshold voltage Vth of the driving transistor DRT in each subpixel, the threshold voltage deviation (ΔVth). Can grasp.

Here, the timing controller 140 may store the received sensing data, the found threshold voltage, or the determined threshold voltage deviation data in a memory (not shown).

The timing controller 140 may calculate a data compensation amount (ΔData) for each subpixel and store the calculated data compensation amount (ΔData) in a memory in order to compensate for the threshold voltage deviation (ΔVth). have.

In this way, after the data compensation amount for each subpixel is calculated, the timing controller 140 changes the data to be supplied to each subpixel based on the data compensation amount for each subpixel and supplies it to the data driver 120. , The data driver 120 converts the supplied data into a data voltage and applies it to the subpixels, so that compensation is actually performed.

The analog-to-digital converter (ADC) described above may be included in each of a plurality of source driver integrated circuits (SDIC #1, ..., SDIC #m) included in the data driver 120.

In this way, by including an analog-to-digital converter (ADC) corresponding to the sensing configuration for compensation in each source driver integrated circuit, the number of components can be reduced, and the sensing operation can be performed in connection with data driving. have.

When the above-described 3T1C subpixel structure is used, intrinsic characteristic values such as threshold voltage and mobility of the driving transistor DRT in the subpixel can be effectively sensed and compensated.

Meanwhile, the reference voltage line RVL is a signal line used for voltage sensing of the analog-to-digital converter ADC, and is also referred to as a sensing line (SL).

One such reference voltage line RVL may exist for each subpixel column or one for each of two or more subpixel columns.

Referring to FIG. 2, the reference voltage line RVL is connected to one electrode of the sensing line capacitor Csl. The same voltage as the reference voltage line RVL is applied to one electrode of the sensing line capacitor Csl.

Meanwhile, referring to FIG. 2, two gate lines GL and GL' that apply two scan signals SCAN and SENSE to the gate nodes of two transistors SWT and SENT in each subpixel are different gates. It may be a line or the same single gate line.

If the two gate lines GL and GL' that apply two scan signals SCAN and SENSE to the gate nodes of the two transistors T1 and T2 in each subpixel are different gate lines, FIG. 1 One gate line GL shown in may be considered to include two gate lines.

In the following, a driving method for sensing the threshold voltage of the driving transistor DRT in the subpixel using the 3T1C subpixel structure of FIG. 2 will be briefly described with reference to FIG. 3.

3 is a timing diagram illustrating a threshold voltage sensing of a driving transistor DRT in a subpixel of the organic light emitting display device 100 according to the present exemplary embodiments.

2 and 3, the driving method for sensing the threshold voltage is a first step (STEP) of initializing voltages of the N1 node (gate node) and the N2 node (source node or drain node) of the driving transistor DRT. 1) and a second step (STEP 2) of increasing the voltage of the N2 node of the driving transistor DRT by floating the N2 node of the driving transistor DRT, and the voltage of the N2 node of the driving transistor DRT If this rises and then saturates, the process proceeds to a third step (STEP 3) of sensing the saturated voltage of the N2 node of the driving transistor DRT.

2 and 3, in a first step (STEP 1), the scan signal SCAN is applied to the gate node of the switching transistor SWT, so that the switching transistor SWT is turned on. In addition, the sense signal SENSE is applied to the gate node of the sensing transistor SENT, so that the sensing transistor SENT is turned on.

2 and 3, in a first step (STEP 1), the N1 node of the driving transistor DRT through the switching transistor SWT in which the data voltage Vdata supplied to the data line DL is turned on. Is applied as.

2 and 3, in a first step (STEP 1), the first switch SPRE is turned on, and the reference voltage Vref is supplied to the reference voltage line RVL. The reference voltage Vref supplied to the reference voltage line RVL is applied to the N2 node of the driving transistor DRT through the turned-on sensing transistor SENT.

Therefore, in the first step (STEP 1), the N1 node (gate node) of the driving transistor DRT is initialized to the data voltage Vdata, and the N2 node (source node or drain node) of the driving transistor DRT is the reference. It is initialized to voltage (Vref).

Accordingly, as shown in FIG. 3, in the first step (STEP 1), the voltage Vsl of the reference voltage line RVL corresponding to the sensing line SL corresponds to the reference voltage Vref.

2 and 3, in the second step (STEP 2) that proceeds after the first step (STEP 1), the scan signal SCAN is continuously applied to the gate node of the switching transistor SWT, so that the switching transistor ( SWT) remains on. In addition, the sense signal SENSE is also continuously applied to the gate node of the sensing transistor SENT, so that the sensing transistor SENT can also maintain the ON state.

However, referring to FIGS. 2 and 3, in the second step (STEP 2), the first switch SPRE is turned off, so that the reference voltage Vref is not supplied to the reference voltage line RVL. Accordingly, the N2 node of the driving transistor DRT is floating.

Referring to FIG. 3, as the N2 node of the driving transistor DRT is floating, the voltage of the N2 node of the driving transistor DRT starts to rise from the reference voltage Vref.

The voltage increase of the N2 node of the driving transistor DRT is performed until a difference between the data voltage Vdata and a predetermined voltage Vth differs.

That is, referring to FIG. 3, when the voltage of the N2 node of the driving transistor DRT becomes Vdata-Vth, the voltage of the N2 node of the driving transistor DRT is saturated. In this case, the threshold voltage Vth of the driving transistor DRT may be a positive value or a negative value.

Referring to FIGS. 2 and 3, in a third system (STEP 3) performed after the second step (STEP 2), the sense signal SENSE is not applied to the gate node of the sensing transistor SENT. That is, the sensing transistor SENT is in an off state.

And, referring to FIGS. 2 and 3, in the third system (STEP 3), the second switch SAM is turned on, and the reference voltage line RVL corresponding to the sensing line SL and the analog-to-digital converter ADC ) Is connected.

Accordingly, the analog-to-digital converter ADC may sense the voltage of the reference voltage line RVL, that is, the sensing line SL.

The analog-to-digital converter ADC may sense a potential difference (voltage) formed at both ends of the reference voltage line RVL, that is, the sensing line capacitor Csl connected to the sensing line SL.

As described above, that the analog-to-digital converter (ADC) senses the voltage of the sensing line SL, that is, senses the potential difference (voltage) formed at both ends of the sensing line capacitor Csl, which means N2 of the driving transistor DRT. It may have the same meaning as sensing the voltage of the node.

In this case, the voltage Vsen sensed by the analog-to-digital converter ADC is “Vdata-Vth”.

In this way, when the analog-to-digital converter ADC senses (measures) the sensing voltage Vsen, since the data voltage Vdata is a known value, the threshold voltage Vth of the driving transistor DRT can be known.

According to the driving method for sensing the threshold voltage as described above, in order to accurately sense the threshold voltage, when the voltage of the N2 node of the driving transistor DRT is saturated, that is, the reference voltage line corresponding to the sensing line SL. Since we have to wait for the voltage of (RVL) to saturate, a long sensing time may be required.

These days, for high resolution implementation, the pixel size is getting smaller and smaller. Accordingly, the size of the driving transistor DRT is also decreasing accordingly.

The reduction in the size of the driving transistor DRT according to the high resolution implementation leads to a decrease in the current driving capability of the driving transistor DRT, thereby increasing the charging time of the sensing line capacitor Csl. For this reason, the sensing time required to sense the threshold voltage is inevitably increased.

The driving transistors on the organic light emitting display panel 110 undergo degradation as the driving time increases, so that the distribution of threshold voltages for the driving transistors on the organic light emitting display panel 110 changes as a whole. In this case, sensing accuracy may be lowered. This will be described again with reference to FIGS. 4 and 5.

4 is a diagram illustrating a distribution of threshold voltages of driving transistors DRT and a change thereof in the organic light emitting display device 100 according to the present exemplary embodiments. 5 is a diagram illustrating a voltage change at a sensing point according to a change in a threshold voltage distribution of driving transistors DRT in the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 4, the driving transistors on the organic light-emitting display panel 110 undergo degradation as the driving time increases, so that the distribution of threshold voltages for the driving transistors on the organic light-emitting display panel 110 is premised. It moves in a positive direction.

Referring to FIG. 4, according to the shift (change) of the threshold voltage distribution, an average value shift (m->m'), a lower limit shift (LSL->LSL'), and an upper limit shift (USL->USL') on the threshold voltage distribution. ) Occurs.

When such a change in the threshold voltage distribution occurs, the waveform of the voltage Vsl of the reference voltage line RVL corresponding to the sensing line SL is also shown in FIG. 5 when sensing the threshold voltage of the individual driving transistor DRT. Change together. However, in FIG. 5, for convenience of explanation, it is assumed that the threshold voltage is negative.

Referring to FIG. 5, in a situation where the initial pre-charge voltage for the sensing line capacitor Csl is always fixed to the reference voltage Vref, the threshold voltage distribution is moved in the negative direction. Accordingly, when the threshold voltage increases from Vth to Vth', the saturation voltage Vsat also increases.

Accordingly, the timing at which the voltage Vsl of the sensing line SL, that is, the voltage of the N2 node of the driving transistor DRT, is saturated is delayed, and the time required to accurately sense the threshold voltage is increased.

However, since the sensing time is constantly limited, even if the threshold voltage distribution of the driving transistors on the organic light emitting display panel 110 changes, the voltage Vsl of the sensing line SL, that is, the driving transistor DRT. It cannot be sensed after waiting enough for the voltage of the N2 node of N2 to saturate, and the voltage must be sensed at a predetermined sensing time. Therefore, when a change in the threshold voltage distribution occurs, voltage sensing is performed before voltage saturation occurs, so that the sensing accuracy is inevitably lowered.

Referring to FIG. 5, since a sensing time is determined, when voltage sensing is performed at a point in time Tsen, a saturated voltage (Vsat=Vdata-Vth) may be sensed as a sensing voltage Vsen before a change in a threshold voltage distribution.

However, after the change in the threshold voltage distribution, before the voltage Vsl of the sensing line SL, that is, the voltage of the N2 node of the driving transistor DRT, rises to the saturation voltage (Vsat=Vdata-Vth'), the Tsen time point Voltage is sensed. Therefore, it is impossible to sense an accurate threshold voltage Vth'.

As described above, in the case of the driving method for sensing the threshold voltage, when high resolution is implemented, the threshold voltage sensing time is too long, and when the threshold voltage distribution is changed, the threshold voltage sensing accuracy may be lowered.

Accordingly, in the following, a method of driving threshold voltage sensing capable of shortening the threshold voltage sensing time and thereby improving the threshold voltage sensing accuracy will be described with reference to FIGS. 6 to 10.

The driving method for sensing the threshold voltage to be described below may shorten the threshold voltage sensing time and improve the sensing accuracy by using a "reference voltage tracking technique".

However, below, for convenience of description, it is assumed that the threshold voltage of the driving transistor DRTk in the subpixel SPk is sensed.

6 is a diagram for describing a reference voltage tracking technique of the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 6, sensing of a threshold voltage for the driving transistor DRTk in an arbitrary subpixel SPk may be performed repeatedly. Therefore, below, the N-1th (N is a natural number greater than 2) threshold voltage sensing is performed, and thereafter, the Nth threshold voltage is sensed according to a specific event (e.g., when a power-off signal is generated) or a request. I assume.

In the Nth sensing period, the data voltage Vdata is applied to the N1 node corresponding to the gate node of the driving transistor DRTk (k is 1 to the number of data lines) in the subpixel SPk, and the driving transistor DRTk After applying a fixed reference voltage (Vref(N)) to the N2 node corresponding to the source node or drain node of ), the N2 node corresponding to the source node or the drain node of the driving transistor DRTk is floated and the driving transistor ( The voltage of the N2 node corresponding to the source node or the drain node of DRTk, that is, the voltage Vsl(N) of the sensing line SL is sensed.

At this time, the time required for saturation of the voltage Vsl(N) of the sensing line SL is ΔTsat.

In the N-th sensing period, the voltage of the N2 node of the driving transistor DRTk, that is, the voltage Vsl(N) of the sensing line SL, is sensed based on the floating time of the N2 node of the driving transistor DRTk. The sensing time up to is ΔTsen, and the sensing voltage Vsen(N) is Vdata-Vth1 (threshold voltage of the driving transistor DRTk).

In the Nth sensing period, the data voltage Vdata is applied to the N1 node corresponding to the gate node of the driving transistor DRTk in the subpixel SPk, and corresponds to the source node or the drain node of the driving transistor DRTk. The initial reference voltage (initial Vref(N)) is applied to the N2 node. After that, Vgs(Vdata(N)-Vref(N)) of the driving transistor is greater than the initial reference voltage (initial Vref(N)) and Vgs(Vdata(N)-Vref(N)) is greater than the threshold voltage. The optimum reference voltage (optimum Vref(N)) is tracked. After applying the optimum reference voltage (optimum Vref(N)) to the N2 node corresponding to the source node or drain node of the driving transistor (DRTk), the N2 node is floated to correspond to the source node or drain node of the driving transistor (DRTk). The voltage of the N2 node, that is, the voltage Vsl(N1) of the sensing line SL is sensed.

At this time, the saturation time required for the voltage Vsl(N) of the sensing line SL to saturate is ΔTsat'.

In the N-th sensing period, the voltage of the N2 node of the driving transistor DRTk, that is, the voltage Vsl(N) of the sensing line SL, is sensed based on the floating time of the N2 node of the driving transistor DRTk. The sensing time until is ΔTsen', and the sensing voltage Vsen(N) is Vdata-Vth1 (threshold voltage of the driving transistor DRTk).

Meanwhile, referring to FIG. 6, in a driving transistor of a predetermined number or more of subpixels in an N-th sensing period, a source node or a drain of the driving transistor DRTk is applied while a data voltage is applied to the gate node of the driving transistor. The last reference voltage at which the sensing voltage for the source node or drain node of the sensed driving transistor DRTk is increased after the reference voltage (Vref(N)) applied to the N2 node corresponding to the node is increased by a certain step is the optimal reference. It can be set to a voltage (optimum Vref(N)).

In the N-th sensing period, when the reference voltage applied to the source node or the drain node of the driving transistor DRTk is set to the above-described optimum reference voltage according to the above-described embodiment, a fixed initial reference voltage (initial Vref(N)) Compared to the case where is applied, the voltage of the N2 node of the driving transistor DRTk, that is, the voltage of the sensing line SL, saturates more quickly.

Therefore, when the reference voltage applied to the source node or the drain node of the driving transistor DRTk is set to the above-described optimal reference voltage in the N-th sensing period according to the above-described embodiment, the saturation required time ΔTsat' is a fixed initial reference voltage. When (initial Vref(N)) is applied, the time required for saturation is shorter than △Tsat. In other words, in the Nth sensing period, the time ΔTsat' for the driving transistor DRTk to reach the saturation state according to the optimum reference voltage (optimum Vref(N)) applied to the source node or the drain node of the driving transistor DRTk is , According to an initial reference voltage applied to the source node or the drain node of the driving transistor DRTk, it may be shorter than the time ΔTsat for the driving transistor DRTk to reach the saturation state.

As the time required for saturation is shortened as described above, even if the voltage is sensed at an earlier time in the N-th sensing period, the threshold voltage can be accurately sensed.

For this reason, the reference voltage applied to the source node or drain node of the driving transistor DRTk according to the above-described embodiment in the N-th sensing period is set as the above-described optimum reference voltage without affecting the threshold voltage sensing accuracy. The sensing time ΔTsen' in the case may be set to be shorter than the sensing time ΔTsen when a fixed initial reference voltage (initial Vref(N)) is applied.

As described above, in the Nth sensing period, the threshold voltage sensing operation is performed by setting the reference voltage Vref(N) for initializing the N2 node of the driving transistor DRTk as the optimum reference voltage (optimum Vref(N)). , It is possible to saturate the voltage of the N2 node of the driving transistor DRTk more quickly. Therefore, through the reference voltage tracking technique, it is possible to shorten the sensing time without deteriorating the threshold voltage sensing accuracy.

In the following, a reference voltage tracking technique will be described in more detail.

7 is a diagram for describing a reference voltage tracking technique for tracking a reference voltage in an Nth sensing section in the organic light emitting display device according to the present embodiments.

Referring to FIG. 7, in the Nth sensing period, Vgs(Vdata(N)-Vref(N)) of the driving transistor DRTk is greater than the initial reference voltage (initial Vref(N)) and is greater than the threshold voltage Vgs( The optimum reference voltage (optimum Vref(N)) at which Vdata(N)-Vref(N)) becomes the minimum is tracked, and the optimum reference voltage (optimum) is applied to the N2 node corresponding to the source node or drain node of the driving transistor (DRTk). Vref(N)) can be applied.

Specifically, in a state where Vgs <Vth of the driving transistor DRTk due to the characteristics of the source-following method, the threshold voltage Vth cannot be sensed as the driving transistor DRTk is turned off. Accordingly, the reference voltage Vref(N) applied to the N2 node corresponding to the source node or the drain node of the driving transistor DRTk cannot be increased indefinitely. By utilizing the characteristic that the driving transistor (DRTk) is turned off when Vgs <Vth, the minimum Vgs (Vdata) before the driving transistor (DRTk) of the total number of pixels in the horizontal direction of the display panel (for example, 3840 units in UHD) is turned off. You can shorten the sensing time by finding (N)-Vref(N)).

As described above, in the driving transistor having a predetermined number of subpixels or more in the N-th sensing period, the reference voltage is changed to the initial reference voltage (the initial Vref(N) when the data voltage is applied to the gate node of the driving transistor DRTk). )), and then setting the last reference voltage at which the sensing voltage to the source node or drain node of the sensed driving transistor (DRTk) increases as the optimum reference voltage (optimum Vref(N)), shortening the sensing time and sensing It is possible to set an effective reference voltage that enables both accuracy improvement. The predetermined number may be one or more than one.

As shown in FIG. 7A, in a state in which a data voltage is applied to the gate node of the driving transistor DRTk, the initial reference voltage (the initial Vref(N) is applied to the source node or the drain node of the driving transistor DRTk) of each of a plurality of subpixels. )) is applied and the sensed voltage to the source node or drain node of the driving transistor DRTk increases, raising the reference voltage applied to the source node or drain node of the driving transistor DRTk by one step. If the sensing voltage for the source node or the drain node of a predetermined number (for example, one) among the driving transistors DRTk does not increase, the source node of the driving transistor DRTk is repeated (repeated twice in FIG. 7A). Alternatively, the reference voltage applied to the drain node may be lowered by one step to set the optimum reference voltage (optimum Vref(N)).

As shown in FIG. 7B, when the sensing voltage increases in the above-described state, the reference voltage applied to the source node or the drain node of the driving transistor DRTk is repeatedly increased one step (repeated twice in FIG. 7B). And, if the sensing voltage for the source node or drain node of a predetermined number (for example, three) among the driving transistors DRTk does not rise, the reference voltage applied to the source node or the drain node of the driving transistor DRTk is It can be lowered by one step and set to the optimum reference voltage (optimum Vref(N)).

At this time, the initial reference voltage (initial Vref(N)) applied to the source node or drain node of the driving transistor in the N-th sensing period is applied to the source node or drain node of the driving transistor in the NK-th (K is a natural number greater than 1) sensing period. It may be an applied optimum reference voltage (optimum Vref(NK)). For example, in this case, the initial reference voltage (initial Vref(N)) applied to the source node or drain node of the driving transistor in the N-th sensing period is the source node of the driving transistor in the N-1th (that is, K=1) sensing period. It may be an optimum reference voltage (optimum Vref(N-1)) applied to the drain node. In this way, the optimum reference voltage (optimum Vref(NK)) is used in the previous NKth (K is a natural number greater than 1) sensing section as the initial reference voltage (initial Vref(N)). It is possible to shorten the tracking time and number of times of Vref(N)).

8 is a timing diagram illustrating a threshold voltage sensing of a driving transistor DRT in a subpixel of the organic light emitting display device 100 according to the present exemplary embodiments. 9 is a flowchart of a driving method for sensing a threshold voltage of the organic light emitting display device 100 according to another exemplary embodiment.

8 and 9, the driving method for sensing the threshold voltage is a first step of tracking the reference voltages of the N1 node (gate node) and the N2 node (source node or drain node) of the driving transistor DRT ( STEP 1, S910), a second step of increasing the voltage of the N2 node of the driving transistor DRT by floating the N2 node of the driving transistor DRT (STEP 2, S920), and the driving transistor DRT When the voltage of the N2 node of is increased and then saturated, the process proceeds to a third step (STEP 3, S930) of sensing the saturated voltage of the N2 node of the driving transistor DRT.

The first step (STEP 1, S910) is a step of applying a data voltage to a gate node of the driving transistor and applying an initial reference voltage to a source node or a drain node of the driving transistor (S911) in the N-th sensing period. In the step of sensing the sensing voltage for sensing the sensing voltage of the source node or the drain node of the transistor (S912), determining whether the sensing voltage is increased (S913), and determining whether the sensing voltage is increased (S913), a plurality of When the sensing voltages of the driving transistors of the subpixels of are all increased, the reference voltage is increased by one step to the source node or the drain node of the driving transistor, and then returned to sensing the sensing voltage (S914) and whether the sensing voltage is increased. If the sensing voltage of more than a predetermined number among the driving transistors of the subpixels does not rise in the step of determining (S913), the reference voltage is lowered by one step to the source node or the drain node of the driving transistor, and the source or the source of the driving transistors of the subpixels And setting the optimal reference voltage applied to the drain (S915).

Specifically, in step S911, the scan signal SCAN is applied to the gate node of the switching transistor SWT, so that the switching transistor SWT is turned on. In addition, the sense signal SENSE is applied to the gate node of the sensing transistor SENT, so that the sensing transistor SENT is turned on. The data voltage Vdata supplied to the data line DL is applied to the N1 node of the driving transistor DRT through the turned-on switching transistor SWT.

When the first switch SPRE is turned on, an initial reference voltage (initial Vref) is supplied to the reference voltage line RVL. The initial reference voltage (initial Vref) supplied to the reference voltage line RVL is applied to the N2 node of the driving transistor DRT through the turned-on sensing transistor SENT. As described above, the initial reference voltage (initial Vref(N)) is the optimum reference voltage (optimum Vref(NK)) applied to the source node or drain node of the driving transistor in the NK-th (K is a natural number greater than 1) sensing period, For example, it may be the optimum reference voltage (optimum Vref(N-1)) in the N-1th sensing period.

In the step of sensing a sensing voltage for sensing a sensing voltage of a source node or a drain node of the driving transistor (S912), the first switch SPRE is turned off, so that the reference voltage Vref is not supplied to the reference voltage line RVL. Does not. Accordingly, the N2 node of the driving transistor DRT is floating. As the N2 node of the driving transistor DRT is floating, the voltage of the N2 node of the driving transistor DRT starts to rise from the reference voltage Vref. Next, the second switch SAM is turned on, and the reference voltage line RVL corresponding to the sensing line SL and the analog-to-digital converter ADC are connected. Accordingly, the analog-to-digital converter ADC may sense the voltage of the reference voltage line RVL, that is, the sensing line SL.

In the step of determining whether the sensing voltage is increased (S913), the sensing line SL for a time (eg, 100 μs) less than the actual threshold voltage sensing time ΔTsen′ (eg 30 ms) of one subpixel (eg, 100 μs). It can only be determined whether the voltage of is increased.

For example, in the step of determining whether the sensing voltage is increased (S913), when the voltages of all the sensing lines SL rise by a certain voltage or more (for example, 30mV), the reference voltage is increased by one step (for example, 500mV) and applied. After that (Vref(N)=initial Verf(N)+500mV), it returns to the step of sensing the sensing voltage (S912).

As shown in FIG. 8, after first applying a reference voltage of Verf(N) + 500mV to the source node or drain node of the driving transistor in step S912, whether the voltages of all sensing lines SL rise by a certain voltage or more in step S913. Judge. In step S913, if the voltage of all sensing lines SL rises above a certain voltage (for example, 30mV), the reference voltage is increased by one step (for example, 500mV) and then applied (Vref(N) = initial Verf(N ) + 1000mV) It returns to the step of sensing the sensing voltage (S912).

In step S912, after first applying a reference voltage of Verf(N)+1000mV to the source node or the drain node of the driving transistor, it is determined in step S913 whether the voltages of all the sensing lines SL rise by a predetermined voltage or more. If the sensing voltage of one of the driving transistors of the subpixels does not rise in the step of determining whether the sensing voltage is increased (S913), the reference voltage is lowered by one step to the source node or the drain node of the driving transistor in step S915, The optimum reference voltage applied to the source or drain of the driving transistors (optimum Vref(N) = initial Verf(N) + 500mV) is set.

In other words, in the step of determining whether the sensing voltage increases (S913), if the sensing voltage of the driving transistors of the subpixels does not increase by more than a predetermined number, the sensing voltage of the source node or the drain node of the driving transistor DRTk increases. The final reference voltage can be set as an optimum reference voltage (optimum Vref(N)) as a boundary line of the threshold voltage distribution of the display panel. The predetermined number may be one as shown in Fig. 7A or two or more (three in Fig. 7B) as shown in Fig. 7B.

Therefore, in the first step (STEP 1, S910), the N1 node (gate node) of the driving transistor DRT is initialized to the data voltage Vdata, and the N2 node (source node or the drain node) of the driving transistor DRT Is initialized to the optimum reference voltage (optimum Vref(N) = initial Verf(N) + 500mV).

In the second step (STEP 2, 920), the first switch SPRE is finally turned off, so that the reference voltage Vref is not supplied to the reference voltage line RVL. Accordingly, the N2 node of the driving transistor DRT is floating. As the N2 node of the driving transistor DRT is floating, the voltage of the N2 node of the driving transistor DRT differs from the reference voltage Vref to the data voltage Vdata by a certain voltage Vth. Rises.

In the third system (STEP 3, S930) performed after the second steps (STEP 2 and S920), the sense signal SENSE is not applied to the gate node of the sensing transistor SENT. That is, the sensing transistor SENT is in an off state. In the third step (STEP 3 and S930), the second switch SAM is turned on again, and the reference voltage line RVL corresponding to the sensing line SL is connected to the analog-to-digital converter ADC. Accordingly, the analog-to-digital converter ADC may sense the voltage of the reference voltage line RVL, that is, the sensing line SL.

The analog-to-digital converter ADC may sense a potential difference (voltage) formed at both ends of the reference voltage line RVL, that is, the sensing line capacitor Csl connected to the sensing line SL. As described above, that the analog-to-digital converter (ADC) senses the voltage of the sensing line SL, that is, senses the potential difference (voltage) formed at both ends of the sensing line capacitor Csl, which means N2 of the driving transistor DRT. It may have the same meaning as sensing the voltage of the node. In this case, the voltage Vsen sensed by the analog-to-digital converter ADC is “Vdata-Vth”.

In this way, when the analog-to-digital converter ADC senses (measures) the sensing voltage Vsen, since the data voltage Vdata is a known value, the threshold voltage Vth of the driving transistor DRT can be known.

As described above, at the beginning of the N-th sensing period, the source node or drain of the driving transistor DRTk sensed after raising the reference voltage by a certain level while applying the data voltage to the gate node of the driving transistor DRTk By setting the last reference voltage at which the sensing voltage for the node increases as the optimum reference voltage (optimum Vref(N)), as shown in FIG. 10, it is present in the reference voltage line RVL corresponding to the sensing line SL. The pre-charge voltage applied to both ends of the sensing line capacitor Csl, which is a capacitor component, can be increased from the initial reference voltage to the optimum reference voltage.

Therefore, as shown in FIG. 10, when the voltage of the N2 node of the driving transistor DRTk rises and then saturates at a faster time, the analog-to-digital converter ADC is the voltage of the N2 node of the driving transistor DRTk. In order to sense (that is, the voltage of the sensing line SL), the voltage Vsen applied to the sensing line capacitor Csl is sampled and sensed.

When performing the reference voltage tracking technique described above, the tracking setting of the reference voltage can be determined by tracking the optimum reference voltage determined by the timing controller 140 from sensing data received from an analog digital converter (ADC). have.

The timing controller 140 may output a control signal to the power controller 150 so that the optimum reference voltage is supplied to the organic light emitting display panel 110.

According to the exemplary embodiments described above, the organic light emitting display panel 110, the organic light emitting display device 100, and a driving method thereof capable of shortening the threshold voltage sensing time can be provided.

According to the present embodiments, it is possible to provide an organic light-emitting display panel 110, an organic light-emitting display device 100, and a driving method thereof, which can increase the accuracy of sensing the threshold voltage.

The description above and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the technical field to which the present invention pertains, combinations of configurations within the scope not departing from the essential characteristics of the present invention. Various modifications and variations, such as separation, substitution, and alteration, will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driver
130: gate driver
140: timing controller

Claims (10)

An organic light emitting display panel on which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed;
A data driver driving the plurality of data lines;
A gate driver driving the plurality of gate lines; And
A timing controller that controls the data driver and the gate driver,
Each of the plurality of subpixels,
An organic light-emitting diode, a driving transistor for driving the organic light-emitting diode, and a switching transistor for transmitting a data voltage to a gate node of the driving transistor,
In the Nth sensing period, the reference voltage applied to the source node or the drain node of the driving transistor of each of the plurality of subpixels is greater than the initial reference voltage, and the Vgs of the driving transistor is greater than the threshold voltage and the Vgs is minimum. Is set to the optimum reference voltage,
The optimum reference voltage is,
In the N-th sensing period, in a driving transistor having a predetermined number or more of subpixels, the reference voltage is increased by a predetermined step from the initial reference voltage while the data voltage is applied to the gate node of the driving transistor, and then sensed. An organic light emitting display device that is a last reference voltage at which a sensing voltage for a source node or a drain node of the driving transistor is increased. delete The method of claim 1,
The predetermined number is one organic light-emitting display device. The method of claim 1,
The first reference voltage is an optimal reference voltage in an Nk-th (k is a natural number greater than 1) sensing section. The method of claim 1,
In the N-th sensing period, a time for the driving transistor to reach a saturation state according to the optimum reference voltage applied to a source node or a drain node of the driving transistor of each of the plurality of subpixels is a source node of the driving transistor. Or an organic light emitting display device that is shorter than a time for the driving transistor to reach a saturation state according to an initial reference voltage applied to a drain node. The method of claim 1,
Each of the plurality of subpixels,
The organic light-emitting diode,
The driving transistor electrically connected between the first electrode of the organic light emitting diode and a driving voltage line,
The switching transistor electrically connected between a first node corresponding to a gate node of the driving transistor and a data line,
A storage capacitor electrically connected between a first node of the driving transistor and a second node corresponding to a source node or a drain node of the driving transistor,
And a sensing transistor electrically connected between a second node of the driving transistor and a reference voltage line. The method of claim 6,
An organic light-emitting display device comprising an analog-to-digital converter electrically connectable to the reference voltage line according to a switching operation of a switch. A plurality of data lines and a plurality of gate lines disposed in a direction crossing each other; And
Including a plurality of subpixels arranged in a matrix type,
Each of the plurality of subpixels,
An organic light-emitting diode, a driving transistor for driving the organic light-emitting diode, and a switching transistor for transmitting a data voltage to a gate node of the driving transistor,
In the Nth sensing period, the reference voltage applied to the source node or the drain node of the driving transistor of each of the plurality of subpixels is greater than the initial reference voltage, and the Vgs of the driving transistor is greater than the threshold voltage and the Vgs is minimum. Is set as the optimum reference voltage,
The optimum reference voltage is,
In the N-th sensing period, in a driving transistor having a predetermined number or more of subpixels, the reference voltage is increased by a predetermined step from the initial reference voltage while the data voltage is applied to the gate node of the driving transistor, and then sensed. An organic light-emitting display panel that is a last reference voltage at which a sensing voltage for a source node or a drain node of the driving transistor is increased. A driving method of an organic light emitting display device comprising a plurality of subpixels each including an organic light emitting diode, a driving transistor driving the organic light emitting diode, and a switching transistor transmitting a data voltage to a gate node of the driving transistor,
Applying a data voltage to a gate node of the driving transistor and applying an initial reference voltage to a source node or a drain node of the driving transistor in an Nth sensing period;
Sensing a sensing voltage of a source node or a drain node of the driving transistor;
Determining whether the sensing voltage is increased;
When the sensing voltages of the driving transistors of the plurality of subpixels are all increased in the step of determining whether the sensing voltage is increased, the reference voltage is increased by one step to the source node or the drain node of the driving transistor, and then the sensing voltage is applied. Returning to the sensing step; And
If the sensing voltage of the driving transistors of the subpixels does not increase by more than a predetermined number in the step of determining whether the sensing voltage is increased, the reference voltage is lowered by one step to the source node or the drain node of the driving transistor to the subpixel. And setting an optimum reference voltage applied to the source or drain of the driving transistors of the organic light emitting diodes. The method of claim 9,
The method of driving an organic light emitting display device in which the predetermined number is one.

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