KR102110754B1 - Method for producing semiconductor chip - Google Patents

Abstract

A method of manufacturing a semiconductor chip is a method of manufacturing a semiconductor chip having a substrate, a conductive portion formed on the substrate, and a micro bump formed on the conductive portion, comprising a step of forming a smooth surface to form a smooth surface on the micro bump, and forming a smooth surface The process includes a heating process in which a reducing gas is introduced into an inert atmosphere to a space where the semiconductor chip is disposed, and heated to a temperature above the melting point of the micro bump, and in the heating process, a pressure applying member is placed on the micro bump, and a pressure applying member is provided. Of the main surfaces, the main surface contacting the micro bump is flat.

Description

Manufacturing method of semiconductor chip {METHOD FOR PRODUCING SEMICONDUCTOR CHIP}

The present invention relates to a method for manufacturing a semiconductor chip.

Conventionally, in the three-dimensional mounting of a semiconductor package, a connection between a semiconductor chip and a semiconductor chip or an interposer is performed using wire bonding. Instead of this wire-bonding, a three-dimensional mounting technique has been developed in which semiconductor chips are connected between through electrodes and bumps. The through electrode has a short connection line length (for example, 50 µm) as a standard, and it is required that the bumps connecting the electrodes are also fine. The technology corresponding to the bump pitch of less than 50 μm is called micro bump. By connecting a semiconductor chip and a semiconductor chip with a through electrode and a micro bump as described in US Patent No. 9136159, the wiring length between the semiconductor chips can be dramatically shortened. Therefore, it is possible to reduce the wiring delay time which increases with miniaturization.

Here, lamination of the semiconductor chip and the semiconductor chip is performed by flip chip mounting. However, when a plurality of semiconductor chips and semiconductor chips are stacked and joined, problems such as misalignment between semiconductor chips occur. Further, even when other electronic components or the like are mounted on the semiconductor chip, it is required to perform bonding more suitably.

The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a semiconductor chip capable of suitably bonding a semiconductor chip to a mating member.

A method of manufacturing a semiconductor chip according to an aspect of the present invention is a method of manufacturing a semiconductor chip having a substrate, a conductive portion formed on the substrate, and micro bumps formed on the conductive portion, and a step of forming a smooth surface on the micro bumps The smooth surface forming process includes a heating process in which a reducing gas is introduced into an inert atmosphere in a space in which a semiconductor chip is disposed, and heated to a temperature above the melting point of the micro bump, and in the heating process, pressure is applied on the micro bump. The main surface of the main surface of the pressure applying member that is raised is a flat surface.

The manufacturing method of this semiconductor chip is provided with the smooth surface formation process which forms a smooth surface in a micro bump. In the heating step provided with the smooth surface forming step, a reducing gas is introduced into and heated in an inert atmosphere in a space where the semiconductor chip is disposed. Thereby, the oxide film formed on the surface of the micro bump is reduced and removed. In addition, in the heating step, by heating to a temperature equal to or higher than the melting point of the micro bump, the micro bump melts to have fluidity. Here, in the heating step, a pressure applying member is placed on the micro bump. Therefore, as the micro bump melts and has fluidity, the micro bump is deformed by the pressure of the pressure imparting member. Among the main surfaces of the pressure applying member, the main surface contacting the micro bump is a flat surface. Therefore, the portion of the melted micro bumps pressed by the pressure applying member is formed as a smooth surface according to the shape of the plane of the pressure applying member. When the semiconductor chip and the mating member are joined, bonding can be performed using a smooth surface of the micro bump, so that suitable bonding can be performed.

In the heating step, the pressure applying member is placed on the plurality of micro bumps, and the main surface of the main surface of the pressure applying member contacting the plurality of micro bumps may be a flat surface. As a result, the pressure applying member can apply pressure to the plurality of micro bumps in a state in which the same plane is in contact. In this case, the smooth surfaces of the plurality of micro bumps coincide with the planes of the pressure imparting member and constitute the same planes with each other. Therefore, it is possible to reduce variations in height between smooth surfaces of a plurality of micro bumps.

You may apply carboxylic acid as a reducing gas. Thereby, the oxide film on the micro bump surface can be satisfactorily removed.

By weight of the pressure-application member is may be a single coating, or less 0.0005㎍ / ㎛ ² or more, 0.1㎍ / ㎛ ² of the micro-bump. Thereby, the pressure applying member can apply the appropriate pressure for removing voids to the micro bump.

A spacer having a constant thickness is disposed on the substrate, and the pressure applying member may be pushed in until it contacts the spacer. Thereby, since the pressure imparting member is stopped by the spacer, it is possible to prevent the micro bump from being too crushed.

ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor chip which can bond suitably with a mating member can be provided.

1 is a schematic cross-sectional view showing an embodiment of a semiconductor package.
2 is a flowchart showing a procedure of a method for manufacturing a semiconductor package.
3A and 3B are schematic cross-sectional views showing a shape in which semiconductor chips are stacked.
4A is a schematic cross-sectional view showing a shape in which semiconductor chips are stacked, and FIG. 4B is a schematic cross-sectional view showing a shape in which semiconductor chips are joined together.
5 is a schematic cross-sectional view showing a micro bump before performing a smooth surface forming process and a micro bump after performing a smooth surface forming process.
6 is a flowchart showing the procedure of a smooth surface forming process (void removal process).
7A to 7G are schematic cross-sectional views showing the sequence of a smooth surface forming process (void removal process).
8A to 8G are schematic cross-sectional views showing the sequence of a smooth surface forming process (void removal process) according to a modification.
9 is a graph showing the profile of the temperature and pressure in the furnace.
10A to 10C are schematic cross-sectional views showing the sequence of a smooth surface forming process (void removal process).
11A to 11B are schematic cross-sectional views showing the sequence of a smooth surface forming process (void removal process).
12A and 12B are schematic views showing an arrangement of light emitting elements.
13A to 13C are schematic views showing a procedure for forming micro bumps.
14A to 14C are schematic diagrams showing a procedure of mounting a light emitting element on a semiconductor chip.
15A and 15B are schematic diagrams showing a problem when mounting a light emitting element on a semiconductor chip.
16 is a table showing a combination of a material of a conductive portion and a plating film of a light-emitting element, and a material of a conductive portion and a plating film of a semiconductor chip.
17 is a table showing test results of Examples and Comparative Examples.
18 is a table showing test results of Examples and Comparative Examples.

Hereinafter, preferred embodiments of a method for manufacturing a semiconductor package according to an aspect of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and overlapping descriptions are omitted.

1 is a schematic cross-sectional view showing an embodiment of a semiconductor package. As shown in FIG. 1, the semiconductor package 100 is a laminate 2 formed by stacking three or more (here 3) semiconductor chips 1 and a laminate 2 through solder balls 3. ) And a mold part 6 formed by covering the organic substrate 4 electrically connected with the laminate and the laminate 2 mounted on the organic substrate 4 with mold resin. In addition, the underfill 7 is filled in the inner space of the mold part 6 so as to fill the gap between the semiconductor chips 1 of the laminate 2. In this embodiment, the laminated body 2 is configured by laminating the semiconductor chip 1A, the semiconductor chip 1B, and the semiconductor chip 1C in the vertical direction. The semiconductor chip 1A and the semiconductor chip 1B are joined through a joint 8 joined by melting a micro bump. The semiconductor chip 1C and the semiconductor chip 1B are joined through a joint 8 joined by melting a micro bump.

For example, as shown in FIG. 4A, the semiconductor chip 1 before bonding has a substrate 11, a conductive portion 12 formed on the substrate 11, and a micro bump 13 formed on the conductive portion 12 Have The substrate 11 is made of, for example, a semiconductor chip such as a silicon (Si) chip, a silicon (Si) interposer, or the like. In addition, the conductive portion 12 is formed only on one main surface of the semiconductor chip 1A and the semiconductor chip 1C. On the semiconductor chip 1B, conductive portions 12 are formed on both main surfaces. In addition, the conductive portions 12 formed on both main surfaces of the semiconductor chip 1B are connected to each other through through-hole electrodes 19 extending in the thickness direction of the substrate 11.

Several conductive parts 12 are formed on the main surface of the substrate 11. The conductive portions 12 are arranged on the main surface of the substrate 11 at a predetermined pitch. The conductive portion 12 includes an electrode pad 14 formed on the main surface of the substrate 11 and a barrier metal layer 16 formed on the top surface of the electrode pad 14. Further, a portion of the main surface of the substrate 11 on which the conductive portion 12 is not formed is covered with an insulating layer 17 (see FIG. 5). As a constituent material of the barrier metal layer 16, for example, Ni and Ni compounds (for example, NiP) are used. As a constituent material of the insulating layer 17, SiO, SiN, polyimide, or the like is used, for example.

The micro bump 13 is formed on the barrier metal layer 16 of the conductive portion 12. The micro bump 13 may contain Sn, Ag, Cu, Ag-Cu, Bi, In, etc. as a constituent material, and an alloy of any two or more of these materials may be used. In particular, the micro bump 13 may contain Sn as a main component. The micro bumps 13 may be formed, for example, by a plating method. Alternatively, the micro bumps 13 may be formed by using micro balls made of a brazing alloy, or may be formed by printing a paste. In addition, a bump having a diameter of less than 50 µm when viewed from above is referred to as a micro bump.

As shown in Fig. 5, the micro bump 13 has a spherical surface immediately after being formed on the substrate 11. A predetermined process is performed on the micro bumps 13 to form a smooth surface 13a on the micro bumps 13. The smooth surface 13a is constituted by a plane widening in the horizontal direction at the upper end of the micro bump 13. In addition, an example of the processing content for forming the smooth surface 13a will be described later. The height of the micro bump 13, that is, the dimension between the smooth surface 13a and the upper surface of the conductive portion 12 can be set in a range of 5 to 50 μm.

Next, a method of manufacturing the semiconductor package 100 according to the present embodiment will be described with reference to FIGS. 2 to 9.

As shown in Fig. 2, first, a semiconductor chip preparation process (step S1) in which the semiconductor chip 1 is prepared by forming the micro bumps 13 on the substrate 11 is performed. Thus, semiconductors 1A, 1B, and 1C are prepared. However, in this step, the smooth surface 13a is not formed in the micro bump 13.

Next, a smooth surface forming step (step S2) of forming the smooth surface 13a on the micro bump 13 is performed. In addition, the smooth surface forming step (S2) also corresponds to the void removing step of removing the void 22 from the inside of the micro bump 13.

Here, the details of the smooth surface forming process (void removal process; S2) will be described with reference to FIG. 6.

6 and 7A, a pressure applying member installation process (step S20) for installing the pressure applying member 21 with respect to the micro bump 13 is performed. In this way, with the pressure applying member 21 raised, the semiconductor chip 1 is disposed inside the heating furnace. In the following description, the temperature and pressure profile in the heating furnace shown in Fig. 9 will be described with reference to appropriate. In Fig. 9, the solid line represents the temperature in the heating furnace, and the broken line represents the pressure in the heating furnace.

As shown in FIG. 10A, in the pressure applying member installation process (S20), the pressure applying member 21 may be placed on the plurality of micro bumps 13. At this time, the main surface 21a of the main surface of the pressure applying member 21 that contacts the plurality of micro bumps 13 is flat. That is, the main surface 21a constituting the same plane is in contact with the plurality of micro bumps 13. In addition, a plurality of micro bumps 13 are arranged in the left-right direction and the front-rear direction of the paper in FIG. 10A. Therefore, the pressure imparting member 21 is placed on the micro bumps 13 arranged in a plurality in the left and right directions of the ground and the front and rear directions of the ground. The pressure imparting member 21 may be used for one semiconductor chip 1 or may be used in plural. That is, the pressure imparting member 21 may be raised against all the micro bumps 13 in the semiconductor chip 1. Alternatively, the semiconductor chip 1 may be divided into a plurality of sections, and the pressure applying member 21 may be raised one by one for each section. However, the pressure applying members 21 may be raised one by one with respect to one micro bump 13.

As a constituent material of the pressure imparting member 21 placed on the micro bump 13, it is preferable that a material that does not react with the micro bump 13 is employed. For example, Si, SiO ₂ , SiN, or the like is employed as a constituent material of the pressure imparting member 21. Moreover, among the main surfaces of the pressure imparting member 21, it is preferable that the main surface 21a in contact with the micro bump 13 is configured as a plane. This is because, for example, when a projection or the like is formed on the main surface 21a, it is difficult to escape when the pressure applying member 21 is removed because the micro bump 13 is caught. It is preferable that the pressure applied by the pressure applying member 21 to the micro bump 13 is made only by the own weight of the pressure applying member 21. Specifically, the pressure it is preferred that only the coating 0.0005㎍ / ㎛ ² or more, 0.1㎍ / ㎛ ² or less of the micro-bump. For example, if the pressure or height by the pressure imparting member 21 is controlled by a method such as flip chip mounting, when the micro bump 13 is changed from a solid to a liquid (from FIG. 7B to FIG. 7C). ), Since the pressure applied to the pressure applying member 21 decreases, a shift occurs in the position of the pressure applying member 21. For a small bump such as the micro bump 13, excessive pressure is applied due to slight displacement.

Next, a decompression step (step S21) is performed to depressurize the space of the heating furnace in which the semiconductor chip 1 is disposed. In the decompression step (S21), the inside of the heating furnace is vacuum-treated to obtain a decompression atmosphere. Oxygen remaining in the heating furnace causes oxidation of the micro bumps 13. Therefore, it is preferable to exhaust the inside of the heating furnace to a depressurized state in an atmospheric pressure state (1.01 x 10 ^ 5 Pa to 1 x 10 ^ 3 Pa or less, particularly 5 Pa or less). Thereby, the pressure in the heating furnace decreases (refer to the graph P1 portion in FIG. 9). An inert gas is introduced into the heating furnace in such a reduced pressure atmosphere. Thereby, the pressure in the heating furnace rises (refer to the portion of graph P2 in FIG. 9). The inert gas realizes melting of the micro bump 13 while further preventing oxidation of the surface of the micro bump 13 when the inside of the heating furnace is raised to a temperature range above the melting temperature of the micro bump 13 (above the melting point). It functions as a heat medium in a heating furnace. As such an inert gas, nitrogen (N ₂ ) gas, argon (Ar) gas, or the like can be used, for example.

Next, a heating process (step S22) is performed in which a reducing gas is introduced into the inert atmosphere to the heating furnace and heated to a temperature equal to or higher than the melting point of the micro bump 13. The heating step S22 is performed after introducing an inert gas into the heating furnace, or almost simultaneously with the introduction of the inert gas. In the heating step (S22), the temperature in the heating furnace is raised at a predetermined heating rate (for example, 35 to 45 ° C / min), and the temperature in the heating furnace in the state where the inert gas is introduced is equal to or higher than the melting point of the micro bump 13 Raise to the area. For example, when the bump is composed of an Sn-Ag-Cu alloy, the melting point varies depending on the composition of the alloy, but since it is approximately 220 to 230 ° C, the temperature in the heating furnace is raised to a temperature range above that temperature.

It is preferable that introduction of the reducing gas is performed before or after the temperature at which the reduction reaction of the oxide film 23 starts. While maintaining the temperature in the furnace (temperature T1 in FIG. 9) above the temperature at which the reduction reaction starts, a reducing gas having a suitable concentration and flow rate is continuously supplied. Thereby, the oxide film 23 existing on the surface of the micro bump 13 can be reduced and removed. As the reducing gas, for example, carboxylic acid (formic acid) is applied. Examples of the carboxylic acid include lower carboxylic acids such as formic acid, acetic acid, acrylic acid and propionic acid. When using formic acid as a reducing gas, it is preferable to introduce formic acid when the temperature in the heating furnace reaches about 110 ° C. Even if formic acid is introduced below the temperature at which the reduction reaction starts, the reaction does not proceed, and if the temperature is too high, the pressure inside the void 22 is increased because the micro bump 13 is heated while leaving the oxide layer 23 on the surface. Rises. When the oxide film 23 is removed while the internal pressure of the void 22 is excessively increased, the pressure of the void 22 is immediately released, and there is a possibility that the liquefied micro bump 13 is scattered. . Therefore, the temperature may be maintained at a temperature T1 at which the reduction reaction begins, and the temperature of the heating furnace may be maintained at a temperature T2 above the melting point of the micro bump 13 in a step where the oxide film 23 is sufficiently removed. (See Figure 9).

When the micro bump 13 is melted, the voids 22 are removed, and the smooth surface 13a is formed, a temperature-lowering step (step S23) of lowering the temperature of the heating furnace is performed. Specifically, in the heating furnace maintained at a temperature T2 above the melting temperature of the micro bump 13, the micro bump 13 is exposed to formic acid for a predetermined time (for example, 0.5 to 3 minutes), followed by a heating furnace. The formic acid introduced therein is evacuated by vacuum treatment. After evacuating formic acid in the heating furnace, or almost simultaneously with evacuation of formic acid, the inside of the heating furnace is cooled at a predetermined temperature drop rate (for example, -5 to -40 ° C / min). In addition, in FIG. 9, vacuum processing is performed before the temperature of the heating furnace goes down. However, where the temperature in the heating furnace is lowered to a temperature range where the molten bump solidifies to some extent, an inert gas such as nitrogen gas or argon gas may be introduced into the heating furnace to return to atmospheric pressure.

As shown in FIGS. 7B to 7G, the void 22 is removed from the micro bump 13 at the same time as the heating process (S22) and the cooling process (S23) are performed as described above. The smooth surface 13a is formed. That is, by heating in an atmosphere of a reducing gas, the oxide film 23 formed on the surface of the micro bump 13 is reduced and removed (see Fig. 7B). Then, the micro bump 13 is melted by heating to a temperature equal to or higher than the melting point of the micro bump 13. Thereby, the micro bump 13 is deformed to be crushed by the pressure of the pressure imparting member 21. Thereby, according to the shape of the main surface 21a of the pressure applying member 21, a shape corresponding to the smooth surface 13a is formed in the micro bump 13 (see FIGS. 7C to 7F). Further, the molten micro bump 13 is pressed against the pressure applying member 21 and flows, so that the void 22 in the micro bump 13 rises and falls out (see FIGS. 7C to 7F). As the temperature of the heating furnace returns, the micro bump 13 is cooled and hardened. Thereby, the smooth surface 13a is formed in the micro bump 13 (refer FIG. 7G).

As shown in FIG. 10, in the heating step (S22), the pressure applying member 21 is put on the plurality of micro bumps 13. As shown in Fig. 10B, the pressure imparting member 21 applies pressure to the plurality of micro bumps 13 in the same state in contact with the same plane. Thereby, the several micro bumps 13 are deformed so that the pressure imparting member 21 is collectively crushed. Thereby, according to the shape of the main surface 21a of the pressure applying member 21, a shape corresponding to the smooth surface 13a is formed in the plurality of micro bumps 13. As the temperature of the heating furnace returns, the micro bump 13 is cooled and hardened. Thereby, the smooth surface 13a is formed in the several micro bumps 13. Thereafter, as shown in Fig. 10C, the pressure applying member 21 is removed from the plurality of micro bumps 13.

2, after the smooth surface forming process (S2) for each semiconductor chip 1 is completed, the micro bumps 13 of one semiconductor chip 1 and the micro bumps of the other semiconductor chip 1 ( By stacking 13), a lamination process (step S3) of laminating three or more semiconductor chips 1 is performed. In this embodiment, in the lamination step (S3), a smooth surface 13a is formed on the micro bump 13 of one semiconductor chip 1 and the other semiconductor chip 1. Then, the micro bump 13 of one semiconductor chip 1 is in contact with the other micro bump 13 on the smooth surface 13a. In the lamination step (S3), the micro bumps 13 of each other are superimposed on all the semiconductor chips 1 in a state in which they are not joined.

Specifically, as shown in FIGS. 3A and 3B, the micro bump 13 of the semiconductor chip 1B is superimposed on the micro bump 13 of the lowermost semiconductor chip 1C. At this time, the smooth surface 13a of the micro bump 13 of the semiconductor chip 1B is raised on the smooth surface 13a of the micro bump 13 of the semiconductor chip 1C. Further, the micro bumps 13 of the semiconductor chip 1C and the micro bumps 13 of the semiconductor chip 1B are not bonded to each other, but are only in contact.

Next, as shown in FIGS. 3B and 4A, the micro bump 13 of the uppermost semiconductor chip 1C is superimposed on the micro bump 13 of the second semiconductor chip 1B from the bottom. At this time, the smooth surface 13a of the micro bump 13 of the semiconductor chip 1C is raised on the smooth surface 13a of the micro bump 13 of the semiconductor chip 1B. In addition, the micro bump 13 of the semiconductor chip 1B and the micro bump 13 of the semiconductor chip 1C are not bonded to each other, but are only in contact.

After the lamination process (S3) is completed, by heating and melting the micro bumps 13, a bonding process (step S4) in which the semiconductor chips 1 are joined to each other through the micro bumps 13 is performed. In the bonding step (S4), all the micro bumps 13 are melted in one batch by heating, and all the semiconductor chips 1 are joined in a batch. Further, in the bonding step (S4), the micro bumps 13 of each semiconductor chip 1 are melted in a reducing atmosphere.

Specifically, as shown in FIG. 4A, a stacked body in which semiconductor chips 1A, 1B, and 1C are stacked through the micro bumps 13 is placed in a heating furnace. Then, by heating the laminate in a heating furnace, all the micro bumps 13 in the laminate are melted, and the micro bumps 13 that are in contact with each other are bonded together. Thereby, as shown in FIG. 4B, the semiconductor chips 1A, 1B, and 1C are joined through a junction portion 8 in which two micro bumps 13 are melted and joined to each other.

After the bonding process S4 is completed, a semiconductor package creation process (step S5) for creating the semiconductor package 100 is performed. In the semiconductor package preparation step (S5), the laminate 2 obtained in the bonding step (S5) is connected to the organic substrate 4, and at the same time, the laminate 2 is covered with the mold part 6. With the above, the semiconductor package 100 is completed, and the manufacturing method shown in FIG. 2 ends.

Next, the operation and effects of the manufacturing method of the semiconductor package 100 according to the present embodiment will be described.

The method of manufacturing the semiconductor chip 1 includes a smooth surface forming step (S2) of forming the smooth surface 13a on the micro bump 13. In the heating step S22 provided with the smooth surface forming step S2, a reducing gas is introduced into the space in which the semiconductor chip 1 is disposed in an inert atmosphere and heated. Thereby, the oxide film 23 formed on the surface of the micro bump 13 is reduced and removed. In addition, in the heating step (S22), by heating to a temperature above the melting point of the micro bump 13, the micro bump 13 melts to have fluidity. Here, in the heating step (S22), the pressure applying member 21 is placed on the micro bump 13. Therefore, as the micro bump 13 melts and has fluidity, the micro bump 13 is deformed to be crushed by the pressure of the pressure applying member 21. Of the main surfaces 21a of the pressure applying member 21, the main surface 21a in contact with the micro bump 13 is flat. Therefore, the portion pressed by the pressure applying member 21 among the melted micro bumps 13 is formed as a smooth surface 13a according to the shape of the plane of the pressure applying member 21. When the semiconductor chip 1 and the mating member are joined, it is possible to perform bonding by using the smooth surface 13a of the micro bump 13, so that bonding can be performed.

In the heating step (S22), the pressure applying member 21 is placed on the plurality of micro bumps 13, and the main surface 21a of the main surface of the pressure applying member 21 contacting the plurality of micro bumps 13 is flat. As a result, the pressure applying member 21 can apply pressure to the plurality of micro bumps 13 in a state in which the same plane is in contact. In this case, the smooth surfaces 13a of the plurality of micro bumps 13 coincide with the planes of the pressure imparting member 21 and form the same planes with each other. Therefore, it is possible to reduce variations in height between the smooth surfaces 13a of the plurality of micro bumps 13.

When the smooth surface 13a is formed by polishing, there is a possibility that damage is caused by a force acting on the micro bump 13 and the conductive portion 12. On the other hand, when the smooth surface 13a is formed using the pressure imparting member 21 as in the above-described embodiment, damage to the micro bump 13 and the conductive portion 12 can be suppressed.

In the manufacturing method of the semiconductor package 100, in the heating step (S22), a reducing gas is introduced into and heated in an inert atmosphere with respect to the space where the semiconductor chip 1 is disposed. Thereby, the oxide film 23 formed on the surface of the micro bump 13 is reduced and removed. In addition, by heating to a temperature equal to or higher than the melting point of the micro bump 13, the micro bump 13 melts to have fluidity. Here, in the heating step (S22), the pressure applying member 21 is placed on the micro bump 13. Therefore, as the micro bump 13 melts and has fluidity, the micro bump 13 is deformed to be crushed by the pressure of the pressure applying member 21. The deformation generates a flow in the micro bump 13, and the void 22 flows in the micro bump 13. Thereby, the voids 22 flowing in the micro bumps 13 are removed from the micro bumps 13 outside. By the above, the void 22 in the micro bump 13 can be easily removed.

You may apply carboxylic acid as a reducing gas. Thereby, the oxide film 23 on the surface of the micro bump 13 can be satisfactorily removed.

By weight of the pressure application member 21 may be a single coating, or less 0.0005㎍ / ㎛ ² or more, 0.1㎍ / ㎛ ² of the micro-bump 13. The Thereby, the pressure applying member 21 can apply the appropriate pressure for removing the voids 22 to the micro bumps 13.

In the manufacturing method of the semiconductor package 100, in the lamination step (S3), a smooth surface 13a is formed on at least one micro bump 13 of one semiconductor chip 1 and the other semiconductor chip 1, , One micro bump 13 is in contact with the other micro bump 13 on the smooth surface 13a. Thus, one semiconductor chip 1 and the other semiconductor chip 1 can be stacked with high positional accuracy by wrapping each other's micro bumps 13 using the smooth surface 13a. Thereby, even in the case of stacking a plurality of semiconductor chips 1 with three or more sheets, it can be stacked in a state where the positional accuracy between the semiconductor chips 1 of each other is good. By performing the bonding process (S4) in such a state, the semiconductor chip 1 and the semiconductor chip 1 can be joined with high positional accuracy.

In the lamination process (S3), all of the semiconductor chips (1) are stacked in a state where the micro bumps (13) of each other are not bonded, and in the bonding process (S4), all the micro bumps (13) are heated by one heating. ) May be melted in a batch, and all the semiconductor chips 1 may be bonded in a batch. Thereby, it can be prevented that the micro bump 13 is melted and the joined joint 8 is repeatedly heated. Therefore, it is possible to prevent the strength of the bonding portion 8 from lowering.

The micro bumps 13 of one semiconductor chip 1 and the micro bumps 13 of the other semiconductor chip 1 all contain Sn, and in the bonding process S4, one semiconductor chip 1 in a reducing atmosphere. ), The micro bumps 13 and the micro bumps 13 of other semiconductor chips 1 may be melted. Thereby, the oxide films 23 formed on the surfaces of the micro bumps 13 of each other are reduced and removed. In addition, since the micro bumps 13 of each other contain Sn, they are mixed and integrated with each other according to melting. Accordingly, the positional displacement between one semiconductor chip 1 and the other semiconductor chip 1 is corrected by the action of the surface tension of the liquefied micro bump 13 (self-alignment effect).

The present invention is not limited to the above-described embodiment.

For example, as shown in FIG. 8, a spacer 26 having a constant thickness is disposed on the substrate 11, and the pressure applying member 21 may be pushed in until it contacts the spacer 26. Thereby, since the pressure imparting member 21 is stopped by the spacer 26, it is possible to prevent the micro bump 13 from being too crushed. For example, before heating, spacers 26 are arranged on both sides of the micro bump 13, and the pressure applying member 21 is raised on the micro bump 13 (see FIG. 8A). In this state, the oxide film is removed by heating in a reducing atmosphere (see Fig. 8B). Then, when the micro bump 13 is melted, the pressure imparting member 21 descends and comes into contact with the upper surface of the spacer 26 (see Fig. 8C). Thereby, the pressure imparting member 21 is supported by the spacer 26 and does not go down any more. On the other hand, in the melted micro bump 13, a flow occurs under the influence of the pressure imparting member 21, and the void 22 is raised and removed (see FIGS. 8D to 8G).

As shown in Fig. 11A, when the pressure applying member 21 is placed on the plurality of micro bumps 13, the spacer 26 may be disposed only at a position corresponding to the edge portion of the pressure applying member 21. Alternatively, as shown in FIG. 11B, spacers 26 may be disposed in the gaps between the respective micro bumps 13. Further, as shown in Fig. 11B, even if the spacers 26 are not disposed in all the gaps, the spacers 26 may be disposed in some gaps.

Further, in the above-described embodiment, the micro bump 13 of the lower semiconductor chip 1 has a smooth surface 13a, and the micro bump 13 of the upper semiconductor chip 1 has a smooth surface 13a. Had. Therefore, the smooth surface 13a of the micro bump 13 on the upper side was raised on the smooth surface 13a of the lower micro bump 13. However, the smooth surface 13a may be formed on only one of the micro bump 13 on the upper side and the micro bump 13 on the lower side, and the smooth surface 13a may not be formed on the other side.

In the above-described embodiment, the mating member for joining the semiconductor chips was another semiconductor chip. Instead of this, other members may be employed as mating mating members. For example, electronic components may be employed as mating mating members. A light emitting element may be employed as an electronic component.

By bonding a plurality of light-emitting elements to a semiconductor chip, components of an LED display can be configured. For example, with respect to a method of controlling the light of a backlight with a transmissive liquid crystal, such as an LCD (liquid crystal display), an LED (light emitting element display) comprises pixels with light emitting elements that are natural light emitting elements. Thus, the LED display has characteristics such as high brightness, high lifespan, and high viewing angle. In order to increase the number of pixels in such an LED display, the light emitting element itself may be made small. When mounting light emitting elements on a semiconductor chip, a method of mounting light emitting elements one by one has been adopted. However, in the above method, as the light emitting element is made smaller, the lead time of mounting increases. For this reason, a method of mounting the light-emitting elements collectively has been studied.

Specifically, as shown in FIG. 12, the plurality of light emitting elements 50 are fixed in a desired arrangement on the upper surface of the fixing jig 51. A red light-emitting element 50A, a green light-emitting element 50B, and a blue light-emitting element 50C are fixed to the fixing jig 51 in a predetermined arrangement pattern. The light emitting element 50 includes a conductive portion 53 and a plating film 52 formed on the conductive portion 53. The fixing jig 51 is made of, for example, a glass plate or the like provided with a UV release sheet on the fixing surface. Thereby, after mounting the light emitting element 50 on a semiconductor chip, the light emitting element can be peeled from the fixed jig 51 by irradiating UV to the fixed jig 51.

It is difficult to print a conventional solder paste when mounting a fine light emitting element of several tens of µm. Therefore, a method of forming a plating on a conductive portion of a semiconductor chip by a plating method and bonding the semiconductor chip and a light emitting element through the plating is adopted. Specifically, as shown in FIG. 13A, a semiconductor chip 60 in which the conductive portion 62 is formed on the substrate 61 is prepared. Next, as shown in FIG. 13B, a plating film 63 is formed on the conductive portion 62. Thereafter, the semiconductor chip 60 is heated in a reducing atmosphere to melt the plated film 63. Thereby, as shown in FIG. 13C, a plurality of micro bumps 64 as a bonding electrode are formed.

Here, as shown in Fig. 15A, there are variations in the thickness of the plurality of micro bumps 64. When the light emitting elements 50 are collectively mounted on the micro bumps 64, as shown in FIG. 15B, some light emitting elements 50 are bonded to the thick micro bumps 64, while being thick. A light emitting element 50 that is not bonded to the thin micro bump 64 is generated.

On the other hand, the manufacturing method of the semiconductor chip 60 is provided with the smooth surface formation process of the same effect as the manufacturing method of the semiconductor chip 1 mentioned above. In the heating step provided with the smooth surface forming step, a reducing gas is introduced into the space in which the semiconductor chip 60 is disposed in an inert atmosphere to heat it. Thereby, the oxide film formed on the surface of the micro bump 64 is reduced and removed. Further, in the heating step, by heating to a temperature equal to or higher than the melting point of the micro bump 64, the micro bump 64 is melted to have fluidity. Here, in the heating step, as shown in FIG. 14A, the pressure applying member 70 is placed on the micro bump 64. Therefore, as the micro bump 64 melts and has fluidity, the micro bump 64 is deformed to be crushed by the pressure of the pressure applying member 70. Of the main surfaces of the pressure applying member 70, the main surface 70a contacting the micro bump 64 is a flat surface. Therefore, the portion of the micro bump 64 that has been pressed by the pressure applying member 70 is formed as a smooth surface 64a according to the shape of the plane of the pressure applying member 70. 14B and 14C, when the semiconductor chip 60 and the light emitting element 50 are collectively bonded, since the smooth surface 64a of the micro bump 64 can be used for bonding, Suitable bonding can be performed.

In addition, in the heating step, the pressure applying member 70 is placed on the plurality of micro bumps 64, and the main surface 70a of the main surface of the pressure applying member 70 in contact with the plurality of micro bumps 64 is flat. As a result, the pressure applying member 70 can apply pressure to the plurality of micro bumps 64 in a state in which the same plane is in contact. In this case, the smooth surfaces 64a of the plurality of micro bumps 64 coincide with the planes of the pressure imparting member 70 and form the same planes with each other. Therefore, variations in height between the smooth surfaces 64a of the plurality of micro bumps 64 can be reduced. Thus, as shown in FIG. 14C, when the plurality of light emitting elements 50 are joined to the semiconductor chip 60 in a batch, it is possible to prevent unconnected micro bumps 64 from occurring in the light emitting elements 50. Can be. Further, the micro bump 64 is melted by heating in a reducing atmosphere. Thereby, the smooth surface of the micro bump 64 can be formed at low cost.

16 is a table showing a combination of the material of the conductive portion 53 and the plating film 52 of the light-emitting element 50 and the material of the conductive portion 62 and the plating film 63 of the semiconductor chip 60. . "○" was displayed when good connectivity was obtained. As shown in FIG. 16, when Sn is contained in the plating film 52 of the light emitting element 50, the plating film 63 of the semiconductor chip 60 is the light emitting element 50 and the semiconductor regardless of the material. The connectivity of the chip 60 can be improved. In addition, when Sn is contained in the plating film 63 of the semiconductor chip 60, the plating film 52 of the light emitting element 50 is irrespective of the material of the light emitting element 50 and the semiconductor chip 60. Connectivity can be improved.

[Example]

Next, examples of the present invention will be described. However, the present invention is not limited to the following examples.

(Examples 1 to 7)

As Example 1, a semiconductor chip having the following micro bumps was manufactured. First, Cu plating, Ni plating, and Sn plating were performed on the substrate by electrolytic plating. After placing this in a heating furnace, the atmospheric pressure in the heating furnace was adjusted, and the concentration and flow rate of nitrogen or formic acid gas supplied to the heating furnace were adjusted. Thus, a sample of a semiconductor chip in which a micro bump was formed by melting a plated film was prepared. The height of the Cu plating layer was 17 μm, the height of the Ni plating layer was 3 μm, the height of the micro bumps was 15 μm, and the diameter of the micro bumps was 35 μm. When this sample was observed with transmission X-rays, voids were observed in the micro bumps. This sample and a pressure applying member were prepared. The pressure imparting member was a Si wafer having an SiO ₂ film. The Si wafer was placed on the micro bump with the SiO ₂ side in contact with the bump. The weight of the pressure imparting member was 0.0005 µg / µm ² per cross-sectional area of the micro bumps. In addition, a spacer as shown in Fig. 8 was not provided. After the semiconductor chip in the state where the pressure applying member was raised was placed in the heating furnace, the inside of the heating furnace was vacuum treated to 5 Pa or less. The atmospheric pressure in the subsequent heating furnace was adjusted, and the concentration and flow rate of nitrogen and formic acid gas supplied to the heating furnace were adjusted. Specifically, heating was performed under the conditions of a heating rate of 45 ° C / min, preheating of 195 ° C (6 minutes), and a maximum of 260 ° C (1 minute). The micro bump was pressurized to the pressure applying member to form a smooth surface. In this way, a micro bump according to Example 1 was obtained.

The micro bump formed using the pressure imparting member of 0.002 µg / µm ² per cross-sectional area of the micro bump was used as Example 2. The micro bump formed using the pressure imparting member of 0.003 µg / µm ² per cross-sectional area of the micro bump was used as Example 3. A micro bump formed using a pressure imparting member of 0.01 µg / µm ² per cross-sectional area of the micro bump was used as Example 4. A micro bump formed using a pressure imparting member of 0.03 µg / µm ² per cross-sectional area of the micro bump was used as Example 5. A micro bump formed using a pressure applying member of 0.06 μg / µm ² per cross-sectional area of the micro bump was used as Example 6. All other conditions of Examples 2 to 6 were the same as in Example 1. Further, a micro bump formed by inserting a 30 µm SUS316 spacer between the pressure applying member and the substrate was used as Example 7. In Example 7, a pressure applying member of 0.03 µg / µm ² per cross-sectional area of the micro bump was used. All other conditions of Example 7 were the same as in Example 1.

(Comparative Examples 1 to 7)

The micro bumps according to Comparative Examples 1 to 7 were formed by heating in the air. In Comparative Example 1, a pressure imparting member of 0.001 μg / µm ² per cross-sectional area of the micro bump was used. In Comparative Example 2, a pressure imparting member having a pressure of 0.002 μg / µm ² per cross-sectional area of the micro bump was used. In Comparative Example 3, a pressure imparting member having a pressure of 0.003 μg / µm ² per cross-sectional area of the micro bump was used. In Comparative Example 4, a pressure imparting member of 0.010 µg / µm ² per cross-sectional area of the micro bump was used. In Comparative Example 5, a pressure applying member of 0.03 µg / µm ² per cross-sectional area of the micro bump was used. In Comparative Example 6, a pressure imparting member having a micro bump of 0.06 g / µm ² per cross-sectional area was used. In Comparative Example 7, a pressure imparting member of 0.10 µg / µm ² per cross-sectional area of the micro bump was used. All other conditions of Comparative Examples 1 to 7 were the same as in Example 1.

(evaluation)

The height of the micro bumps of each example and each comparative example is shown in "micro bump height (mu m)" in FIG. In addition, in each of the Examples and Comparative Examples, “○” was indicated in “Void” in FIG. 10 for the decrease in voids after reflow, and “X” was indicated for the void not decreased. In each of the Examples and Comparative Examples, the pressure imparting member was removed from the micro bumps after the reflow, and when the micro bumps were not collapsed, “○” was indicated in “Fall of Electrodes” in FIG. 10 and the micro bumps were collapsed. "X" was indicated for this.

As shown in Fig. 17, in Examples 1 to 6, the effect of void reduction was confirmed, and there was no collapse of the micro bumps. However, in Example 6, since molten Sn flows into the electrode pad, it was set to "Δ". In Example 7, since the height of the bump is the same as the thickness of the spacer by inserting the spacer, there was an effect of preventing excessive push-in. Therefore, it was confirmed that Example 7 prevented the molten Sn from flowing to the electrode pad as compared with Example 6. On the other hand, it was confirmed that in Comparative Examples 1 to 6, the effect of void reduction could not be obtained. This was presumed to be due to the fact that the micro bumps are hardly deformed by the influence of the formed oxide film on the surface of the micro bumps, and that the rigid oxide film on the surface inhibits the fluidity of the interior. In addition, in Comparative Example 7, it was confirmed that the micro bump collapsed because the weight of the pressure imparting member was excessive.

(Examples 8 to 11)

As Example 8, a semiconductor chip having the following micro bumps was manufactured. First, Cu plating, Ni plating, and Sn plating were performed on the substrate by electrolytic plating. After placing this in a heating furnace, the atmospheric pressure in the heating furnace was adjusted, and the concentration and flow rate of nitrogen or formic acid gas supplied to the heating furnace were adjusted. Thus, a sample of a semiconductor chip in which a micro bump was formed by melting a plated film was prepared. The height of the Cu plating layer was 17 μm, the height of the Ni plating layer was 3 μm, the height of the micro bumps was 15 μm, and the diameter of the micro bumps was 35 μm. This sample and a pressure applying member were prepared. The pressure imparting member was a Si wafer having an SiO ₂ film. The Si wafer was placed on the micro bump so that the SiO ₂ side was in contact with the bump. The weight of the pressure imparting member was 0.0005 µg / µm ² per cross-sectional area of the micro bumps. In addition, a spacer as shown in Fig. 8 was not provided. After the semiconductor chip in the state where the pressure applying member was raised was placed in the heating furnace, the inside of the heating furnace was vacuum treated to 5 Pa or less. The atmospheric pressure in the subsequent heating furnace was adjusted, and the concentration and flow rate of nitrogen and formic acid gas supplied to the heating furnace were adjusted. Specifically, heating was performed under the conditions of a heating rate of 45 ° C / min, preheating of 195 ° C (6 minutes), and a maximum of 260 ° C (1 minute). The micro bump was pressurized to the pressure applying member to form a smooth surface. A semiconductor chip having such a micro bump was prepared, and three semiconductor chips were stacked and bonded to each other. In addition, the number of reflows at the time of joining was performed once, and the reflow was performed in the air. The layered product of the semiconductor chip thus obtained was referred to as Example 1.

When the semiconductor chips were joined together, Example 9 was obtained by reflowing in an atmosphere of nitrogen and formic acid. The number of stacked semiconductor chips was set to 5, and Example 10 was used. The number of stacked semiconductor chips was set to 5, and Example 11 was performed when reflowing was performed in an atmosphere of nitrogen and formic acid when bonding the semiconductor chips. All other conditions of Examples 9 to 11 were the same as in Example 1.

(Comparative Examples 8 and 9)

A micro bump having no smooth surface formed thereon was used as Comparative Example 8. The number of stacked semiconductor chips was set to 5, and a micro bump having no smooth surface was formed as Comparative Example 9. All other conditions of Comparative Examples 8 and 9 were the same as in Example 8.

(evaluation)

In order to evaluate the mounting accuracy of the micro bumps, the positional displacement of the centers of the micro bumps of the first and second semiconductor chips was measured when the third semiconductor chip was stacked. In Examples 8 to 11 and Comparative Examples 8 and 9, "○" was displayed for "stacking accuracy" in FIG. 18, and "x" was displayed for 5 µm or more for a position shift of less than 5 µm. In order to measure the peel mode of the micro bumps, the substrate after bonding and the substrate were removed. In Examples 8 to 11 and Comparative Examples 8 and 9, for those broken inside the micro bump, "○" was indicated in "Bump Peeling Mode" in FIG. 18, and peeling was performed at the interface between the micro bump and the Ni plating layer, or "X" was indicated for cracks. In order to evaluate the bonding precision, the displacement of the center of the micro bump after melt bonding was measured. In Examples 8 to 11 and Comparative Examples 8 and 9, for deviations of less than 5 μm, “○” was indicated for “joint precision” in FIG. 18, and “△” was indicated for 5 μm or more and 10 μm or less. , For larger than 10 μm, “×” was indicated.

In Comparative Example 8, when the third chip was stacked, the following chips were shifted. That is, in Comparative Example 8, it was confirmed that the lamination accuracy was low, and the joining accuracy was also lowered for this reason. In Comparative Example 9, the lamination accuracy and the bonding accuracy were also improved by bonding one sheet at a time. However, in Comparative Example 9, it was confirmed that the alloy layer of Ni and Sn grew by repeating the reflow, and the strength of the joint decreased. In Example 8, it was confirmed that since the micro bumps have a smooth surface, there is little misalignment at the time of enveloping, and the bonding precision is also increased. In Example 9, the oxide film was removed by reflowing in a reducing atmosphere, and the bonding precision was further improved by the effect of self-alignment due to the surface tension of the molten Sn. In Examples 10 and 11, since the number of reflows was performed once, it was confirmed that there was little decrease in strength of the joint.

One… Semiconductor chip, 2 ... Laminate, 11 ... Substrate, 12 ... Challenge Department, 13… Micro bump, 13a… Smooth surface, 21… Pressure imparting member, 22 ... Boyd, 23 ... Oxide film, 26 ... Spacer.

Claims (5)

A method of manufacturing a semiconductor chip having a substrate, a conductive portion formed on the substrate, and a micro bump formed on the conductive portion,
It has a smooth surface forming process for forming a smooth surface on the micro bump,
The smooth surface forming process includes a heating process in which a reducing gas is introduced into an inert atmosphere in a space in which the semiconductor chip is disposed, and heated to a temperature equal to or higher than the melting point of the micro bump,
In the heating step, a pressure applying member is placed on the micro bump,
After the heating process, the pressure applying member is removed on the micro bump,
A method of manufacturing a semiconductor chip, wherein a main surface of the main surface of the pressure applying member that contacts the micro bump is a flat surface. According to claim 1,
In the heating step, a pressure applying member is placed on the plurality of micro bumps,
A method of manufacturing a semiconductor chip, wherein a main surface of the main surface of the pressure applying member that comes into contact with a plurality of micro bumps is a flat surface. The method of claim 1 or 2,
A method for manufacturing a semiconductor chip, in which carboxylic acid is applied as the reducing gas. The method of claim 1 or 2,
By weight of the pressure application member is a method for producing a single coating, 0.0005㎍ / ㎛ ² or more, 0.1㎍ / ㎛ ² or less, the semiconductor chip of the micro-bump. The method of claim 1 or 2,
A method of manufacturing a semiconductor chip, wherein a spacer having a constant thickness is disposed on the substrate, and the pressure applying member is pushed until it contacts the spacer.

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