JP4709563B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4709563B2
JP4709563B2 JP2005100331A JP2005100331A JP4709563B2 JP 4709563 B2 JP4709563 B2 JP 4709563B2 JP 2005100331 A JP2005100331 A JP 2005100331A JP 2005100331 A JP2005100331 A JP 2005100331A JP 4709563 B2 JP4709563 B2 JP 4709563B2
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substrate
manufacturing
semiconductor device
connection electrode
terminal
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JP2006286666A (en
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一生 下川
泰造 冨岡
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Description

本発明は、半導体素子を基板にはんだ付け接合する半導体装置の製造方法に関し、特に表面粗さの厚い基板に良好に接合できるものに関する。   The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is soldered and bonded to a substrate, and more particularly to a method capable of satisfactorily bonding to a substrate having a large surface roughness.

近年、窒化ガリウム(GaN)系化合物半導体に関するプロセス技術の進展と、蛍光体に関する技術の進展とにより、半導体発光素子(以下、「LED:Light Emitting Diode」とする。)の応用分野は飛躍的に拡大している。   In recent years, the application field of semiconductor light-emitting devices (hereinafter referred to as “LED: Light Emitting Diode”) has dramatically increased due to progress in process technology related to gallium nitride (GaN) -based compound semiconductors and technology related to phosphors. It is expanding.

特に、紫外光から可視光までの波長帯の光を放射できるLEDと適正な蛍光体とを組み合わせた半導体発光装置は、演色性に優れた白色光が得られるため、液晶ディスプレイのバックライト、ボタン照明、自動車の各種照明等への応用が益々増加している。また、懐中電灯やカメラのフラッシュ等の光源として用いる高出力型の半導体発光装置の開発も進められている。   In particular, semiconductor light-emitting devices that combine LEDs that can emit light in the wavelength band from ultraviolet light to visible light and appropriate phosphors can produce white light with excellent color rendering, so backlights and buttons for liquid crystal displays Applications to lighting and various lighting of automobiles are increasing. In addition, development of high-power semiconductor light-emitting devices used as light sources for flashlights and camera flashes is also underway.

ところで近年、図22に示すような、複数のLEDチップを1つのパッケージ内に実装した新規パッケージが製品化された。このパッケージは、セラミック基板100上に、複数のチップ200をダイマウントしたものである。   In recent years, a new package in which a plurality of LED chips are mounted in one package as shown in FIG. 22 has been commercialized. In this package, a plurality of chips 200 are die mounted on a ceramic substrate 100.

セラミック基板100にジャンクションダウン構造のLEDチップ200をダイマウントする場合、図23に示すように、セラミック基板100の電極表面101がRzで3〜7μm前後と粗いため、従来から使用されている2〜3μmの厚さのはんだ膜102(例えば、特許文献1参照。)では、セラミック基板100の電極表面101の粗さを吸収することができず、接合不良が発生することがある。   When the LED chip 200 having a junction down structure is die-mounted on the ceramic substrate 100, as shown in FIG. 23, the electrode surface 101 of the ceramic substrate 100 has a rough Rz of about 3 to 7 μm. The solder film 102 having a thickness of 3 μm (see, for example, Patent Document 1) cannot absorb the roughness of the electrode surface 101 of the ceramic substrate 100 and may cause poor bonding.

この問題を解決するためには、はんだ膜102の厚さをセラミック基板100の電極表面101の粗さと同程度にする方法が考えられる。しかしながら、セラミック基板100の表面粗さにもばらつきがあるため、ばらつきの小さい電極表面101にLEDチップ200をダイマウントした場合に、溶融したはんだがLEDチップの側面にはみ出し、LEDチップ200の側壁と接触するという問題がある。
特開2003−234482号公報
In order to solve this problem, a method is conceivable in which the thickness of the solder film 102 is made approximately the same as the roughness of the electrode surface 101 of the ceramic substrate 100. However, since the surface roughness of the ceramic substrate 100 also varies, when the LED chip 200 is die-mounted on the electrode surface 101 with a small variation, the molten solder protrudes to the side surface of the LED chip, and the side wall of the LED chip 200 There is a problem of contact.
JP 2003-234482 A

上述した半導体装置の製造方法では、次のような問題があった。すなわち、上述のようなセラミック基板100上にジャンクションダウン構造のLEDチップ200をダイマウントする場合、セラミック基板100の電極表面101がRz3〜7μm前後と粗いため、2〜3μm厚さのはんだ膜102をそのまま載せただけでは、図24に示すように、粗さを緩和できず、隙間が残る。このため、この部分から気泡111が発生しやすい。固化したはんだ材中に気泡111が残ると、発熱したLEDチップ200から熱をセラミック基板100側に逃がしにくいという問題があった。また、はんだにクラックが入ると、気泡の部分はクラックが発展しやすく、接続抵抗が増大する等、信頼性の点で問題があった。   The above-described semiconductor device manufacturing method has the following problems. That is, when the LED chip 200 having the junction down structure is die-mounted on the ceramic substrate 100 as described above, the electrode surface 101 of the ceramic substrate 100 is as rough as Rz 3 to 7 μm, so that the solder film 102 having a thickness of 2 to 3 μm is formed. If it is placed as it is, as shown in FIG. 24, the roughness cannot be reduced and a gap remains. For this reason, bubbles 111 are likely to be generated from this portion. If bubbles 111 remain in the solidified solder material, there is a problem that heat is not easily released from the heated LED chip 200 to the ceramic substrate 100 side. In addition, when cracks occur in the solder, there are problems in terms of reliability, such as the cracks tend to develop in the bubbles and the connection resistance increases.

この問題を解決するためには、はんだ膜の厚さを電極表面の粗さと同程度にする方法があるが、蒸着やスパッタにより生成されるはんだ膜の厚膜化はコストの面から困難である。   In order to solve this problem, there is a method of making the thickness of the solder film as high as the roughness of the electrode surface, but it is difficult to increase the thickness of the solder film generated by vapor deposition or sputtering from the viewpoint of cost. .

また、はんだ膜を厚く形成できた場合であっても、配線基板の表面粗さにもばらつきがあるため、ばらつきの小さい電極にダイマウントした場合、加圧加熱してチップをマウントする従来の接合方式では、溶融したはんだがチップ側面にはみ出し側壁と接触するため、プロセスの難易度が高くなるという問題もある。   In addition, even when the solder film can be formed thick, the surface roughness of the wiring board also varies, so when die-mounted on an electrode with small variations, conventional bonding in which the chip is mounted by pressure heating In the system, since the melted solder protrudes to the side surface of the chip and comes into contact with the side wall, there is a problem that the difficulty of the process becomes high.

このため、2〜3μmのはんだ膜厚さが接続電極に形成された半導体素子を用いて、セラミックなどの電極表面の粗い接続基材に良好なはんだ接合を低コストで実現する製造方法が必要となっている。   For this reason, the manufacturing method which implement | achieves a good solder joint to the connection base material with rough electrode surfaces, such as a ceramic, at low cost using the semiconductor element in which the solder film thickness of 2-3 micrometers was formed in the connection electrode is required. It has become.

そこで本発明は、半導体素子をセラミック基板等の表面の粗い基板に接合する場合であっても、信頼性が高く、かつ、良好な接合を低コストで実現することができる半導体装置の製造方法を提供することを目的としている。   Therefore, the present invention provides a method for manufacturing a semiconductor device that can achieve high-reliability and good bonding at low cost even when a semiconductor element is bonded to a substrate having a rough surface such as a ceramic substrate. It is intended to provide.

前記課題を解決し目的を達成するために、本発明の半導体装置の製造方法は次のように構成されている。   In order to solve the above-mentioned problems and achieve the object, a semiconductor device manufacturing method of the present invention is configured as follows.

(1)半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、上記接続電極に金属バルク材を超音波併用熱圧着する工程と、上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、上記基板を加熱する工程と、上記基板に、上記端子にはんだ膜が形成された半導体素子をマウントし、上記はんだ膜を溶融して上記端子と上記接続電極とを接合する工程とを備え、上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする。 (1) In a method of manufacturing a semiconductor device in which a terminal of a semiconductor element is joined to a connection electrode of a substrate, a step of thermocompression bonding a metal bulk material to the connection electrode with ultrasonic waves and a contact surface of the metal bulk material are flat. A step of flattening by pressing with a tool, a step of heating the substrate, a semiconductor element having a solder film formed on the terminal is mounted on the substrate, the solder film is melted, and the terminal and the connection are connected and a step of bonding the electrode, in the step of the flattening, the ultrasonic vibrations perpendicular to the load direction of said tool, and characterized in that it applied to the two-way direction orthogonal to each other.

(2)半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、上記接続電極に金錫系の金属バルク材を超音波併用熱圧着する工程と、上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、上記基板を加熱する工程と、上記基板に、上記端子に錫系の金属膜が成形された半導体素子をマウントし、上記金属膜を溶融して上記端子と上記接続電極とを接合する工程とを備え、上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする。 (2) In a method of manufacturing a semiconductor device in which a terminal of a semiconductor element is joined to a connection electrode of a substrate, a step of ultrasonically bonding a gold-tin metal bulk material to the connection electrode together with the ultrasonic contact with the metal bulk material A step of flattening by pressing with a tool having a flat surface, a step of heating the substrate, a semiconductor element having a tin-based metal film formed on the terminal is mounted on the substrate, and the metal film is melted and a step of joining the said terminal and the connection electrode, in the step of the flattening, the ultrasonic vibrations perpendicular to the load direction of said tool, and, applying the two-way direction orthogonal to each other It is characterized by.

(3)半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、上記接続電極に金属バルク材を超音波併用熱圧着する工程と、上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、上記基板に、上記端子に金属膜が形成された半導体素子を超音波振動を併用して熱圧着する工程とを備え、上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする。 (3) In a method for manufacturing a semiconductor device in which a terminal of a semiconductor element is bonded to a connection electrode of a substrate, a step of thermocompression bonding a metal bulk material to the connection electrode with ultrasonic waves and a contact surface of the metal bulk material are flat. A step of flattening by pressing with a tool, and a step of thermocompression bonding a semiconductor element having a metal film formed on the terminal to the substrate by using ultrasonic vibration. the ultrasonic vibration orthogonal to the load direction of said tool, and characterized in that it applied to the two-way direction orthogonal to each other.

本発明によれば、半導体素子をセラミック基板等の表面の粗い基板に接合する場合であっても、信頼性が高く、かつ、良好な接合を低コストで実現することが可能である。   According to the present invention, even when a semiconductor element is bonded to a substrate having a rough surface such as a ceramic substrate, high reliability and good bonding can be realized at low cost.

図1〜図3は、本発明の各実施の形態に適用されるLED30の一例を示す図であって、図1は平面図、図2は側面図、図3は底面図である。また、図4は、同様に各実施の形態に適用されるセラミック基板40を示す平面図である。   1-3 is a figure which shows an example of LED30 applied to each embodiment of this invention, Comprising: FIG. 1 is a top view, FIG. 2 is a side view, FIG. 3 is a bottom view. FIG. 4 is a plan view showing a ceramic substrate 40 similarly applied to each embodiment.

LED30は、ジャンクションダウン構造の両面電極LEDであり、Si化合物により形成された四角錐台状のチップ本体31を有している。ダイマウント面(図2中下側)のチップサイズは0.3mm角であり、その対面(図2中上側)は0.2mm角である。   The LED 30 is a double-sided electrode LED having a junction-down structure, and has a quadrangular frustum-shaped chip body 31 formed of a Si compound. The chip size of the die mount surface (lower side in FIG. 2) is 0.3 mm square, and the opposite surface (upper side in FIG. 2) is 0.2 mm square.

チップ本体31の上面31aには、ワイヤボンディングパッド32が設けられ、下面31bにはエピタキシャル層33が形成され、その下面に端子電極34が形成されている。端子電極34は、バリアメタルの上にNi膜が成膜されており、さらに接合のための金錫系のはんだ膜が2.0μmの厚さで形成されている。   A wire bonding pad 32 is provided on the upper surface 31a of the chip body 31, an epitaxial layer 33 is formed on the lower surface 31b, and a terminal electrode 34 is formed on the lower surface. In the terminal electrode 34, a Ni film is formed on the barrier metal, and a gold-tin solder film for bonding is formed to a thickness of 2.0 μm.

なお、はんだの這い上がりによる短絡不良を防ぐために、端子電極34のサイズはチップ面積よりも小さく、例えば0.2mm角である。チップ本体31の下面31bの端子電極34以外の領域は、ポリイミドによりパシベーション膜35が成膜されている。   In order to prevent a short circuit failure due to solder creeping up, the size of the terminal electrode 34 is smaller than the chip area, for example, 0.2 mm square. In a region other than the terminal electrode 34 on the lower surface 31b of the chip body 31, a passivation film 35 is formed of polyimide.

セラミック基板40は、アルミナ材製の基材41を備え、この基材41上にはタングステンにより形成された配線42が設けられている。基材41のサイズは、例えば5.0mm角、厚さ0.3mmである。配線42のタングステン表面にはNiが5.0μmの厚さで電解メッキされ、さらにNi上に金が0.5μmの厚さで電解メッキされている。さらに配線42の一部には、接続電極43が形成されている。その配線幅は、LED30の端子電極34よりも広く形成されており、例えば0.4mmである。セラミック基板40の基材41は、焼成により成形されているため、接続電極43の表面は粗く、Rzで7.0μm前後である。   The ceramic substrate 40 includes a base material 41 made of an alumina material, and a wiring 42 formed of tungsten is provided on the base material 41. The size of the base material 41 is, for example, 5.0 mm square and a thickness of 0.3 mm. On the tungsten surface of the wiring 42, Ni is electrolytically plated with a thickness of 5.0 μm, and gold is electrolytically plated on the Ni with a thickness of 0.5 μm. Further, a connection electrode 43 is formed on a part of the wiring 42. The wiring width is formed wider than the terminal electrode 34 of the LED 30 and is, for example, 0.4 mm. Since the base material 41 of the ceramic substrate 40 is formed by firing, the surface of the connection electrode 43 is rough, and the Rz is around 7.0 μm.

図5〜図10は、本発明の第1の実施の形態に係るLED製造方法を模式的に示す断面図、図11は加熱プロファイルを示すグラフである。なお、金属バンプ(金属バルク材)を形成するための金属ワイヤに、純度99.99%でワイヤ径25μmの金ワイヤを使用した。また、フラックスには、RMAの活性力を有するロジン系フラックスを使用した。   5-10 is sectional drawing which shows typically the LED manufacturing method based on the 1st Embodiment of this invention, FIG. 11 is a graph which shows a heating profile. A gold wire having a purity of 99.99% and a wire diameter of 25 μm was used as a metal wire for forming a metal bump (metal bulk material). Moreover, the rosin type flux which has the activity power of RMA was used for the flux.

最初に、セラミック基板40を250℃に加熱し、金ワイヤの先端に形成したφ70μmの金ボールを、キャピラリを用いて、0.6Nの荷重で加圧し、振幅1.0μmの超音波振動を30ms印加する。これにより、接続電極43上に金バンプ(金属バルク材)50が接合される(図5)。キャピラリはアルミナセラミック製のものを使用する。金バンプを形成する変わりに、ウェッジボンディングにより、接続電極43に金属(金属バルク材)を供給してもよい。   First, the ceramic substrate 40 is heated to 250 ° C., a 70 μm gold ball formed at the tip of the gold wire is pressurized with a load of 0.6 N using a capillary, and an ultrasonic vibration with an amplitude of 1.0 μm is applied for 30 ms. Apply. Thereby, the gold bump (metal bulk material) 50 is joined on the connection electrode 43 (FIG. 5). A capillary made of alumina ceramic is used. Instead of forming the gold bump, metal (metal bulk material) may be supplied to the connection electrode 43 by wedge bonding.

次に、セラミック基板40を200℃に加熱し、平面粗さRa0.1μm、平面度1.0μmの平坦化ツール60を1バンプあたり10Nの荷重で押し付け、250μmφのフラット面を形成する(図6)。平坦化ツール60は例えば超硬合金D30で成形され、先端は気相成長させた人工ダイヤでコートされている。   Next, the ceramic substrate 40 is heated to 200 ° C., and a flattening tool 60 having a surface roughness Ra of 0.1 μm and a flatness of 1.0 μm is pressed with a load of 10 N per bump to form a flat surface of 250 μmφ (FIG. 6). ). The flattening tool 60 is formed of, for example, a cemented carbide D30, and the tip is coated with an artificial diamond that is vapor-phase grown.

平坦化ツール60で押し付けることにより、接続電極43表面にメッキされたNiも変形し、直径250μmのフラット面の形成が可能になる。また、平坦化ツール60に振幅2.0μmの超音波振動を印加して、金バンプ50を平坦化することにより、押し広げられた金バンプ50が接続電極43にメッキされた金と固相拡散し、より良好な接合の確保が可能となる。   By pressing with the flattening tool 60, Ni plated on the surface of the connection electrode 43 is also deformed, and a flat surface having a diameter of 250 μm can be formed. Further, by applying ultrasonic vibration having an amplitude of 2.0 μm to the flattening tool 60 and flattening the gold bump 50, the gold bump 50 that has been spread is solid-phase diffused with gold plated on the connection electrode 43. As a result, better bonding can be ensured.

さらに、超音波の印加を平坦化ツール60の荷重印加方向に印加することにより、金バンプ50を同心円上に押し広げることができる。振幅を荷重方向に対して直交する方向に印加する場合には、振幅方向に金バンプ50が押し広げられ、フラット面が楕円形になる。この対策として、平坦化工程を2回に分け、セラミック基板40の面方向であって、互いに直交する2方向に超音波を印加することにより、真円に近い平坦化面を形成することが可能である。   Furthermore, by applying ultrasonic waves in the load application direction of the flattening tool 60, the gold bumps 50 can be spread out concentrically. When the amplitude is applied in a direction orthogonal to the load direction, the gold bump 50 is expanded in the amplitude direction, and the flat surface becomes elliptical. As a countermeasure, it is possible to form a flattened surface close to a perfect circle by dividing the flattening process into two steps and applying ultrasonic waves in two directions perpendicular to each other in the surface direction of the ceramic substrate 40. It is.

平坦化した後、金バンプ50上にディスペンスによりフラックス51を供給し(図7)、LED30を0.5Nの荷重でマウントする(図8)。LED30をマウント後、セラミック基板40をリフロー炉に通して、端子電極34に形成された金錫はんだ膜を溶融させ、はんだ接合する(図9)。加熱プロファイルは、例えば図11に示すように、室温から300℃まで60秒で一定速度昇温した後、冷却する。リフローの後、イソプロピルアルコールにサンプルを浸漬し、38kHzの超音波を15分間印加して、フラックス51の残渣の洗浄を行い、ダイマウント工程を完了する(図10)。   After planarization, the flux 51 is supplied onto the gold bump 50 by dispensing (FIG. 7), and the LED 30 is mounted with a load of 0.5 N (FIG. 8). After the LED 30 is mounted, the ceramic substrate 40 is passed through a reflow furnace, and the gold-tin solder film formed on the terminal electrode 34 is melted and soldered (FIG. 9). In the heating profile, for example, as shown in FIG. 11, the temperature is raised from room temperature to 300 ° C. at a constant rate in 60 seconds and then cooled. After the reflow, the sample is immersed in isopropyl alcohol, and 38 kHz ultrasonic waves are applied for 15 minutes to clean the residue of the flux 51, thereby completing the die mounting process (FIG. 10).

上述したように、本第1の実施の形態に係る半導体装置の製造方法によれば、LED30を表面が粗いセラミック基板40に実装する場合において、LED30側の端子電極34に厚くはんだ膜を形成できない場合であっても金バンプ50等により十分、かつ、気泡の無い金属バルク材を供給することで、セラミック基板40の粗さを緩和でき、リフロー溶融の際にボイドの発生等による接合不良を防止することができる。   As described above, according to the manufacturing method of the semiconductor device according to the first embodiment, when the LED 30 is mounted on the ceramic substrate 40 having a rough surface, a thick solder film cannot be formed on the terminal electrode 34 on the LED 30 side. Even in such a case, by supplying a metal bulk material that is sufficient and free of bubbles from the gold bump 50 or the like, the roughness of the ceramic substrate 40 can be alleviated, and poor bonding due to generation of voids during reflow melting is prevented. can do.

なお、金バンプ50の平坦化後にフラックス51を供給せず、セラミック基板40を端子電極34の金錫系はんだ膜の融点よりも高い温度に加熱し、N95%+H5%の還元雰囲気下で半導体素子30をセラミック基板40にマウントするようにしてもよい。この場合も、良好なはんだ接合を実施するこがも可能である。 Note that the flux 51 is not supplied after the flattening of the gold bump 50, and the ceramic substrate 40 is heated to a temperature higher than the melting point of the gold-tin solder film of the terminal electrode 34, and a reducing atmosphere of N 2 95% + H 2 5%. The semiconductor element 30 may be mounted on the ceramic substrate 40 below. In this case as well, it is possible to carry out a good solder joint.

図12〜図15は、本発明の第2の実施の形態に係る半導体装置の製造方法を模式的に示す断面図である。本実施の形態においては、上述した平坦膜状の金属バルク材を形成する際に金バンプ50の代わりに金属膜52を用いている(図12)。金属膜52は純度99.99%で端子電極34よりも1辺が50μm大きい250μm角、10μm厚さに形成されている。金薄膜52を加熱した接続電極43にマウントし、平坦化ツール60を使用して、超音波を印加しながら加圧する(図13)。平坦化した後、金薄膜52上にディスペンスによりフラックス51を供給し、LED30を0.5Nの荷重でマウントする(図14)。LED30をマウント後、セラミック基板40をリフロー炉に通して、端子電極34に形成された金錫はんだ膜を溶融させ、はんだ接合する。リフローの後、イソプロピルアルコールにサンプルを浸漬し、38kHzの超音波を15分間印加して、フラックス51の残渣の洗浄を行い、ダイマウント工程を完了する(図15)。   12 to 15 are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the present embodiment, the metal film 52 is used in place of the gold bump 50 when the flat film-like metal bulk material described above is formed (FIG. 12). The metal film 52 has a purity of 99.99% and is formed to have a 250 μm square and a 10 μm thickness with one side 50 μm larger than the terminal electrode 34. The gold thin film 52 is mounted on the heated connection electrode 43, and is pressed using the planarizing tool 60 while applying ultrasonic waves (FIG. 13). After flattening, the flux 51 is supplied onto the gold thin film 52 by dispensing, and the LED 30 is mounted with a load of 0.5 N (FIG. 14). After the LED 30 is mounted, the ceramic substrate 40 is passed through a reflow furnace, and the gold-tin solder film formed on the terminal electrode 34 is melted and soldered. After reflow, the sample is immersed in isopropyl alcohol, and 38 kHz ultrasonic waves are applied for 15 minutes to clean the residue of the flux 51, thereby completing the die mount process (FIG. 15).

本第2の実施の形態における半導体装置の製造方法においても、上述した第1の実施の形態である半導体装置の製造方法と同様に良好なはんだ接合可能な金属平坦化膜を形成することが可能である。   In the method of manufacturing the semiconductor device according to the second embodiment, it is possible to form a metal flattening film that can be satisfactorily soldered similarly to the method of manufacturing the semiconductor device according to the first embodiment described above. It is.

図16〜図18は、本発明の第3の実施の形態に係る半導体装置の製造方法を模式的に示す断面図である。なお、LED30の端子電極34には錫系のはんだ膜が形成されている。   16 to 18 are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. Note that a tin-based solder film is formed on the terminal electrode 34 of the LED 30.

本実施の形態においては、接続電極43上に金錫共晶合金バンプ53を形成する(図16)。次に、金錫共晶合金バンプ53上にフラックス51を滴下し(図17)、接続電極43に端子電極34を位置合わせしてLED30をマウントする。次に、リフロー炉で加熱し、金錫共晶合金バンプ53及び端子電極34上の錫系のはんだ膜を溶融させてはんだ接合をする(図18)。これははんだ材内部の錫の割合を十分に多くすることで、液相から固相となるまで時間を長くし、気泡が抜けやすいようにするためである。したがって、気泡の少ないはんだ接合が可能になる。最後にフラックス残渣を洗浄し、チップと基板のはんだ接合を完了する。   In the present embodiment, a gold-tin eutectic alloy bump 53 is formed on the connection electrode 43 (FIG. 16). Next, the flux 51 is dropped on the gold-tin eutectic alloy bump 53 (FIG. 17), the terminal electrode 34 is aligned with the connection electrode 43, and the LED 30 is mounted. Next, heating is performed in a reflow furnace, and the tin-based solder film on the gold-tin eutectic alloy bump 53 and the terminal electrode 34 is melted and soldered (FIG. 18). This is because by increasing the ratio of tin in the solder material sufficiently, the time is increased from the liquid phase to the solid phase so that bubbles can be easily removed. Therefore, solder joining with less bubbles is possible. Finally, the flux residue is washed to complete the solder bonding between the chip and the substrate.

また、本実施の形態によれば、接続電極43に形成した金錫共晶合金バンプ53を溶融させることができるので、端子電極34にはんだ以外の金属、例えばAu、Niなどの金属膜を成膜した場合であっても良好なはんだ接合を行うことができる。   Further, according to the present embodiment, since the gold-tin eutectic alloy bump 53 formed on the connection electrode 43 can be melted, a metal film other than solder, such as Au or Ni, is formed on the terminal electrode 34. Even if it is a film | membrane, favorable soldering can be performed.

なお、上述した工程においては、金錫共晶合金バンプ53を平坦化していないが、第1の実施の形態と同様に平坦化ツール60を用いて、金錫共晶合金バンプ53を平坦化してもよい。これにより、LED30をマウントする際に接続電極43が受けるダメージを軽減することが可能である。   In the above-described process, the gold-tin eutectic alloy bump 53 is not flattened, but the gold-tin eutectic alloy bump 53 is flattened using the flattening tool 60 as in the first embodiment. Also good. Thereby, it is possible to reduce the damage which the connection electrode 43 receives when mounting the LED 30.

図19〜図21は、本発明の第4の実施の形態に係る半導体装置の製造方法を模式的に示す断面図である。なお、LED30の端子電極34にはスパッタ若しくは蒸着により、0.1μm厚さで金膜が形成されている。   19 to 21 are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Note that a gold film having a thickness of 0.1 μm is formed on the terminal electrode 34 of the LED 30 by sputtering or vapor deposition.

本製造方法では、上述した第1の実施の形態に係る半導体の製造方法と同様に、金バンプ50を形成し(図19)、金バンプ50を平坦化した後(図20)、200℃に加熱した基板上にLED30をボンディングツール61で吸着し、振幅1.0μmの超音波振動を印加しながら4Nの荷重をかけて30ms間加圧する(図21)。これにより、端子電極34の金膜と金バンプ50とにおいて、金と金の固相拡散が行われ、良好な接合を確保することができる。なお、ボンディングツール61は、平坦化ツール60と同様に、超硬合金D30で作製し、先端は気相成長させた人工ダイヤでコートされている。   In this manufacturing method, as in the semiconductor manufacturing method according to the first embodiment described above, the gold bumps 50 are formed (FIG. 19), and after the gold bumps 50 are planarized (FIG. 20), the temperature is increased to 200.degree. The LED 30 is adsorbed on the heated substrate with the bonding tool 61, and is pressurized for 30 ms with a load of 4N while applying ultrasonic vibration with an amplitude of 1.0 μm (FIG. 21). Thereby, in the gold film of the terminal electrode 34 and the gold bump 50, solid phase diffusion of gold and gold is performed, and good bonding can be ensured. Note that the bonding tool 61 is made of a cemented carbide D30, as with the planarization tool 60, and the tip is coated with an artificial diamond that is vapor-phase grown.

本第4の実施の形態における半導体装置の製造方法においても、上述した第1の実施の形態である半導体装置の製造方法と同様に良好なはんだ接合可能な金属平坦化膜を形成することが可能である。   In the method of manufacturing the semiconductor device according to the fourth embodiment, it is possible to form a metal flattening film that can be satisfactorily soldered in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment described above. It is.

なお、上述した各実施の形態では、半導体素子の端子を基板の接続電極に接合する場合について説明したが、単に半導体素子を基板上に接着するためのいわゆるダイボンディングにも適用可能である。   In each of the above-described embodiments, the case where the terminal of the semiconductor element is bonded to the connection electrode of the substrate has been described. However, the present invention can also be applied to so-called die bonding for simply bonding the semiconductor element on the substrate.

なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

本発明の各実施の形態に用いられる半導体発光素子を示す平面図。The top view which shows the semiconductor light-emitting device used for each embodiment of this invention. 同半導体発光素子を示す側面図。The side view which shows the semiconductor light-emitting device. 同半導体発光素子を示す底面図。The bottom view which shows the same semiconductor light-emitting device. 同実施の形態に用いられるセラミック基板を示す平面図。The top view which shows the ceramic substrate used for the embodiment. 本発明の第1の実施の形態に係る半導体装置の製造方法の工程を模式的に示す断面図。Sectional drawing which shows typically the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程でのリフロー加熱プロファイルを示すグラフ。The graph which shows the reflow heating profile in the same process. 本発明の第2の実施の形態に係る半導体装置の製造方法の工程を模式的に示す断面図。Sectional drawing which shows typically the process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 本発明の第3の実施の形態に係る半導体装置の製造方法の工程を模式的に示す断面図。Sectional drawing which shows typically the process of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 本発明の第4の実施の形態に係る半導体装置の製造方法の工程を模式的に示す断面図。Sectional drawing which shows typically the process of the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 同工程を模式的に示す断面図。Sectional drawing which shows the same process typically. 従来例に係る複数のLEDチップを1つのパッケージ内に実装した新規パッケージの半導体装置の斜視図。The perspective view of the semiconductor device of the new package which mounted the some LED chip which concerns on a prior art example in one package. 従来例に係る電極表面が粗いセラミック基板を使用した半導体装置の構成図。The block diagram of the semiconductor device which uses the ceramic substrate with the rough electrode surface which concerns on a prior art example. 従来例に係る接合部に気泡が入った半導体装置の構成図。The block diagram of the semiconductor device which the bubble entered into the junction part which concerns on a prior art example.

符号の説明Explanation of symbols

30…LED、34…端子電極、40…セラミック基板、43…接続電極、50…金バンプ、51…フラックス、52…金属膜、53…金錫共晶合金バンプ、60…平坦化ツール、61…ボンディングツール。   30 ... LED, 34 ... terminal electrode, 40 ... ceramic substrate, 43 ... connection electrode, 50 ... gold bump, 51 ... flux, 52 ... metal film, 53 ... gold-tin eutectic alloy bump, 60 ... flattening tool, 61 ... Bonding tool.

Claims (3)

半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、
上記接続電極に金属バルク材を超音波併用熱圧着する工程と、
上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、
上記基板を加熱する工程と、
上記基板に、上記端子にはんだ膜が形成された半導体素子をマウントし、上記はんだ膜を溶融して上記端子と上記接続電極とを接合する工程とを備え、
上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device in which a terminal of a semiconductor element is bonded to a connection electrode of a substrate,
A step of thermocompression bonding of a metal bulk material to the connection electrode with ultrasonic waves;
The metal bulk material is flattened by pressing with a tool having a flat contact surface;
Heating the substrate;
Mounting a semiconductor element having a solder film formed on the terminal on the substrate, melting the solder film, and joining the terminal and the connection electrode;
In the step of the flattening, the ultrasonic vibrations perpendicular to the load Direction of the tool, and a method of manufacturing a semiconductor device, which comprises applying to the two-way direction orthogonal to each other.
半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、
上記接続電極に金錫系の金属バルク材を超音波併用熱圧着する工程と、
上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、
上記基板を加熱する工程と、
上記基板に、上記端子に錫系の金属膜が成形された半導体素子をマウントし、上記金属膜を溶融して上記端子と上記接続電極とを接合する工程とを備え、
上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする半導体装置の製造方法
In a method for manufacturing a semiconductor device in which a terminal of a semiconductor element is bonded to a connection electrode of a substrate,
A step of thermocompression bonding a gold-tin metal bulk material to the connection electrode with ultrasonic waves;
The metal bulk material is flattened by pressing with a tool having a flat contact surface;
Heating the substrate;
Mounting a semiconductor element in which a tin-based metal film is formed on the terminal on the substrate, melting the metal film, and joining the terminal and the connection electrode;
In the step of the flattening, the ultrasonic vibrations perpendicular to the load Direction of the tool, and a method of manufacturing a semiconductor device, which comprises applying to the two-way direction orthogonal to each other
半導体素子の端子を基板の接続電極に接合する半導体装置の製造方法において、
上記接続電極に金属バルク材を超音波併用熱圧着する工程と、
上記金属バルク材を、接触面が平坦なツールで加圧して平坦化する工程と、
上記基板に、上記端子に金属膜が形成された半導体素子を超音波振動を併用して熱圧着する工程とを備え、
上記平坦化する工程において、超音波振動を上記ツールの荷重方向に直交し、かつ、互いに直交する2方向に印加することを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device in which a terminal of a semiconductor element is bonded to a connection electrode of a substrate,
A step of thermocompression bonding of a metal bulk material to the connection electrode with ultrasonic waves;
The metal bulk material is flattened by pressing with a tool having a flat contact surface;
The substrate is provided with a step of thermocompression bonding a semiconductor element having a metal film formed on the terminal together with ultrasonic vibration,
In the step of the flattening, the ultrasonic vibrations perpendicular to the load Direction of the tool, and a method of manufacturing a semiconductor device, which comprises applying to the two-way direction orthogonal to each other.
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JP2003297874A (en) * 2002-03-29 2003-10-17 Nec Electronics Corp Connection structure and connection method for electronic component

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