KR102026506B1 - 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 - Google Patents
다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 Download PDFInfo
- Publication number
- KR102026506B1 KR102026506B1 KR1020157020111A KR20157020111A KR102026506B1 KR 102026506 B1 KR102026506 B1 KR 102026506B1 KR 1020157020111 A KR1020157020111 A KR 1020157020111A KR 20157020111 A KR20157020111 A KR 20157020111A KR 102026506 B1 KR102026506 B1 KR 102026506B1
- Authority
- KR
- South Korea
- Prior art keywords
- single crystal
- front surface
- crystal silicon
- silicon substrate
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
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- H01L21/76254—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
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- H01L21/265—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261746822P | 2012-12-28 | 2012-12-28 | |
| US61/746,822 | 2012-12-28 | ||
| PCT/US2013/077491 WO2014105828A1 (en) | 2012-12-28 | 2013-12-23 | Method for low temperature layer transfer in the preparation of multilayer semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20150099847A KR20150099847A (ko) | 2015-09-01 |
| KR102026506B1 true KR102026506B1 (ko) | 2019-09-27 |
Family
ID=50031514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157020111A Active KR102026506B1 (ko) | 2012-12-28 | 2013-12-23 | 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9281233B2 (https=) |
| JP (2) | JP2016508291A (https=) |
| KR (1) | KR102026506B1 (https=) |
| DE (1) | DE112013006244B4 (https=) |
| TW (1) | TWI603387B (https=) |
| WO (1) | WO2014105828A1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102015210384A1 (de) | 2015-06-05 | 2016-12-08 | Soitec | Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung |
| JP6632462B2 (ja) * | 2016-04-28 | 2020-01-22 | 信越化学工業株式会社 | 複合ウェーハの製造方法 |
| WO2019236320A1 (en) * | 2018-06-08 | 2019-12-12 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
| CN110739217B (zh) * | 2019-10-28 | 2025-10-10 | 沈阳硅基科技有限公司 | 一种降低soi硅片应力的制备方法 |
| PL445432A1 (pl) * | 2023-06-30 | 2025-01-07 | Sieć Badawcza Łukasiewicz - Instytut Mikroelektroniki I Fotoniki | Sposób modyfikacji podłoża z monokrystalicznego SiC, zmodyfikowane podłoże, urządzenie zawierające takie podłoże i zastosowanie takiego urządzenia |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010278342A (ja) * | 2009-05-29 | 2010-12-09 | Shin-Etsu Chemical Co Ltd | Soi基板の製造方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2617798B2 (ja) | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
| FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
| FR2774511B1 (fr) * | 1998-01-30 | 2002-10-11 | Commissariat Energie Atomique | Substrat compliant en particulier pour un depot par hetero-epitaxie |
| JP3456521B2 (ja) * | 1998-05-12 | 2003-10-14 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
| FR2797347B1 (fr) * | 1999-08-04 | 2001-11-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
| FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
| KR100511656B1 (ko) * | 2002-08-10 | 2005-09-07 | 주식회사 실트론 | 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼 |
| FR2847075B1 (fr) * | 2002-11-07 | 2005-02-18 | Commissariat Energie Atomique | Procede de formation d'une zone fragile dans un substrat par co-implantation |
| US20060240275A1 (en) * | 2005-04-25 | 2006-10-26 | Gadkaree Kishor P | Flexible display substrates |
| FR2898431B1 (fr) * | 2006-03-13 | 2008-07-25 | Soitec Silicon On Insulator | Procede de fabrication de film mince |
| US7575988B2 (en) * | 2006-07-11 | 2009-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a hybrid substrate |
| FR2914110B1 (fr) * | 2007-03-20 | 2009-06-05 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat hybride |
| JP2008153411A (ja) * | 2006-12-18 | 2008-07-03 | Shin Etsu Chem Co Ltd | Soi基板の製造方法 |
| US7795111B2 (en) * | 2007-06-27 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate and manufacturing method of semiconductor device |
| JP4631946B2 (ja) * | 2008-08-11 | 2011-02-16 | 住友電気工業株式会社 | Iii族窒化物半導体層貼り合わせ基板の製造方法 |
| US9257328B2 (en) | 2008-11-26 | 2016-02-09 | Corning Incorporated | Glass-ceramic-based semiconductor-on-insulator structures and method for making the same |
| US8367519B2 (en) * | 2009-12-30 | 2013-02-05 | Memc Electronic Materials, Inc. | Method for the preparation of a multi-layered crystalline structure |
-
2013
- 2013-12-19 US US14/133,893 patent/US9281233B2/en active Active
- 2013-12-23 KR KR1020157020111A patent/KR102026506B1/ko active Active
- 2013-12-23 JP JP2015550735A patent/JP2016508291A/ja active Pending
- 2013-12-23 DE DE112013006244.5T patent/DE112013006244B4/de active Active
- 2013-12-23 WO PCT/US2013/077491 patent/WO2014105828A1/en not_active Ceased
- 2013-12-27 TW TW102148841A patent/TWI603387B/zh active
-
2018
- 2018-01-24 JP JP2018009428A patent/JP2018085536A/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010278342A (ja) * | 2009-05-29 | 2010-12-09 | Shin-Etsu Chemical Co Ltd | Soi基板の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI603387B (zh) | 2017-10-21 |
| WO2014105828A1 (en) | 2014-07-03 |
| JP2018085536A (ja) | 2018-05-31 |
| US9281233B2 (en) | 2016-03-08 |
| US20140187020A1 (en) | 2014-07-03 |
| JP2016508291A (ja) | 2016-03-17 |
| DE112013006244B4 (de) | 2020-03-05 |
| DE112013006244T5 (de) | 2015-10-08 |
| TW201435991A (zh) | 2014-09-16 |
| KR20150099847A (ko) | 2015-09-01 |
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| US9881832B2 (en) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof | |
| US10068795B2 (en) | Methods for preparing layered semiconductor structures | |
| US9209069B2 (en) | Method of manufacturing high resistivity SOI substrate with reduced interface conductivity | |
| US12183625B2 (en) | Method for transfer of a thin layer of silicon | |
| KR102026506B1 (ko) | 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법 | |
| JP7160943B2 (ja) | 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成 | |
| CN103026460A (zh) | 用于制备多层式晶体结构的方法 |
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St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
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