KR101992352B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

Info

Publication number
KR101992352B1
KR101992352B1 KR1020120106707A KR20120106707A KR101992352B1 KR 101992352 B1 KR101992352 B1 KR 101992352B1 KR 1020120106707 A KR1020120106707 A KR 1020120106707A KR 20120106707 A KR20120106707 A KR 20120106707A KR 101992352 B1 KR101992352 B1 KR 101992352B1
Authority
KR
South Korea
Prior art keywords
layer
penetrating electrode
metal
alloy layer
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020120106707A
Other languages
English (en)
Korean (ko)
Other versions
KR20140039895A (ko
Inventor
문광진
강성희
김태성
박병률
박연상
방석철
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020120106707A priority Critical patent/KR101992352B1/ko
Priority to US14/028,523 priority patent/US9153522B2/en
Priority to JP2013197964A priority patent/JP5865881B2/ja
Publication of KR20140039895A publication Critical patent/KR20140039895A/ko
Priority to US14/809,159 priority patent/US9679829B2/en
Application granted granted Critical
Publication of KR101992352B1 publication Critical patent/KR101992352B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
KR1020120106707A 2012-09-25 2012-09-25 반도체 장치 Active KR101992352B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020120106707A KR101992352B1 (ko) 2012-09-25 2012-09-25 반도체 장치
US14/028,523 US9153522B2 (en) 2012-09-25 2013-09-16 Semiconductor devices and methods of fabricating the same
JP2013197964A JP5865881B2 (ja) 2012-09-25 2013-09-25 半導体装置及びその製造方法
US14/809,159 US9679829B2 (en) 2012-09-25 2015-07-24 Semiconductor devices and methods of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120106707A KR101992352B1 (ko) 2012-09-25 2012-09-25 반도체 장치

Publications (2)

Publication Number Publication Date
KR20140039895A KR20140039895A (ko) 2014-04-02
KR101992352B1 true KR101992352B1 (ko) 2019-06-24

Family

ID=50338075

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120106707A Active KR101992352B1 (ko) 2012-09-25 2012-09-25 반도체 장치

Country Status (3)

Country Link
US (2) US9153522B2 (https=)
JP (1) JP5865881B2 (https=)
KR (1) KR101992352B1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673132B2 (en) * 2012-04-27 2017-06-06 Taiwan Semiconductor Manufacting Company, Ltd. Interconnection structure with confinement layer
KR20140011137A (ko) * 2012-07-17 2014-01-28 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
WO2014039546A1 (en) * 2012-09-05 2014-03-13 Research Triangle Institute, International Electronic devices utilizing contact pads with protrusions and methods for fabrication
US9514986B2 (en) * 2013-08-28 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Device with capped through-substrate via structure
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US9583417B2 (en) * 2014-03-12 2017-02-28 Invensas Corporation Via structure for signal equalization
KR102320821B1 (ko) 2014-09-11 2021-11-02 삼성전자주식회사 반도체 패키지
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
JP2016139648A (ja) 2015-01-26 2016-08-04 株式会社東芝 半導体装置及びその製造方法
US10074594B2 (en) * 2015-04-17 2018-09-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9761509B2 (en) * 2015-12-29 2017-09-12 United Microelectronics Corp. Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
US10050139B2 (en) 2016-06-24 2018-08-14 Infineon Technologies Ag Semiconductor device including a LDMOS transistor and method
US10622284B2 (en) 2016-06-24 2020-04-14 Infineon Technologies Ag LDMOS transistor and method
US9875933B2 (en) * 2016-06-24 2018-01-23 Infineon Technologies Ag Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures
US10242932B2 (en) 2016-06-24 2019-03-26 Infineon Technologies Ag LDMOS transistor and method
US10432172B2 (en) 2016-09-01 2019-10-01 Samsung Electro-Mechanics Co., Ltd. Bulk acoustic filter device and method of manufacturing the same
US10276528B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device and manufacturing method thereof
KR102542614B1 (ko) * 2017-10-30 2023-06-15 삼성전자주식회사 이미지 센서
JP7219598B2 (ja) * 2018-11-27 2023-02-08 新光電気工業株式会社 配線基板及びその製造方法
US11398408B2 (en) * 2019-09-24 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate with trace connected to via at a level within a dielectric layer
US20210398846A1 (en) * 2020-06-17 2021-12-23 Tokyo Electron Limited Method for area selective deposition using a surface cleaning process

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110193199A1 (en) * 2010-02-09 2011-08-11 International Business Machines Corporation Electromigration immune through-substrate vias

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
MY144574A (en) * 1998-09-14 2011-10-14 Ibiden Co Ltd Printed circuit board and method for its production
US6884335B2 (en) * 2003-05-20 2005-04-26 Novellus Systems, Inc. Electroplating using DC current interruption and variable rotation rate
US7019402B2 (en) 2003-10-17 2006-03-28 International Business Machines Corporation Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor
US6979625B1 (en) * 2003-11-12 2005-12-27 Advanced Micro Devices, Inc. Copper interconnects with metal capping layer and selective copper alloys
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP4800585B2 (ja) 2004-03-30 2011-10-26 ルネサスエレクトロニクス株式会社 貫通電極の製造方法、シリコンスペーサーの製造方法
US7232513B1 (en) * 2004-06-29 2007-06-19 Novellus Systems, Inc. Electroplating bath containing wetting agent for defect reduction
US8004087B2 (en) * 2004-08-12 2011-08-23 Nec Corporation Semiconductor device with dual damascene wirings and method for manufacturing same
US7884483B2 (en) * 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
JP4581864B2 (ja) 2005-06-21 2010-11-17 パナソニック電工株式会社 半導体基板への貫通配線の形成方法
JP4552770B2 (ja) 2005-06-21 2010-09-29 パナソニック電工株式会社 半導体基板への貫通配線の形成方法
JP2007005404A (ja) 2005-06-21 2007-01-11 Matsushita Electric Works Ltd 半導体基板への貫通配線の形成方法
US7528006B2 (en) 2005-06-30 2009-05-05 Intel Corporation Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7892972B2 (en) * 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
JP5231733B2 (ja) 2006-11-27 2013-07-10 パナソニック株式会社 貫通孔配線構造およびその形成方法
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
US7678696B2 (en) 2008-08-08 2010-03-16 International Business Machines Corporation Method of making through wafer vias
KR20100021856A (ko) 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US8097953B2 (en) 2008-10-28 2012-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit stacking-joint interface structure
US20100200408A1 (en) * 2009-02-11 2010-08-12 United Solar Ovonic Llc Method and apparatus for the solution deposition of high quality oxide material
US8610283B2 (en) * 2009-10-05 2013-12-17 International Business Machines Corporation Semiconductor device having a copper plug
KR101302564B1 (ko) 2009-10-28 2013-09-02 한국전자통신연구원 비아 형성 방법 및 이를 이용하는 적층 칩 패키지의 제조 방법
KR20110050957A (ko) 2009-11-09 2011-05-17 삼성전자주식회사 반도체 소자의 관통 비아 콘택 및 그 형성 방법
JP2011216867A (ja) * 2010-03-17 2011-10-27 Tokyo Electron Ltd 薄膜の形成方法
KR101692434B1 (ko) 2010-06-28 2017-01-18 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP5504147B2 (ja) * 2010-12-21 2014-05-28 株式会社荏原製作所 電気めっき方法
JP2012151435A (ja) * 2010-12-27 2012-08-09 Elpida Memory Inc 半導体装置の製造方法
CN103907192A (zh) * 2011-09-13 2014-07-02 爱德斯托科技有限公司 具有合金化电极的电阻切换器件及其形成方法
US8785790B2 (en) * 2011-11-10 2014-07-22 Invensas Corporation High strength through-substrate vias
US9269612B2 (en) * 2011-11-22 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of forming damascene interconnect structures
KR20140011137A (ko) * 2012-07-17 2014-01-28 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110193199A1 (en) * 2010-02-09 2011-08-11 International Business Machines Corporation Electromigration immune through-substrate vias

Also Published As

Publication number Publication date
JP2014068014A (ja) 2014-04-17
JP5865881B2 (ja) 2016-02-17
US20140084473A1 (en) 2014-03-27
KR20140039895A (ko) 2014-04-02
US9679829B2 (en) 2017-06-13
US20150332967A1 (en) 2015-11-19
US9153522B2 (en) 2015-10-06

Similar Documents

Publication Publication Date Title
KR101992352B1 (ko) 반도체 장치
KR102064863B1 (ko) 관통 비아 구조체를 갖는 반도체 소자 제조 방법
CN111613612B (zh) 包括嵌入式表面贴装器件的半导体封装件及其形成方法
KR101931115B1 (ko) 반도체 장치 및 그 제조 방법
US12278222B2 (en) Method of fabricating semiconductor package including sub-interposer substrates
US8786058B2 (en) Semiconductor devices and methods of manufacturing the same
KR101959284B1 (ko) 반도체 장치 및 그 형성방법
US9698080B2 (en) Conductor structure for three-dimensional semiconductor device
KR20140073163A (ko) 반도체 장치 및 그의 형성방법
US20150130078A1 (en) Semiconductor chip and semiconductor package having same
US20150123278A1 (en) Semiconductor devices, methods of manufacturing the same, memory cards including the same and electronic systems including the same
KR101801137B1 (ko) 반도체 장치 및 그 제조 방법
KR20090013417A (ko) 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 이의제조방법
US20140141569A1 (en) Semiconductor devices having through-via and methods of fabricating the same
KR20140104778A (ko) 관통전극을 갖는 반도체 소자의 제조방법
CN103378057B (zh) 半导体芯片以及其形成方法
US9059067B2 (en) Semiconductor device with interposer and method manufacturing same
US9431332B2 (en) Semiconductor package
CN107452686A (zh) 包括升高焊盘上的贯穿模球的半导体封装及其制造方法
US20250167123A1 (en) Semiconductor die having a metal plate layer
US20120049349A1 (en) Semiconductor chips and methods of forming the same
KR20150019089A (ko) 관통전극을 갖는 반도체 소자 및 그 제조방법
KR20150016798A (ko) 반도체 장치 및 그 제조 방법
US11688707B2 (en) Semiconductor package
CN103378032A (zh) 半导体芯片以及其形成方法

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000