KR101973029B1 - Electronic component - Google Patents

Abstract

Provided is a method for manufacturing an electronic component capable of modifying the surface of a baking electrode layer provided in a laminate while suppressing cleavage and breakage of the laminate.
The electronic component includes a laminate 12 including a first end face 12e and a second end face 12f, a first side face and a second side face, and a first major face 12a and a second major face 12b, The first external electrode 15B includes a first external electrode 15B and a second external electrode 16B and the first external electrode 15B includes a first bake electrode layer 15a and a first resin layer 15d, The electrode 16B includes a second baking electrode layer 16a and a second resin layer 16d and each of the first baking electrode layer 15a and the second baking electrode layer 16a is provided on the stack 12 And each of the first resin layer 15d and the second resin layer 16d includes a metal particle and the first resin layer 15d and the second resin layer 16d ) Has a portion where the metal particles are exposed at a ratio of 72.6% to 90.9%.

Description

[0001] ELECTRONIC COMPONENT [

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component including a laminate including alternately laminated dielectric layers and internal electrode layers.

Conventionally, as a document that discloses a method of manufacturing a multilayer ceramic capacitor as an electronic component, for example, Japanese Unexamined Patent Application Publication No. 2009-239204 (Patent Document 1) can be cited. In the method of manufacturing a multilayer ceramic capacitor disclosed in Patent Document 1, after the end face of a laminate having a substantially rectangular parallelepiped shape is immersed in a conductor paste, a paste is attached to the end face, Press on the plate and release the laminate from the plate to trim the shape of the paste attached to the end face. After repeating this several times, the conductive paste is sintered. The external electrode is formed by plating on the sintered conductive paste.

Japanese Patent Application Laid-Open No. 2009-239204

However, the multilayer ceramic capacitor manufactured by the method of manufacturing a multilayer ceramic capacitor disclosed in Patent Document 1 is weak in impact and may not satisfy the characteristics as a capacitor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an electronic part which is strong against impact and has high reliability.

An electronic component based on the present invention has a first end face and a second end face facing each other in the longitudinal direction, a first side face and a second side facing each other in the width direction orthogonal to the longitudinal direction, A laminate including a first main surface and a second main surface facing each other in a height direction orthogonal to the width direction, a first external electrode provided on the first end surface, and a second external electrode provided on the second end surface, Wherein the first external electrode includes a first bake electrode layer provided on the first end face and a first resin layer provided on the first bake electrode layer, And a second resin layer provided on the second baking electrode layer, wherein each of the first baking electrode layer and the second electrode layer is provided on the laminate, and the gap and the oil Wherein the first resin layer and the second resin layer comprise metal particles, and each of the surface layers of the first resin layer and the second resin layer has an area of 72.6% to 90.9% Of the total area of the exposed surface.

In the electronic component according to the present invention, in the portion where the metal particles are exposed at a ratio of 72.6% or more and 90.9% or less, each surface of the first resin layer and the second resin layer has a flat shape It is preferable that the metal particles are formed in a continuously aligned state.

In the electronic component according to the present invention, it is preferable that the surface roughness (Ra) of the first resin layer and the surface roughness (Ra) of the second resin layer are 0.38 탆 or less.

Industrial Applicability According to the present invention, it is possible to provide an electronic part that is strong against impact and highly reliable.

1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention.
2 is a cross-sectional view taken along the line II-II of the multilayer ceramic capacitor shown in FIG.
3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG.
4 is a partial cross-sectional view showing in detail the baking electrode layer of the multilayer ceramic capacitor according to the first embodiment.
5 is a flow chart showing a method of manufacturing a multilayer ceramic capacitor according to the first embodiment.
6 is a view showing a surface treatment apparatus for carrying out the surface treatment of the baking electrode layer shown in Fig.
7 is a plan view of the stirring tank shown in Fig.
8 is a cross-sectional view of the stirring tank shown in Fig.
9 is a plan view showing the positional relationship between the stirring tank and the elastic member shown in Fig.
10 is a flow chart showing in detail the step of performing the surface treatment of the baking electrode layer shown in Fig.
11 is a view showing a step of applying vibration energy to a plurality of stacked bodies and a plurality of media in the step of imparting vibration to the stirring tank shown in Fig. 10. Fig.
12 is a partial cross-sectional view showing in detail the baking electrode layer of the multilayer ceramic capacitor manufactured according to the method for manufacturing a multilayer ceramic capacitor according to the second embodiment.
13 is a cross-sectional view of a multilayer ceramic capacitor manufactured according to the method of manufacturing a multilayer ceramic capacitor according to the third embodiment.
14 is a cross-sectional view showing the state of the resin layer on the side of the center section of the end face of the multilayer ceramic capacitor according to the third embodiment.
15 is a flow chart showing a method of manufacturing a multilayer ceramic capacitor according to the third embodiment.
Fig. 16 is a diagram showing conditions and results of the first verification experiment performed to verify the effects of the embodiment. Fig.
17 is a cross-sectional view showing the state of the resin layer in the vicinity of the corner portion before the surface treatment in the second verification test conducted to verify the effect of the embodiment.
18 is a cross-sectional view showing the state of the resin layer in the vicinity of the corner after the surface treatment in the second verification test conducted to verify the effect of the embodiment.
Fig. 19 is a cross-sectional view showing the state of the resin layer on the side of the center section of the end surface before the surface treatment in the second verification experiment conducted to verify the effect of the embodiment. Fig.
20 is a cross-sectional view showing the state of the resin layer on the side of the center of the end face after the surface treatment in the second verification test conducted to verify the effect of the embodiment.
Fig. 21 is a diagram showing conditions and results of a third verification experiment performed to verify the effects of the embodiment. Fig.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. On the other hand, the embodiments described below exemplify a multilayer ceramic capacitor as an electronic component, and illustrate a method of manufacturing a multilayer ceramic capacitor as a method of manufacturing an electronic component. In the following embodiments, the same or common components are denoted by the same reference numerals in the drawings, and description thereof will not be repeated.

(Embodiment 1)

(Multilayer Ceramic Capacitor)

1 is a perspective view of a multilayer ceramic capacitor manufactured according to the method for manufacturing a multilayer ceramic capacitor according to the first embodiment. 2 is a cross-sectional view taken along the line II-II of the multilayer ceramic capacitor shown in FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG.

As shown in Figs. 1 to 3, the multilayer ceramic capacitor 10 has a multilayer body 12 (ceramic body), a first external electrode 15 and a second external electrode 16.

The layered body 12 has a substantially rectangular parallelepiped outer shape. The stacked body 12 includes a plurality of stacked dielectric layers 13 and a plurality of internal electrode layers 14. The stacked body 12 has a first side face 12c and a second side face 12d opposed to each other in the width direction W and a second side face 12d opposed to each other in the height direction T orthogonal to the width direction W. [ The first major surface 12a and the second major surface 12b and the first and second end surfaces 12e and 12f facing each other in the longitudinal direction L orthogonal to both the width direction W and the height direction T, .

The layered body 12 has a substantially rectangular parallelepipedal outer shape, and it is preferable that the corner portion and the ridge line portion are rounded. The corner portion is a portion where three sides of the layered body 12 intersect, and the ridgeline portion is a portion where two sides of the layered body 12 intersect. At least one of the first major surface 12a, the second major surface 12b, the first side surface 12c, the second side surface 12d, the first end surface 12e, and the second end surface 12f has irregularities .

The outer dimensions of the laminate 12 are set so that the dimension in the longitudinal direction L is 0.2 mm or more and 5.7 mm or less and the dimension in the width direction W is 0.1 mm or more and 5.0 mm or less, Is not less than 0.1 mm and not more than 5.0 mm. The external dimensions of the multilayer ceramic capacitor 10 can be measured by a micrometer.

The laminate 12 is divided into a pair of outer layer portions and inner layer portions in the width direction W. [ One of the pair of outer layer portions is a portion including the first main surface 12a of the layered body 12 and includes a first main surface 12a and a first inner electrode layer 141 which is closest to the first main surface 12a And a dielectric layer 13 interposed therebetween. The other of the pair of outer layers is a portion including the second main surface 12b of the layered body 12 and the second main surface 12b and the second inner electrode layer And a dielectric layer 13 disposed between the dielectric layers.

The inner layer portion is a region sandwiched between the pair of outer layer portions. That is, the inner layer portion is composed of a plurality of dielectric layers 13 that do not constitute an outer layer portion and all the inner electrode layers 14.

The number of laminated layers of the plurality of dielectric layers 13 is preferably 20 or more and 1000 or less. The thickness of each of the pair of outer layers preferably ranges from 30 占 퐉 to 850 占 퐉. The thickness of each of the plurality of dielectric layers 13 included in the inner layer portion is preferably 0.3 mu m or more and 30 mu m or less.

The dielectric layer 13 is made of a perovskite type compound containing Ba or Ti. As a material constituting the dielectric layer 13, dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, CaZrO3 or the like as a main component can be used. A material to which a Mn compound, a Mg compound, a Si compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, an Al compound, a V compound or a rare earth compound is added as a subcomponent to these main components may also be used.

The plurality of internal electrode layers 14 include a plurality of first internal electrode layers 141 connected to the first external electrodes 15 and a plurality of second internal electrode layers 142 connected to the second external electrodes 16 do.

The number of stacked layers of the plurality of internal electrode layers 14 is preferably 10 or more and 1000 or less. The thickness of each of the plurality of internal electrode layers 14 is preferably 0.3 mu m or more and 1.0 mu m or less.

As a material constituting the internal electrode layer 14, one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd and Au can be used. The internal electrode layer 14 may include dielectric particles having the same composition as that of the dielectric ceramics contained in the dielectric layer 13.

The first internal electrode layer 141 and the second internal electrode layer 142 are alternately arranged at equal intervals in the width direction W of the laminate body 12. The first internal electrode layer 141 and the second internal electrode layer 142 are disposed so as to face each other with the dielectric layer 13 interposed therebetween.

The first internal electrode layer 141 has a first counter electrode portion opposed to the second internal electrode layer 142 and a second counter electrode portion 141 extending from the first counter electrode portion toward the first end face 12e side of the multilayer body 12 1 extraction electrode unit.

The second internal electrode layer 142 includes a second counter electrode portion facing the first internal electrode layer 141 and a second counter electrode portion extending from the second counter electrode portion toward the second end face 12f side of the multilayer body 12 2 extraction electrode unit.

The dielectric layer 13 is formed between the counter electrode portion of the first internal electrode layer 141 and the counter electrode portion of the second internal electrode layer 142 to form a capacitance. As a result, the capacitor functions.

In the laminate body 12, the position between the opposing electrode portion and the first side face 12c as viewed from the height direction T of the layered body 12 is defined as a first side margin, And the position between the two side faces 12d is the second side margin. The position between the opposing electrode portion and the first end face 12e as viewed from the height direction T of the layered body 12 is defined as a first end margin and a position between the opposing electrode portion and the second end face 12f Is the second end margin.

The first end margin is constituted by a first drawing electrode portion of the first internal electrode layer 141 and a plurality of dielectric layers 13 adjacent to the first drawing electrode portion. The second end margin is constituted by a second extending electrode portion of the second internal electrode layer 142 and a plurality of dielectric layers 13 adjacent thereto.

The first external electrode 15 is formed on the first end face 12e. More specifically, the first external electrode 15 extends from the first end face 12e to the first major surface 12a and the second major surface 12b, and to the first side surface 12c and the second side surface 12d Respectively.

The second external electrode 16 is formed on the second end face 12f. More specifically, the second external electrode 16 extends from the second end face 12f to the first major surface 12a and the second major surface 12b, and to the first side surface 12c and the second side surface 12d Respectively.

The first external electrode 15 includes a first bake electrode layer 15a as a lower electrode layer and a plating layer 15b and a plating layer 15c provided on the first bake electrode layer 15a.

The second external electrode 16 includes a second baking electrode layer 16a as a lower electrode layer and a plating layer 16b and a plating layer 16c provided on the second baking electrode layer 16a.

The first bake electrode layer 15a and the second bake electrode layer 16a include a gap and glass and metal. Examples of the metal contained in the first and second baking electrode layers 15a and 16a include metals such as Ni, Cu, Ag, Pd, Au, and Ag-Pd alloys. As the metal, Cu or Ag having high malleability is preferably used. On the other hand, the metals contained in the first and second bake electrode layers 15a and 16a can be confirmed after polishing the multilayer ceramic capacitor 10 by using a wavelength dispersive X-ray analyzer (WDX). On the other hand, at the time of polishing, for example, the multilayer ceramic capacitor 10 is polished up to the center position in the width direction W to expose the cut surface orthogonal to the width direction W. [

The first bake electrode layer 15a and the second bake electrode layer 16a may be composed of a plurality of laminated layers. The first baking electrode layer 15a and the second baking electrode layer 16a are baked layers formed by applying a conductive paste containing glass and metal to the stacked body 12. [ The first and second baking electrode layers 15a and 16a may be formed by firing simultaneously with the internal electrode layer 14 or may be formed by firing the internal electrode layer 14 and then baking.

The maximum thickness of the first bake electrode layer 15a and the second bake electrode layer 16a is preferably 10 占 퐉 or more and 200 占 퐉 or less. The thickness of the first bake electrode layer 15a and the thickness of the second bake electrode layer 16a becomes thinner at the edge of the laminate 12. [

The details of the first baking electrode layer 15a and the second baking electrode layer 16a will be described later with reference to FIG.

As a material constituting the plating layer 15b, the plating layer 15c, the plating layer 16b and the plating layer 16c, one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd, Au and Sn, Based alloy.

For example, the plating layer 15b and the plating layer 16b are Ni plating layers, and the plating layers 15c and 16c are, for example, Sn plating layers. The Ni plating layer has a function of preventing the lower electrode layer from being eroded by the solder when the multilayer ceramic capacitor is mounted. The Sn plating layer has a function of facilitating the mounting of the multilayer ceramic capacitor by improving the wettability with the solder when the multilayer ceramic capacitor is mounted. The thickness per layer of the plated layer is preferably 1.5 탆 or more and 15.0 탆 or less. On the other hand, the plating layer may be composed of a single layer, or may be a Cu plating layer or an Au plating layer.

4 is a partial cross-sectional view showing in detail the baking electrode layer of the multilayer ceramic capacitor according to the first embodiment. The circular shape included in the first baking electrode layer 15a shown in Fig. 4 represents a gap or glass. The details of the first baking electrode layer 15a will be described with reference to FIG. The structure of the second bake electrode layer 16a is the same as that of the first bake electrode layer 15a, and thus the description thereof is omitted.

The first bake electrode layer 15a has a first region 15a1 and a second region 15a2 from the side of the layered body 12 toward the surface layer side of the first bake electrode layer 15a .

The first region 15a1 includes a considerable gap and glass. The first region 15a1 occupies most of the first baking electrode layer 15a. Since the first region 15a1 includes a gap, the first baking electrode layer 15a has cushioning property. As a result, it is possible to absorb an external load applied to the multilayer ceramic capacitor 10.

In the second region 15a2, the denseness of the metal is increased in the thickness direction from the surface layer. The second region 15a2 hardly contains glass and gaps. The surface of the second area 15a2 is made smooth. The thickness of the second region 15a2 is, for example, 0.1 占 퐉 or more and 10 占 퐉 or less. The thickness of the second region 15a2 is set to 0.1 mu m or more and a metal dense film is formed on the surfaces of the first baking electrode layer and the second baking electrode layer so as to improve the plating affinity or inhibit the penetration of plating, The reliability of the condenser 10 can be improved. On the other hand, the second area 15a2 is formed by rubbing the medium 20 (see FIG. 11) on the surface layer of the baking electrode by using the surface treatment apparatus 100 (see FIG. 6) as described later. Thus, by setting the thickness of the second region 15a2 to 10 mu m or less, damage to the laminate 12 can be suppressed, and chipping and cracking of the laminate 12 can be suppressed have.

On the other hand, the thickness of the second region 15a2 can be confirmed by observing the multilayer ceramic capacitor 10 after polishing by SEM. Concretely, for example, the multilayer ceramic capacitor 10 is polished to a position about half the dimension of the width direction W to expose a cut surface along the longitudinal direction L and the height direction T, The thickness from the edge connecting the first end face 12e to the first main surface 12a to the apex of the second region 15a2 located on the edge is measured. It is preferable that the average value of the thickness of the second region 15a2 obtained from the ten multilayer ceramic capacitors 10 be the thickness of the second region 15a2.

The second area 15a2 covers the first area 15a1. The moisture resistance of the layered product 12 can be improved by providing the second region 15a2 having a high density of metal on the surface layer side. In addition, since the surface of the second area 15a2 is made smooth, defects can be prevented from being formed in the plating layer 15b and the plating layer 15c when the plating layer 15b and the plating layer 15c are formed. Further, the continuity of the plating layer 15b and the plating layer 15c can be improved.

On the other hand, the second region 15a2 is formed by subjecting the first baking electrode layer 15a to a surface treatment in the surface treatment step of the baking electrode layer described later.

(Manufacturing Method of Multilayer Ceramic Capacitor)

5 is a flow chart showing a method of manufacturing a multilayer ceramic capacitor according to the first embodiment. A method of manufacturing the multilayer ceramic capacitor according to the first embodiment will be described with reference to FIG.

As shown in Fig. 5, when the multilayer ceramic capacitor 10 is manufactured, first, the ceramic dielectric slurry is prepared in the step S1. Specifically, the ceramic dielectric powder, the additive powder, the binder resin, the dissolving liquid and the like are dispersed and mixed to prepare the ceramic dielectric slurry. The ceramic dielectric slurry may be either solvent-based or aqueous-based. When a ceramic dielectric slurry is used as a water-based paint, a ceramic dielectric slurry is prepared by mixing a water-soluble binder, a dispersant, and the like and a dielectric material dissolved in water.

Next, in step S2, a ceramic dielectric sheet is formed. Specifically, the ceramic dielectric slurry is formed on a carrier film in the form of a sheet using a die coater, a gravure coater, a microgravure coater, or the like and dried to form a ceramic dielectric sheet. The thickness of the ceramic dielectric sheet is preferably 3 m or less from the viewpoint of downsizing and high capacity of the multilayer ceramic capacitor 10. [

Next, in step S3, a mother sheet is formed. Specifically, a conductive paste is applied to a ceramic dielectric sheet so as to have a predetermined pattern, thereby forming a mother sheet having a predetermined internal electrode pattern on a ceramic dielectric sheet. As a method of applying the conductive paste, a screen printing method, an inkjet method, a gravure printing method, or the like can be used. The thickness of the internal electrode pattern is preferably 1.5 占 퐉 or less from the viewpoint of downsizing and high capacity of the multilayer ceramic capacitor 10. [ On the other hand, as the mother sheet, a ceramic dielectric sheet not subjected to the above step S3 other than the mother sheet having the internal electrode pattern is also prepared.

Next, in step S4, a plurality of mother sheets are laminated. Specifically, a predetermined number of mother sheets made of only a ceramic dielectric sheet are stacked without internal electrode patterns formed. A predetermined number of the mother sheets provided with the internal electrode patterns are stacked thereon. Further, a predetermined number of mother sheets made of only a ceramic dielectric sheet are stacked without forming an internal electrode pattern thereon. As a result, a mother sheet group is constituted.

Next, in step S5, the mother sheet group is pressed to form a laminated block. More specifically, the mother sheet group is pressed in the stacking direction by the hydrostatic press or the rigid press to form the laminated block.

Next, in step S6, the laminated block is divided to form a laminated chip. More specifically, the laminated blocks are divided into a matrix shape by press-cutting, dicing or laser cutting, and are separated into a plurality of laminated chips.

Next, barrel polishing of the multilayer chip is performed in step S7. More specifically, the multilayer chip is enclosed in a small box called a barrel together with a medium ball having a higher hardness than the dielectric material, and the multilayer chip is polished by rotating the barrel. As a result, the edge portion and the ridge line portion of the multilayer chip become round.

Next, firing of the multilayer chip is performed in step S8. Specifically, the multilayer chip is heated, whereby the dielectric material and the conductive material contained in the multilayer chip are baked to form the multilayer body 12. The firing temperature is suitably set according to the dielectric material and the conductive material, and is preferably 900 DEG C or more and 1300 DEG C or less.

Next, in Step S9, conductive paste is applied to the first end face 12e and the second end face 12f of the layered product 12 by dipping or the like. The conductive paste includes conductive fine particles and the like as well as glass and resin.

Next, in step S10, the conductive paste applied to the layered product 12 is dried. Concretely, the conductive paste is subjected to hot air drying at a temperature of, for example, 60 占 폚 or more and 180 占 폚 or less for approximately 10 minutes.

Next, the dried conductive paste is baked in step S11. The baking temperature is preferably 700 ° C or higher and 900 ° C or lower. In this baking step, the disappearance of the eliminator causes a plurality of gaps to be formed in the baking electrode layer. In the state after the step S11), the baking electrode layer is in the state of the first region 15a1 from the laminate body 12 side to the surface layer side. That is, a gap is formed on the surface side of the baking electrode layer, and glass is included.

Next, the surface treatment of the baking electrode layer is performed in step S12. The surface layer of the baking electrode layer is polished by rubbing the medium 20 on the surface layer of the baking electrode layer by stirring a laminate provided with a baking electrode layer and a medium 20 described later (see Fig. 11) in a stirring tank 150 described later . As a result, the glass contained in the surface layer of the baking electrode is reduced and the surface layer of the baking electrode layer is made flat. As a result, the state of the surface layer of the baking electrode layer is modified to form the above-described second region 15a2 having a highly dense and smooth surface of the metal. The details of the surface treatment will be described with reference to Figs. 6 to 10. Fig.

6 is a view showing a surface treatment apparatus for carrying out the surface treatment of the baking electrode layer shown in Fig. 7 is a plan view of the stirring tank shown in Fig. 8 is a cross-sectional view of the stirring tank shown in Fig. 9 is a plan view showing the positional relationship between the stirring tank and the elastic member shown in Fig. The surface treatment apparatus 100 used in step S12 will be described with reference to Figs. 6 to 9. Fig.

6, the surface treatment apparatus 100 includes a first base portion 110, a second base portion 120, a third base portion 130, a vibration receiving plate 140, a stirring tank A detecting unit 200 for detecting a vibration state of the driving motor 150, the driving motor 160, the eccentric load 170, the plurality of elastic members 180, the driving motor supporting unit 190, and the stirring tank 150, And a driving motor control unit 210.

The first base portion 110 has a plate-like shape. The first base portion 110 constitutes a lower portion (lower portion) of the surface treatment apparatus 100. The first base portion 110 is installed on the bottom surface, and maintains the horizontality of the surface treatment apparatus 100.

The second base portion 120 has a substantially rectangular parallelepiped shape. The second base portion 120 functions as a support for supporting the load of the drive motor 160 and the eccentric load 170 supported by the vibration receiving plate 140, the stirring tank 150 and the vibration receiving plate 140 do. The second base portion 120 is configured to be able to penetrate the driving motor 160.

The third base portion 130 has a plate-like shape. The third base portion 130 is disposed on the second base portion 120. The third base portion 130 is configured to be able to penetrate the driving motor 160.

The first base portion 110, the second base portion 120, and the third base portion 130 may be formed of different independent members or may be integrally formed.

The vibration receiving plate 140 has a substantially plate-like shape. The vibration receiving plate (140) is supported by a plurality of elastic members (180). A driving motor supporting portion 190 is provided on a lower surface of the vibration receiving plate 140. The drive motor support portion 190 supports the drive motor 160 provided so that the eccentric load 170 is rotatable. The load imposed by the drive motor 160 and the eccentric load 170 is applied to the vibration receiving plate 140 via the drive motor support portion 190. [

The stirring tank arranging portion 145 is provided on the upper surface of the vibration receiving plate 140. The stirring tank 150 is disposed in the stirring tank arranging part 145.

As shown in Figs. 6 to 8, the stirring tank 150 has a cylindrical shape with a bottom. On the other hand, the stirring tank 150 has a bottom portion 151, a peripheral wall portion 152, a shaft portion 155, and a flange portion 156.

The bottom portion 151 has a substantially disc shape. The bottom portion 151 is made flat. On the other hand, the bottom portion 151 may not be flat. The peripheral wall portion 152 is connected to the peripheral edge of the bottom portion 151. The peripheral wall portion 152 rises upward from the peripheral edge of the bottom portion 151. The peripheral wall portion 152 includes a curved portion 153 connected to the bottom portion 151 and a cylindrical portion 154 extending linearly along the vertical direction. A flange portion 156 protruding in the radial direction is provided at the upper end of the cylindrical portion 154.

The shaft portion 155 is provided at the center of the bottom portion 151. The shaft portion 155 extends along the vertical direction. On the other hand, the shaft portion 155 may not be provided.

Further, the shape of the stirring tank 150 is not limited to a bottomed cylindrical shape, but may be a hemispherical shape or a bowl shape. When the stirring tank 150 has a hemispherical shape, the bottom portion 151 forms a hemispherical lower side, and the peripheral wall portion 152 forms a hemispherical upper side. Further, when the stirring tank 150 has a ball shape, the bottom portion 151 has a curved shape that expands downward.

On the other hand, as described later, a plurality of stacked chips and a plurality of media 20, in which a baking electrode layer is formed, are injected into the stirring tank 150.

The inner surface of the stirring tank 150 is preferably provided with a coating layer having flexibility such as urethane. Particularly, when handling a large-size multilayer chip having a length dimension larger than 2.0 mm, a width dimension larger than 1.2 mm, and a thickness dimension larger than 1.2 mm, there is a risk of cleavage and breakage of the multilayer chip, It is preferable to use a member having elasticity.

On the other hand, when handling a small-sized multilayer chip having a length dimension of 2.0 mm or less, a width dimension of 1.2 mm or less, and a thickness dimension of 1.2 mm or less, the coating layer may be omitted because there is less risk of cleavage and breakage.

The stirring tank 150 is preferably detachably disposed in the stirring tank arrangement portion 145. When handling the small-sized laminated chip as described above, the inside of the stirring tank 150 can be cleaned by separating the stirring tank 150. As a result, mixing of chips can be prevented.

On the other hand, the stirring tank 150, the stirring tank arranging portion 145, and the vibration receiving plate 140 may be formed separately or integrally.

6 and 9, the plurality of elastic members 180 are arranged at a predetermined pitch in the circumferential direction around the shaft portion 155 when viewed from the direction of extension of the shaft portion 155. As shown in Fig. The plurality of elastic members 180 are fixed on the base portion 130.

As shown in Fig. 6, the drive motor 160 has a rotation shaft 161 extending in the vertical direction. The driving motor 160 rotates the rotating shaft 161 to rotate the eccentric load 170 attached to the rotating shaft 161 around the rotating shaft 161.

By rotating the eccentric load 170, the center position of the vibration receiving plate 140 is varied, thereby causing a bias in the expansion and contraction of the plurality of elastic members 180. The stirring tank 150 can be vibrated as described above by using such a deviation of the expansion and contraction of the plurality of elastic members 180. [

The detection unit (200) detects the vibration state of the stirring tank (150). The detection result detected by the detection unit 200 is input to the drive motor control unit 210. [ As the detection unit 200, for example, an acceleration sensor or a laser displacement meter is used.

When the acceleration sensor is used as the detection unit 200, the vibration state of the stirring tank 150 can be detected by directly measuring the acceleration of the medium 20 at the time of vibration. As the acceleration sensor, for example, GH313A or GH613 (all manufactured by KEYENCE) can be employed as the sensor head, and GA-245 (manufactured by KEYENCE) can be used as the amplifier unit.

The acceleration of the medium 20 is preferably 2.5 G or more and 20.0 G or less. When the acceleration of the medium 20 is less than 2.5G, sufficient energy for extending the metal contained in the bake electrode layer can not be obtained. On the other hand, if the acceleration of the medium 20 is larger than 10.0 G, the damage to the multilayer chip becomes large.

When the laser displacement meter is used as the detection unit 200, the oscillation tank 150 can be detected by irradiating a laser to the stirring tank 150 to measure the movement amount of the stirring tank 150.

In this way, the vibration state of the stirring tank 150, more specifically, the frequency of the stirring tank 150 can be detected by measuring the acceleration of the medium 20 or the moving amount of the stirring tank 150.

The drive motor control unit 210 controls the operation of the drive motor 160 based on the detection result detected by the detection unit 200. [

10 is a flow chart showing in detail the step of performing the surface treatment of the baking electrode layer shown in Fig. The step S12 of performing the surface treatment of the baking electrode layer will be described in detail with reference to Fig.

10, in the step S12 of performing the surface treatment of the baking electrode layer, the first end face 12e and the second end face 12f facing each other in the step S121, A first main surface 12c and a second side surface 12d and a first main surface 12a and a second major surface 12b facing each other and a first bake electrode layer 15a is provided on the first end surface 12e A plurality of stacked bodies 12 provided with a second baking electrode layer 16a on the second end face 12f and a plurality of media (not shown in Fig.

The medium 20 has a spherical shape. The diameter of the medium 20 is preferably smaller than the diagonal line of the first end face 12e and the second end face 12f. With such a diameter, it is possible to easily separate the medium 20 and the laminated chip using a mesh-shaped body.

Specifically, the diameter of the medium 20 is preferably 0.2 mm or more and 2.0 mm or less, more preferably 0.4 mm or more and 1.0 mm or less.

As the material of the medium 20, for example, tungsten (which may be cobalt, super steel including chromium) or zirconium may be used. The surface of the medium 20 is preferably smooth, and the surface roughness Sa of the medium 20 is preferably 200 nm or less.

The specific gravity of the medium 20 is preferably 5 or more and 18 or less. If the specific gravity is too small, the kinetic energy of the medium 20 becomes small, and the metal exposed to the surface layer of the bake electrode layer can not be sufficiently extended. On the other hand, if the specific gravity is too large, it damages the stacked chips.

The hardness of the medium 20 is preferably 1000 HV or more and 2500 HV or less in terms of Vickers hardness. If the hardness is too small, the medium 20 is broken. If the hardness is too large, it damages the stacked chips.

It is preferable that the sum of the volumes of the plurality of stacked bodies 12 charged into the stirring tank 150 is equal to or less than half of the total volume of the plurality of media 20 charged into the stirring tank 150, More preferably 1/3 or less. If the amount of the plurality of stacked bodies 12 to the plurality of media 20 is excessively increased, the workability by the medium 20 becomes worse and cracks may be generated at the corners of the stacked body 12, Splits or breaks.

11 is a view showing a step of applying vibration energy to a plurality of stacked bodies and a plurality of media 20 in the step of imparting vibration to the stirring tank shown in Fig. As shown in Fig. 11, the center position of the drive motor 160 and the vibration receiving plate 140 is shifted by rotating the eccentric load 170 in the surface treatment apparatus 100. Fig. As a result, the oscillation receiving plate 140 is inclined, and the elongation and shrinkage of each of the plurality of elastic members 180 occurs. The inclination of the vibration receiving plate 140 also tilts the central axis C of the bottom portion 151 of the stirring tank 150 as well.

The position of the eccentric load 170 is continuously changed in accordance with the rotation so that the inclination of the vibration receiving plate 140 is changed in accordance with the position of the eccentric load 170. [ As a result, the position where the biasing of the elastic member 180 becomes large also shifts in the circumferential direction. As described above, the plurality of elastic members 180 expand and contract to oscillate from the plurality of elastic members 180 to the stirring tank 150 such that the inclination direction of the central axis C of the bottom portion 151 is continuously changed.

The slanting direction of the central axis C of the bottom portion 151 is also continuously changed so that the center axis C of the bottom portion 151 in the state before oscillating the tank 150 is oscillated, The laminate 12 and the medium 20 are stacked so as to form a spiral trajectory spirally surrounding the imaginary axis VL along the axial direction of the imaginary axis VL when the virtual axis VL of the imaginary axis VL is imaginary. Vibration is applied to the body (12) and the medium (20).

Vibrations of the stirring tank 150 are transmitted to the plurality of laminated chips put in the stirring tank 150 and the plurality of media 20 so that the plurality of laminated chips and the plurality of media 20 are spirally rotated and stirred. As a result, the medium 20 collides with the bake electrode layer to increase the surface layer of the bake electrode layer, thereby reducing the amount of glass contained in the surface layer of the bake electrode layer. As a result, the state of the surface layer of the baking electrode layer is modified to form the above-described second region 15a2 having a highly dense and smooth surface of the metal.

Since the stirring tank 150 itself is not rotated around the central axis C although the direction of inclination of the stirring tank 150 changes in the circumferential direction, The excessive force from the stirring tank 150 is not given to the laminate. As a result, cracking and breakage of the multilayer chip can be suppressed.

In the stirring tank 150, the vibration is largely transmitted to the laminated chip and the medium 20 put into the stirring tank 150 as they move away from the shaft portion 155 in the radial direction. Also, since the bottom portion 151 is inclined and the shaft portion 155 is also inclined, the shaft portion 155 is more likely to be subjected to vibration from the adjacent elastic members 180 as it approaches one of the plurality of elastic members 180.

A plurality of stacked chips and a plurality of media 20 are provided by arranging a plurality of stacked chips and a plurality of media 20 in a position away from the shaft portion 155 in the axial direction in the stirring tank 150, The vibration can be transmitted effectively. As a result, the surface treatment of the bake electrode layer can be performed more efficiently.

It is also preferable that the stirring tank 150 is vibrated so that the frequency of the stirring tank 150 resonates with the natural frequency of the stirring tank 150. The natural frequency is a frequency at which the vibration intensity is increased, that is, the processing energy is increased. The surface treatment of the baking electrode layer can be efficiently performed by vibrating the stirring tank 150 so that the frequency of the stirring tank 150 is a natural frequency.

The frequency of the stirring tank 150 can be adjusted by changing the speed at which the eccentric load 170 is rotated by the drive motor 160, for example. In order to perform such adjustment, the detection unit 200 detects the vibration state of the stirring tank 150. [

The driving motor control unit 210 determines that the frequency of the stirring tank 150 is close to the natural frequency of the stirring tank 150 when the detecting unit 200 detects that the frequency of the stirring tank 150 is deviated from the natural frequency The operation of the drive motor 160 is controlled.

Next, as shown in Fig. 5 again, the plating process is performed on the layered product 12 having the baking electrode layer in which the second region 15a2 is formed in the process S13. Ni plating and Sn plating are performed in this order on the baking electrode layer to form a plating layer 15b, a plating layer 16b, a plating layer 15c, and a plating layer 16c. As a result, the first external electrode 15 and the second external electrode 16 are formed on the outer surface of the layered body 12.

The multilayer ceramic capacitor 10 can be manufactured through the above-described series of steps.

As described above, the method for manufacturing a multilayer ceramic capacitor according to the first embodiment is characterized in that the first end face 12e and the second end face 12f located facing each other, the first side face 12c and the second side face 12c And a first main surface 12a and a second main surface 12b facing each other and having a first baking electrode layer 15a on the first end face 12e and a second baking electrode layer 15b on the second end face 12f, A plurality of stacked bodies 12 provided with a bake electrode layer 16a, a step of feeding a plurality of media 20 into a vessel, a step of vibrating the stirring tank 150 to form a plurality of stacked bodies 12 and a plurality of media 20 to the vibrational energy.

In the step of imparting vibration to the plurality of stacked bodies 12 and the plurality of media 20, the stacked body 12 and the media 20 are stacked on the virtual axis VL by vibrating the stirring tank 150. [ Vibration is applied to the laminate 12 and the medium 20 so as to form a helical trajectory spirally surrounding the imaginary axis VL along the axial direction. As described above, in the present embodiment, there is no case in which the stirring tank 150 is rotated about the center axis C of the bottom portion as compared with the sandblasting method in which the basket is rotated around the axis while spraying the abrasive powder on the laminate. Therefore, even when a plurality of stacked bodies 12 are brought into contact with the inner surface of the stirring tank 150, excessive force from the stirring tank 150 can be suppressed from being applied to the stacked body. As a result, cleavage and breakage of the multilayer chip can be suppressed.

The laminated body provided with the first baking electrode layer 15a and the second baking electrode layer 16a and the medium 20 are agitated by applying vibration energy to the plurality of stacked bodies 12 and the plurality of media 20, The surface layer of the baking electrode layer is polished by rubbing the medium 20 on the surface layer of the first baking electrode layer 15a and the second baking electrode layer 16a.

This reduces the amount of glass contained in the surface layers of the first and second baking electrode layers 15a and 16a and extends the metal contained in the first and second baking electrode layers 15a and 16a The surface layer of the first baking electrode layer 15a and the surface of the second baking electrode layer 16a are flattened. As a result, the surfaces of the first and second baking electrode layers 15a and 16a become smooth and the denseness of the metal can be enhanced on the surface side of the first baking electrode layer 15a and the second baking electrode layer 16a The first bake electrode layer 15a and the second bake electrode layer 16a can be modified.

(Embodiment 2)

(Multilayer Ceramic Capacitor)

12 is a partial cross-sectional view showing in detail the baking electrode layer of the multilayer ceramic capacitor manufactured according to the method for manufacturing a multilayer ceramic capacitor according to the second embodiment. The multilayer ceramic capacitor 10A manufactured according to the method for manufacturing a multilayer ceramic capacitor according to the second embodiment will be described with reference to FIG.

As shown in Fig. 12, the multilayer ceramic capacitor 10A according to the second embodiment differs from the multilayer ceramic capacitor 10 according to the first embodiment in that the first bake electrode layer 15aA and the second bake electrode layer City) is different. Other configurations are almost the same. On the other hand, since the structure of the second baking electrode layer is the same as that of the first baking electrode layer 15aA, a description thereof will be omitted.

In the first baking electrode layer 15aA, the second region 15a2 is in contact with the edge portion of the layered body 12. [ As an example, on the edge portion C1 connecting the first main surface 12a of the layered body 12 and the first end surface 12e of the layered body 12, a second region of the first baking electrode layer 15aA 15a2 are provided. Here, the corner portion C1 refers to a first imaginary line VL1 passing through a ridge portion where the first main surface 12a and the first side surface 12c intersect, Is a curved portion located inside the second imaginary line (VL2) passing through the ridge portion where the cross section (12e) and the first side surface (12c) intersect.

On the side of the first end face 12e on the first main surface 12a of the layered body 12, the first region 15a1 and the second region 15a1 of the first baking electrode layer 15aA 15a2 are provided in this order. The first region 12a of the first baking electrode layer 15aA from the side of the layered structure 12 on the side of the first end face 12e on the second main surface 12b of the layered body 12, A first area 15a1 and a second area 15a2 are provided in this order. A first region 15a1 and a second region 15a2 of the first baking electrode layer 15aA are provided on the first end face 12e of the layered body 12 from the side of the layered body 12.

The first baking electrode layer 15aA is formed by applying a conductive paste containing glass and a metal to the first end face 12e by dipping or the like and baking after drying. When the conductive paste is applied to the first end face 12e, it tends to become thin at the corner portion.

Therefore, the baking electrode layer formed when the conductive paste applied to the first end face 12e is baked also becomes thinner at the corner portion. When the baking electrode layer formed on the corner portion is considerably thin, only the second region 15a2 having a high density of metal and a smooth surface is formed by extending to the medium 20 when the surface treatment of the baking electrode layer is performed. The thickness of the second region 15a2 is, for example, 0.1 占 퐉 or more and 10 占 퐉 or less.

On the other hand, the baking electrode layer formed on the portion other than the corner portion is thicker than the baking electrode layer formed on the corner portion. Therefore, when the surface treatment of the baking electrode layer is performed, the second region 15a2 having a high density of metal and high surface smoothness is formed only on the surface layer side, and the first region 15a2, (15a1) is formed.

Particularly, in the case of handling a small-size multilayer chip having a length dimension of 1.6 mm or less, a width dimension of 0.8 mm or less and a thickness dimension of 0.8 mm or less, as described above, The metal tends to be elongated, and the structure of the multilayer ceramic capacitor 10A as in the second embodiment tends to be formed.

Even in the case of the above configuration, the moisture resistance of the layered product 12 can be improved by providing the second region 15a2 having a high metal denseness on the surface layer side of the first and second baking electrode layers.

In addition, since the surface of the second region 15a2 is smooth, defects can be prevented from being formed in the plating layer 15b and the plating layer 15c when the plating layer 15b and the plating layer 15c are formed. Further, the continuity of the plating layer 15b and the plating layer 15c can be improved.

In addition, since the first region 15a1 includes a gap, the first baking electrode layer 15a has cushioning property at portions other than the corner portions, so that it is possible to absorb external impact applied to the multilayer ceramic capacitor 10A .

(Manufacturing Method of Multilayer Ceramic Capacitor)

The method for manufacturing the multilayer ceramic capacitor 10A according to the second embodiment basically corresponds to the method for manufacturing the multilayer ceramic capacitor 10 according to the first embodiment.

When manufacturing the multilayer ceramic capacitor 10A in accordance with the method of manufacturing the multilayer ceramic capacitor 10A according to the second embodiment, substantially the same processes as the steps S1 to S8 according to the first embodiment are performed.

Next, in the process according to Step S9 according to Embodiment 1, the film thickness of the conductive paste on the edge portion of the layered product 12 is adjusted such that the thickness of the first main surface 12a and the second main surface 12b, The conductive paste is applied to the first end face 12e side and the second end face 12e so that the conductive paste applied to the first end face 12c and the second side face 12d becomes thinner than the film thickness of the conductive paste applied to the first end face 12e and the second end face 12f, 2 side face 12f side.

Next, the first baking electrode layer and the second baking electrode layer, which are formed so as to have a thickness corresponding to the edge portion of the layered body 12 thinner than the other portions, (Prepare) a plurality of stacked bodies provided with two bake electrode layers.

Next, in the step according to the step S12 according to the first embodiment, the plurality of stacked bodies and a plurality of the media 20 are put into the stirring tank 150. [ Vibrational energy is imparted to the plurality of stacked bodies 12 and the plurality of media 20 by vibrating the stirring tank 150. [ In the step of imparting vibration energy to the plurality of stacked bodies (12) and the plurality of media (20), a second region (15a2) having a highly dense and smooth surface of metal is formed in the baking electrode layer, Thereby forming a first region 15a1. At this time, the second region 15a2 is formed to be in contact with the edge portion of the layered body 12 in the portion corresponding to the corner portion of the layered body 12 in the baking electrode layer, and the layered body 12 A first region 15a1 is formed on the first region 15a1 and a second region 15a2 is formed to cover the first region 15a1.

Next, a process substantially similar to that of the process S13 according to the first embodiment is performed. The multilayer ceramic capacitor 10A according to the second embodiment is manufactured through the above-described steps.

As described above, also in the method of manufacturing the multilayer ceramic capacitor 10A according to the second embodiment, almost the same effect as the method of manufacturing the multilayer ceramic capacitor 10 according to the first embodiment can be obtained.

(Embodiment 3)

(Multilayer Ceramic Capacitor)

13 is a cross-sectional view of a multilayer ceramic capacitor manufactured according to the method of manufacturing a multilayer ceramic capacitor according to the third embodiment. The multilayer ceramic capacitor 10B manufactured according to the method for manufacturing a multilayer ceramic capacitor according to the third embodiment will be described with reference to FIG.

As shown in Fig. 13, the multilayer ceramic capacitor 10B according to the third embodiment is different from the multilayer ceramic capacitor 10 according to the first embodiment in that the first external electrode 15A and the second external electrode 16B The configuration is different. Other configurations are almost the same.

The first external electrode 15B includes a first baking electrode layer 15a and a resin layer 15d as a first resin layer and a plating layer 15b and a plating layer 15c in this order from the side of the multilayer body 12 do. The first bake electrode layer 15a and the resin layer 15d function as a lower electrode. The resin layer 15d is provided on the first baking electrode layer 15a. The resin layer 15d is provided between the first baking electrode layer 15a and the plating layer 15b.

The second external electrode 16B includes a second baking electrode layer 16a, a resin layer 16d as a second resin layer, a plating layer 16b, and a plating layer 16c in this order from the side of the layered body 12 do. The second baking electrode layer 16a and the resin layer 16d function as a lower electrode. The resin layer 16d is provided on the second baking electrode layer 16a. The resin layer 16d is provided between the second baking electrode layer 16a and the plating layer 16b.

The resin layer 15d and the resin layer 16d include conductive particles and a thermosetting resin. As the conductive particles, metal particles such as Cu or Ag can be used. As the thermosetting resin, for example, a phenol resin, an acrylic resin, a silicone resin, an epoxy resin, a polyimide resin, or the like can be used.

The resin layer 15d and the resin layer 16d may be composed of a plurality of laminated layers. The thickness of the resin layer 15d and the resin layer 16d is preferably 10 占 퐉 or more and 90 占 퐉 or less. The surface roughness Ra of the resin layer 15d and the resin layer 16d is 0.38 占 퐉 or less. Preferably, the surface roughness Ra of the resin layer 15d and the resin layer 16d is 0.30 占 퐉 or less.

Each of the resin layer 15d and the resin layer 16d has a portion where the metal particles are exposed at a ratio of 72.6% to 90.9%. For example, each of the resin layer 15d and the resin layer 16d has continuity in which metal particles are successively exposed in a predetermined range of 72.6% or more and 90.9% or less on the edge portion of the layered body 12 .

Preferably, each of the resin layer 15d and the resin layer 16d has a portion where the metal particles are exposed at a ratio of 80% or more and 90% or less. For example, each of the resin layer 15d and the resin layer 16d has continuity in which the metal particles are successively exposed at 80% or more and 90% or less in a predetermined range on the edge portion of the layered product 12 I have.

On the other hand, the metal particles may not be in the form of particles but may have a flat shape such as a film shape.

The continuity of the metal particles can be confirmed by observing the multilayer ceramic capacitor 10B after polishing and SEM observation. On the other hand, at the time of polishing, for example, the multilayer ceramic capacitor 10 is polished up to the center position in the width direction W to expose the cut surface orthogonal to the width direction W. [

14 is a cross-sectional view showing the state of the resin layer on the side of the center section of the end face of the multilayer ceramic capacitor according to the third embodiment. In Fig. 14, the resin layer 15d formed on the first end face side is shown, and the resin layer 16b formed on the second end face side is also configured similarly to the resin layer 15d.

As shown in Fig. 14, the surface of each of the resin layer 15d and the resin layer 16d is formed such that the metal particles extending in a flat shape are continuously aligned. On the other hand, the fact that the metal particles are continuously aligned includes not only an aspect in which neighboring metal particles are aligned with no gap in the alignment direction of the metal particles but also an aspect in which the metal particles are aligned with a gap .

The metal particles extending in a flat shape refer to metal particles extending along the extending direction of the outer surface of the resin layer on a predetermined cut surface across the external electrode. For example, in the central portion of the cross section perpendicular to the width direction W of the multilayer ceramic capacitor, the extending direction of the outer surface of the resin layer is parallel to the height direction of the multilayer ceramic capacitor, The particles are biased along the height direction of the multilayer ceramic capacitor.

The metal particles extending in a flat shape indicate that the length of the metal particles in the extending direction is larger than the thickness of the metal particles in the thickness direction of the resin layer (from the plating layer toward the baking electrode layer).

Even in the case of the above configuration, the moisture resistance of the layered product 12 can be improved by providing the second region 15a2 having a high metal denseness on the surface layer side of the first and second baking electrode layers.

Since the first area 15a1 includes a gap, the first baking electrode layer 15a has a cushioning property at portions other than the corner portions, so that it is possible to absorb the external impact applied to the multilayer ceramic capacitor 10B have.

The surface of the second region 15a2 is smooth so that the first baking electrode layer 15a and the resin layer 15d are formed at the end portions of the folded portions of the first external electrode 15B and the second external electrode 16B, The delamination between the second baking electrode layer 16a and the resin layer 16d is likely to occur. On the other hand, the surface roughness (Ra) of the second region is 0.38 占 퐉 or less. Preferably, the surface roughness (Ra) of the second region is 0.30 占 퐉 or less.

When the multilayer ceramic capacitor 10 is mounted on the mounting substrate, the mounting substrate is warped, so that an external force may be applied to the multilayer ceramic capacitor 10B. Such an external force is likely to be concentrated on the end side of the folded portion of the first external electrode 15B and the second external electrode 16B. When the above external force is concentrated at the end portion of the folded portion, delamination occurs at the boundary between the first bake electrode layer 15a and the resin layer 15d and at the boundary between the second bake electrode layer 16a and the resin layer 16d The stress acting on the laminate 12 can be relaxed. As a result, it is possible to prevent the stacked body 12 from being broken.

(Manufacturing Method of Multilayer Ceramic Capacitor)

15 is a flow chart showing a method of manufacturing a multilayer ceramic capacitor according to the third embodiment. A method of manufacturing the multilayer ceramic capacitor according to the third embodiment will be described with reference to FIG.

As shown in Fig. 15, when the multilayer ceramic capacitor 10B is manufactured according to the method of manufacturing the multilayer ceramic capacitor 10B according to the third embodiment, substantially the same process as in the first embodiment is performed in the steps S1 to S12 do.

Next, in step S13A, a thermosetting resin including conductive particles is applied on the first baking electrode layer 15a and the second baking electrode layer 16a, and this is heated and cured. As a result, the resin layer 15d and the resin layer 16d having conductivity are formed.

Next, in step S13A1, the surface treatment of the resin layer 15d and the resin layer 16d is performed. Specifically, the laminate 12 provided with the resin layer 15d and the resin layer 16d and the medium 20 are put into the stirring tank 150 in accordance with the step S12 according to the first embodiment. Vibrational energy is imparted to the plurality of stacked bodies 12 and the plurality of media 20 by vibrating the stirring tank 150 in the same manner as in the first embodiment.

The surface layer of the resin layer is polished by rubbing the medium 20 on the surface layer of the resin layers 15d and 16d in the step of imparting vibration energy to the plurality of stacked bodies 12 and the plurality of media 20. [ As a result, the metal particles in the surface layer of the resin layer extend in a flat shape. The surface of each of the resin layer 15d and the resin layer 16d is formed with the metal particles extended in this flat shape being continuously aligned. As a result, portions where the metal particles are exposed at a ratio of 72.6% to 90.9% are formed, and the surface of the resin layer 15d and the surface of the resin layer 16d are modified. Preferably, a portion where the metal particles are exposed in a ratio of 80% or more and 90% or less is formed.

The surface of the resin layers 15d and 16d is smoothed by exposing the metal particles to the surfaces of the resin layers 15d and 16d at a ratio of 72.6% to 90.9%. As a result, the plating property is improved and the surface state of the plating layer is improved. As a result, the mounting state of the solder at the time of mounting is also improved, so that defective solder at the time of mounting is also suppressed.

Subsequently, in step S13B, substantially the same processing as in step S13 according to the first embodiment is performed to form a plating layer 15b and a plating layer 15c on the resin layer 15d, and a plating layer 16b and a plated layer 16c are formed.

The multilayer ceramic capacitor 10B according to the third embodiment can be manufactured through the above-described steps.

As described above, also in the multilayer ceramic capacitor 10B according to the third embodiment, the second region 15a2 is formed in the surface layer of the baking electrode layer, the second region 15a2 having a high metal density and a smooth surface, A first region 15a1 having cushioning property is formed. Therefore, also in the multilayer ceramic capacitor 10B according to the third embodiment, almost the same effect as the multilayer ceramic capacitor 10 according to the first embodiment can be obtained.

In addition, since the resin layers 15d and 16d are provided, resin layers 15d and 16d having elasticity can be stacked even when the mounting substrate is warped in a state where the multilayer ceramic capacitor 10B is mounted on the mounting substrate. And elastically deforms according to the external force applied to the ceramic capacitor 10B to absorb the external force. As a result, it is possible to prevent the external force directly from acting on the stacked body 12, thereby preventing the stacked body 12 from being cracked. Thus, the multilayer ceramic capacitor 10B can exhibit its characteristics stably and reliability is improved.

When the external force is applied to the multilayer ceramic capacitor 10B as described above, the first baking electrode layer 15a and the resin layer 15d are formed by forming the resin layers 15d and 16d on the surface- The interlayer delamination occurs at the boundary portion between the second baking electrode layer 16a and the resin layer 16d, thereby relieving the stress acting on the layered body 12. This also makes it possible to further prevent cracks from being generated in the layered product 12. [ As a result, the multilayer ceramic capacitor 10B can exhibit its characteristics stably and reliability is further improved.

On the other hand, when the resin layers 15d and 16d are surface-treated using the sandblasting method instead of the step of applying the vibration energy to the laminate 12 and the plurality of media 20, Element, it is possible to extend the metal particles to some extent, but the surface roughness can not be improved. In addition, the cutting ability is deteriorated by attaching the cutting powder to the resin surface. As a result, defective solder in mounting can not be suppressed.

In the present embodiment, as described above, the surface of the resin layer is smoothed by imparting vibration energy to the plurality of stacked bodies 12 and the plurality of media 20, and the plating state, So that defective solder at the time of mounting can be suppressed. Thus, reliability of the multilayer ceramic capacitor in the mounted state can be improved.

(First verification test)

Fig. 16 is a diagram showing conditions and results of the first verification experiment performed to verify the effects of the embodiment. Fig. The first verification test conducted to verify the effects of the embodiment will be described with reference to FIG.

The first baking electrode layer 15a is provided on the side of the first end face 12e of the multilayer body 12 and the second baking electrode layer 15b is provided on the side of the second end face 12f, A plurality of stacked bodies 12 according to Examples 1 and 2 and Comparative Examples 1 to 7, each of which was provided with the resin layer 16a, were prepared. On the other hand, in the prepared state, the surface treatment is not performed on the first bake electrode layer 15a and the second bake electrode layer 16a.

Each stacked body 12 had a length dimension of 1.0 mm, a width dimension of 0.5 mm, and a height dimension of 0.5 mm.

The surface treatment of the baking electrode layer was performed on the laminate according to the prepared examples 1 and 2 and the comparative examples 1 to 7 using the surface treatment apparatus 100 described above so that the presence or absence of cracks and the surface of the baking electrode layer were modified I was checking to see if it was.

In Comparative Example 1, the sum of the volumes of the plurality of stacked bodies put into the stirring tank 150 was set to 1/2 of the total volume of the plurality of media 20 fed into the stirring tank 150. Further, the processing time was set to 7 hours, and the frequency of the stirring tank 150 was set to 15 Hz, which is smaller than the natural frequency of the stirring tank 150. [

In this case, no cracks occurred in the laminate after the surface treatment, but the surface condition was not improved. That is, the second region 15a2 could not be formed sufficiently.

In Comparative Example 2, the sum of the volumes of the plurality of stacked bodies put into the stirring tank 150 was set to 1/2 of the total volume of the plurality of media 20 injected into the stirring tank 150. Further, the processing time was set to 7 hours, and the frequency of the stirring tank 150 was set to 35 Hz, which is larger than the natural frequency of the stirring tank 150. [

In this case, no cracks occurred in the laminate after the surface treatment, but the surface condition was not improved. That is, the second region 15a2 could not be formed sufficiently.

In Comparative Example 3, the total volume of the plurality of stacked bodies put into the stirring tank 150 was set to 6/10 of the total of the volumes of the plurality of media 20 put into the stirring tank 150. Further, the processing time was set to 3 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after the surface treatment, cracks were formed in four stacked bodies among 100 stacked bodies. Further, the surface state was not improved, and the second region 15a2 could not be sufficiently formed.

In Comparative Example 4, the total volume of the plurality of stacked bodies put into the stirring tank 150 was set to 6/10 of the total volume of the plurality of media 20 to be fed into the stirring tank 150. Further, the processing time was set to 5 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after the surface treatment, cracks occurred in six stacked bodies among 100 stacked bodies. Further, the surface state was not improved, and the second region 15a2 could not be sufficiently formed.

In Comparative Example 5, the total volume of the plurality of stacked bodies put into the stirring tank 150 was set to 8/10 of the total volume of the plurality of media 20 charged into the stirring tank 150. Further, the processing time was set to 5 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after surface treatment, cracks were formed in 35 stacked bodies out of 100 stacked bodies. Further, the surface state was not improved, and the second region 15a2 could not be sufficiently formed.

In Comparative Example 6, the total of the volumes of the plurality of stacked bodies put into the stirring tank 150 was made equal to the sum of the volumes of the plurality of media 20 injected into the stirring tank 150. Further, the processing time was set to 5 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after the surface treatment, cracks were formed in 41 of the 100 stacked bodies. Further, the surface state was not improved, and the second region 15a2 could not be sufficiently formed.

In Comparative Example 7, the total volume of the plurality of stacked bodies put into the stirring tank 150 was made equal to the sum of the volumes of the plurality of media 20 put into the stirring tank 150. Further, the processing time was set to 7 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150. [

In this case, after surface treatment, cracks occurred in 58 stacked bodies among 100 stacked bodies. Further, the surface state was not improved, and the second region 15a2 could not be sufficiently formed.

The total volume of the plurality of stacked bodies put into the stirring tank 150 is set to 1/3 or less of the total volume of the plurality of media 20 charged into the stirring tank 150 ). Further, the processing time was set to 5 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after the surface treatment, the layered product was not cracked, and the surface state was improved. The second region 15a2 can be sufficiently formed on the surface layer of the bake electrode layer.

In the first embodiment, the total volume of the plurality of stacked bodies put into the stirring tank 150 is set to 1/2 of the total volume of the plurality of media 20 fed into the stirring tank 150. Further, the processing time was set to 5 hours, and the frequency of the stirring tank 150 was set to 23 Hz, which is equal to the natural frequency of the stirring tank 150.

In this case, after the surface treatment, the layered product was not cracked, and the surface state was improved. The second region 15a2 can be sufficiently formed on the surface layer of the bake electrode layer.

As described above, as shown in the results of Examples 1 and 2, by using the production method of the multilayer ceramic capacitor according to the present embodiment, the surface of the baking electrode layer provided in the multilayer body can be prevented from cracking It can be said that it can be reformed. It is possible to modify the surface of the baking electrode layer provided in the laminate while suppressing cleavage and breakage of the laminate.

The sum of the volumes of the plurality of stacked bodies 12 put into the stirring tank 150 is set to be a half of the total volume of the plurality of media 20 charged into the stirring tank 150 , It was confirmed that the workability of the medium 20 can be improved and cracks can be generated in the corner portion of the layered product 12 or that the layered product 12 can be prevented from splitting or cracking. The total volume of the plurality of stacked bodies 12 charged into the stirring tank 150 is set to 1/3 or less of the total volume of the plurality of media 20 charged into the stirring tank 150, It was confirmed that the state can be obtained.

Even if the processing time is shortened by setting the frequency of the stirring tank 150 to be the frequency of the stirring tank 150 as the frequency of the stirring tank 150 in comparison with the first and second embodiments and the first and second comparative examples, It is possible to prevent cracks or cracks or cracks in the stacked body 12, and the surface of the baking electrode layer can be modified. Thus, by making the frequency of the stirring tank 150 a unique frequency of the stirring tank 150, vibrations can be effectively transmitted to the plurality of stacked bodies and the plurality of media 20, and the surface treatment can be performed efficiently .

(Second verification test)

Specifically, in the second verification test, the first baking electrode layer 15a, the second baking electrode layer 16a, the resin layer 15d, and the resin layer 16d are formed on the layered body 12, A multilayer ceramic capacitor in a state before it was formed was prepared and observed using a metallurgical microscope and a scanning electron microscope.

On the other hand, in the second verification test, the resin layer 15d is provided on the first baking electrode layer 15a in the state where the surface treatment is not performed on the first baking electrode layer 15a and the second baking electrode layer 16a , And a resin layer 16d was formed on the second baking electrode layer 16a. That is, in the second verification test, the first bake electrode layer 15a and the second bake electrode layer 16a include only the first region described above, and the surface thereof is uneven.

17 is a cross-sectional view showing the state of the resin layer in the vicinity of the corner portion before the surface treatment in the second verification test conducted to verify the effect of the embodiment. 18 is a cross-sectional view showing the state of the resin layer in the vicinity of the corner after the surface treatment in the second verification test conducted to verify the effect of the embodiment. With reference to Figs. 17 and 18, the state of the resin layer in the vicinity of the corner on the second end face side before and after the surface treatment will be described.

17 and 18 show the state of the resin layer observed with a scanning electron microscope. The portion of the resin layer 16d that appears bright is the metal particle, and the black portion seen between the metal particles is the resin.

As shown in Fig. 17, in the resin layer near the corner portion before the surface treatment, the surface of the resin layer 16d was rugged according to the irregularities of the surface of the baking electrode layer. In addition, the metal particles located on the surface of the resin layer are often in the form of particles, and they are arranged to some extent with an interval.

As shown in Fig. 18, in the resin layer in the vicinity of the corner portion after the surface treatment, the surface of the resin layer 16d was not observed, and the surface of the resin layer 16d was smooth. The metal particles located on the surface of the resin layer were flat and arranged continuously.

Fig. 19 is a cross-sectional view showing the state of the resin layer at the central portion of the end surface before the surface treatment in the second verification test conducted to verify the effects of the embodiment. Fig. 20 is a cross-sectional view showing the state of the resin layer at the center of the end face after the surface treatment in the second verification test conducted to verify the effect of the embodiment. The state of the resin layer at the center of the cross section before and after the surface treatment will be described with reference to Figs. 19 and 20. Fig.

19 and 20 show the state of the resin layer observed with a scanning electron microscope. The portion of the resin layer 15d that appears bright is the metal particle, and the black portion seen between the metal particles is the resin.

As shown in Fig. 19, in the resin layer on the center side of the second end surface before the surface treatment, the surface of the resin layer 16d was rugged according to the irregularities on the surface of the baking electrode layer. In addition, the metal particles located on the surface of the resin layer 16d are often in the form of particles, and they are arranged to some extent with an interval.

20, unevenness was not observed on the surface of the resin layer 16d, and the surface of the resin layer 16d was smooth even in the resin layer 16d at the central portion of the second end face after the surface treatment. The metal particles located on the surface of the resin layer were flat and arranged continuously.

17 to 20, it was confirmed that the surface state of the resin layer was modified by performing the surface treatment on the resin layer based on the embodiment.

(Third verification test)

Fig. 21 is a diagram showing conditions and results of a third verification experiment performed to verify the effects of the embodiment. Fig. A third verification test conducted to verify the effects of the embodiment will be described with reference to FIG.

In the third verification test, the first baking electrode layer 15a, the second baking electrode layer 16a, the resin layer 15d and the resin layer 16d are formed on the laminate 12, Lt; / RTI > were prepared. As multilayer ceramic capacitors, multilayer ceramic capacitors according to Examples 3 to 6 and Comparative Examples 8 to 10 to be described later were prepared.

The surface state of the resin layer of these multilayer ceramic capacitors was observed to calculate the ratio of metal particles occupying the outer surface of the resin layer in a predetermined range. On the other hand, the ratio of the metal particles was calculated from the image observed using SEM. Specifically, the multilayer ceramic capacitor 10 was polished to a position in the center of the width direction W, and a cut surface orthogonal to the width direction W was exposed, and the cut surface was observed with an SEM.

The length of the surface of the resin layer was measured in the predetermined range determined in the SEM image and the total sum of the lengths of the metal particles contained in the surface of the resin layer was measured. The total sum of the lengths of the metal particles was divided by the length of the surface of the resin layer to calculate the ratio of the metal particles occupying the outer surface of the resin layer.

The surface roughness Ra of the resin layer 15d and the surface roughness Ra of the resin layer 16d were also measured.

Further, a plating layer was formed on these multilayer ceramic capacitors to observe the surface state of the plating layer. Further, the multilayer ceramic capacitor having the plating layer formed thereon was immersed in a solder bath to observe the wetted surface of the solder. At this time, the number of evaluations was 10, and the number of defects caused by the surface state of the plating layer among the ten plating layers was confirmed.

As the multilayer ceramic capacitors according to Examples 4 to 6, those having a resin layer surface-treated in accordance with the manufacturing method according to Embodiment 3 were used. The vibration frequency of the stirring tank 150 is set to 23 Hz which is the same as the natural frequency of the stirring tank 150 in the step of imparting vibration to the plurality of stacked bodies and the plurality of media in the surface treatment.

As the multilayer ceramic capacitor according to Comparative Example 8, a thermosetting resin including conductive particles is applied on the first baking electrode layer 15a and the second baking electrode layer 16a, and the resultant is heated and cured to form a resin layer, As the surface treatment, the surface of the resin layer was polished by sandblasting.

As the multilayer ceramic capacitor according to the comparative example 9, a thermosetting resin including conductive particles is applied on the first baking electrode layer 15a and the second baking electrode layer 16a, and this is heated and cured to form a resin layer, And those without surface treatment were used.

As the multilayer ceramic capacitor according to Comparative Example 10, the multilayer ceramic capacitor was subjected to surface treatment so as to reduce the vibration applied to the multilayer ceramic capacitor as compared with Examples 4 to 6. Specifically, in the step of imparting vibration to a plurality of stacked bodies and a plurality of media, the frequency of the stirring tank 150 is set to 15 Hz, which is smaller than those in Examples 4 to 6. [

In Example 3, the ratio of the metal particles occupying the outer surface of the resin layer was 72.6%, and the surface roughness (Ra) of the resin layer was 0.38 μm. In this case, the surface state of the plated layer was good. As a result, a multilayer ceramic capacitor having defects in observing the solder surface was not found.

In Example 4, the ratio of the metal particles occupying the outer surface of the resin layer was 83.1%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.33 탆. In this case, the surface state of the plated layer was very good. As a result, a multilayer ceramic capacitor having defects in observing the solder surface was not found.

In Example 5, the ratio of the metal particles occupying the outer surface of the resin layer was 85.2%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.33 탆. In this case, the surface state of the plated layer was very good. As a result, a multilayer ceramic capacitor having defects in observing the solder surface was not found.

In Example 6, the ratio of metal particles occupying the outer surface of the resin layer was 90.9%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.32 μm. In this case, the surface state of the plated layer was very good. As a result, a multilayer ceramic capacitor having defects in observing the solder surface was not found.

In Comparative Example 8, the ratio of the metal particles occupying the outer surface of the resin layer was 74.4%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.72 μm. In this case, the surface state of the plated layer was defective. As a result, defects were found in three multilayer ceramic capacitors among the ten multilayer ceramic capacitors in the observation of the solder surface.

In Comparative Example 9, the ratio of the metal particles occupying the outer surface of the resin layer was 61.2%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.75 占 퐉. In this case, the surface state of the plated layer was defective. As a result, in the observation of the solder surface, defects were found in one of the ten multilayer ceramic capacitors.

In Comparative Example 10, the ratio of metal particles occupying the outer surface of the resin layer was 68.7%, and the surface roughness (Ra) of the resin layers 15d and 16d was 0.75 占 퐉. In this case, the surface state of the plated layer was somewhat poor. On the other hand, a multilayer ceramic capacitor having defects in observing the solder surface was not found.

In consideration of the above results, in the comparative example 8, the metal layer included in the resin layer can be extended to some extent. However, since the surface treatment is carried out using the sandblasting method involving the cutting element, The part could not be alleviated. As a result, the plating state became defective, and defects were generated when the solder was adhered to the plating layer.

In Comparative Example 9, in a state where a thermosetting resin including conductive particles was applied on the first baking electrode layer 15a and the second baking electrode layer 16a and heated and cured to form a resin layer, The surface was bumpy because it was not done. As a result, the plating state became defective, and defects were generated when the solder was adhered to the plating layer.

In Comparative Example 10, surface treatment was performed in accordance with Embodiment 3 in comparison with Comparative Example 9. However, since the vibration applied to the multilayer ceramic capacitor was small, the surface of the resin layer could not be sufficiently improved. As a result, the plating state became somewhat defective. On the other hand, no defect was generated when the solder was attached to the plating layer.

In Examples 3 to 6, metal particles included in the resin layer were extended by surface treatment of the resin layer in accordance with Embodiment 3, whereby metal particles occupying the outer surface of the resin layer as compared with Comparative Example 9 Of the total. In Examples 3 to 6, the ratio of the metal particles occupying the outer surface of the resin layer was 72.6% or more and 90.9% or less.

Further, since the surface of the resin layer slides on the medium, the metal particles extend, and the surface roughness (Ra) of the resin layer is remarkably improved as compared with Comparative Examples 1 and 2. In Examples 3 to 6, the surface roughness (Ra) of the resin layer was also 0.38 占 퐉 or less. As a result, the plating state was good or very good, and defects were not generated when the solder was attached to the plating layer.

As described above, each surface layer of the resin layers 15d and 16d has a portion where the metal particles are exposed at a ratio of 72.6% to 90.9%, whereby the surface layer of the resin layer becomes dense and the surface roughness can be improved . It was confirmed that the plating property and the adhesion of the solder were improved by improving the surface roughness and the solder defect in the mounting was suppressed. As a result, it has been confirmed that the reliability of the multilayer ceramic capacitor can be improved.

It is also confirmed that the surface condition of the plating layer is improved by making the surface roughness (Ra) of the resin layer 0.38 占 퐉 or less, thereby improving the plating property and the adhesion of the solder, .

In the above-described Embodiments 1 to 3, the internal structure of the multilayer ceramic capacitor is not limited to the structure disclosed in Embodiments 1 to 3, and can be suitably changed.

In the above-described first to third embodiments, the case where the electronic component is a multilayer ceramic capacitor is described as an example. However, the present invention is not limited to this, and various electronic components including external electrodes such as piezoelectric parts, thermistors, and inductors can do.

On the other hand, in the third embodiment described above, the case where the surface treatment is performed on the bake electrode layer and the surface treatment is performed on the resin layer has been described. However, the present invention is not limited to this, A resin layer may be formed on the baking electrode layer, and the resin layer may be subjected to a surface treatment. In this case, too, the baking electrode layer includes a considerable gap and glass, and is constituted by the first region having cushioning property, so that it is possible to absorb an external load applied to the multilayer ceramic capacitor 10. As a result, the impact resistance is improved.

Further, as shown in the second verification test described above, the surface of the resin layer is modified and smoothed by performing the surface treatment on the resin layer. As a result, the plating can be adhered to the resin layer well, and deterioration of the adhesion of the plating in the corner portion can be prevented. As a result, it is possible to reduce mounting defects that occur when the multilayer ceramic capacitor 10 is mounted on the mounting substrate.

Further, since the resin layer is provided, even if the mounting board is warped in the state that the multilayer ceramic capacitor is mounted on the mounting board, the resin layer having elasticity is elastically deformed in accordance with the external force applied to the multilayer ceramic capacitor, do. As a result, it is possible to mitigate the action of the external force directly on the laminate, thereby preventing cracks from being generated in the laminate. Therefore, the multilayer ceramic capacitor can stably exhibit its characteristics and reliability is improved.

While the embodiments of the present invention have been described above, the embodiments disclosed herein are illustrative and non-restrictive in all respects. The scope of the present invention is defined by the appended claims, and includes all changes within the meaning and scope equivalent to the claims.

10, 10A, 10B: multilayer ceramic capacitor 12: laminate
12a: first main surface 12b: second main surface
12c: first side, 12d: second side
12e: first end face 12f: second end face
13: dielectric layer 14: internal electrode layer
15, 15A, 15B: first outer electrode 15a, 15aA: first baking electrode layer
15a1: first region 15a2: second region
15b, 15c: plating layer 15d, 16d: resin layer
16, 16B: second external electrode 16a: second baking electrode layer
16b, 16c: plating layer 16d: resin layer
20: Media 100: Surface treatment device
110: first base part 120: second base part
130: third base part 140: oscillating receiving plate
141: first internal electrode layer 142: second internal electrode layer
145: Arrangement part 150: Stirring tank
151: bottom part 152: peripheral wall part
153: bend section 154:
155: shaft portion 156: flange portion
160: Driving motor 161:
170: eccentric load 180: elastic member
190: driving motor support part 200:
210: drive motor control section

Claims (3)

A first side face and a second side face facing each other in a width direction orthogonal to the longitudinal direction and a first side face and a second side face which are perpendicular to the longitudinal direction and the width direction, A laminate including a first main surface and a second major surface facing each other in the height direction,
A first external electrode provided on the first end face,
And a second external electrode provided on the second end face,
Wherein the first external electrode includes a first bake electrode layer provided on the first end face and a first resin layer provided on the first bake electrode layer,
The second external electrode includes a second bake electrode layer provided on the second end face and a second resin layer provided on the second bake electrode layer,
Wherein each of the first and second baking electrode layers and the second baking electrode layer is provided on the laminate and has a region including a gap and a glass formed in the first and second baking electrode layers,
Wherein the first resin layer and the second resin layer include metal particles,
Wherein each of the surface layers of the first resin layer and the second resin layer has a portion in which the metal particles are exposed in a ratio of 72.6% to 90.9%. The method according to claim 1,
Wherein the metal particles are exposed at a ratio of 72.6% to 90.9%, the surface of each of the first resin layer and the second resin layer is in a state in which the metal particles having a flat shape are continuously aligned And an electronic component. 3. The method according to claim 1 or 2,
Wherein a surface roughness (Ra) of the first resin layer and a surface roughness (Ra) of the second resin layer are 0.38 탆 or less.

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