JP2018060999A - Electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component which enables the quality modification of a surface of each baked electrode layer provided on a laminate while suppressing cracking and chipping of the laminate.SOLUTION: An electronic component comprises: a laminate 12 including a first end face 12e and a second end face 12f, first and second side faces, and a first principal face 12a and a second principal face 12b; a first external electrode 15B; and a second external electrode 16B. The first external electrode 15B includes a first baked electrode layer 15a and a first resin layer 15d. The second external electrode 16B includes a second baked electrode layer 16a and a second resin layer 16d. The first baked electrode layer 15a and the second baked electrode layer 16a are each provided on the laminate 12, and have a region including cavities and glass. The first resin layer 15d and the second resin layer 16d each include metal particles. A surface layer of each of the first resin layer 15d and the second resin layer 16d has a portion where the metal particles are exposed at a rate of 72.6-90.9%.SELECTED DRAWING: Figure 13

Description

  The present invention relates to an electronic component including a laminate including dielectric layers and internal electrode layers that are alternately laminated.

  Conventionally, as a document disclosing a method for manufacturing a multilayer ceramic capacitor as an electronic component, for example, JP 2009-239204 A (Patent Document 1) is cited. In the method for manufacturing a multilayer ceramic capacitor disclosed in Patent Document 1, the end surface of a multilayer body having a substantially rectangular parallelepiped shape is immersed in a conductor paste, and after the paste is attached to the end surface, the paste attached to the end surface The shape of the paste adhered to the end face is adjusted by pressing a part of the laminate against the plate and pulling the laminate away from the plate. After repeating this several times, the conductive paste is sintered. An external electrode is formed by performing a plating process on the sintered conductive paste.

JP 2009-239204 A

  However, the multilayer ceramic capacitor manufactured by the method for manufacturing a multilayer ceramic capacitor disclosed in Patent Document 1 is vulnerable to impact and may not satisfy the characteristics as a capacitor.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an electronic component that is resistant to impact and excellent in reliability.

  An electronic component according to the present invention includes a first end surface and a second end surface positioned relative to a length direction, a first side surface and a second side surface positioned relative to a width direction orthogonal to the length direction, and A laminated body including a first main surface and a second main surface positioned relative to a height direction orthogonal to the length direction and the width direction; a first external electrode provided on the first end surface; A second external electrode provided on the second end surface, wherein the first external electrode is provided on the first baked electrode layer provided on the first end surface and the first baked electrode layer. The second external electrode includes a first resin layer, the second external electrode includes a second baked electrode layer provided on the second end surface, and a second resin layer provided on the second baked electrode layer. Each of 1 baking electrode layer and the said 2nd electrode layer is provided on the said laminated body, and a space | gap and glass The first resin layer and the second resin layer contain metal particles, and the surface layer of each of the first resin layer and the second resin layer contains 72.6% or more of the metal particles. It has a portion exposed at a rate of 90.9% or less.

  In the electronic component according to the present invention, the metal particles having a flat shape are continuously arranged in a portion where the metal particles are exposed at a ratio of 72.6% to 90.9%. Thus, it is preferable that the surfaces of the first resin layer and the second resin layer are formed.

  In the electronic component according to the present invention, the surface roughness Ra of the first resin layer and the surface roughness Ra of the second resin layer are preferably 0.38 μm or less.

  According to the present invention, it is possible to provide an electronic component that is resistant to impact and excellent in reliability.

1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment. It is sectional drawing along the II-II line of the multilayer ceramic capacitor shown in FIG. It is sectional drawing along the III-III line of the multilayer ceramic capacitor shown in FIG. 3 is a partial cross-sectional view showing details of a baked electrode layer of the multilayer ceramic capacitor according to Embodiment 1. FIG. 3 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor according to Embodiment 1. FIG. It is a figure which shows the surface treatment apparatus for implementing the surface treatment of the printing electrode layer shown in FIG. It is a top view of the stirring tank shown in FIG. It is sectional drawing of the stirring tank shown in FIG. It is a top view which shows the positional relationship of the stirring tank shown in FIG. 6, and an elastic member. It is a flowchart which shows the detail of the process of implementing the surface treatment of the baking electrode layer shown in FIG. It is a figure which shows the process of providing a vibration energy to a some laminated body and a some medium in the process of providing a vibration to the stirring tank shown in FIG. 6 is a partial cross-sectional view showing details of a baked electrode layer of a multilayer ceramic capacitor manufactured according to the method for manufacturing a multilayer ceramic capacitor according to Embodiment 2. FIG. 7 is a cross-sectional view of a multilayer ceramic capacitor manufactured according to the method for manufacturing a multilayer ceramic capacitor according to Embodiment 3. FIG. FIG. 6 is a cross-sectional view showing a state of a resin layer on the end surface center side of a multilayer ceramic capacitor according to a third embodiment. 10 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor according to Embodiment 3. FIG. It is a figure which shows the conditions and result of a 1st verification experiment implemented in order to verify the effect of embodiment. It is sectional drawing which shows the state of the resin layer of the corner | angular vicinity before surface treatment in the 2nd verification experiment implemented in order to verify the effect of embodiment. It is sectional drawing which shows the state of the resin layer of the corner | angular part vicinity after surface treatment in the 2nd verification experiment implemented in order to verify the effect of embodiment. It is sectional drawing which shows the state of the resin layer of the end surface center part side before surface treatment in the 2nd verification experiment implemented in order to verify the effect of embodiment. It is sectional drawing which shows the state of the resin layer of the end surface center part side after surface treatment in the 2nd verification experiment implemented in order to verify the effect of embodiment. It is a figure which shows the conditions and result of a 3rd verification experiment implemented in order to verify the effect of embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment described below, a multilayer ceramic capacitor is exemplified as an electronic component, and a method of manufacturing a multilayer ceramic capacitor is illustrated as a method of manufacturing the electronic component. In the following embodiments, the same or common parts are denoted by the same reference numerals in the drawings, and description thereof will not be repeated.

(Embodiment 1)
(Multilayer ceramic capacitor)
1 is a perspective view of a multilayer ceramic capacitor manufactured according to the method of manufacturing a multilayer ceramic capacitor according to Embodiment 1. FIG. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG.

  As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a multilayer body (ceramic body) 12, a first external electrode 15, and a second external electrode 16.

  The laminate 12 has a substantially rectangular parallelepiped outer shape. The stacked body 12 includes a plurality of dielectric layers 13 and a plurality of internal electrode layers 14 that are stacked. The laminate 12 includes a first side surface 12c and a second side surface 12d that are opposed in the width direction W, a first main surface 12a and a second main surface 12b that are opposed in the height direction T orthogonal to the width direction W, and the width direction. It includes a first end face 12e and a second end face 12f that face each other in the length direction L orthogonal to both W and the height direction T.

  Although the laminated body 12 has a substantially rectangular parallelepiped outer shape, it is preferable that corners and ridge lines are rounded. The corner portion is a portion where three surfaces of the laminate 12 intersect, and the ridge line portion is a portion where two surfaces of the laminate 12 intersect. Irregularities may be formed on at least one of the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, the first end surface 12e, and the second end surface 12f.

  The outer dimensions of the laminate 12 are, for example, the dimension in the length direction L is 0.2 mm or more and 5.7 mm or less, the dimension in the width direction W is 0.1 mm or more and 5.0 mm or less, and the width direction W The dimension is 0.1 mm or more and 5.0 mm or less. The external dimensions of the multilayer ceramic capacitor 10 can be measured with a micrometer.

  The laminated body 12 is divided into a pair of outer layer portions and inner layer portions in the width direction W. One of the pair of outer layer portions is a portion including the first main surface 12a of the multilayer body 12, and is between the first main surface 12a and a first internal electrode layer 141 (described later) closest to the first main surface 12a. It is comprised with the dielectric material layer 13 located in. The other of the pair of outer layer portions is a portion including the second main surface 12b of the multilayer body 12, and is between the second main surface 12b and a second internal electrode layer 142 described later that is closest to the second main surface 12b. It is comprised with the dielectric material layer 13 located in.

  The inner layer portion is a region sandwiched between a pair of outer layer portions. That is, the inner layer portion is composed of a plurality of dielectric layers 13 that do not constitute the outer layer portion, and all the internal electrode layers 14.

  The number of laminated dielectric layers 13 is preferably 20 or more and 1000 or less. The thickness of each of the pair of outer layer portions is preferably 30 μm or more and 850 μm or less. The thickness of each of the plurality of dielectric layers 13 included in the inner layer portion is preferably 0.3 μm or more and 30 μm or less.

  The dielectric layer 13 is made of a perovskite type compound containing Ba or Ti. As a material constituting the dielectric layer 13, dielectric ceramics mainly composed of BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like can be used. In addition, a material in which a Mn compound, Mg compound, Si compound, Fe compound, Cr compound, Co compound, Ni compound, Al compound, V compound or rare earth compound is added as a minor component to these main components is used. Also good.

  The plurality of internal electrode layers 14 include a plurality of first internal electrode layers 141 connected to the first external electrodes 15 and a plurality of second internal electrode layers 142 connected to each of the second external electrodes 16.

  The number of laminated internal electrode layers 14 is preferably 10 or more and 1000 or less. The thickness of each of the plurality of internal electrode layers 14 is preferably 0.3 μm or more and 1.0 μm or less.

  As a material constituting the internal electrode layer 14, one type of metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au can be used. The internal electrode layer 14 may include dielectric particles having the same composition as the dielectric ceramics included in the dielectric layer 13.

  The first internal electrode layers 141 and the second internal electrode layers 142 are alternately arranged at equal intervals in the width direction W of the multilayer body 12. The first internal electrode layer 141 and the second internal electrode layer 142 are disposed so as to face each other with the dielectric layer 13 interposed therebetween.

  The first internal electrode layer 141 includes a first counter electrode portion facing the second internal electrode layer 142 and a first lead extended from the first counter electrode portion to the first end face 12e side of the multilayer body 12. It is comprised from the electrode part.

  The second internal electrode layer 142 includes a second counter electrode portion facing the first internal electrode layer 141, and a second lead extended from the second counter electrode portion toward the second end face 12f of the multilayer body 12. It is comprised from the electrode part.

  The dielectric layer 13 is positioned between the counter electrode portion of the first internal electrode layer 141 and the counter electrode portion of the second internal electrode layer 142, thereby forming a capacitance. Thereby, the function of the capacitor is generated.

  In the multilayer body 12, when viewed from the height direction T of the multilayer body 12, the position between the counter electrode portion and the first side surface 12c is the position between the first side margin and the counter electrode portion and the second side surface 12d. Is the second side margin. Further, when viewed from the height direction T of the multilayer body 12, the position between the counter electrode portion and the first end surface 12e is the first end margin, and the position between the counter electrode portion and the second end surface 12f is the second end. It is a margin.

  The first end margin is configured by the first extraction electrode portion of the first internal electrode layer 141 and the plurality of dielectric layers 13 adjacent thereto. The second end margin is configured by the second extraction electrode portion of the second internal electrode layer 142 and the plurality of dielectric layers 13 adjacent thereto.

  The first external electrode 15 is formed on the first end face 12e. More specifically, the first external electrode 15 is formed to extend from the first end surface 12e to the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d.

  The second external electrode 16 is formed on the second end face 12f. More specifically, the second external electrode 16 is formed so as to extend from the second end surface 12f to the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d.

  The first external electrode 15 includes a first baked electrode layer 15a as a base electrode layer, and a plating layer 15b and a plating layer 15c provided on the first baked electrode layer 15a.

  The second external electrode 16 includes a second baking electrode layer 16a as a base electrode layer, and a plating layer 16b and a plating layer 16c provided on the second baking electrode layer 16a.

  The first baked electrode layer 15a and the second baked electrode layer 16a include voids, glass, and a metal. Examples of the metal contained in the first baked electrode layer 15a and the second baked electrode layer 16a include appropriate metals such as Ni, Cu, Ag, Pd, Au, and Ag—Pd alloy. As the metal, Cu and Ag having high malleability are preferably used. The metal contained in the first baked electrode layer 15a and the second baked electrode layer 16a can be confirmed using a wavelength dispersive X-ray analyzer (WDX) after polishing the multilayer ceramic capacitor 10. In the polishing, for example, the multilayer ceramic capacitor 10 is polished to the center position in the width direction W to expose a cross section orthogonal to the width direction W.

  The 1st baking electrode layer 15a and the 2nd baking electrode layer 16a may be comprised by the laminated | stacked several layer. The first baked electrode layer 15a and the second baked electrode layer 16a are layers obtained by applying a conductive paste containing glass and metal to the laminate 12 and baking it. The first baked electrode layer 15a and the second baked electrode layer 16a may be formed by baking simultaneously with the internal electrode layer 14, or may be formed by baking after baking the internal electrode layer 14.

  The maximum thickness of the first baked electrode layer 15a and the second baked electrode layer 16a is preferably 10 μm or more and 200 μm or less. The thicknesses of the first baked electrode layer 15 a and the second baked electrode layer 16 a are reduced at the corners of the stacked body 12.

  The details of the first baked electrode layer 15a and the second baked electrode layer 16a will be described later with reference to FIG.

  As a material constituting the plating layer 15b, the plating layer 15c, the plating layer 16b, and the plating layer 16c, one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or this metal is used. Consists of alloy containing.

  For example, the plating layer 15b and the plating layer 16b are Ni plating layers, and the plating layers 15c and 16c are, for example, Sn plating layers. The Ni plating layer has a function of preventing the base electrode layer from being eroded by solder when the multilayer ceramic capacitor is mounted. The Sn plating layer has a function of improving the wettability with the solder when mounting the multilayer ceramic capacitor and facilitating the mounting of the multilayer ceramic capacitor. The thickness of each plating layer is preferably 1.5 μm or more and 15.0 μm or less. The plating layer may be composed of a single layer, or a Cu plating layer or an Au plating layer.

  FIG. 4 is a partial cross-sectional view showing details of a baked electrode layer of the multilayer ceramic capacitor according to the first embodiment. The circular thing contained in the 1st baking electrode layer 15a shown in FIG. 4 represents the space | gap or glass. With reference to FIG. 4, the detail of the 1st baking electrode layer 15a is demonstrated. In addition, since the structure of the 2nd baking electrode layer 16a is the same as that of the 1st baking electrode layer 15a, the description is abbreviate | omitted.

  As shown in FIG. 4, the 1st baking electrode layer 15a has 1st area | region 15a1 and 2nd area | region 15a2 toward the surface layer side of the 1st baking electrode layer 15a from the laminated body 12 side.

  The first region 15a1 includes a considerable amount of voids and glass. The first region 15a1 occupies most of the first baking electrode layer 15a. When the first region 15a1 includes a gap, the first baking electrode layer 15a has a cushioning property. Thereby, it is possible to absorb an external impact applied to the multilayer ceramic capacitor 10.

  The second region 15a2 has high metal density in the thickness direction from the surface layer. The second region 15a2 is substantially free of glass and voids. The surface of the second region 15a2 is configured smoothly. The thickness of the second region 15a2 is, for example, not less than 0.1 μm and not more than 10 μm. The thickness of the second region 15a2 is set to 0.1 μm or more, and a metal dense film is formed on the surfaces of the first and second baked electrode layers, thereby improving the plating property and preventing the penetration of the plating. The reliability of the multilayer ceramic capacitor 10 can be improved. In addition, the 2nd area | region 15a2 is formed by rubbing the medium 20 (refer FIG. 11) to the surface layer of a baking electrode using the surface treatment apparatus 100 (refer FIG. 6) so that it may mention later. For this reason, by setting the thickness of the second region 15a2 to 10 μm or less, damage to the stacked body 12 can be suppressed, and chipping of the stacked body 12 can be suppressed.

  The thickness of the second region 15a2 can be confirmed by SEM observation after the multilayer ceramic capacitor 10 is polished. Specifically, for example, by polishing the multilayer ceramic capacitor 10 to a position about ½ of the dimension in the width direction W, the cross section along the length direction L and the height direction T is exposed, and the first end face 12e. The thickness from the corner connecting the first main surface 12a to the apex of the second region 15a2 located on the corner is measured. The average value of the thicknesses of the second regions 15a2 obtained from the ten multilayer ceramic capacitors 10 is preferably the thickness of the second regions 15a2.

  The second area 15a2 covers the first area 15a1. By providing the second region 15a2 having a high metal density on the surface layer side, the moisture resistance of the stacked body 12 can be improved. Moreover, when the surface of 2nd area | region 15a2 is comprised smoothly, when forming the plating layer 15b and the plating layer 15c, it can suppress that a defect is formed in the plating layer 15b and the plating layer 15c. . Moreover, the continuity of the plating layer 15b and the plating layer 15c can be improved.

  In addition, the 2nd area | region 15a2 is formed by surface-treating to the 1st baking electrode layer 15a and the 2nd baking electrode layer 16a in the surface treatment process of the baking electrode layer mentioned later.

(Manufacturing method of multilayer ceramic capacitor)
FIG. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor according to the first embodiment. With reference to FIG. 5, a method of manufacturing the multilayer ceramic capacitor according to the first embodiment will be described.

  As shown in FIG. 5, when manufacturing the multilayer ceramic capacitor 10, first, a ceramic dielectric slurry is prepared in step S1. Specifically, ceramic dielectric powder, additive powder, binder resin, solution, and the like are dispersed and mixed, thereby preparing a ceramic dielectric slurry. The ceramic dielectric slurry may be either solvent-based or water-based. When the ceramic dielectric slurry is used as a water-based paint, a ceramic dielectric slurry is prepared by mixing a water-soluble binder, a dispersing agent, and the like with a dielectric material dissolved in water.

  Next, a ceramic dielectric sheet is formed in step S2. Specifically, the ceramic dielectric sheet is formed by forming the ceramic dielectric slurry into a sheet shape using a die coater, a gravure coater, a micro gravure coater or the like on the carrier film and drying it. The thickness of the ceramic dielectric sheet is preferably 3 μm or less from the viewpoint of miniaturization and higher capacity of the multilayer ceramic capacitor 10.

  Next, a mother sheet is formed in step S3. Specifically, by applying a conductive paste to the ceramic dielectric sheet so as to have a predetermined pattern, a mother sheet provided with a predetermined internal electrode pattern on the ceramic dielectric sheet is formed. As a method for applying the conductive paste, a screen printing method, an ink jet method, a gravure printing method, or the like can be used. The thickness of the internal electrode pattern is preferably 1.5 μm or less from the viewpoint of reducing the size and increasing the capacity of the multilayer ceramic capacitor 10. As the mother sheet, in addition to the mother sheet having the internal electrode pattern, a ceramic dielectric sheet not subjected to the step S3 is also prepared.

  Next, in step S4, a plurality of mother sheets are laminated. Specifically, a predetermined number of mother sheets made of only ceramic dielectric sheets without any internal electrode pattern are laminated. On top of that, a predetermined number of mother sheets provided with internal electrode patterns are laminated. Further, a predetermined number of mother sheets made of only ceramic dielectric sheets without any internal electrode pattern are laminated thereon. Thereby, a mother sheet group is configured.

  Next, in step S5, the mother sheet group is pressure-bonded to form a laminated block. Specifically, the mother sheet group is pressed in the laminating direction by a hydrostatic pressure press or a rigid body press and pressed to form a laminated block.

  Next, in step S6, the laminated block is divided to form a laminated chip. Specifically, the laminated blocks are divided into a matrix by pressing, dicing or laser cutting, and separated into a plurality of laminated chips.

  Next, barrel polishing of the laminated chip is performed in step S7. Specifically, the multilayer chip is enclosed in a small box called a barrel together with a media ball having a hardness higher than that of the dielectric material, and the multilayer chip is polished by rotating the barrel. Thereby, the corner | angular part and ridgeline part of a laminated chip are rounded.

  Next, in step S8, the multilayer chip is fired. Specifically, the multilayer chip is heated, whereby the dielectric material and the conductive material included in the multilayer chip are baked, and the multilayer body 12 is formed. The firing temperature is appropriately set according to the dielectric material and the conductive material, and is preferably 900 ° C. or higher and 1300 ° C. or lower.

  Next, in step S9, a conductive paste is applied to the first end surface 12e and the second end surface 12f of the laminate 12 by a dipping method or the like. The conductive paste contains a loss agent such as glass and resin in addition to the conductive fine particles and the like.

  Next, in step S10, the conductive paste applied to the laminate 12 is dried. Specifically, the conductive paste is dried with hot air for about 10 minutes at a temperature of 60 ° C. or higher and 180 ° C. or lower, for example.

  Next, in step S11, the dried conductive paste is baked. The baking temperature is preferably 700 ° C. or higher and 900 ° C. or lower. In this baking step, the disappearance agent disappears, whereby a plurality of voids are formed in the baking electrode layer. In the subsequent state of step S11), the baked electrode layer is in the state of the first region 15a1 from the laminated body 12 side to the surface layer side. That is, on the surface layer side of the baked electrode layer, voids are formed and glass is included.

  Next, in step S12, the surface treatment of the baked electrode layer is performed. In a stirring tank 150 to be described later, a layered body provided with a baking electrode layer and a medium 20 (see FIG. 11) to be described later are stirred to rub the baking electrode layer while rubbing the medium 20 on the surface layer of the baking electrode layer. The surface layer of is polished. Thereby, while reducing the glass contained in the surface layer of a baking electrode, the surface layer of a baking electrode layer is made flat. As a result, the state of the surface layer of the baked electrode layer is modified, and the above-mentioned second region 15a2 having a high metal density and a smooth surface is formed. Details of the surface treatment will be described with reference to FIGS.

  FIG. 6 is a view showing a surface treatment apparatus for performing the surface treatment of the baked electrode layer shown in FIG. FIG. 7 is a plan view of the stirring tank shown in FIG. FIG. 8 is a cross-sectional view of the stirring tank shown in FIG. FIG. 9 is a plan view showing the positional relationship between the stirring tank shown in FIG. 6 and the elastic member. The surface treatment apparatus 100 used in step S12 will be described with reference to FIGS.

  As shown in FIG. 6, the surface treatment apparatus 100 includes a first base part 110, a second base part 120, a third base part 130, a vibration receiving plate 140, a stirring tank 150 as a container, a drive motor 160, and an eccentric load 170. , A plurality of elastic members 180, a drive motor support unit 190, a detection unit 200 that detects a vibration state of the stirring tank 150, and a drive motor control unit 210.

  The first base part 110 has a plate shape. The first base part 110 constitutes the lower part of the surface treatment apparatus 100. The first base unit 110 is installed on the floor surface and maintains the level of the surface treatment apparatus 100.

  The second base portion 120 has a substantially rectangular parallelepiped shape. The second base portion 120 functions as a base for supporting the loads of the vibration receiving plate 140, the stirring tank 150, the driving motor 160 supported by the vibration receiving plate 140 and the eccentric load 170. The second base portion 120 is configured to be able to penetrate the drive motor 160.

  The third base portion 130 has a plate shape. The third base part 130 is placed on the second base part 120. The third base portion 130 is configured to be able to penetrate the drive motor 160.

  The 1st base part 110, the 2nd base part 120, and the 3rd base part 130 may be comprised by the independent separate member, and may be comprised integrally.

  The vibration receiving plate 140 has a substantially plate shape. The vibration receiving plate 140 is supported by a plurality of elastic members 180. A drive motor support portion 190 is provided on the lower surface side of the vibration receiving plate 140. The drive motor support 190 supports the drive motor 160 to which the eccentric load 170 is rotatably attached. Thereby, the load by the drive motor 160 and the eccentric load 170 is applied to the vibration receiving plate 140 via the drive motor support portion 190.

  Further, on the upper surface side of the vibration receiving plate 140, a stirring tank mounting portion 145 is provided. The stirring tank 150 is mounted on the stirring tank mounting portion 145.

  As shown in FIGS. 6 to 8, the stirring tank 150 has a bottomed cylindrical shape. The stirring tank 150 has a bottom portion 151, a peripheral wall portion 152, a shaft portion 155, and a flange portion 156.

  The bottom part 151 has a substantially disk shape. The bottom 151 is configured to be flat. Note that the bottom 151 may not be flat. The peripheral wall portion 152 is connected to the periphery of the bottom portion 151. The peripheral wall portion 152 rises upward from the periphery of the bottom portion 151. The peripheral wall portion 152 includes a curved portion 153 connected to the bottom portion 151 and a cylindrical portion 154 extending linearly along the vertical direction. A flange portion 156 that protrudes in the radial direction is provided at the upper end of the cylindrical portion 154.

  The shaft portion 155 is provided at the center of the bottom portion 151. The shaft portion 155 extends along the vertical direction. Note that the shaft portion 155 may not be provided.

  Moreover, the shape of the stirring tank 150 is not limited to a bottomed cylindrical shape, and may be a hemispherical shape or a bowl shape. When the agitation tank 150 has a hemispherical shape, the bottom 151 constitutes the lower side of the hemispherical shape, and the peripheral wall portion 152 constitutes the upper side of the hemispherical shape. Further, when the stirring tank 150 has a bowl shape, the bottom 151 has a curved shape that bulges downward.

  In addition, as will be described later, a plurality of laminated chips on which a baked electrode layer is formed and a plurality of media 20 are put into the stirring tank 150.

  The inner surface of the stirring tank 150 is preferably provided with a flexible coating layer such as urethane. In particular, when dealing with a large-sized multilayer chip having a length dimension larger than 2.0 mm, a width dimension larger than 1.2 mm, and a thickness dimension larger than 1.2 mm, there is a concern about chipping of the multilayer chip. Therefore, it is preferable to use an elastic member such as rubber as the coating layer.

  On the other hand, when handling a small multilayer chip having a length dimension of 2.0 mm or less, a width dimension of 1.2 mm or less, and a thickness dimension of 1.2 mm or less, there is less fear of cracking chipping, The coating layer may be omitted.

  The agitation tank 150 is preferably placed on the agitation tank placement part 145 so as to be removable. When handling a small laminated chip as described above, the inside of the stirring tank 150 can be cleaned by removing the stirring tank 150. Thereby, mixing of a chip can be prevented.

  The agitation tank 150, the agitation tank mounting part 145, and the vibration receiving plate 140 may be formed separately or integrally.

  As shown in FIGS. 6 and 9, the plurality of elastic members 180 are arranged at a predetermined pitch in the circumferential direction around the shaft portion 155 when viewed from the extending direction of the shaft portion 155. The plurality of elastic members 180 are fixed on the base portion 130.

  As shown in FIG. 6, the drive motor 160 has a rotating shaft 161 extending in the vertical direction. The drive motor 160 rotates the rotating shaft 161 to rotate the eccentric load 170 attached to the rotating shaft 161 around the rotating shaft.

  By rotating the eccentric load 170, the position of the center of gravity of the vibration receiving plate 140 fluctuates, so that the elastic members 180 expand and contract. The stirring tank 150 can be vibrated as described above by utilizing such bias of expansion and contraction of the plurality of elastic members 180.

  The detection unit 200 detects the vibration state of the stirring tank 150. A detection result detected by the detection unit 200 is input to the drive motor control unit 210. As the detection unit 200, for example, an acceleration sensor or a laser displacement meter is used.

  When an acceleration sensor is used as the detection unit 200, the vibration state of the agitation tank 150 can be detected by directly measuring the acceleration of the medium 20 during vibration. As the acceleration sensor, for example, GH313A or GH613 (both manufactured by Keyence Corporation) can be employed as the sensor head, and GA-245 (manufactured by Keyence Corporation) can be employed as the amplifier unit.

  The acceleration of the medium 20 is preferably 2.5G or more and 20.0G or less. When the acceleration of the medium 20 is less than 2.5 G, it is not possible to obtain sufficient energy for extending the metal contained in the baked electrode layer. On the other hand, when the acceleration of the medium 20 is greater than 10.0 G, damage to the multilayer chip is increased.

  When a laser displacement meter is used as the detection unit 200, the vibration state of the stirring tank 150 can be detected by irradiating the stirring tank 150 with a laser and measuring the amount of movement of the stirring tank 150.

  Thus, by measuring the acceleration of the medium 20 or the amount of movement of the stirring tank 150, the vibration state of the stirring tank 150, more specifically, the vibration frequency of the stirring tank 150 can be detected.

  The drive motor control unit 210 controls the operation of the drive motor 160 based on the detection result detected by the detection unit 200.

  FIG. 10 is a flowchart showing details of a step of performing the surface treatment of the baking electrode layer shown in FIG. With reference to FIG. 10, the detail of process S12 which implements the surface treatment of a baking electrode layer is demonstrated.

  As shown in FIG. 10, in step S <b> 12 for performing the surface treatment of the baked electrode layer, first, in step S <b> 121, the first end surface 12 e and the second end surface 12 f that are positioned relative to each other, It includes a side surface 12c and a second side surface 12d, and a first main surface 12a and a second main surface 12b that are positioned opposite to each other. A plurality of laminates 12 provided with two baking electrode layers 16a and a plurality of media (not shown in FIG. 10) are put into a stirring tank 150.

  The medium 20 has a spherical shape. The diameter of the medium 20 is preferably smaller than the diagonal line of the first end surface 12e and the second end surface 12f. By setting it as such a diameter, the media 20 and a lamination | stacking chip | tip can be easily isolate | separated using a mesh-shaped sieve.

  Specifically, the diameter of the medium 20 is preferably 0.2 mm or more and 2.0 mm or less, and preferably 0.4 mm or more and 1.0 mm or less.

  As the material of the medium 20, for example, tungsten (which may be super steel containing cobalt or chromium) or zirconium can be used. The surface of the medium 20 is preferably smooth, and the surface roughness Sa of the medium 20 is preferably 200 nm or less.

  The specific gravity of the medium 20 is preferably 5 or more and 18 or less. If the specific gravity is too small, the kinetic energy of the medium 20 becomes small, and the metal exposed to the surface layer of the baked electrode layer cannot be sufficiently extended. On the other hand, if the specific gravity is too large, the laminated chip is damaged.

  The medium 20 preferably has a Vickers hardness of 1000 HV to 2500 HV. If the hardness is too small, the media 20 will crack. If the hardness is too large, the laminated chip will be damaged.

  Moreover, it is preferable that the sum total of the volume of the some laminated body 12 thrown in in the stirring tank 150 is 1/2 or less of the sum total of the volume of the some medium 20 thrown into the stirring tank 150, and 1/3. More preferably, it is as follows. If the amount of the plurality of laminated bodies 12 with respect to the plurality of media 20 is excessively increased, the workability by the media 20 is deteriorated, and cracks are generated at the corners of the laminated body 12, or the laminated body 12 is chipped or broken.

  FIG. 11 is a diagram illustrating a step of applying vibration energy to the plurality of stacked bodies and the plurality of media 20 in the step of applying vibration to the stirring tank illustrated in FIG. 10 illustrated in FIG. 10. As shown in FIG. 11, by rotating the eccentric load 170 in the surface treatment apparatus 100, the gravity center positions of the drive motor 160 and the vibration receiving plate 140 are shifted. As a result, the vibration receiving plate 140 is inclined, and the expansion and contraction of each of the plurality of elastic members 180 is biased. Further, when the vibration receiving plate 140 is inclined, the central axis C of the bottom portion 151 of the stirring tank 150 is also inclined.

  As the position of the eccentric load 170 changes continuously with the rotation, the inclination of the vibration receiving plate 140 changes according to the position of the eccentric load 170. As a result, the position where the bias of expansion and contraction of the elastic member 180 becomes large also moves in the circumferential direction. As the plurality of elastic members 180 expand and contract in this way, vibration is propagated from the plurality of elastic members 180 to the agitation tank 150 so that the inclination direction of the central axis C of the bottom portion 151 changes continuously.

  When the inclination direction of the central axis C of the bottom portion 151 is also continuously changed, when an annular virtual axis VL that surrounds the central axis C of the bottom portion 151 in the state before the stirring tank 150 is vibrated is assumed. Vibration is applied to the stacked body 12 and the medium 20 so that the stacked body 12 and the medium 20 draw a spiral trajectory that spirally surrounds the virtual axis VL along the axial direction of the virtual axis VL.

  The vibration of the agitation tank 150 is transmitted to the plurality of laminated chips and the plurality of media 20 put in the agitation tank 150, whereby the plurality of laminated chips and the plurality of media 20 are agitated while spirally rotating. The Thereby, the medium 20 extends the surface layer of the baking electrode layer while colliding with the baking electrode layer, thereby reducing the glass contained in the surface layer of the baking electrode layer. As a result, the state of the surface layer of the baked electrode layer is modified, and the above-mentioned second region 15a2 having a high metal density and a smooth surface is formed.

  Moreover, although the inclination direction of the stirring tank 150 changes in the circumferential direction, since the stirring tank 150 itself does not rotate around the central axis C, even when the laminated chip contacts the stirring tank 150 An excessive force is not applied to the laminate from the stirring tank 150. Thereby, the cracking chip of the laminated chip can be suppressed.

  In the stirring tank 150, the vibration is greatly transmitted to the laminated chip and the medium 20 that are put in the stirring tank 150 as the distance from the shaft portion 155 in the radial direction increases. Further, since the bottom portion 151 is inclined and the shaft portion 155 is also inclined, the closer the shaft portion 155 is to any one of the plurality of elastic members 180, the easier it is to receive vibration from the adjacent elastic members 180.

  For this reason, by providing a structure in which a plurality of laminated chips and a plurality of media 20 are retained in a position away from the shaft portion 155 in the radial direction in the agitation tank 150, an effect is exerted on the plurality of laminated chips and the plurality of media 20. Vibration can be transmitted. Thereby, the surface treatment of the baked electrode layer can be performed more efficiently.

  Moreover, it is preferable to vibrate the stirring tank 150 so that the frequency of the stirring tank 150 resonates with the natural frequency of the stirring tank 150. The natural frequency is a frequency at which the vibration intensity increases, that is, the processing energy increases. The surface treatment of the baking electrode layer can be efficiently performed by vibrating the stirring tank 150 so that the frequency of the stirring tank 150 becomes the natural frequency.

  The frequency of the stirring tank 150 can be adjusted, for example, by changing the speed at which the eccentric load 170 is rotated by the drive motor 160. In order to perform such adjustment, the detection unit 200 detects the vibration state of the agitation tank 150.

  When the detection unit 200 detects that the frequency of the stirring tank 150 is deviated from the natural frequency, the drive motor control unit 210 determines that the frequency of the stirring tank 150 is equal to the natural frequency of the stirring tank 150. The operation of the drive motor 160 is controlled so as to approach.

  Next, as shown in FIG. 5 again, in step S13, the laminated body 12 having the baked electrode layer in which the second region 15a2 is formed is plated. Ni plating and Sn plating are performed in this order on the baked electrode layer to form a plating layer 15b, a plating layer 16b, a plating layer 15c, and a plating layer 16c. Thereby, the first external electrode 15 and the second external electrode 16 are formed on the outer surface of the multilayer body 12.

  The multilayer ceramic capacitor 10 can be manufactured through the series of steps described above.

  As described above, the manufacturing method of the multilayer ceramic capacitor according to the first embodiment includes the first end surface 12e and the second end surface 12f that are positioned relative to each other, the first side surface 12c and the second side surface 12d that are positioned relative to each other, and The first baked electrode layer 15a is provided on the first end surface 12e, and the second baked electrode layer 16a is provided on the second end surface 12f. A step of putting a plurality of laminates 12 and a plurality of media 20 into a container, and a step of applying vibration energy to the plurality of laminates 12 and the plurality of media 20 by vibrating the agitation tank 150. .

  In the step of applying vibration to the plurality of stacked bodies 12 and the plurality of media 20, the stacked body 12 and the media 20 are caused to vibrate along the virtual axis VL along the axial direction of the virtual axis VL by vibrating the stirring tank 150. A vibration is applied to the laminate 12 and the medium 20 so as to draw a spiral trajectory surrounding the medium. As described above, in the present embodiment, the stirring tank 150 is not rotated around the central axis C at the bottom as compared with the sandblasting method in which the basket is rotated around the axis while the polishing powder is sprayed on the laminated body. For this reason, even if it is a case where the some laminated body 12 contacts the stirring tank 150, it can suppress that an excessive force is applied to a laminated body from the stirring tank 150. FIG. As a result, cracking of the laminated chip can be suppressed.

  Further, by applying vibration energy to the plurality of laminated bodies 12 and the plurality of media 20, the laminated body provided with the first baked electrode layer 15a and the second baked electrode layer 16a and the medium 20 are stirred, and the first The surface layer of the baked electrode layer is polished while the medium 20 is rubbed against the surface layers of the baked electrode layer 15a and the second baked electrode layer 16a.

  Thereby, the glass contained in the surface layer of the 1st baked electrode layer 15a and the 2nd baked electrode layer 16a reduces, and while extending the metal contained in the 1st baked electrode layer 15a and the 2nd baked electrode layer 16a, the 1st baked electrode The surface layers of the layer 15a and the second baking electrode layer 16a are flattened. As a result, the surfaces of the first baked electrode layer 15a and the second baked electrode layer 16a become smooth, and the metal denseness can be increased on the surface layer side of the first baked electrode layer 15a and the second baked electrode layer 16a. The surfaces of the first baked electrode layer 15a and the second baked electrode layer 16a can be modified.

(Embodiment 2)
(Multilayer ceramic capacitor)
FIG. 12 is a partial cross-sectional view illustrating details of a baked electrode layer of the multilayer ceramic capacitor manufactured according to the method for manufacturing the multilayer ceramic capacitor according to the second embodiment. With reference to FIG. 12, a multilayer ceramic capacitor 10A manufactured according to the method of manufacturing a multilayer ceramic capacitor according to the second embodiment will be described.

  As shown in FIG. 12, the multilayer ceramic capacitor 10A according to the second embodiment has a first baked electrode layer 15aA and a second baked electrode layer (not shown) when compared with the multilayer ceramic capacitor 10 according to the first embodiment. ) Is different. Other configurations are almost the same. In addition, since the structure of the 2nd baking electrode layer is the same as that of the 1st baking electrode layer 15aA, the description is abbreviate | omitted.

  In the 1st baking electrode layer 15aA, it has the structure which the 2nd area | region 15a2 contacts the corner | angular part of the laminated body 12. FIG. As an example, only the second region 15a2 of the first baking electrode layer 15aA is provided on the corner portion C1 that connects the first main surface 12a of the multilayer body 12 and the first end surface 12e of the multilayer body 12. Yes. Here, when viewed from the width direction W, the corner portion C1 refers to the first imaginary line VL1 that passes through the ridge line portion where the first main surface 12a and the first side surface 12c intersect, the first end surface 12e, and the first end surface 12e. It is a curved part located inside the 2nd virtual line VL2 which passes the ridgeline part which the side surface 12c crosses.

  On the other hand, on the first end surface 12e side on the first main surface 12a of the multilayer body 12, the first region 15a1 and the second region 15a2 of the first baking electrode layer 15aA are sequentially provided from the multilayer body 12 side. Although not shown in FIG. 12, similarly, on the first end surface 12 e side on the second main surface 12 b of the multilayer body 12, the first region 15 a 1 of the first baking electrode layer 15 a A from the multilayer body 12 side and The second region 15a2 is provided in order. On the first end surface 12e of the multilayer body 12, the first region 15a1 and the second region 15a2 of the first baking electrode layer 15aA are provided from the multilayer body 12 side.

  The first baking electrode layer 15aA is formed by applying the conductive paste containing glass and metal to the first end surface 12e by a dipping method or the like, and baking after drying. When applying the conductive paste to the first end face 12e, the corner tends to be thin.

  For this reason, the baking electrode layer formed when baking the electrically conductive paste apply | coated to the 1st end surface 12e also becomes thin in a corner | angular part. When the baked electrode layer formed at the corner is considerably thin, it is extended to the medium 20 when the surface treatment of the baked electrode layer is performed, so that the second region has a high metal density and a smooth surface. Only 15a2 is formed. The thickness of the second region 15a2 is, for example, not less than 0.1 μm and not more than 10 μm.

  On the other hand, the baked electrode layer formed in a portion other than the corner is thicker than the baked electrode layer formed in the corner. Therefore, when the surface treatment of the baked electrode layer is performed, the second region 15a2 having a high metal density and a smooth surface is formed only on the surface layer side, and voids and glass remain on the laminate 12 side. The first region 15a1 thus formed is formed.

  In particular, in the case of handling a small laminated chip having a length dimension of 1.6 mm or less, a width dimension of 0.8 mm or less, and a thickness dimension of 0.8 mm or less, as described above, the surface treatment is performed. The metal of the baked electrode layer at the corner tends to extend during the process, and there is a tendency to have the configuration of the multilayer ceramic capacitor 10A as in the second embodiment.

  Even when configured as described above, the second region 15a2 having a high metal density is provided on the surface layer side of the first and second baked electrode layers. Can be improved.

  Moreover, when the surface of 2nd area | region 15a2 is comprised smoothly, when forming the plating layer 15b and the plating layer 15c, it suppresses that a defect is formed in the plating layer 15b and the plating layer 15c. Can do. Moreover, the continuity of the plating layer 15b and the plating layer 15c can be improved.

  In addition, since the first region 15a1 includes a gap, the first baked electrode layer 15a has a cushioning property in a portion other than the corner portion, and can absorb an external impact applied to the multilayer ceramic capacitor 10A. it can.

(Manufacturing method of multilayer ceramic capacitor)
The method for manufacturing the multilayer ceramic capacitor 10A according to the second embodiment is basically the same as the method for manufacturing the multilayer ceramic capacitor 10 according to the first embodiment.

  When manufacturing the multilayer ceramic capacitor 10A according to the method for manufacturing the multilayer ceramic capacitor 10A according to the second embodiment, processes substantially similar to those in the steps S1 to S8 according to the first embodiment are performed.

  Next, in the step according to step S9 according to the first embodiment, the film thickness of the conductive paste on the corners of the laminate 12 is such that the first main surface 12a and a part of the second main surface 12b, the first The conductive paste is applied to the first end face 12e side and the second end face so as to be thinner than the part of the side face 12c and the second side face 12d, and the thickness of the conductive paste applied to the first end face 12e and the second end face 12f. It is applied to the end face 12f side.

  Next, substantially the same processing as in step S10 and step S11 according to the first embodiment was performed, and the thickness of the portion corresponding to the corner portion of the laminate 12 was configured to be thinner than the thickness of the other portions. A plurality of laminated bodies provided with the first baked electrode layer and the second baked electrode layer are formed (prepared).

  Next, in the step based on step S12 according to the first embodiment, the plurality of laminated bodies and the plurality of media 20 are charged into the stirring tank 150. And vibration energy is provided to the some laminated body 12 and the some media 20 by vibrating the stirring tank 150. FIG. In the step of applying vibration energy to the plurality of laminates 12 and the plurality of media 20, the baking electrode layer includes a second region 15a2 having a high metal density and a smooth surface, glass, and voids. One region 15a1 is formed. At this time, in the portion corresponding to the corner portion of the multilayer body 12 in the baking electrode layer, the second region 15a2 is formed so as to contact the corner portion of the multilayer body 12, and in the other portion, the multilayer body 12 is formed. A first region 15a1 is formed on the side, and a second region 15a2 is formed so as to cover the first region 15a1.

  Next, substantially the same process as step S13 according to the first embodiment is performed. Through the steps described above, the multilayer ceramic capacitor 10A according to the second embodiment is manufactured.

  As described above, even in the method for manufacturing the multilayer ceramic capacitor 10A according to the second embodiment, substantially the same effect as the method for manufacturing the multilayer ceramic capacitor 10 according to the first embodiment can be obtained.

(Embodiment 3)
(Multilayer ceramic capacitor)
FIG. 13 is a cross-sectional view of a multilayer ceramic capacitor manufactured according to the method of manufacturing a multilayer ceramic capacitor according to the third embodiment. With reference to FIG. 13, a multilayer ceramic capacitor 10B manufactured according to the method of manufacturing a multilayer ceramic capacitor according to Embodiment 3 will be described.

  As shown in FIG. 13, the multilayer ceramic capacitor 10B according to the third embodiment is different from the multilayer ceramic capacitor 10 according to the first embodiment in the configuration of the first external electrode 15A and the second external electrode 16B. . Other configurations are almost the same.

  The first external electrode 15B includes a first baking electrode layer 15a, a resin layer 15d as a first resin layer, a plating layer 15b, and a plating layer 15c in order from the laminated body 12 side. The first baked electrode layer 15a and the resin layer 15d function as a base electrode. The resin layer 15d is provided on the first baking electrode layer 15a. The resin layer 15d is provided between the first baking electrode layer 15a and the plating layer 15b.

  The second external electrode 16B includes a second baking electrode layer 16a, a resin layer 16d as a second resin layer, a plating layer 16b, and a plating layer 16c in order from the laminated body 12 side. The second baked electrode layer 16a and the resin layer 16d function as a base electrode. The resin layer 16d is provided on the second baking electrode layer 16a. The resin layer 16d is provided between the second baking electrode layer 16a and the plating layer 16b.

  The resin layer 15d and the resin layer 16d include conductive particles and a thermosetting resin. As the conductive particles, metal particles such as Cu or Ag can be used. As the thermosetting resin, for example, phenol resin, acrylic resin, silicone resin, epoxy resin, polyimide resin or the like can be used.

  The resin layer 15d and the resin layer 16d may be composed of a plurality of stacked layers. The thickness of the resin layer 15d and the resin layer 16d is preferably 10 μm or more and 90 μm or less. The surface roughness Ra of the resin layer 15d and the resin layer 16d is 0.38 μm or less. Preferably, the surface roughness Ra of the resin layer 15d and the resin layer 16d is 0.30 μm or less.

  Each of the resin layer 15d and the resin layer 16d has a portion where the metal particles are exposed at a rate of 72.6% or more and 90.9% or less. For example, each of the resin layer 15d and the resin layer 16d has a continuity in which metal particles are continuously exposed at 72.6% or more and 90.9% or less in a predetermined range on the corner portion of the laminate 12. Have

  Preferably, each of resin layer 15d and resin layer 16d has a portion where metal particles are exposed at a rate of 80% or more and 90% or less. For example, each of the resin layer 15d and the resin layer 16d has a continuity in which metal particles are continuously exposed at 80% or more and 90% or less in a predetermined range on the corners of the laminate 12.

  Note that the metal particles do not have to be in the form of particles, and may be flat, for example, like a film.

  The continuity of the metal particles can be confirmed by SEM observation after polishing the multilayer ceramic capacitor 10B. In the polishing, for example, the multilayer ceramic capacitor 10 is polished to the center position in the width direction W to expose a cross section orthogonal to the width direction W.

  FIG. 14 is a cross-sectional view showing a state of the resin layer on the end face center portion side of the multilayer ceramic capacitor according to the third embodiment. Although FIG. 14 shows the resin layer 15d formed on the first end face side, the resin layer 16 formed on the second end face side is also configured in the same manner as the resin layer 15d.

  As shown in FIG. 14, the surface of each of the resin layer 15d and the resin layer 16d is formed by continuously arranging metal particles extended into a flat shape. Note that the term “metal particles are continuously arranged” does not mean only an aspect in which adjacent metal particles are arranged with no gap in the direction in which the metal particles are arranged, but also includes an aspect in which the metal particles are arranged with a gap. Shall be.

  Moreover, the metal particle extended in the flat shape points out the metal particle extended along the extension direction of the outer surface of a resin layer in the predetermined cross section which crosses an external electrode. For example, in the central portion of the end face in the cross section perpendicular to the width direction W of the multilayer ceramic capacitor, the extending direction of the outer surface of the resin layer is parallel to the height direction of the multilayer ceramic capacitor and is extended into a flat shape. The metal particles are ubiquitous along the height direction of the multilayer ceramic capacitor.

  Further, the metal particles extended into a flat shape are such that the length of the metal particles in the extending direction is greater than the thickness of the metal particles in the thickness direction of the resin layer (the direction from the plating layer toward the baking electrode layer). Point to the big one.

  Even when configured as described above, the second region 15a2 having a high metal density is provided on the surface layer side of the first and second baked electrode layers. Can be improved.

  In addition, since the first region 15a1 includes a gap, the first baked electrode layer 15a has a cushioning property in a portion other than the corner portion, and can absorb an external impact applied to the multilayer ceramic capacitor 10B. it can.

  Further, since the surface of the second region 15a2 is configured smoothly, the first baked electrode layer 15a and the resin layer 15d are formed on the end portions of the first external electrode 15B and the folded portion of the second external electrode 16B. Delamination is likely to occur at the boundary between the second baking electrode layer 16a and the resin layer 16d. Note that the surface roughness Ra of the second region is 0.38 μm or less. Preferably, the surface roughness Ra of the second region is 0.30 μm or less.

  When the multilayer ceramic capacitor 10 is mounted on the mounting substrate, an external force may be applied to the multilayer ceramic capacitor 10B due to bending of the mounting substrate. Such an external force tends to concentrate on the end side of the folded portion of the first external electrode 15B and the second external electrode 16B. When the external force is concentrated on the end of the folded portion, delamination occurs at the boundary between the first baked electrode layer 15a and the resin layer 15d and at the boundary between the second baked electrode layer 16a and the resin layer 16d. As a result, the stress acting on the laminate 12 can be relaxed. As a result, the laminated body 12 can be prevented from cracking.

(Manufacturing method of multilayer ceramic capacitor)
FIG. 15 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor according to the third embodiment. With reference to FIG. 15, the manufacturing method of the multilayer ceramic capacitor according to the third embodiment will be described.

  As shown in FIG. 15, when the multilayer ceramic capacitor 10B is manufactured according to the method for manufacturing the multilayer ceramic capacitor 10B according to the third embodiment, processes similar to those in the first embodiment are performed in steps S1 to S12. To do.

  Next, in step S13A, a thermosetting resin containing conductive particles is applied onto the first baked electrode layer 15a and the second baked electrode layer 16a, and this is heated and cured. Thereby, the resin layer 15d and the resin layer 16d having conductivity are formed.

  Next, in step S13A1, the surface treatment of the resin layer 15d and the resin layer 16d is performed. Specifically, in accordance with step S12 according to the first embodiment, the laminate 12 provided with the resin layer 15d and the resin layer 16d and the medium 20 are put into the stirring tank 150. And the vibration energy is provided to the some laminated body 12 and the some media 20 by vibrating the stirring tank 150 similarly to Embodiment 1. FIG.

  In the step of applying vibration energy to the plurality of laminates 12 and the plurality of media 20, the surface layer of the resin layer is polished while rubbing the media 20 against the surface layer of the resin layers 15d and 16d. Thereby, the metal particles on the surface layer of the resin layer are extended into a flat shape. The surface of each of the resin layer 15d and the resin layer 16d is formed by continuously arranging the metal particles extended in this flat shape. As a result, a portion where the metal particles are exposed at a rate of 72.6% or more and 90.9% or less is formed, and the surfaces of the resin layer 15d and the resin layer 16d are modified. Preferably, a portion where the metal particles are exposed at a rate of 80% or more and 90% or less is formed.

  When the metal particles are exposed on the surfaces of the resin layers 15d and 16d at a ratio of 72.6% or more and 90.9% or less, the surfaces of the resin layers 15d and 16d become smooth. Thereby, the plating property is improved and the surface state of the plating layer is improved. As a result, the state of solder adhesion at the time of mounting is also improved, and solder defects at the time of mounting are suppressed.

  Next, in step S13B, substantially the same process as in step S13 according to Embodiment 1 is performed to form plating layer 15b and plating layer 15c on resin layer 15d, and plating layer on resin layer 16d. 16b and the plating layer 16c are formed.

  Through the steps as described above, the multilayer ceramic capacitor 10B according to Embodiment 3 can be manufactured.

  As described above, even in the multilayer ceramic capacitor 10B according to the third embodiment, the second region 15a2 having a high metal density and a smooth surface is formed on the surface layer of the baked electrode layer. A first region 15a1 having cushioning properties is formed on the laminated body 12 side of the layer. Thereby, even in the multilayer ceramic capacitor 10B according to the third embodiment, substantially the same effect as the multilayer ceramic capacitor 10 according to the first embodiment can be obtained.

  In addition, since the resin layers 15d and 16d are provided, even if the mounting substrate is bent while the multilayer ceramic capacitor 10B is mounted on the mounting substrate, the resin layers 15d and 16d having elasticity are stacked. It elastically deforms according to the external force applied to the ceramic capacitor 10B and absorbs the external force. Thereby, it can relieve | moderate that the said external force acts on the laminated body 12 directly, and can prevent that the laminated body 12 generate | occur | produces a crack. For this reason, the multilayer ceramic capacitor 10 </ b> B can stably exhibit the specification, and the reliability is improved.

  Further, when the external force is applied to the multilayer ceramic capacitor 10B as described above by forming the resin layers 15d and 16d on the surface-treated baking electrode layer, the first baking electrode layer 15a and the resin layer are applied. The delamination occurs at the boundary between 15d and the boundary between the second baked electrode layer 16a and the resin layer 16d, so that the stress acting on the laminate 12 can be relaxed. Also by this, it can further prevent that the laminated body 12 generate | occur | produces a crack. As a result, the multilayer ceramic capacitor 10 </ b> B can stably exhibit the specification, and the reliability is further improved.

  In addition, when the resin layers 15d and 16d are surface-treated using the sand blasting method instead of the step of applying vibration energy to the laminate 12 and the plurality of media 20, the sand blasting method includes cutting elements, Although the metal particles can be extended, the surface roughness cannot be improved. Moreover, plating property will deteriorate when cutting powder adheres to the resin surface. As a result, it is not possible to suppress solder defects during mounting.

  In the present embodiment, as described above, by applying vibration energy to the plurality of laminates 12 and the plurality of media 20, the surface of the resin layer becomes smooth, and the plating state and, consequently, the adhesion state of the solder is improved. In addition, solder defects during mounting are also suppressed. This also improves the reliability of the multilayer ceramic capacitor in the mounted state.

(First verification experiment)
FIG. 16 is a diagram illustrating conditions and results of a first verification experiment performed to verify the effects of the embodiment. With reference to FIG. 16, the 1st verification experiment implemented in order to verify the effect of embodiment is demonstrated.

  As shown in FIG. 16, in the verification experiment, the first baking electrode layer 15a is provided on the first end face 12e side, and the second baking electrode layer 16a is provided on the second end face 12f side of the multilayer body 12. A plurality of laminates 12 according to Examples 1 and 2 and Comparative Examples 1 to 7 were prepared. In the prepared state, the surface treatment is not performed on the first baked electrode layer 15a and the second baked electrode layer 16a.

  Each laminate 12 has a length dimension of 1.0 mm, a width dimension of 0.5 mm, and a height dimension of 0.5 mm.

  The prepared laminates according to Examples 1 and 2 and Comparative Examples 1 to 7 are subjected to surface treatment of the baked electrode layer using the surface treatment apparatus 100 described above, and the presence or absence of cracks and the baked electrode layer It was confirmed whether the surface was modified.

  In Comparative Example 1, the total volume of the plurality of laminated bodies charged into the stirring tank 150 was set to ½ of the total volume of the plurality of media 20 charged into the stirring tank 150. Further, the processing time was 7 hours, and the frequency of the stirring tank 150 was 15 Hz, which was smaller than the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, the laminate was not cracked, but the surface condition was not improved. That is, the second region 15a2 could not be formed sufficiently.

  In Comparative Example 2, the sum of the volumes of the plurality of laminated bodies put into the stirring tank 150 was set to ½ of the total volume of the plurality of media 20 put into the stirring tank 150. Further, the processing time was 7 hours, and the frequency of the stirring tank 150 was set to 35 Hz, which was larger than the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, the laminate was not cracked, but the surface condition was not improved. That is, the second region 15a2 could not be formed sufficiently.

  In Comparative Example 3, the sum of the volumes of the plurality of laminated bodies put into the stirring tank 150 was 6/10 of the total volume of the plurality of media 20 put into the stirring tank 150. The processing time was 3 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, cracks occurred in four of the 100 laminates. Further, the surface condition was not improved, and the second region 15a2 could not be sufficiently formed.

  In Comparative Example 4, the total volume of the plurality of laminated bodies charged into the stirring tank 150 was set to 6/10 of the total volume of the plurality of media 20 charged into the stirring tank 150. The processing time was 5 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, cracks occurred in six of the 100 laminates. Further, the surface condition was not improved, and the second region 15a2 could not be sufficiently formed.

  In Comparative Example 5, the total volume of the plurality of laminated bodies charged into the stirring tank 150 was 8/10 of the total volume of the plurality of media 20 charged into the stirring tank 150. The processing time was 5 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, cracks occurred in 35 laminated bodies out of 100 laminated bodies. Further, the surface condition was not improved, and the second region 15a2 could not be sufficiently formed.

  In Comparative Example 6, the sum of the volumes of the plurality of laminated bodies put into the stirring tank 150 was made the same as the sum of the volumes of the plurality of media 20 put into the stirring tank 150. The processing time was 5 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, cracks occurred in 41 of the 100 laminates. Further, the surface condition was not improved, and the second region 15a2 could not be sufficiently formed.

  In Comparative Example 7, the total volume of the plurality of laminated bodies charged into the stirring tank 150 was made the same as the total volume of the plurality of media 20 charged into the stirring tank 150. The processing time was 7 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, cracks occurred in 58 laminates out of 100 laminates. Further, the surface condition was not improved, and the second region 15a2 could not be sufficiently formed.

  In Example 2, the sum of the volumes of the plurality of laminated bodies charged into the stirring tank 150 was set to 1/3 or less (3/10) of the total volume of the plurality of media 20 charged into the stirring tank 150. . The processing time was 5 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, the laminate was not cracked, and the surface state was improved. The second region 15a2 could be sufficiently formed on the surface layer of the baked electrode layer.

  In Example 1, the sum of the volumes of the plurality of laminated bodies put into the stirring tank 150 was set to ½ of the sum of the volumes of the plurality of media 20 put into the stirring tank 150. The processing time was 5 hours, and the frequency of the stirring tank 150 was 23 Hz, which is the same as the natural frequency of the stirring tank 150.

  In this case, after the surface treatment, the laminate was not cracked, and the surface state was improved. The second region 15a2 could be sufficiently formed on the surface layer of the baked electrode layer.

  As described above, as shown in the results of Example 1 and Example 2, by using the method for manufacturing a multilayer ceramic capacitor according to the present embodiment, it is provided in the multilayer body while suppressing cracking of the multilayer body. It can be said that the surface of the obtained baked electrode layer can be modified. The surface of the baked electrode layer provided in the laminate can be modified while suppressing cracking and chipping of the laminate.

  In carrying out the surface treatment, the total volume of the plurality of laminated bodies 12 put into the stirring tank 150 is made ½ or less of the total volume of the plurality of media 20 put into the stirring tank 150. It was confirmed that the workability by the media 20 can be improved, and the corners of the laminate 12 can be prevented from cracking, and the laminate 12 can be prevented from being chipped or cracked. Furthermore, by setting the total volume of the plurality of laminated bodies 12 put into the stirring tank 150 to 1/3 or less of the total volume of the plurality of media 20 thrown into the stirring tank 150, a good surface state It was confirmed that

  Even if the processing time is shortened by comparing the examples 1 and 2 with the comparative examples 1 and 2 and setting the vibration frequency of the stirring tank 150 to the natural frequency of the stirring tank 150, the laminate 12 It was possible to prevent cracks at the corners, chipping or cracking of the laminate 12, and improve the surface of the baked electrode layer. From this, by setting the vibration frequency of the stirring tank 150 to a unique frequency of the stirring tank 150, vibration can be effectively transmitted to the plurality of laminates and the plurality of media 20, and surface treatment can be performed efficiently. It can be said that it can be implemented.

(Second verification experiment)
In the second verification experiment, specifically, the first baked electrode layer 15a, the second baked electrode layer 16a, the resin layer 15d, and the resin layer 16d are formed on the laminate 12, and a plating layer is formed. A multilayer ceramic capacitor in a state before being prepared was prepared, and observed using a metal microscope and a scanning electron microscope.

  In the second verification experiment, a resin layer 15d is provided on the first baked electrode layer 15a in a state where surface treatment is performed on the first baked electrode layer 15a and the second baked electrode layer 16a, and the second baked electrode layer 16a. A resin layer 16d was formed thereon. That is, in the second verification experiment, the first baked electrode layer 15a and the second baked electrode layer 16a include only the above-described first region, and the surfaces thereof are uneven.

  FIG. 17 is a cross-sectional view showing the state of the resin layer in the vicinity of the corner before the surface treatment in the second verification experiment conducted to verify the effect of the embodiment. FIG. 18 is a cross-sectional view showing a state of the resin layer in the vicinity of the corner after the surface treatment in the second verification experiment conducted to verify the effect of the embodiment. With reference to FIG. 17 and FIG. 18, the state of the resin layer in the vicinity of the corner portion on the second end face side before and after the surface treatment will be described.

  17 and 18 show the state of the resin layer observed with a scanning electron microscope. The bright portions of the resin layer 16d are metal particles, and the black portions between the metal particles are resin. It is.

  As shown in FIG. 17, in the resin layer near the corner before the surface treatment, the surface of the resin layer 16d was uneven according to the unevenness of the surface of the baked electrode layer. Moreover, the metal particles located on the surface of the resin layer are often granular and are arranged side by side with a certain distance.

  As shown in FIG. 18, in the resin layer near the corner after the surface treatment, no irregularities were confirmed on the surface of the resin layer 16d, and the surface of the resin layer 16d was smooth. The metal particles located on the surface of the resin layer have a flat shape and are arranged side by side.

  FIG. 19 is a cross-sectional view showing a state of the resin layer at the center portion of the end surface before the surface treatment in the second verification experiment performed to verify the effect of the embodiment. FIG. 20 is a cross-sectional view showing the state of the resin layer at the center of the end face after the surface treatment in the second verification experiment conducted to verify the effect of the embodiment. With reference to FIG. 19 and FIG. 20, the state of the resin layer at the center of the end surface before and after the surface treatment will be described.

  19 and 20 show the state of the resin layer observed with a scanning electron microscope. The bright portions of the resin layer 15d are metal particles, and the black portions between the metal particles are resin. It is.

  As shown in FIG. 19, in the resin layer on the center side of the second end surface before the surface treatment, the surface of the resin layer 16d was uneven according to the unevenness of the surface of the baking electrode layer. In addition, the metal particles located on the surface of the resin layer 16d are often granular and are arranged side by side with a certain distance.

  As shown in FIG. 20, even in the resin layer 16d at the center of the second end surface after the surface treatment, no unevenness was confirmed on the surface of the resin layer 16d, and the surface of the resin layer 16d was smooth. The metal particles located on the surface of the resin layer have a flat shape and are arranged side by side.

  From the results of FIGS. 17 to 20 described above, it was confirmed that the surface state of the resin layer was modified by performing the surface treatment on the resin layer based on the embodiment.

(Third verification experiment)
FIG. 21 is a diagram illustrating conditions and results of a third verification experiment performed to verify the effects of the embodiment. With reference to FIG. 21, a third verification experiment performed to verify the effect of the embodiment will be described.

  In the third verification experiment, the first baked electrode layer 15a, the second baked electrode layer 16a, the resin layer 15d, and the resin layer 16d are formed on the laminate 12, and the state before the plating layer is formed. A multilayer ceramic capacitor was prepared. As the multilayer ceramic capacitor, multilayer ceramic capacitors according to Examples 3 to 6 and Comparative Examples 8 to 10 described later were prepared.

  The surface state of the resin layer of these multilayer ceramic capacitors was observed, and the ratio of the metal particles occupying the outer surface of the resin layer was calculated within a predetermined range. In addition, the ratio of the metal particle was calculated from the image observed using SEM. Specifically, the multilayer ceramic capacitor 10 was polished to a center position in the width direction W, a cross section perpendicular to the width direction W was exposed, and the cross section was observed with an SEM.

  In the predetermined range determined in the SEM image, the length of the surface of the resin layer was measured, and the total length of the metal particles contained in the surface of the resin layer was measured. By dividing the total length of the metal particles by the length of the surface of the resin layer, the ratio of the metal particles occupying the outer surface of the resin layer was calculated.

  Further, the surface roughness Ra of the resin layer 15d and the surface roughness Ra of the resin layer 16d were also measured.

  Furthermore, a plating layer was formed on these multilayer ceramic capacitors, and the surface state of the plating layer was observed. Moreover, the multilayer ceramic capacitor in which the plating layer was formed was immersed in a solder bath, and the surface on which the solder was wet was observed. At this time, the evaluation number was 10, and the number of defects generated due to the surface state of the plating layer among the 10 was confirmed.

  As the multilayer ceramic capacitors according to Examples 4 to 6, those having a resin layer surface-treated in accordance with the manufacturing method according to Embodiment 3 were used. In the surface treatment, the vibration frequency of the stirring tank 150 was set to 23 Hz, which is the same as the natural frequency of the stirring tank 150, in the step of applying vibration to the plurality of laminated bodies and the plurality of media.

  As the multilayer ceramic capacitor according to Comparative Example 8, a thermosetting resin containing conductive particles is applied on the first baked electrode layer 15a and the second baked electrode layer 16a, and is heated and cured to form a resin layer. After forming the film, the surface treatment was performed by polishing the surface of the resin layer using a sand blast method.

  As the multilayer ceramic capacitor according to Comparative Example 9, a thermosetting resin containing conductive particles is applied on the first baked electrode layer 15a and the second baked electrode layer 16a, and is heated and cured to form a resin layer. After forming the resin layer, a resin layer that was not subjected to surface treatment after formation was used.

  As the multilayer ceramic capacitor according to Comparative Example 10, a capacitor subjected to surface treatment so as to reduce vibration applied to the multilayer ceramic capacitor was used as compared with Examples 4 to 6. Specifically, in the step of applying vibration to the plurality of laminates and the plurality of media, the frequency of the stirring tank 150 was set to 15 Hz, which is smaller than those in Examples 4 to 6.

  In Example 3, the ratio of the metal particles occupying the outer surface of the resin layer was 72.6%, and the surface roughness Ra of the resin layer was 0.38 μm. In this case, the surface state of the plating layer was good. Thereby, in observation of a solder surface, the multilayer ceramic capacitor which has a defect was not confirmed.

  In Example 4, the ratio of the metal particles occupying the outer surface of the resin layer was 83.1%, and the surface roughness Ra of the resin layers 15d and 16d was 0.33 μm. In this case, the surface state of the plating layer was extremely good. Thereby, in observation of a solder surface, the multilayer ceramic capacitor which has a defect was not confirmed.

  In Example 5, the ratio of the metal particles occupying the outer surface of the resin layer was 85.2%, and the surface roughness Ra of the resin layers 15d and 16d was 0.33 μm. In this case, the surface state of the plating layer was extremely good. Thereby, in observation of a solder surface, the multilayer ceramic capacitor which has a defect was not confirmed.

  In Example 6, the ratio of the metal particles occupying the outer surface of the resin layer was 90.9%, and the surface roughness Ra of the resin layers 15d and 16d was 0.32 μm. In this case, the surface state of the plating layer was extremely good. Thereby, in observation of a solder surface, the multilayer ceramic capacitor which has a defect was not confirmed.

  In Comparative Example 8, the ratio of the metal particles occupying the outer surface of the resin layer was 74.4%, and the surface roughness Ra of the resin layers 15d and 16d was 0.72 μm. In this case, the surface state of the plating layer was poor. As a result, in the observation of the solder surface, defects were found in three of the ten multilayer ceramic capacitors.

  In Comparative Example 9, the ratio of the metal particles occupying the outer surface of the resin layer was 61.2%, and the surface roughness Ra of the resin layers 15d and 16d was 0.75 μm. In this case, the surface state of the plating layer was poor. Thereby, in the observation of the solder surface, a defect was found in one of the 10 multilayer ceramic capacitors.

  In Comparative Example 10, the ratio of the metal particles occupying the outer surface of the resin layer was 68.7%, and the surface roughness Ra of the resin layers 15d and 16d was 0.75 μm. In this case, the surface state of the plating layer was somewhat poor. On the other hand, in the observation of the solder surface, a multilayer ceramic capacitor having a defect was not confirmed.

  In consideration of the above results, in Comparative Example 8, the metal layer included in the resin layer can be extended to some extent, but since the surface treatment is performed using the sand blast method including the cutting element, it is included in the surface of the resin layer. Uneven portions could not be reduced. Thereby, the plating state became defective, and defects were generated when the solder was attached to the plating layer.

  In Comparative Example 9, a thermosetting resin containing conductive particles was applied on the first baked electrode layer 15a and the second baked electrode layer 16a, and this was heated and cured to form a resin layer. In the state, since the surface treatment was not performed, the surface was uneven. Thereby, the plating state became defective, and defects were generated when the solder was attached to the plating layer.

  In Comparative Example 10, the surface treatment is performed in accordance with Embodiment 3 as compared with Comparative Example 9, but the vibration applied to the multilayer ceramic capacitor is small, so that the surface of the resin layer is sufficiently improved. I could not. Thereby, the plating state became slightly poor. On the other hand, no defects were generated when the solder was attached to the plating layer.

  In Examples 3 to 6, the resin layer is subjected to surface treatment in accordance with Embodiment 3, thereby extending the metal particles contained in the resin layer. The proportion of metal particles occupying the outer surface of the layer increased. In Examples 3 to 6, the ratio of the metal particles occupying the outer surface of the resin layer was 72.6% or more and 90.9% or less.

  Moreover, the surface roughness Ra of the resin layer was significantly improved as compared with Comparative Examples 1 and 2 by extending the metal particles by sliding the surface of the resin layer against the media. In Examples 3 to 6, the surface roughness Ra of the resin layer was also 0.38 μm or less. Thereby, the plating state was also good or extremely good, and no defects were generated when the solder was attached to the plating layer.

  As described above, the surface layer of each of the resin layers 15d and 16d has a portion where the metal particles are exposed at a ratio of 72.6% or more and 90.9% or less, so that the surface layer of the resin layer becomes dense, It was confirmed that the surface roughness can be improved. It was confirmed that by improving the surface roughness, plating ability and solder adhesion were improved, and solder defects during mounting could be suppressed. This also confirmed that the reliability of the multilayer ceramic capacitor can be improved.

  In addition, when the surface roughness Ra of the resin layer is 0.38 μm or less, the surface state of the plating layer is improved, thereby improving the plating property and the adhesion of the solder, and suppressing solder defects during mounting. Was confirmed.

  In the first to third embodiments described above, the internal structure of the multilayer ceramic capacitor is not limited to the structure disclosed in the first to third embodiments, and can be changed as appropriate.

  In the first to third embodiments described above, the case where the electronic component is a monolithic ceramic condenser has been described as an example. The electronic parts can be adopted.

  In the above-described third embodiment, the case where the surface treatment is performed on the baked electrode layer and the surface treatment is further performed on the resin layer is described as an example. A resin layer may be formed on the baked electrode layer without performing the treatment, and surface treatment may be performed on the resin layer. Also in this case, the baked electrode layer includes a considerable amount of voids and glass and is configured by the first region having cushioning properties, and can absorb external shocks applied to the multilayer ceramic capacitor 10. it can. Thereby, impact resistance improves.

  In addition, as shown in the second verification experiment described above, by applying a surface treatment to the resin layer, the surface of the resin layer is modified and smoothed. Thereby, plating can be made to adhere favorably to the resin layer, and it is possible to prevent the plating from getting worse at the corners. As a result, it is possible to reduce mounting defects that occur when the multilayer ceramic capacitor 10 is mounted on the mounting substrate.

  In addition, since the resin layer is provided, even if the mounting substrate is bent in a state where the multilayer ceramic capacitor is mounted on the mounting substrate, the resin layer having elasticity is applied to the external force applied to the multilayer ceramic capacitor. In response, it elastically deforms and absorbs the external force. This can also alleviate the action of the external force directly on the laminate and prevent the laminate from cracking. For this reason, the multilayer ceramic capacitor can exhibit its specification stably, and the reliability is improved.

  Although the embodiments of the present invention have been described above, the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, and includes meanings equivalent to the terms of the claims and all modifications within the scope.

  10, 10A, 10B Multilayer ceramic capacitor, 12 multilayer body, 12a first main surface, 12b second main surface, 12c first side surface, 12d second side surface, 12e first end surface, 12f second end surface, 13 dielectric layer, 14 Internal electrode layer, 15, 15A, 15B First external electrode, 15a, 15aA First baked electrode layer 15a1 First region, 15a2 Second region, 15b, 15c Plating layer, 15d, 16d Resin layer, 16, 16B Second External electrode, 16a Second baked electrode layer, 16b, 16c Plating layer, 16d Resin layer, 20 Media, 100 Surface treatment device, 110 First base portion, 120 Second base portion, 130 Third base portion, 140 Vibration receiving plate , 141 first internal electrode layer, 142 second internal electrode layer, 145 placement part, 150 stirring tank, 151 bottom part, 152 peripheral wall part, 153 bending portion, 154 cylindrical portion, 155 shaft portion, 156 flange portion, 160 drive motor, 161 rotating shaft, 170 eccentric load, 180 elastic member, 190 drive motor support portion, 200 detection portion, 210 drive motor control portion.

Claims (3)

First end surface and second end surface positioned relative to the length direction, first side surface and second side surface positioned relative to the width direction orthogonal to the length direction, and the length direction and the width direction A laminated body including a first main surface and a second main surface positioned relative to a height direction orthogonal to
A first external electrode provided on the first end surface;
A second external electrode provided on the second end face,
The first external electrode includes a first baking electrode layer provided on the first end face, and a first resin layer provided on the first baking electrode layer,
The second external electrode includes a second baking electrode layer provided on the second end face, and a second resin layer provided on the second baking electrode layer,
Each of the first baked electrode layer and the second baked electrode layer has a region that is provided on the laminate and includes voids and glass,
The first resin layer and the second resin layer include metal particles,
Each of the surface layers of the first resin layer and the second resin layer has an area where the metal particles are exposed at a rate of 72.6% or more and 90.9% or less.   In the portion where the metal particles are exposed at a rate of 72.6% to 90.9%, the first resin layer and the second resin layer are formed by continuously arranging the metal particles having a flat shape. The electronic component according to claim 1, wherein each of the surfaces is formed.   3. The electronic component according to claim 1, wherein a surface roughness Ra of the first resin layer and a surface roughness Ra of the second resin layer are 0.38 μm or less.