JP2022174958A - Multi-layer ceramic electronic component - Google Patents

Abstract

To provide a multi-layer ceramic electronic component that, in an external electrode having a Cu plating layer, can suppress, reduction in reliability based on pulling stress remaining in the Cu plating layer.SOLUTION: A multi-layer ceramic capacitor 10A being an example of a multi-layer ceramic electronic component according to the present invention comprises: a laminate 12 in which a plurality of ceramic layers 14 and a plurality of internal electrode layers 16 are laminated; and a pair of external electrodes 30, the external electrodes are electrically connected with the internal electrode layers 16 and formed on one/the other of both end faces of the laminate 12. The pair of external electrodes 30 each has a base electrode layer 32 having a metal component and a ceramic component, and a Cu plating layer 34 arranged on the base electrode layer 32. In the Cu plating layer 34, compression stress is applied to the Cu plating layer 34 arranged on both principal surfaces 12a, 12b and surfaces of both side faces 12c, 12d of the laminate 12. The compression stress is 50 MPa or more and 300 MPa or less.SELECTED DRAWING: Figure 2

Description

The present invention relates to multilayer ceramic electronic components.

2. Description of the Related Art Conventionally, ceramic electronic components typified by ceramic capacitors have been used in electronic devices such as mobile phones and portable music players. In recent years, miniaturization of ceramic electronic components has progressed. In order to further reduce the size of ceramic electronic components, for example, Patent Document 1 discloses a ceramic electronic component that can be embedded in a wiring board.

In Patent Document 1, the above-described multilayer ceramic electronic component includes a ceramic body, a base electrode layer having a metal that can diffuse into Cu and an inorganic binder provided on the ceramic body, and a Cu plating film. , is described. Further, Patent Literature 1 describes that a heat treatment is performed after forming a Cu plating film. In general, by performing a heat treatment after forming a Cu plating film, it is possible to improve the adhesion between the Cu plating film and the base electrode layer and to ensure moisture resistance reliability.

JP 2014-207254 A

However, in a ceramic electronic component having a base electrode layer and a Cu plating film (Cu plating layer) as disclosed in Patent Document 1, when heat treatment is performed after forming the Cu plating film, grain growth of Cu in the Cu plating layer occurs. Since it is sintered, a tensile stress is applied to the Cu plating film. Here, in a state where tensile stress is applied to the Cu plating film and the stress remains, if stress due to impact such as dropping or bending stress generated by thermal expansion and contraction of the mounting substrate due to thermal cycles is added, tensile Further stress is applied to the Cu plating film to which the stress is applied, and it is conceivable that cracks occur in the ceramic body starting from the tip portion of the base electrode layer where the stress tends to concentrate.

Therefore, the main object of the present invention is to provide a multilayer ceramic electronic component that can suppress deterioration in reliability due to tensile stress remaining in the Cu-plated layer in external electrodes having the Cu-plated layer.

A laminated ceramic electronic component according to the present invention includes a plurality of laminated ceramic layers, and has first and second main surfaces facing each other in a height direction and a width direction perpendicular to the height direction. A laminate having a first side surface and a second side surface, and a first end surface and a second end surface facing each other in a length direction orthogonal to the height direction and the width direction, and arranged on a plurality of ceramic layers a first internal electrode layer positioned inside the laminate; a second internal electrode layer positioned on the plurality of ceramic layers and positioned inside the laminate; a first external electrode disposed on a portion of the main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; In a multilayer ceramic electronic component having a part of the main surface, a part of the second main surface, a part of the first side surface, and a second external electrode arranged on a part of the second side surface, The first external electrode and the second external electrode have a base electrode layer having a metal component and a ceramic component, and a Cu plating layer disposed on the surface of the base electrode layer, and are the first main component of the laminate. Compressive stress is applied to the Cu plating layers arranged on the surface and the second main surface and on the first side surface and the second side surface, and the compressive stress is 50 MPa or more and 300 MPa or less. electronic components.

In the multilayer ceramic electronic component according to the present invention, the first external electrode and the second external electrode include a base electrode layer having a metal component and a ceramic component, and a Cu plating layer disposed on the base electrode layer. Since a compressive stress of 50 MPa or more and 300 MPa or less is applied to the Cu plated layer, the Cu plated layer is in a state where the compressive stress is applied. As a result, it is possible to relax the stress applied to the tip portion of the base electrode layer, where the stress due to the tensile stress remaining in the Cu plating layer tends to concentrate, and to suppress cracks in the laminate. can.
More specifically, the Cu plating layer can provide a stress in the opposite direction to the direction of the stress applied to the end portion of the base electrode layer, which has been a problem in conventional multilayer ceramic electronic components. Therefore, the stress applied to the laminate from the end portion of the base electrode layer can be canceled, and the stress applied to the tip portion of the base electrode layer can be alleviated. As a result, cracks in the laminate can be suppressed.

According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of suppressing deterioration in reliability due to tensile stress remaining in the Cu-plated layer in the external electrode having the Cu-plated layer.

The above object, other objects, features and advantages of the present invention will become more apparent from the following description of the mode for carrying out the invention with reference to the drawings.

1 is an external perspective view showing an example of a laminated ceramic capacitor as a laminated ceramic electronic component according to a first embodiment of the present invention; FIG. 1 is a front view showing an example of a laminated ceramic capacitor as a laminated ceramic electronic component according to a first embodiment of the invention; FIG. Figure 2 is a cross-sectional view along line III-III of Figure 1; FIG. 2 is a cross-sectional view along IV-IV in FIG. 1; (a) is a cross-sectional view taken along line III-III in FIG. 1 showing a structure in which the opposing electrode portion of the internal electrode layer of the multilayer ceramic capacitor according to the first embodiment of the present invention is divided into two; ) is a cross-sectional view taken along line III-III in FIG. 1 showing a structure in which the counter electrode portion of the internal electrode layer of the multilayer ceramic capacitor according to the present invention is divided into three; (c) the multilayer ceramic capacitor according to the present invention; FIG. 2 is a cross-sectional view taken along line III-III in FIG. 1 showing a structure in which a counter electrode portion of an internal electrode layer is divided into four; It is a cross-sectional schematic diagram explaining the stress which acts on a laminated ceramic capacitor. FIG. 3 is an external perspective view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to a second embodiment of the present invention; FIG. 5 is a top view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to a second embodiment of the present invention; FIG. 5 is a front view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to a second embodiment of the present invention; FIG. 8 is a cross-sectional view taken along line XX of FIG. 7; FIG. 8 is a cross-sectional view along line XI-XI of FIG. 7; 11 is a cross-sectional view taken along line XII-XII of FIG. 10; FIG. FIG. 11 is a cross-sectional view along line XIII-XIII of FIG. 10;

1. Laminated Ceramic Capacitor (1) First Embodiment A laminated ceramic capacitor will be described as an example of a laminated ceramic electronic component according to a first embodiment of the present invention.

FIG. 1 is an external perspective view showing an example of a laminated ceramic capacitor as a laminated ceramic electronic component according to a first embodiment of the invention. FIG. 2 is a front view showing an example of a laminated ceramic capacitor as a laminated ceramic electronic component according to the first embodiment of the invention. FIG. 3 is a cross-sectional view along line III--III of FIG. FIG. 4 shows IV-I in FIG.
FIG. 3 is a cross-sectional view at V;

As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 10A includes a rectangular parallelepiped laminate 12 and external electrodes 30 arranged at both ends of the laminate 12. As shown in FIGS.

The laminate 12 has a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layers 14 . Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b facing in the height direction x, and a first side surface 12c and a second main surface 12c facing in the width direction y orthogonal to the height direction x. and a first end face 12e and a second end face 12f facing each other in a length direction z orthogonal to the height direction x and width direction y. The laminate 12 has rounded corners and ridges. A corner portion is a portion where three adjacent surfaces of the laminate intersect, and a ridge portion is a portion where two adjacent surfaces of the laminate intersect. In addition, unevenness or the like is formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. may have been The ceramic layers 14 and the internal electrode layers 16 are laminated in the height direction x.

The laminate 12 has an effective portion 18 composed of one or more ceramic layers 14 and a plurality of internal electrode layers 16 disposed thereon. The internal electrode layer 16 has a first internal electrode layer 16a drawn out to the first end surface 12e and a second internal electrode layer 16b drawn out to the second end surface 12f. One internal electrode layer 16a and a second internal electrode 16b face each other with the ceramic layer 14 interposed therebetween.

The laminate 12 is located on the side of the first principal surface 12a, and is located between the first principal surface 12a, the outermost surface of the effective portion 18 on the first principal surface 12a side, and a straight line on the outermost surface. It has a first main surface side outer layer portion 20 a formed from a plurality of ceramic layers 14 .
Similarly, the laminate 12 is located on the second main surface 12b side, and between the second main surface 12b and the outermost surface of the effective portion 18 on the second main surface 12b side and the straight line on the outermost surface. has a second main surface side outer layer portion 20b formed from a plurality of ceramic layers 14 located at .

The laminate 12 is located on the first side surface 12c side and is formed of a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the effective portion 18 on the first side surface 12c side. 1 side outer layer portion 22a.
Similarly, the laminate 12 is formed from a plurality of ceramic layers 14 located on the second side surface 12d side and located between the second side surface 12d and the outermost surface of the effective portion 18 on the second side surface 12d side. It has a second side outer layer portion 22b that is attached.

The laminate 12 is positioned on the first end face 12e side and is formed of a plurality of ceramic layers 14 positioned between the first end face 12e and the outermost surface of the effective portion 18 on the first end face 12e side. It has one end surface side outer layer portion 24a.
Similarly, the laminate 12 is formed from a plurality of ceramic layers 14 positioned on the second end face 12f side and positioned between the second end face 12f and the outermost surface of the effective portion 18 on the second end face 12f side. It has a second end surface side outer layer portion 24b that is attached.

The first main surface side outer layer portion 20a is located on the first main surface 12a side of the laminate 12, and is between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. It is an aggregate of a plurality of ceramic layers 14 positioned.
The second main surface side outer layer portion 20b is located on the second main surface 12b side of the laminate 12, and is between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. It is an aggregate of a plurality of ceramic layers 14 positioned.

The dimensions of the laminate 12 are not particularly limited, but the dimension in the length direction z is 0.186 mm or more and 9.59 mm or less, the dimension in the width direction y is 0.086 mm or more and 4.83 mm or less, and the dimension in the height direction x is It is preferably 0.036 mm or more and 4.83 mm or less.

Ceramic layer 14 can be formed of a dielectric material, for example, as a ceramic material. Dielectric ceramics containing components such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , or CaZrO ₃ can be used as such dielectric materials. When the dielectric material described above is included as a main component, depending on the desired properties of the laminate 12, for example, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or other secondary component having a smaller content than the main component. You may use what added the component.

When a piezoelectric ceramic material is used for the ceramic layer 14, the laminated ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.
Moreover, when a semiconductor ceramic material is used for the ceramic layer 14, the laminated ceramic electronic component functions as a thermistor. Specific examples of semiconductor ceramic materials include, for example, spinel-based ceramic materials.
Moreover, when a magnetic ceramic material is used for the ceramic layer 14, the laminated ceramic electronic component functions as an inductor. Moreover, when functioning as an inductor, the internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for example, ferrite ceramic materials.

The thickness of the ceramic layer 14 after firing is preferably 0.5 μm or more and 10 μm or less. The number of laminated ceramic layers 14 is preferably 15 or more and 700 or less. The number of ceramic layers 14 is the sum of the number of ceramic layers 14 in the effective portion 18 and the number of ceramic layers 14 in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b. be.

The laminate 12 has, as the plurality of internal electrode layers 16, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b, for example. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded so as to be alternately arranged at equal intervals along the height direction x of the laminate 12 with the ceramic layers 14 interposed therebetween. ing.

The first internal electrode layers 16 a are arranged on the plurality of ceramic layers 14 and located inside the laminate 12 . The first internal electrode layer 16a is positioned on one end side of the first internal electrode layer 16a and the first counter electrode portion 26a facing the second internal electrode layer 16b, and the electrode from the first counter electrode portion 26a. and a first extraction electrode portion 28 a extending to the first end surface 12 e of the laminate 12 . The first extraction electrode portion 28 a has its end extracted to the surface of the first end surface 12 e and exposed from the laminate 12 .

Although the shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, it is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be obliquely formed in plan view (tapered shape). Moreover, it may have a tapered shape in a plan view that is inclined toward either direction.

Although the shape of the first extraction electrode portion 28a of the first internal electrode layer 16a is not particularly limited, it is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be obliquely formed in plan view (tapered shape). Moreover, it may have a tapered shape in a plan view that is inclined toward either direction.

The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first extraction electrode portion 28a of the first internal electrode layer 16a may be the same, or either One width may be formed narrower.

The second internal electrode layers 16 b are arranged on the plurality of ceramic layers 14 and located inside the laminate 12 . The second internal electrode layer 16b is located on a second counter electrode portion 26b facing the first internal electrode layer 16a, and on one end side of the second internal electrode layer 16b. It has a second extraction electrode portion 28b extending to the second end surface 12f of the laminate 12 . The second extraction electrode portion 28b is exposed from the laminated body 12 with its end being extracted to the surface of the second end surface 12f.

Although the shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, it is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be obliquely formed in plan view (tapered shape). Moreover, it may have a tapered shape in a plan view that is inclined toward either direction.

Although the shape of the second extraction electrode portion 28b of the second internal electrode layer 16b is not particularly limited, it is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be obliquely formed in plan view (tapered shape). Moreover, it may have a tapered shape in a plan view that is inclined toward either direction.

The width of the second counter electrode layer 26b of the second internal electrode layer 16b and the width of the second extraction electrode portion 28b of the second internal electrode layer 16b may be the same, or either One width may be formed narrower.

The first internal electrode layers 16a and the second internal electrode layers 16b are made of, for example, metals such as Ni, Cu, Ag, Pd, and Au, and alloys containing at least one of these metals, such as Ag—Pd alloys. suitable conductive material.

The thickness of each of the internal electrode layers 16, that is, the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 0.2 μm or more and 2.0 μm or less.
Also, the total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 15 or more and 200 or less.

External electrodes 30 are arranged on the first end surface 12e side and the second end surface 12f side of the laminate 12, as shown in FIGS.

The external electrode 30 includes a base electrode layer 32 containing a metal component and a ceramic component, and a Cu plating layer 34 arranged on the surface of the base electrode layer 32 . Moreover, the external electrode 30 preferably includes an upper plated layer 36 arranged on the surface of the Cu plated layer 34 .

The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

The first external electrode 30a is connected to the first internal electrode layer 16a and arranged on at least the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the laminate 12 to extend from a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c. It is also arranged on a portion and a portion of the second side 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

The second external electrode 30b is connected to the second internal electrode layer 16b and arranged on at least the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the second end surface 12f to extend a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c and a portion of the second main surface 12b. 2 is also arranged on a part of the side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

In the laminate 12, the first counter electrode portion 26a of the first internal electrode layer 16a and the second counter electrode portion 26b of the second internal electrode layer 16b face each other with the ceramic layer 14 interposed therebetween. , a capacitance is formed. Therefore, a capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 16a is connected and the second external electrode 30b to which the second internal electrode layer 16b is connected. , the characteristics of the capacitor appear.

5, in addition to the first internal electrode layers 16a and the second internal electrode layers 16b, the laminate 12 shown in FIG. A floating internal electrode layer 16c that is not pulled out to either side may be provided, and the counter electrode portion 26c may be divided into a plurality of parts by the floating internal electrode layer 16c. For example, it may be a double structure as shown in FIG. 5(a), a triple structure as shown in FIG. 5(b), or a quadruple structure as shown in FIG. 5(c). stomach. By dividing the counter electrode portion 26c into a plurality of pieces in this way, a plurality of capacitor components are formed between the opposing internal electrode layers 16a, 16b, and 16c, and these capacitor components are connected in series. configuration. Therefore, the voltage applied to each capacitor component is lowered, and the multilayer ceramic capacitor 10A can be made to have a high withstand voltage.

The base electrode layer 32 includes at least one selected from a baked layer, a thin film layer, and the like.
Hereinafter, each configuration in the case where the base electrode layer 32 is the above baked layer and thin film layer will be described.

The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

The first base electrode layer 32a is connected to the first internal electrode layer 16a and arranged on the surface of the first end surface 12e. In addition, the first base electrode layer 32a extends from the first end surface 12e to part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c. It is also arranged on part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

The second base electrode layer 32b is connected to the second internal electrode layer 16b and arranged on the surface of the second end surface 12f. In addition, the second base electrode layer 32b extends from the second end surface 12f to part of the first principal surface 12a, part of the second principal surface 12b, part of the first side surface 12c, and part of the second principal surface 12b. It is also arranged on part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

(For baked layer)
The baking layer contains a metal component and a ceramic component. The ceramic component may be the same type of ceramic material as the ceramic layer 14, or may be a different type of ceramic material. The ceramic component includes at least one selected from BaTiO ₃ , CaTiO ₃ , (Ba, Ca)TiO ₃ , SrTiO ₃ , CaZrO ₃ and the like, for example. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, Au, and the like. The metal component of the baking layer is preferably the same as the metal used for the internal electrode layers 16 . The baking layer is obtained by applying a conductive paste containing a ceramic material and a metal to the laminate and baking the paste. The baked layer is formed by simultaneously firing the laminated chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminated chip. The baking layer may be multiple layers.

The thickness in the length direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the first base electrode layer 32a located on the first end face 12e is, for example, 3 μm or more and 160 μm. It is preferable that the degree is as follows.
The thickness in the length direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is, for example, 3 μm or more and 160 μm. It is preferable that the degree is as follows.

The first base electrode layer 32a located on a part of the first main surface 12a and the second main surface 12b is located at a central portion in the length direction z connecting the first end surface 12e and the second end surface 12f of the first base electrode layer 32a. It is preferable that the thickness in the height direction x connecting the main surface 12a and the second main surface 12b is, for example, about 3 μm or more and 40 μm or less.
In addition, at the central portion in the length direction z connecting the first end surface 12e and the second end surface 12f of the second base electrode layer 32b located on a part of the first main surface 12a and the second main surface 12b, It is preferable that the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b is, for example, about 3 μm or more and 40 μm or less.

A first side surface at a central portion in the length direction z connecting the first end surface 12e and the second end surface 12f of the first base electrode layer 32a located on a part of the first side surface 12c and the second side surface 12d The thickness in the width direction y connecting 12c and second side surface 12d is preferably, for example, about 3 μm or more and 40 μm or less.
In addition, the first edge in the longitudinal direction z connecting the first end face 12e and the second edge face 12f of the second base electrode layer 32b located on a part of the first side face 12c and the second side face 12d. It is preferable that the thickness in the width direction y connecting the side surface 12c and the second side surface 12d is, for example, about 3 μm or more and 40 μm or less.

(For thin film layers)
When the base electrode layer 32 is formed of a thin film layer, the thin film layer is a layer of 1 μm or less on which metal particles are deposited by a thin film forming method such as a sputtering method or a vapor deposition method.

The Cu plating layer 34 has a first Cu plating layer 34a and a second Cu plating layer 34b.

The first Cu plating layer 34a is arranged to cover the surface of the first base electrode layer 32a.
The second Cu plating layer 34b is arranged to cover the surface of the second base electrode layer 32b.

A compressive stress is applied to the Cu plating layer 34 arranged on the first main surface 12a and the second main surface 12b and on the first side surface 12c and the second side surface 12d.

Specifically, the respective first Cu plating layers 34a arranged on the first main surface 12a and the second main surface 12b and the first side surface 12c and the second side surface 12d of the laminate 12 is applied with a compressive stress in the direction from the first end surface 12e of the laminate 12 toward the second end surface 12f.
In addition, the second Cu plating layers 34b arranged on the first main surface 12a and the second main surface 12b and the first side surface 12c and the second side surface 12d of the laminate 12 have Compressive stress is applied in the direction from the second end surface 12f of the laminate 12 toward the first end surface 12e.
The compressive stress applied to the first Cu plating layer 34a and the second Cu plating layer 34b is 50 MPa or more and 300 MPa or less.
In this specification, compressive stress refers to stress in the direction from both end surfaces or both side surfaces to the intermediate portion of the laminate 12, and tensile stress refers to stress in the direction from the intermediate portion of the laminate 12 to both end surfaces or both side surfaces. It refers to the stress in the direction to which it faces.

When the compressive stress applied to the Cu plating layer 34 becomes smaller than 50 MPa, the first main surface 12a and the second main surface 12b of the laminate 12 and the first side surface 12c and the second side surface In some cases, the stress relieving force applied to the tip portion of the base electrode layer 32 disposed on 12d is weakened, and cracks in the laminate 12 cannot be suppressed. Moreover, when the compressive stress applied to the Cu plating layer 34 exceeds 300 Pa, cracks may occur in the laminate 12 due to the impact when the compressive stress is applied to the Cu plating layer 34 .

A more preferable range of compressive stress applied to the first Cu plating layer 34a and the second Cu plating layer 34b is 80 MPa or more and 200 MPa or less. As a result, the effect of the present invention becomes more pronounced, and the laminate 12 can be prevented from cracking.

As a method for measuring the compressive stress applied to the Cu plating layer 34, it can be measured from the surface of the Cu plating layer 34 by μ-XRD according to the procedure described below.
(i) First, if a Ni-plated layer and a Sn-plated layer are formed on the surface of the Cu-plated layer 34, the Ni-plated layer and the Sn-plated layer are removed.
(ii) As a method for stripping the Sn plating layer, the multilayer ceramic capacitor 10A is immersed in a Sn stripping solution to strip Sn. As the liquid, a liquid that dissolves Sn but hardly dissolves the underlying Ni is preferred. For example, Melstrip HN980M is used. The immersion time is about 10 minutes. The immersion time varies depending on the size of the product and the concentration of the solution, so it should be adjusted each time.
(iii) As a method for stripping the Ni plating layer, the laminated ceramic capacitor 10A is immersed in a Ni stripping solution to strip the Ni. As the liquid, a liquid that dissolves Ni and hardly dissolves Cu of the underlying Cu plating layer 34 is preferable. For example, Enstrip NP is used. The immersion time is about 120 minutes. The immersion time varies depending on the size of the product and the concentration of the solution, so it should be adjusted each time. At this time, the surface of the Cu plating layer 34 may be oxidized and discolored, but since it is only the surface layer, it does not affect the X-ray stress measurement performed later.
(iv) After removing the Sn plating layer and the Ni plating layer, the The stress of the Cu plating layer 34 can be measured at the central portion of the Cu plating layer 34 in the length direction z and the width direction y using a micro-part stress measuring device (XRD).

The thickness of the Cu plating layer 34 is preferably 2 μm or more and 15 μm or less.

The upper plated layer 36 has a first upper plated layer 36a and a second upper plated layer 36b.

The first upper plated layer 36a is arranged to cover the first Cu plated layer 34a.
The second upper plated layer 36b is arranged to cover the second Cu plated layer 34b.
As a result, the upper plated layer 36 is arranged on the surface of the Cu plated layer 34, so that reliability and mountability of the multilayer ceramic capacitor 10A can be improved.

The upper plated layer 36 contains, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag—Pd alloy, Au, and the like.

The upper plated layer 36 may be formed of multiple layers. A two-layer structure of a Ni plating layer and a Sn plating layer is preferred. The Ni-plated layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10A, and the Sn-plated layer prevents wetting of the solder when mounting the multilayer ceramic capacitor 10A. It is possible to improve the property and easily mount the multilayer ceramic capacitor 10A on the mounting board. By forming the upper plated layer 36 with a plurality of layers in this manner, the reliability and mountability of the multilayer ceramic capacitor 10A can be efficiently improved.

The thickness of each upper plating layer 36 is preferably 1 μm or more and 15 μm or less.

The dimension in the length direction z of the multilayer ceramic capacitor 10A including the multilayer body 12, the first external electrode 30a and the second external electrode 30b is defined as the L dimension, and the multilayer body 12, the first external electrode 30a and the second external electrode The dimension in the height direction x of the multilayer ceramic capacitor 10A including the electrode 30b is defined as the dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10A including the laminate 12, the first external electrode 30a and the second external electrode 30b is defined as T dimension. W dimension.
The dimensions of the multilayer ceramic capacitor 10A are such that the L dimension in the length direction z is 0.2 mm or more and 10.0 mm or less, the W dimension in the width direction y is 0.1 mm or more and 5.0 mm or less, and the T dimension in the height direction x is 0. 05 mm or more and 5.0 mm or less. Also, the dimensions of the laminated ceramic capacitor 10A can be measured with a microscope.

A multilayer ceramic capacitor 10A shown in FIG. 1 has a Cu plating layer 34 disposed on the surface of a base electrode layer 32 . The Cu plating layer 34 has high moisture resistance, and can further suppress the intrusion of moisture from the outside into the inside of the external electrode 30 . In addition, since it is possible to control the compressive stress of the Cu plating layer 34 as described above and apply the compressive stress to the Cu plating layer 34, on the first main surface 12a and the second main surface 12b of the laminate 12, It is also possible to relax the stress that tends to concentrate on the tip portions of the base electrode layer 32 disposed on the first side surface 12c and the second side surface 12d. As a result, it is possible to suppress the occurrence of cracks in the laminate 12 . More specifically, as shown in FIG. 6, a conventional problem with the multilayer ceramic capacitor 10A is that the stress in the direction opposite to the direction of the stress applied to the end portion of the base electrode layer 32 is applied to the Cu plating layer. 34 can be given. Therefore, the stress applied to the laminate 12 from the end portion of the base electrode layer 32 can be canceled, and the stress applied to the tip portion of the base electrode layer 32 can be relaxed. As a result, it is possible to suppress cracks in the laminate 12 .

(2) Second Embodiment Next, a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) will be described as a laminated ceramic electronic component according to a second embodiment.

FIG. 7 is an external perspective view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to a second embodiment of the present invention. FIG. 8 is a top view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to the second embodiment of the present invention. FIG. 9 is a front view showing an example of a laminated ceramic capacitor (three-terminal type laminated ceramic capacitor) as a laminated ceramic electronic component according to the second embodiment of the present invention. 10 is a cross-sectional view taken along line XX of FIG. 7. FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 7. FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 10. FIG. FIG. 13 is a cross-sectional view along line XIII-XIII of FIG.

As shown in FIG. 7, a laminated ceramic capacitor 10B includes, for example, a rectangular parallelepiped laminate 12 and external electrodes 30. As shown in FIG.

The laminate 12 has a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 116 laminated on the ceramic layers 14 . The ceramic layers 14 and the internal electrode layers 116 are laminated in the height direction x.

The laminate 12 has a first main surface 12a and a second main surface 12b facing in the height direction x, and a first side surface 12c and a second side surface facing in the width direction y orthogonal to the height direction x. 12d, and a first end face 12e and a second end face 12f facing each other in a length direction z orthogonal to the height direction x and width direction y. The laminate 12 has rounded corners and ridges. A corner portion is a portion where three adjacent surfaces of the laminate intersect, and a ridge portion is a portion where two adjacent surfaces of the laminate intersect. In addition, unevenness or the like is formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. may have been

The laminate 12 has an effective portion 18 composed of one or more ceramic layers 14 and a plurality of internal electrode layers 116 disposed thereon. The internal electrode layer 116 includes a first internal electrode layer 116a drawn out to the first end surface 12e and the second end surface 12f and a second internal electrode layer 116b drawn out to the second side surface 12c and the second side surface 12d. In the effective portion 18, a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b face each other with the ceramic layers 14 interposed therebetween.

The laminate 12 is located on the side of the first principal surface 12a, and is located between the first principal surface 12a, the outermost surface of the effective portion 18 on the first principal surface 12a side, and a straight line on the outermost surface. It has a first main surface side outer layer portion 20 a formed from a plurality of ceramic layers 14 .
Similarly, the laminate 12 is located on the second main surface 12b side, and between the second main surface 12b and the outermost surface of the effective portion 18 on the second main surface 12b side and the straight line on the outermost surface. has a second main surface side outer layer portion 20b formed from a plurality of ceramic layers 14 located at .

Moreover, the laminate 12 is located on the side of the first side surface 12c and is formed of a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the effective portion 18 on the side of the first side surface 12c. It has a first side outer layer portion 22a.
Similarly, the laminate 12 is formed from a plurality of ceramic layers 14 located on the second side surface 12d side and located between the second side surface 12d and the outermost surface of the effective portion 18 on the second side surface 12d side. It has a second side outer layer portion 22b that is attached.

Furthermore, the laminated body 12 is formed from a plurality of ceramic layers 14 positioned on the first end face side 12e side and positioned between the first end face 12e and the outermost surface of the effective portion 18 on the first end face 12e side. It has a first end face side outer layer portion 24a that is
Similarly, the laminate 12 is formed from a plurality of ceramic layers 14 positioned on the second end face 12f side and positioned between the second end face 12f and the outermost surface of the effective portion 18 on the second end face 12f side. It has a second end surface side outer layer portion 24b that is attached.

The first main surface side outer layer portion 20a is located on the first main surface 12a side. The first main surface side outer layer portion 20a is an assembly of a plurality of ceramic layers 14 positioned between the first main surface 12a and the internal electrode layers 116 closest to the first main surface 12a.
The second main surface side outer layer portion 20b is located on the second main surface 12b side. The second main surface side outer layer portion 20b is an assembly of a plurality of ceramic layers 14 positioned between the second main surface 12b and the internal electrode layers 116 closest to the second main surface 12b.

The dimensions of the laminate 12 are not particularly limited, but the dimension in the length direction z is 0.186 mm or more and 9.59 mm or less, the dimension in the width direction y is 0.086 mm or more and 4.59 mm or less, and the dimension in the height direction x is It is preferably 0.036 mm or more and 4.83 mm or less.

The material of the ceramic layer 14 is the same as that of the multilayer ceramic capacitor 10A, so the explanation thereof is omitted.
Also, the average thickness of the ceramic layers 14 after firing in the height direction x is the same as that of the multilayer ceramic capacitor 10A, so the description thereof will be omitted.

The laminate 12 has, as the plurality of internal electrode layers 116, a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b. The plurality of first internal electrode layers 116a and the plurality of second internal electrode layers 116b are buried so as to be alternately arranged at regular intervals along the height direction x of the laminate 12 .

As shown in FIG. 12, the first internal electrode layer 116a is formed by a first counter electrode portion 126a facing the second internal electrode layer 116b, and a first end face of the laminate 12 from the first counter electrode portion 126a. One first lead-out electrode portion 128a ₁ led out to the surface of 12e and the other first lead-out electrode portion 128a ₂ led out to the surface of the second end face 12f of the laminate 12 from the first counter electrode portion 126a. Prepare. Specifically, one first extraction electrode portion 128 _{a 1} is exposed on the surface of the first end surface 12 e of the laminate 12 , and the other first extraction electrode portion 128 a ₂ is exposed on the second surface of the laminate 12 . is exposed on the surface of the end face 12f. Therefore, the first internal electrode layer 116a is not exposed on the surfaces of the first side surface 12c and the second side surface 12d of the laminate 12. As shown in FIG.

As shown in FIG. 13, the second internal electrode layer 116b has a substantially cross shape, a second counter electrode portion 126b facing the first internal electrode layer 116a, and a laminate from the second counter electrode portion 126b. One second extraction electrode portion 128 b 1 is extracted to the surface of the first side surface 12 c of the laminate 12 , and the other second extraction electrode portion 128 b ₁ is extracted to the surface of the second side surface 12 d of the laminate 12 from the second counter electrode portion 126 b. A lead electrode portion 128b ₂ is provided. Specifically, one second extraction electrode portion 128 b ₁ is exposed on the surface of the first side surface 12 c of the laminate 12 , and the other second extraction electrode portion 128 b 2 is exposed on the surface of the second extraction electrode 128 b ₂ of the laminate 12 . is exposed on the surface of the side surface 12d. Therefore, the second internal electrode layer 116b is not exposed on the surface of the first end surface 12e and the surface of the second end surface 12f of the laminate 12. As shown in FIG.

Although the four corners of the second counter electrode portion 126b in the second internal electrode layer 116b are not chamfered, they may be chamfered. This makes it possible to prevent the corners of the first internal electrode layers 116a from overlapping with the corners of the first opposing electrode portions 126a, thereby suppressing electric field concentration. As a result, it is possible to suppress dielectric breakdown of the ceramic capacitor that may occur due to electric field concentration.

Since the material of the internal electrode layer 116 is the same as the material of the internal electrode layer 16, the description thereof is omitted. Also, the thickness and the number of layers of the internal electrode layers 116 are the same as those of the internal electrode layers 16, so the description thereof will be omitted.

External electrodes 30 are arranged on the first end surface 12e side, the second end surface 12f side, and the first side surface 12c side and the second side surface 12d side of the laminate 12 .

The external electrode 30 includes a base electrode layer 32 containing a metal component and a ceramic component, and a Cu plating layer 34 arranged on the surface of the base electrode layer 32 . Moreover, the external electrode 30 preferably includes an upper plated layer 36 arranged on the surface of the Cu plated layer 34 .

The external electrode 30 has a first external electrode 30a, a second external electrode 30b, a third external electrode 30c and a fourth external electrode 30d.

The first external electrode 30a is connected to the first internal electrode layer 116a and arranged on the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the laminate 12 to extend from a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c. It is also arranged on a portion and a portion of the second side 12d. In this case, the first external electrode 30a is electrically connected to one of the first extraction electrode portions 128a ₁ of the first internal electrode layer 116a.

The second external electrode 30b is connected to the first internal electrode layer 116a and arranged on the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the first end surface 12f of the laminate 12 to extend from a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c. It is also arranged on a portion and a portion of the second side 12d. In this case, the second external electrode 30b is electrically connected to the other first extraction electrode portion 128a ₂ of the first internal electrode layer 116a.

The third external electrode 30c is connected to the second internal electrode layer 116b and arranged on the surface of the first side surface 12c. In addition, the third external electrode 30c extends from the first side surface 12c of the laminate 12 and is arranged on part of the first principal surface 12a and part of the second principal surface 12b. In this case, the third external electrode 30c is electrically connected to one second extraction electrode portion 128b ₁ of the second internal electrode layer 116b.

The fourth external electrode 30d is connected to the second internal electrode layer 116b and arranged on the surface of the second side surface 12d. Further, the fourth external electrode 30d extends from the first side surface 12d of the laminate 12 and is arranged on part of the first principal surface 12a and part of the second principal surface 12b. In this case, the fourth external electrode 30d is electrically connected to the other second extraction electrode portion 128b ₂ of the second internal electrode layer 116b.

In the laminate 12, the first counter electrode portion 126a of the first internal electrode layer 116a and the second counter electrode portion 126b of the second internal electrode layer 116b face each other with the ceramic layer 14 interposed therebetween. , a capacitance is formed. Therefore, the first external electrode 30a and the second external electrode 30b to which the first internal electrode layer 116a is connected and the third external electrode 30c and the fourth external electrode to which the second internal electrode layer 116b is connected 30d, the capacitance can be obtained and the characteristics of the capacitor are developed.

The underlying electrode layer 32 has a first underlying electrode layer 32a, a second underlying electrode layer 32b, a third underlying electrode layer 32c, and a fourth underlying electrode layer 32d.

The first base electrode layer 32a is connected to the first internal electrode layer 116a and arranged on the surface of the first end surface 12e. In addition, the first base electrode layer 32a extends from the first end surface 12e to part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c. It is also arranged on part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to one of the first extraction electrode portions 128a ₁ of the first internal electrode layer 116a.
The second base electrode layer 32b is connected to the first internal electrode layer 116a and arranged on the surface of the second end surface 12f. In addition, the second base electrode layer 32b extends from the second end surface 12f to part of the first principal surface 12a, part of the second principal surface 12b, part of the first side surface 12c, and part of the second principal surface 12b. It is also arranged on part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the other first extraction electrode portion 128a ₂ of the first internal electrode layer 116a.

The third base electrode layer 32c is connected to the second internal electrode layer 116b and arranged on the surface of the first side surface 12c. In addition, the third base electrode layer 32c extends from the first side surface 12c and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third base electrode layer 32c is electrically connected to one of the second lead electrode portions 128b ₁ of the second internal electrode layer 116b.
The fourth base electrode layer 32d is connected to the second internal electrode layer 116b and arranged on the surface of the second side surface 12d. Further, the fourth base electrode layer 32d extends from the second side surface 12d and is also arranged on a portion of the first principal surface 12a and a portion of the second principal surface 12b. In this case, the fourth base electrode layer 32d is electrically connected to the other second extraction electrode portion 128b ₂ of the second internal electrode layer 116b.

The Cu plating layer 34 has a first Cu plating layer 34a, a second Cu plating layer 34b, a third Cu plating layer 34c and a fourth Cu plating layer 34d.

The first Cu plating layer 34a is arranged to cover the surface of the first base electrode layer 32a.
The second Cu plating layer 34b is arranged to cover the surface of the second base electrode layer 32b.
The third Cu plating layer 34c is arranged to cover the surface of the third base electrode layer 32c.
The fourth Cu plating layer 34d is arranged to cover the surface of the fourth base electrode layer 32d.

A compressive stress is applied to the Cu plating layer 34 arranged on the first main surface 12a and the second main surface 12b and on the first side surface 12c and the second side surface 12d.

Specifically, the respective first Cu plating layers 34a arranged on the first main surface 12a and the second main surface 12b and the first side surface 12c and the second side surface 12d of the laminate 12 is applied with a compressive stress in the direction from the first end surface 12e of the laminate 12 toward the second end surface 12f.
In addition, the second Cu plating layers 34b arranged on the first main surface 12a and the second main surface 12b and the first side surface 12c and the second side surface 12d of the laminate 12 have Compressive stress is applied in the direction from the second end surface 12f of the laminate 12 toward the first end surface 12e.
The compressive stress applied to the first Cu plating layer 34a and the second Cu plating layer 34b is 50 MPa or more and 300 MPa or less, more preferably 80 MPa or more and 200 MPa or less.

Further, each of the third Cu plating layers 34c arranged on the first main surface 12a and the second main surface 12b of the laminate 12 has the first side surface 12c to the second side surface of the laminate 12. A compressive stress is applied in the direction toward 12d.
Further, each of the fourth Cu plating layers 34d arranged on the first main surface 12a and the second main surface 12b of the laminate 12 has the second side surface 12d to the first side surface of the laminate 12. A compressive stress is applied in the direction toward 12c.
The compressive stress applied to the third Cu plating layer 34c and the fourth Cu plating layer 34d is 50 MPa or more and 300 MPa or less, more preferably 80 MPa or more and 200 MPa or less.

The upper plating layer 36 includes a first upper plating layer 36a, a second upper plating layer 36b, a third upper plating layer 36c and a fourth upper plating layer 36d.

The first upper plated layer 36a is arranged to cover the surface of the first Cu plated layer 34a.
The second upper plated layer 36b is arranged to cover the surface of the second Cu plated layer 34b.
The third upper plated layer 36c is arranged to cover the surface of the third Cu plated layer 34c.
The fourth upper plated layer 36d is arranged to cover the surface of the fourth Cu plated layer 34d.

The upper plated layer 36 may be formed of multiple layers. A two-layer structure of a Ni plating layer and a Sn plating layer is preferred. The Ni-plated layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10B, and the Sn-plated layer prevents solder wetting when mounting the multilayer ceramic capacitor 10B. Therefore, the multilayer ceramic capacitor 10B can be easily mounted on the mounting board. Thus, by forming the upper plated layer 36 with a plurality of layers, the reliability and mountability of the multilayer ceramic capacitor 10B can be efficiently improved.

The material, structure, etc. of the underlying electrode layers in the multilayer ceramic capacitor 10B are the same as those in the multilayer ceramic capacitor 10A, and thus description thereof will be omitted.
Further, since the material, structure, etc. of the Cu plating layer in the multilayer ceramic capacitor 10B are common to those in the multilayer ceramic capacitor 10A, the description thereof will be omitted.
Furthermore, the material, structure, etc. of the upper plated layer in the multilayer ceramic capacitor 10B are the same as those in the multilayer ceramic capacitor 10A, so the description thereof will be omitted.

The dimension in the length direction z of the multilayer ceramic capacitor 10B including the multilayer body 12 and the first external electrodes 30a to the fourth external electrodes 30d is defined as L dimension, and the multilayer body 12 and the first external electrodes 30a to the fourth external electrodes The dimension in the height direction x of the multilayer ceramic capacitor 10B including the electrode 30d is defined as the dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10B including the laminate 12 and the first external electrode 30a to the fourth external electrode 30d is defined as T. W dimension.
The dimensions of the multilayer ceramic capacitor 10B are not particularly limited, but the L dimension in the length direction z is 0.2 mm or more and 10.0 mm or less, the W dimension in the width direction y is 0.1 mm or more and 5.0 mm or less, and the height direction x The T dimension of is 0.05 mm or more and 5.0 mm or less. The dimensions of the laminated ceramic capacitor 10B can be measured with a microscope.

A multilayer ceramic capacitor 10B shown in FIG. 7 has the same effects as the multilayer ceramic capacitor 10A described above.

3. Method for Manufacturing Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described. As an example, a method for manufacturing the laminated ceramic capacitor 10A will be described.

First, a dielectric sheet for ceramic layers and a conductive paste for internal electrode layers are prepared. The conductive paste for dielectric sheets and internal electrode layers contains a binder and a solvent. Binders and solvents may be known in the art.

Then, a conductive paste for internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. As a result, a dielectric sheet on which the pattern of the first internal electrode layer is formed and a dielectric sheet on which the pattern of the second internal electrode layer is formed are prepared.

Subsequently, a predetermined number of outer layer dielectric sheets on which the patterns of the internal electrode layers are not printed are laminated to form a portion to be the second main surface side outer layer portion on the second main surface side. . Then, the dielectric sheet printed with the pattern of the first internal electrode layer and the dielectric sheet printed with the pattern of the second internal electrode layer on the portion to be the outer layer portion on the second main surface side are provided. By successively laminating layers so as to form the structure of the invention, a portion that becomes an effective portion is formed. A predetermined number of outer layer dielectric sheets on which the patterns of the internal electrode layers are not printed are laminated on the portion to be the effective portion, thereby forming a first main surface side outer layer portion on the first main surface side. is formed. Thereby, a laminated sheet is produced.

Next, a laminated block is produced by pressing the laminated sheet in the lamination direction by means such as isostatic pressing.

Then, the laminated chip is cut out by cutting the laminated block into a predetermined size. At this time, the corners and ridges of the laminated chip may be rounded by barrel polishing or the like.

Next, a conductive paste, which will serve as base electrode layers, is applied to both end faces of the laminated chip. In this embodiment, the base electrode layer is a baked layer. The conductive paste includes metal components, ceramic components, solvents, dispersants, and the like. As a method of applying the conductive paste to the laminated chip, for example, a method such as a dipping method or a screen printing method is used. For example, Ni can be used as the metal component, and BaTiO ₃ can be used as the ceramic component. After that, a baking process is performed to form a base electrode layer.

When the base electrode layer is formed of a thin film layer, the base electrode layer can be formed by a thin film formation method such as a sputtering method or a vapor deposition method. The base electrode layer formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

Subsequently, the unfired laminated chip having the internal electrode layer and the ceramic layer and the conductive paste for the base electrode layer applied to the unfired laminated chip are simultaneously baked (fired) to form the base electrode layer. to form a laminated body. At this time, the baking temperature (firing temperature) is preferably 900° C. or higher and 1400° C. or lower. The baking layer may be multiple layers.

Next, a Cu plating layer is formed. The Cu plating layer is formed by plating on the surface of the base electrode layer. Either electroplating or electroless plating may be employed for the plating treatment. However, electroless plating requires pretreatment with a catalyst or the like in order to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, it is usually preferable to adopt electrolytic plating.

Next, heat treatment is performed after forming the Cu plating layer. The heat treatment temperature is preferably 250° C. or higher and 800° C. or lower. By heat-treating the Cu plating layer, the inside of the Cu plating layer, the interface between the Cu plating layer and the underlying electrode layer (Ni co-fire), and further, the water in the Cu plating solution residue in the Ni co-fire film evaporates. It scatters to the outside and can improve humidity resistance reliability. In addition, the adhesion between the Ni co-fired electrode of the underlying electrode layer and the Cu plating layer can be enhanced.

Here, by applying a mechanical impact such as barrel or powder blasting to the Cu plating layer, it is possible to apply a compressive stress to the Cu plating layer due to the shot peening effect on the Cu plating layer, and the stress is reduced to 50 MPa. It can be set to 300 MPa or less. At this time, the value of the compressive stress of the Cu plating layer is controlled by making the surface of the Cu plating layer collide with cobblestones of the barrel or the powder of the powder blast treatment, and applying the compressive stress by plastic deformation. Specifically, it can be controlled by controlling the size of the colliding boulder or split body, the impact force for colliding, time, and the like.

Next, an upper plated layer is formed on the surface of the Cu plated layer. Either electroplating or electroless plating can be used for plating, but electroless plating requires pretreatment with a catalyst or the like in order to increase the rate of plating deposition, which complicates the process. There is a disadvantage. Therefore, it is usually preferable to adopt electrolytic plating. As the plating method, barrel plating is preferably used. Also, if necessary, an upper layer plating electrode may be formed in the same manner on the surface of the lower layer plating electrode. In the multilayer ceramic capacitor 10A shown in FIG. 1, the Ni plating layer is formed so as to cover the Cu plating layer, and the Sn plating layer is formed so as to cover the Ni plating layer. The Ni plating layer and the Sn plating layer are sequentially formed by, for example, barrel plating.

As described above, the multilayer ceramic capacitor 10A according to the present embodiment is manufactured.

4. Experimental Example A multilayer ceramic capacitor as a sample was produced according to the manufacturing method described above, and evaluated by measuring the stress in the Cu plating layer and confirming the presence or absence of cracks in the laminate.

(a) Specification of Sample of Example As an example, a laminated ceramic capacitor having the following specifications was prepared. For the prepared samples of Examples 1 to 8, as shown in Table 1, the magnitude of stress applied to the Cu plating layer was varied.

・Dimensions of laminated ceramic capacitor (design value): L×W×T=2.0 mm×1.2 mm×0.65 mm
・Capacitor type: 3-terminal capacitor (see Figure 7)
・Material of the main component of the ceramic layer: BaTiO ₃
・Capacity: 22μF
・Rated voltage: 4V
・Layer thickness of ceramic layer: 0.65 μm
・Internal electrode layer material: Ni

・Specifications of the external electrode layer Specifications of the base electrode layer ・Base electrode layer: Baked layer containing metal and ceramic components ・Metal component: Ni
・Thickness of base electrode layer ・Thickness in length direction z at the central portion in height direction x of the baking layer located on the first end surface and the second end surface: 11 μm
・Thickness in the height direction x connecting the first main surface and the second main surface at the central portion in the length direction z of the baking layer located on the first main surface and the second main surface (e dimension central portion Partial base electrode layer thickness): 3 μm
The thickness in the width direction y connecting the first side and the second side at the center in the length direction z of the baking layers located on the first side and the second side (the base electrode layer in the center part of the e dimension thickness): 3 μm

・Specification of Cu plating layer ・Compressive stress: See Table 1 ・Thickness: 6 μm
Specifications of lower plating layer

・Specifications of upper plating layer ・Structure of upper plating layer: Two-layer structure of Ni plating layer and Sn plating layer ・Thickness of Ni plating layer: 4 μm
・ Thickness of Sn plating layer: 4 μm

(b) Specifications of Samples of Comparative Examples As Comparative Example 1, specifications were the same as those of Examples except that a tensile stress of 30 MPa was applied to a Cu plating layer having a thickness of 6 μm.
As Comparative Example 2, the specifications were the same as those of the Example except that a compressive stress of 5 MPa was applied to a Cu plating layer having a thickness of 6 μm.
As Comparative Example 3, the specifications were the same as those of the Example except that a compressive stress of 400 MPa was applied to a Cu plating layer having a thickness of 6 μm.

(c) Measurement and test method (crack test and confirmation method for the presence or absence of cracks)
As a method for confirming the presence or absence of cracks, first, a multilayer ceramic capacitor as a sample was mounted on a mounting substrate of a glass epoxy substrate (single layer) having a thickness of 0.8 mm using solder paste. After that, the back surface of the substrate on which the sample multilayer ceramic capacitor was not mounted was bent with a push rod having a width of 20 mm to apply mechanical stress. The holding time at this time was 20 seconds, and the amount of bending was changed to 1.5 mm, 2.0 mm, and 3.0 mm. In this test, the conditions were stricter than the normal conditions. After bending the substrate, the multilayer ceramic capacitor is removed from the substrate, the cross section is polished, and the presence or absence of cracks is observed. Cross-sectional polishing is performed so that the LT surface of the multilayer ceramic capacitor is exposed to a position that is 1/2 W of the dimension W in the width direction y of the multilayer along the plane direction parallel to the side surface of the multilayer ceramic capacitor. was polished. The observation magnification was x100. Then, when there was a crack extending inward of the laminate starting from the vicinity of the tip of the external electrode located on the first main surface and the second main surface, it was determined that there was a crack. The number of samples in each example and each comparative example was 20.

(Method for measuring stress)
The compressive stress in the Cu plating layer was measured by the method described below.
First, the Ni plating layer and the Sn plating layer formed on the surface of the Cu plating layer were peeled off.
As a method for stripping the Sn plating layer, the laminated ceramic capacitor was immersed in a Sn stripping solution to strip Sn. As the liquid, a liquid that dissolves Sn but hardly dissolves the underlying Ni was used, and Melstrip HN980M was used. The immersion time was about 10 minutes. Since the immersion time varies depending on the size of the product and the liquid concentration, it was adjusted each time.
As a method for removing the Ni plating layer, the laminated ceramic capacitor was immersed in a Ni removing solution to remove the Ni. As the liquid, a liquid that dissolves Ni but hardly dissolves the underlying Cu was used, and ENSTRIP NP was used. The immersion time was about 120 minutes. Since the immersion time varies depending on the size of the product and the liquid concentration, it was adjusted each time. At this time, the surface of the Cu plating layer may be discolored due to oxidation, but since it is only the surface layer, it does not affect the stress measurement by X-rays performed later.
Then, after peeling off the Sn plating layer and the Ni plating layer, the length direction of the Cu plating layer located on the first main surface or the second main surface, the first side surface or the second side surface of the multilayer ceramic capacitor The stress of the Cu plating layer was measured using a micro stress measuring device (XRD) at the central portion in the z and width direction y.

(d) Results Table 1 shows the measurement results of compressive stress for each sample of Examples 1 to 6 and Comparative Examples 1 to 3, and cracks inside the laminate due to changes in the amount of bending of the substrate. The test results of presence/absence are shown.

According to Table 1, in the samples of Examples 1 to 6, the compressive stress applied to the Cu plating layer was in the range of 50 MPa to 300 MPa. Good results were obtained with no cracks in any of the 20 samples.
Furthermore, in the samples of Examples 2 to 5, the compressive stress applied to the Cu plating layer was within the range of 80 MPa or more and 200 MPa or less. Better results were obtained for all samples without cracks.

On the other hand, in the sample of Comparative Example 1, a tensile stress of 30 MPa was applied to the Cu plating layer. Starting from near the tip of the external electrode located on the main surface of the laminate, a crack extending toward the inside of the laminate is generated. Cracks extending toward the inside of the laminate were generated starting from the vicinity of the tips of the external electrodes located on the main surface and the second main surface.

In addition, in the sample of Comparative Example 2, only a compressive stress of 5 MPa was applied to the Cu plating layer. Starting from near the tip of the external electrode located on the main surface of the laminate, a crack extending toward the inside of the laminate occurs. Cracks extending toward the inside of the laminate were generated starting from the vicinity of the tips of the external electrodes located on the main surface and the second main surface.

Furthermore, in the sample of Comparative Example 3, a compressive stress of 400 MPa was applied to the Cu plating layer. Starting from near the tip of the external electrode located on the main surface of the laminate, a crack extending toward the inside of the laminate is generated. Cracks extending toward the inside of the laminate were generated starting from the vicinity of the tips of the external electrodes located on the main surface and the second main surface.

From the above results, in the present invention, compressive stress is applied to the Cu plating layer due to the above configuration. It was suggested that it becomes possible to relax the stress applied to the tip part, and it is possible to suppress the occurrence of cracks in the laminate.
More specifically, the conventional problem with multilayer ceramic capacitors is that the Cu plating layer can provide a stress in the opposite direction to the direction of the stress applied to the ends of the base electrode layer. The compressive stress of a predetermined magnitude within the above-described range can cancel the stress applied to the laminate from the ends of the underlying electrode layers, and can relax the stress applied to the tip portions of the underlying electrode layers. As a result, it was suggested that cracks in the laminate can be suppressed.

As described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.
That is, without departing from the scope of the technical idea and purpose of the present invention, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. and they are included in the present invention.

10A, 10B laminated ceramic capacitor 12 laminated body 12a first main surface 12b second main surface 12c first side surface 12d second side surface 12e first end surface 12f second end surface 14 ceramic layer 16, 116 internal electrode layer 16a, 116a first internal electrode layer 16b, 116b second internal electrode layer 18 effective portion 20a first main surface side outer layer portion 20b second main surface side outer layer portion 22a first side outer layer portion 22b second second side surface side outer layer portion 24a first end surface side outer layer portion 24b second end surface side outer layer portion 26a, 126a first counter electrode portion 26b, 126b second counter electrode portion 28a, 128a ₁ , 128a ₂ first drawer Electrode portions 28b, 128b ₁ , 128b ₂ Second extraction electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Underlying electrode layer 32a Base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 Cu plating layer 34a First Cu plating layer 34b Second Cu plating layer 34c Third Cu plating layer 34d Fourth Cu plating layer 36 Upper plating layer 36a First upper plating layer 36b Second upper plating layer 36c Third upper plating layer 36d Fourth upper plating layer x height direction y width direction z length direction

Claims (7)

A first main surface and a second main surface facing each other in a height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal to the height direction, including a plurality of laminated ceramic layers. and a first end surface and a second end surface facing each other in a length direction orthogonal to the height direction and the width direction;
a first internal electrode layer disposed on the plurality of ceramic layers and positioned inside the laminate;
a second internal electrode layer disposed on the plurality of ceramic layers and positioned inside the laminate;
a first main surface disposed on the first end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface; an external electrode of
A second surface disposed on the second end surface, a portion of the first main surface, a portion of the second main surface, a portion of the first side surface and a portion of the second side surface. an external electrode of
In a multilayer ceramic capacitor having
The first external electrode and the second external electrode each have a base electrode layer having a metal component and a ceramic component, and a Cu plating layer disposed on the surface of the base electrode layer,
Compressive stress is applied to the Cu plating layers arranged on the first main surface and the second main surface and on the first side surface and the second side surface of the laminate, The laminated ceramic electronic component, wherein the compressive stress is 50 MPa or more and 300 MPa or less. The first internal electrode layer has a first facing portion facing the second internal electrode layer, and a first lead portion drawn out from the first facing portion to a first end surface. The internal electrode layer of claim 1 has a second facing portion facing the first internal electrode layer and a second lead-out portion drawn out from the second facing portion to the second end surface. A laminated ceramic electronic component as described. 3. The multilayer ceramic electronic component according to claim 1, wherein said compressive stress is 80 MPa or more and 200 MPa or less. 4. The multilayer ceramic electronic component according to claim 1, wherein an upper plated layer is arranged on the surface of said Cu plated layer. 5. The laminated ceramic electronic component according to claim 4, wherein said upper plated layer contains at least one selected from Cu, Ni, Sn, Ag, Pd, Ag--Pd alloy, and Au. 6. The multilayer ceramic electronic component according to claim 4, wherein said upper plated layer is arranged in a plurality of layers. The first internal electrode layers are arranged on a plurality of ceramic layers and are drawn out to a first end face and a second end face,
The second internal electrode layers are arranged on a plurality of ceramic layers and are drawn out to the first side surface and the second side surface,
a third external electrode connected to the second internal electrode exposed on the first side surface; and a fourth external electrode connected to the second internal electrode exposed on the second side surface. 7. The multilayer ceramic electronic component according to claim 1, comprising:

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