KR101967446B1 - Tunneling Transistor and manufacturing the same - Google Patents

Abstract

According to an embodiment of the present invention, there is provided a liquid crystal display comprising: a first electrode disposed on a substrate; A first insulating layer disposed on the first electrode; A floating electrode disposed on the first insulating layer; A second insulating layer disposed on the floating electrode; A second electrode disposed on the second insulating layer; And a gate electrode disposed to be insulated from the first electrode and the second electrode, the gate electrode controlling a tunneling current between the first electrode and the second electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to a tunneling transistor,

Embodiments of the present invention relate to a tunneling transistor, and more particularly to a tunneling transistor including a floating electrode.

A transistor is an element that acts as an amplifier or switch by regulating current or voltage flow. These transistors have been reduced in size from tens of micrometers to tens of nanometers over the past half century and have played a major role in miniaturization and low power operation of various electronic devices such as PCs, tablets and smart phones.

An increasing number of transistors are disposed within a single chip, thereby reducing the spacing between the transistors. That is, as the distance between the electrodes included in the transistor becomes closer to each other, electrons included in one electrode are inadvertently moved to other electrodes due to quantum tunneling phenomenon.

The tunneling transistor is a transistor that uses the problem of the conventional transistor as a reverse, and uses a method of controlling the tunneling current through a method of raising or lowering an energy barrier between the input electrode and the output electrode.

Tunneling transistors can be driven with less energy and are suitable for miniaturization because the spacing between the electrodes is very small, ranging from several to several tens of nanometers.

However, there is a problem that an unintended leakage current can easily occur due to a very small distance between the electrodes of the tunneling transistor, and there is a growing demand for a technique for precisely controlling the tunneling current while minimizing such leakage current .

KR 10-2011-0111743 A, 2011.10.12

An object of the present invention is to provide a vertical tunneling transistor in which a distance between a source electrode and a drain electrode is easily adjusted by arranging a source electrode and a drain electrode vertically.

It is another object of the present invention to provide a tunneling transistor capable of controlling a tunneling current while minimizing a leakage current by disposing a floating electrode between a source electrode and a drain electrode.

However, these problems are exemplary and do not limit the scope of the present invention.

According to one aspect of the present invention, there is provided a liquid crystal display comprising: a first electrode disposed on a substrate; A first insulating layer disposed on the first electrode; A floating electrode disposed on the first insulating layer; A second insulating layer disposed on the floating electrode; A second electrode disposed on the second insulating layer; And a gate electrode disposed to be insulated from the first electrode and the second electrode, the gate electrode controlling a tunneling current between the first electrode and the second electrode.

The floating electrode and the gate electrode are disposed between the first insulating layer and the second insulating layer and may be made of the same material.

The gate electrode includes a first gate electrode and a second gate electrode disposed on both sides of the floating electrode, and the first gate electrode and the second gate electrode may be electrically connected or insulated.

The first electrode and the second electrode may be disposed so as to overlap each other in a plane with the floating electrode.

The first electrode and the second electrode may have different shapes.

The second electrode may include a main region and a sharped region where the width gradually decreases from a portion connected to the main region to an end.

The pointed area may be plural.

The second electrode may be a nanotube, a nanowire, or a nanocylinder extending in a direction perpendicular to the main surface of the substrate.

The width of the floating electrode in the first direction may be greater than the width of at least one of the first electrode and the second electrode in the first direction.

The gate electrode may be disposed in the first direction with respect to the floating electrode.

The distance between the first electrode and the floating electrode and the distance between the second electrode and the floating electrode may be 1 nm to 150 nm, respectively.

The distance between the gate electrode and the floating electrode may be between 1 nm and 10 [mu] m.

The gate electrode may have a frame shape or a ring shape formed so as to surround the floating electrode.

The distance between the gate electrode and the first electrode may be at least four times the distance between the first electrode and the floating electrode.

The floating electrode may include at least one edge including a plurality of irregularities.

The floating electrode may include at least one hole.

The floating electrode may include a plurality of irregularities formed on at least one of a surface facing the first electrode and a surface facing the second electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first electrode on a substrate; Forming a first insulating layer on the first electrode; Forming a gate electrode and a floating electrode on the first insulating layer; Forming a second insulating layer covering the gate electrode and the floating electrode on the first insulating layer; And forming a second electrode on the second insulating layer.

The gate electrode and the floating electrode may be formed of the same material through the same process.

Other aspects, features and advantages of the present invention will become apparent from the following detailed description, claims, and drawings.

According to one embodiment of the present invention as described above, a vertical tunneling transistor having a source electrode and a drain electrode arranged vertically and easily adjusting a distance between a source electrode and a drain electrode can be provided.

Also, by disposing the floating electrode between the source electrode and the drain electrode, it is possible to provide a tunneling transistor capable of controlling the tunneling current while minimizing the leakage current.

1 is a plan view schematically illustrating a tunneling transistor according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II-II 'of FIG.
3 is a cross-sectional view schematically showing a tunneling transistor according to a comparative example.
4 to 6 are perspective views schematically illustrating a tunneling transistor according to another embodiment of the present invention.
7 to 9 are plan views schematically showing a floating electrode according to another embodiment of the present invention.
10 is a cross-sectional view schematically illustrating a floating electrode according to another embodiment of the present invention.
11 and 12 are plan views schematically showing a gate electrode according to another embodiment of the present invention.
13 is a flowchart illustrating a method of manufacturing a tunneling transistor according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods of achieving them will be apparent with reference to the embodiments described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout the drawings, and a duplicate description thereof will be omitted .

In the following embodiments, when various components such as layers, films, regions, plates, and the like are referred to as being " on " other components, . Also, for convenience of explanation, the components may be exaggerated or reduced in size. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

In the following embodiments, the x-axis, the y-axis, and the z-axis are not limited to three axes on the orthogonal coordinate system, and can be interpreted in a broad sense including the three axes. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

FIG. 1 is a plan view schematically showing a tunneling transistor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG.

Referring to FIGS. 1 and 2, a tunneling transistor 1 according to an embodiment includes a first electrode 110 disposed on a substrate 101, a first insulating layer (not shown) disposed on the first electrode 110, A floating electrode 140 disposed on the first insulating layer 103; a second insulating layer 105 disposed on the floating electrode 140; a second insulating layer 105 disposed on the second insulating layer 105; And a gate electrode 130 that is insulated from the first and second electrodes 110 and 120 and controls the tunneling current between the first and second electrodes 110 and 120. The first electrode 110 and the second electrode 120 are formed on the first electrode 110 and the second electrode 120, .

The substrate 101 may be made of various materials such as glass or plastic, and may be, for example, a silicon-based insulating substrate. In particular, since a high-temperature process is not required, substrates of various materials can be used regardless of heat resistance.

The first electrode 110 may be a source electrode or a drain electrode. The first electrode 110 may be an output electrode through which a signal is output.

A floating electrode 140 insulated from the first electrode 110 by the first insulating layer 103 may be disposed on the first electrode 110. The floating electrode 140 may be a dummy electrode that is not connected to other conductors included in the tunneling transistor 1 and may be a dummy electrode having an influence of an electric field caused by the first electrode 110 and / .

According to one embodiment, the gate electrode 130 may be disposed on the first insulating layer 103. That is, the floating electrode 140 and the gate electrode 130 may be disposed on the same layer between the first insulating layer 103 and the second insulating layer 105, and may be formed of the same material. For example, the first electrode 110, the gate electrode 130, and the floating electrode 140 may be made of chrome (Cr) or aluminum (Al) having a low work function. A control voltage is applied to the gate electrode 130 and a tunneling current flowing between the first electrode 110 and the second electrode 120 can be controlled according to a voltage applied by the gate electrode 130. This will be described later.

A second insulating layer 105 covering the gate electrode 130 and the floating electrode 140 may be disposed on the first insulating layer 103 and a second electrode 120 may be disposed on the second insulating layer 105. have. 11, the insulating layer 103 and second insulating layer 105 may comprise a highly inorganic insulating material or organic insulating material insulating properties, for example, SiO _2, Al ₂ O _3, HfO, BaTiO _3, SrTiO _3, An inorganic material such as PbTiO ₃ , (Ba, Sr) TiO ₃ (BST) and Pb (Zr, Ti) O ₃ (PZT), an organic material such as PVDF, PMMA and PDMS or a 2D material such as BN.

The second electrode 120 may be a drain electrode (when the first electrode 110 is a source electrode) or a source electrode (when the first electrode 110 is a drain electrode). Also, the second electrode 120 may be an input electrode.

The tunneling transistor 1 according to one embodiment is a vertical tunneling transistor in which a first electrode 110 and a second electrode 120 are disposed along a third direction z perpendicular to the main surface of the substrate 101 .

The tunneling transistor is an element that amplifies or acts as a switch by using a quantum tunneling phenomenon instead of using a semiconductor material. By disposing two electrodes sandwiching an insulating layer so that tunneling can occur, The electrons are moved to the output electrode by tunneling to generate a tunneling current.

According to an embodiment of the present invention, the distance between the first electrode 110 and the second electrode 120 is an important factor affecting the characteristics of the tunneling transistor, for example, the characteristics of the tunneling current depending on the applied voltage. However, when the first electrode 110 and the second electrode 120 are formed in a horizontal direction (x direction or y direction) with respect to the main surface of the substrate 101, a horizontal tunneling transistor , There is a process difficulty in forming the first electrode 110 and the second electrode 120 to maintain a distance of several nanometers to several tens of nanometers. For example, it is difficult to form the first electrode 110 and the second electrode 120 to be separated from each other by a distance of several nanometers to several tens of nanometers by a photolithography process generally used for patterning a conductive material.

 However, according to the embodiment of the present invention, since the first electrode 110 and the second electrode 120 are arranged in the third direction z perpendicular to the substrate 101, Since the first insulating layer 103 and the second insulating layer 105 disposed between the two electrodes 120 can be easily formed to a thickness of about several nanometers, a desired degree of tunneling current can be secured.

A floating electrode 140 is disposed between the first electrode 110 and the second electrode 120 and the floating electrode 140 is electrically connected to the second electrode 120, And transmits the electrons to the first electrode 110, which is an output electrode. A first thickness t ₁ of the first insulating layer 103 disposed between the first electrode 110 and the floating electrode 140 and a second thickness t ₁ of the second insulating layer 103 disposed between the second electrode 120 and the floating electrode 140 The second thickness t ₂ of the second insulating layer 105 may have a value at which a desired degree of tunneling may occur. For example, the first thickness t ₁ and the second thickness t ₂ may each have a value of 1 nm to 150 nm. Thicknesses less than 1 nm are practically difficult to implement, and tunneling phenomena may not occur if they exceed 150 nm. The first thickness t ₁ and the second thickness t ₂ may be determined depending on the kind of material constituting the first insulating layer 103 and the second insulating layer 105 and the characteristics of the desired tunneling transistor, More preferably, the first thickness t ₁ and the second thickness t ₂ may have values of 1 nm to 10 nm.

The tunneling current flowing between the first electrode 110 and the second electrode 120 needs to be controlled by using a separate control electrode, that is, the gate electrode 130 like the conventional semiconductor-based transistor. According to an embodiment of the present invention, a gate electrode 130 for controlling a tunneling current may be disposed between the first electrode 110 and the second electrode 120 by applying a control voltage.

1 and 2, the gate electrode 130 includes a first gate electrode 130a and a second gate electrode 130b disposed on both sides of the floating electrode. The first gate electrode 130a and the second gate electrode 130b may be electrically connected or may be insulated from each other. The first gate electrode 130a and the second gate electrode 130b may be supplied with the same voltage, different voltages, or both.

However, the present invention is not limited to this, and according to another embodiment, only one gate electrode 130 may be disposed on one side of the floating electrode. According to another embodiment, the first gate electrode 130a and the second gate electrode 130b may be different portions of one gate electrode 130 connected to each other. This will be described later.

In order to effectively control the tunneling current between the first electrode 110 and the second electrode 120, an electric field generated by the voltage applied by the gate electrode 130 is applied to the first electrode 110 And the second electrode 120. The second electrode 120 may be formed of a conductive material. Hereinafter, referring to an embodiment of the present invention shown in FIG. 2 and a comparative example shown in FIG. 3, a case where the floating electrode 140 is provided and a case where the floating electrode 140 is not provided will be described.

FIG. 3 shows a tunneling thin film transistor according to a comparative example. Referring to FIG. 3, a first electrode 110 'disposed horizontally relative to a main surface of a substrate 101' by a gate electrode 130 ' ) And the second electrode 120 'are controlled.

When the distance between the gate electrode 130 'and the first electrode 110' / the second electrode 120 'is long, the electric field strength of the electric field is inversely proportional to the square of the distance, Is significantly smaller than the electric field between the first electrode 110 'and the second electrode 120', and the tunneling current can not be precisely controlled by the gate electrode 130 '.

Therefore, in order to effectively control the tunneling current between the first electrode 110 'and the second electrode 120', the distance d ₂ 'between the gate electrode 130' and the first electrode 110 ' The distance d ₃ 'between the second electrode 120' and the gate electrode 130 'is formed to be similar to the distance d ₁ ' between the first electrode 110 'and the second electrode 120' do.

In this case, however, the distance between the gate electrode 130 'and the first electrode 110' / the second electrode 120 'becomes too close to cause tunneling to the gate electrode 130' 130 '.

In addition, when the distance between the gate electrode 130 'and the first electrode 110' / the second electrode 120 'is increased, a larger voltage is applied to the gate electrode 130' The current is leaked to the gate electrode 130 '. That is, leakage current is inevitably generated by the gate electrode 130 '.

However, according to an embodiment of the present invention, a floating electrode 140 is disposed between the first electrode 110 and the second electrode 120, and the first electrode 110, the second electrode 120, The electrodes 140 are arranged so as to overlap each other along the plane, that is, the third direction (x). The floating electrode 140 is a conductor that acts as a bridge between the first electrode 110 and the second electrode 120. The floating electrode 140 has a tunneling current between the first electrode 110 and the second electrode 120, value is dependent on the distance (d ₁₂₎ between the first electrode 110 and the distance between the floating electrode 140 (d ₁₁₎ and the second electrode 120 and the floating electrode 140.

 The voltage of the floating electrode 140 is changed by the electric field generated by the gate electrode 130, that is, the first gate electrode 130a and / or the second gate electrode 130b. This changes the probability of tunneling from the first electrode 110 as the input electrode to the floating electrode 140 and the tunneling probability from the floating electrode 140 to the second electrode 120 as the output electrode, The tunneling current between the electrode 110 and the second electrode 120 can be changed.

In this case, the distance between the gate electrode 130 and the floating electrode 140, that is, the distance d ₅₁ between the first gate electrode 130a and the floating electrode 140 and the distance between the second gate electrode 130b and the floating electrode 140 The distance d ₅₂ between the first electrode 110 and the floating electrode 140 is similar to the distance d ₁₁ between the first electrode 110 and the floating electrode 140 and the distance between the second electrode 120 and the floating electrode d ₁₂ .

For example, the distance d ₁₁ between the first electrode 110 and the floating electrode 140 and the distance between the second electrode 120 and the floating electrode d ₁₂ may be 1 nm to 150 nm, 130 and the floating electrode 140 may also be between 1 nm and 150 nm.

According to one embodiment, the following conditional expression can be satisfied.

<Expression>

According to another embodiment, the electric field by the gate electrode 130 can be adjusted by changing the intensity of the voltage applied by the gate electrode 130, so that the distance between the gate electrode 130 and the floating electrode 140 is several micro Meter. That is, the distance between the gate electrode 130 and the floating electrode 140 may be 1 nm to 10 μm.

The distance d ₂ between the gate electrode 130 and the first electrode 110 and the distance d ₂ between the gate electrode 130 and the gate electrode 130 are different from each other in the case of the tunneling transistor 1 including the floating electrode 140. [ The distance d ₃ between the two electrodes 120 is a distance d ₁₁ between the first electrode 110 and the floating electrode 140 and a distance d ₁₁ between the second electrode 120 and the floating electrode 140 ₁₂ ). For example, the distance between the gate electrode 130 and the first electrode 110 may be at least four times the distance between the first electrode 110 and the floating electrode 140. With this configuration, the tunneling current between the first electrode 110 and the second electrode 120 can be efficiently controlled by using the gate electrode 130, and the leakage current to the gate electrode 130 can be removed or reduced have.

Gate electrode 130 and the first electrode 110 / the second distance between the electrode (120), (d _2, d _3), the zoom to form, the width of the first direction (x) of the floating electrode 140 The width W _{140 of} the first electrode 110 may be greater than the width W ₁₁₀ of the first electrode ₁₁₀ and the width W ₁₂₀ of the second electrode 120 in the first direction x. The first direction x indicates the direction in which the gate electrode 130 is disposed with respect to the floating electrode 140. That is, the gate electrode 130 is disposed in the first direction x with respect to the floating electrode 140.

That is, the floating electrode 140 may include a protruding region protruding in the first direction (x) with respect to the first electrode 110 and the second electrode 120.

For example, when the width W _a of the protruding region is 1 μm and the distance d ₁₁ between the first electrode 110 and the floating electrode 140 is 5 nm with respect to the first electrode 110 of the floating electrode 140, And the distance d ₅₁ between the gate electrode 130 and the floating electrode 140 is 10 nm, arithmetically, the distance d ₂ between the gate electrode 130 and the floating electrode 140 is about 1.01 um.

That is, by employing the floating electrode 140, the first thickness t ₁ of the first insulation layer and the second thickness t _{1 of} the second insulation layer disposed between the first electrode 110 and the second electrode 120 the distance (d _2, d ₃₎ between the gate electrode 130 and first electrode 110 / the second electrode 120 as compared to t ₂₎ can be sufficiently large. Therefore, the leakage current to the gate electrode 130 can be removed or reduced.

According to an embodiment of the present invention, the first electrode 110 and the second electrode 120 have different shapes, and thus may be asymmetric with respect to each other. 2, the second electrode 120 may include a main region 120a and a sharped region 120b having a width less than the width W ₁₂₀ of the main region 120a. have. The pointed region 120b may have a pointed shape whose width gradually decreases from a portion connected to the main region 120a to an end thereof.

According to one embodiment, the second electrode 120 may be an input electrode to which a voltage is applied. When a predetermined voltage is applied to the second electrode 120, a strong electric field is formed in the sharp region 120b. The tunneling barrier can be lowered to increase the number of electrons moving from the second electrode 120 to the floating electrode 140 and consequently to the first electrode 110, that is, the current value.

Although the above description has been made on the case where the second electrode 120 is the input electrode and the first electrode 110 is the output electrode, the present invention is not limited thereto. That is, the first electrode 110 may be an input electrode and the second electrode 120 may be an output electrode. Also, the first electrode 110 may include a pointed region, or both the first and second electrodes 110 and 120 may include a pointed region.

4 through 6 are cross-sectional views schematically showing a tunneling transistor according to another embodiment of the present invention.

Hereinafter, the tunneling transistors 2, 3 and 4 of FIGS. 4 to 6 will be described focusing on the difference from the tunneling transistor 1 of FIGS. 1 and 2. The tunneling transistor 1 and the tunneling transistor 1 of FIGS. Description of the same configuration will be omitted.

4, the tunneling transistor 2 according to one embodiment includes a first electrode 210 disposed on a substrate 201, a first insulating layer 203 disposed on the first electrode 210, A floating electrode 240 disposed on the first insulating layer 203, a second insulating layer 205 disposed on the floating electrode 240, a second electrode 220 disposed on the second insulating layer 205, And a gate electrode 230 insulated from the first and second electrodes 210 and 220 and controlling the tunneling current between the first and second electrodes 210 and 220.

The gate electrode 230 includes a first gate electrode 230a and a second gate electrode 230b that are electrically connected or isolated from each other and the floating electrode 240 includes a first electrode 210 and a second electrode 220 to transmit the electrons tunneled from the first electrode 210 to the second electrode 220. [

The electric field generated by the first gate electrode 230a and the second gate electrode 230b may change the voltage of the floating electrode 240 and may result in tunneling between the first electrode 210 and the second electrode 220. [ Change the current. At this time, since the distance between the gate electrode 230 and the first electrode 210 / the second electrode 220 is sufficiently longer than the distance between the first electrode 210 and the second electrode 220, the gate electrode 230 Can be minimized.

The first electrode 210 and the second electrode 220 are asymmetric with respect to each other and the second electrode 220 has a shape elongated in a direction perpendicular to the main surface of the substrate 201 . That is, the second electrode 220 may be formed of a nanotube, a nanowire, a nanocylinder, or the like having a large aspect ratio.

For example, the second electrode 220 may be an input electrode to which a voltage is applied, and the second electrode 220 may be formed of a conductor having a large aspect ratio, 240, and as a result, the number of electrons tunneled to the first electrode 210 can be increased. That is, the tunneling current can be increased only by changing the shape of the second electrode 220 without increasing the applied voltage.

5, a tunneling transistor 3 according to one embodiment includes a first electrode 310 disposed on a substrate 301, a first insulating layer 303 disposed on the first electrode 310, A floating electrode 340 disposed on the first insulating layer 303, a second insulating layer 305 disposed on the floating electrode 340, a second electrode 320 disposed on the second insulating layer 305, And a gate electrode 330 which is insulated from the first and second electrodes 310 and 320 and controls a tunneling current between the first and second electrodes 310 and 320.

The gate electrode 330 may include a first gate electrode 330a and a second gate electrode 330b which are electrically connected or isolated from each other.

The first electrode 310 and the second electrode 320 are asymmetrical with respect to each other and the second electrode 320 has a width smaller than the width of the main region 320a and the main region 320a And a plurality of sharped regions 320b1, 320b2, and 320b3 having a plurality of sharped regions 320b1, 320b2, and 320b3. The plurality of sharped regions 320b1, 320b2, and 320b3 may each have a pointed shape that gradually decreases in width from a portion connected to the main region 320a.

According to one embodiment, the second electrode 320 may be an input electrode to which a voltage is applied. When a predetermined voltage is applied to the second electrode 320, a plurality of sharp areas 320b1, 320b2, and 320b3 A strong electric field is formed in the first electrode 310. This configuration reduces the tunneling barrier to increase the number of electrons moving from the second electrode 320 to the floating electrode 340 and consequently to the first electrode 310, have. That is, although the second electrode 120 of FIG. 1 includes one pointed region 120b, the second electrode 320 of FIG. 5 includes a plurality of pointed regions 320b1, 320b2, and 320b3, Configuration can achieve high tunneling current even at low applied voltage.

Referring to FIG. 6, the tunneling transistor 4 according to one embodiment includes a first electrode 410 disposed on a substrate 401, a first insulating layer 403 disposed on the first electrode 410, A floating electrode 440 disposed on the first insulating layer 403, a second insulating layer 405 disposed on the floating electrode 440, a second electrode 420 disposed on the second insulating layer 405, And a gate electrode 430 insulated from the first and second electrodes 410 and 420 and controlling the tunneling current between the first and second electrodes 410 and 420.

According to one embodiment, the second electrode 420 may not include a pointed region unlike the second electrode 120 of FIG. That is, the second electrode 420 may have substantially the same shape as the first electrode 410, and may be symmetrical to each other. Unlike the gate electrode 130 of FIG. 1, the gate electrode 430 included in the tunneling transistor 4 of FIG. 6 may be disposed only on one side of the floating electrode 440.

The gate electrode 430 can control the tunneling current between the first electrode 410 and the second electrode 420 by changing the voltage of the floating electrode 440 and the gate electrode 430, The distance between the first electrode 410 and the second electrode 420 can be made much larger than the distance between the first electrode 410 and the second electrode 420 so that the leakage current can be removed or reduced have.

7 to 9 are plan views schematically showing a floating electrode according to another embodiment of the present invention. Although the floating electrode 140 of FIG. 1 may be rectangular, the floating electrode 140 may be formed as shown in FIGS. 7 to 9 to increase the tunneling current between the first electrode 110 and the second electrode 120 And can be implemented in various forms as well.

Referring to FIG. 7, a floating electrode 540 included in a tunneling transistor 5 according to an embodiment is disposed between a first electrode 110 (FIG. 1) and a second electrode 120 (FIG. 1) One edge may include a plurality of concavities 540b.

The gate electrode 530 includes a first gate electrode 530a and a second gate electrode 530b disposed on both sides of the floating electrode 540. The plurality of protrusions 540b are formed on the first gate electrode 530a, And the second gate electrode 530b.

That is, the first gate electrode 530a and the second gate electrode 530b are disposed along the first direction x about the floating electrode 540, and the plurality of protrusions 540b are disposed on the floating electrode 540 May be included at both ends disposed in the second direction (y) with respect to the central region.

Referring to FIG. 8, the floating electrode 640 included in the tunneling transistor 6 according to one embodiment may include a plurality of holes 640h. The gate electrode 630 may include a first gate electrode 630a and a second gate electrode 630b disposed on both sides of the floating electrode 640, respectively.

9, the floating electrode 740 included in the tunneling transistor 7 according to one embodiment includes a first floating electrode 741 and a second floating electrode 742, and the first floating electrode 741 And the second floating electrode 742 may each include concave and convex portions on at least one edge thereof. The gate electrode 730 may include a first gate electrode 730a and a second gate electrode 730b disposed on both sides of the first and second floating electrodes 741 and 742, respectively.

7 through 9, the floating electrodes 540, 640, and 650 may include concavities and convexities, and through such a structure, a high electric field may be formed in the floating electrodes 540, 640, and 650 The tunneling current can be increased.

10 is a cross-sectional view schematically illustrating a floating electrode according to another embodiment of the present invention.

10, the floating electrode 840 included in the tunneling transistor 8 according to an exemplary embodiment is disposed between the first gate electrode 830a and the second gate electrode 830b, And may include concave and convex portions 840p. The gate electrode 830 may include a first gate electrode 830a and a second gate electrode 830b that are electrically connected or insulated from each other.

The floating electrodes 540, 640, and 740 of FIGS. 7 to 9 may also be modified to include a top surface and a bottom surface irregular portion 840p as shown in FIG.

With this configuration, the intensity of the electric field formed in the floating electrode 840 can be increased to increase the tunneling current.

11 and 12 are plan views schematically showing a gate electrode according to another embodiment of the present invention.

11 and 12, the electrodes 930 and 1030 included in the tunneling transistors 9 and 10 according to an embodiment are arranged to surround the rectangular or circular floating electrodes 940 and 1040 May be a gate electrode 930 in the form of a frame or a gate electrode 1030 in the form of a ring.

A uniform electric field is formed on the floating electrodes 840 and 940 according to the voltages applied to the gate electrodes 830 and 930 and the first electrodes 110 and the second electrodes 120 and 120 are formed in the floating electrodes 840 and 940, 1) can be effectively controlled.

13 is a flowchart illustrating a method of manufacturing a tunneling transistor according to an embodiment of the present invention. Hereinafter, a method of manufacturing a tunneling transistor will be described with reference to FIG.

Referring to FIG. 13, a method of manufacturing a tunneling transistor 1 according to an embodiment includes forming a first electrode 110 on a substrate 101 (S110), forming a first electrode 110 on the first electrode 110 A step S130 of forming a gate electrode 130 and a floating electrode 140 on the first insulating layer 103 and a step S130 of forming a gate electrode 130 and a floating electrode 140 on the first insulating layer 103 A step S140 of forming a second insulating layer 105 covering the gate electrode 130 and the floating electrode 140 and a step S150 forming a second electrode 120 on the second insulating layer 105 ).

The gate electrode 130 and the floating electrode 140 may be simultaneously formed through the same process, and may be formed of the same material.

The first electrode 110, the second electrode 120, the gate electrode 130, and the floating electrode 140 may be formed in various shapes as described above.

The tunneling transistors 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 according to the embodiments described above are connected to the first electrodes 110, 210, 310, 410 and the second electrodes 120, 240, 340, 440, 540, 540, 640, 740, 840, 940, 1040 disposed between the floating electrodes 140, 240, The gate electrodes 130, 230, 330, 430, 530, 630, 730, 830, 930, and 1030 may be disposed adjacent to the gate electrodes 640, 740, 840, 940,

The floating electrodes 140, 240, 340, 440, 540, 640, 740, 840, 940 and 1040 are arranged to receive electrons tunneled from input electrodes, for example, first electrodes 110, 210, 310 and 410, 2 electrodes 120, 220, 320, and 420, respectively.

The gate electrodes 130, 230, 330, 430, 530, 630, 730, 830, 930 and 1030 are connected to the floating electrodes 140, 240, 340, 440, 540, 640, 740, 840, 940, And controls the tunneling current between the first electrode 110, 210, 310, 410 and the second electrode 120, 220, 320, 420.

According to one embodiment of the present invention, the width of the floating electrodes 140, 240, 340, 440, 540, 640, 740, 840, 940, The distance between the first electrodes 110, 210, 310, 410 and the second electrodes 120, 220, 320, 420 can be adjusted. The current leakage to the electrodes 130, 230, 330, 430, 530, 630, 730, 830, 930, 1030 can be eliminated or reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art . Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

1, 2, 3, 4, 5, 6, 7, 8, 9, 10: Tunneling transistors
103, 203, 303, 403: a first insulating layer
105, 205, 305, 405: a second insulating layer
110, 210, 310, 410: a first electrode
210, 220, 320, 420: the second electrode
130, 230, 330, 430, 530, 630, 730, 830, 930,
140, 240, 340, 440, 540, 640, 740, 840, 940, 1040:

Claims (19)

A first electrode disposed on the substrate;
A first insulating layer disposed on the first electrode;
A floating electrode disposed on the first insulating layer;
A second insulating layer disposed on the floating electrode;
A second electrode disposed on the second insulating layer; And
And a gate electrode disposed between the first insulating layer and the second insulating layer and controlling a tunneling current between the first electrode and the second electrode. The method according to claim 1,
Wherein the floating electrode and the gate electrode are made of the same material. The method according to claim 1,
Wherein the gate electrode includes a first gate electrode and a second gate electrode disposed on both sides of the floating electrode,
Wherein the first gate electrode and the second gate electrode are electrically connected or isolated from each other. The method according to claim 1,
Wherein the first electrode and the second electrode are disposed so as to overlap each other in a plane with the floating electrode, The method according to claim 1,
Wherein the first electrode and the second electrode have different shapes. 6. The method of claim 5,
Wherein the second electrode comprises a main region and a sharped region where the width gradually decreases from a portion connected to the main region to an end thereof. The method according to claim 6,
And the pointed region has a plurality of tunneling transistors. 6. The method of claim 5,
Wherein the second electrode comprises nanotubes, nanowires, or nanocylinders extending in a direction perpendicular to a major surface of the substrate. The method according to claim 1,
Wherein a width of the floating electrode in a first direction is greater than a width of at least one of the first electrode and the second electrode in the first direction. 10. The method of claim 9,
And the gate electrode is disposed in the first direction with respect to the floating electrode. The method according to claim 1,
Wherein a distance between the first electrode and the floating electrode and a distance between the second electrode and the floating electrode are 1 nm to 150 nm, respectively. 12. The method of claim 11,
Wherein the distance between the gate electrode and the floating electrode is between 1 nm and 10 占 퐉. The method according to claim 1,
And the gate electrode has a frame shape or a ring shape formed so as to surround the periphery of the floating electrode. The method according to claim 1,
Wherein the distance between the gate electrode and the first electrode is at least four times the distance between the first electrode and the floating electrode. The method according to claim 1,
Wherein the floating electrode comprises at least one edge comprising a plurality of irregularities. The method according to claim 1,
Wherein the floating electrode comprises at least one hole. The method according to claim 1,
Wherein the floating electrode includes a plurality of irregularities formed on at least one of a surface facing the first electrode and a surface facing the second electrode, Forming a first electrode on the substrate;
Forming a first insulating layer on the first electrode;
Forming a gate electrode and a floating electrode on the first insulating layer;
Forming a second insulating layer covering the gate electrode and the floating electrode on the first insulating layer; And
And forming a second electrode on the second insulating layer. 19. The method of claim 18,
Wherein the gate electrode and the floating electrode are formed of the same material through the same process.

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