JP2010145796A - Electrooptical device, method for manufacturing electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrooptical device wherein non-volatile memories and pixel TFTs can be formed on the same substrate and both of which can operate favorably. <P>SOLUTION: A gate insulation film 18 of the pixel TFT is composed of a tunnel insulation film (a first insulation film) 35 of the non-volatile memory and a second insulation film 37 having larger film thickness than that of the tunnel insulation film 35. The face on a control gate electrode 60 side of a floating gate electrode 36 is made irregular and, by the irregularity, the surface area of the floating gate electrode 36 is increased. Thus, the capacitance between the floating gate electrode 36 and the control gate electrode 60 is made larger than the capacitance between the floating gate electrode 36 and a semiconductor layer 33. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  In general, an electro-optical device such as a liquid crystal device includes a pixel portion including a plurality of pixels arranged in a matrix and a driving circuit such as a scanning line driving circuit and a data line driving circuit for driving the pixel portion. . Each pixel and the drive circuit are provided with a switching element made of a thin film transistor (TFT). In recent years, with the increase in functionality and functionality of electro-optical devices, a memory as a storage device has been mounted on the electro-optical device. As such a memory, there is a nonvolatile memory capable of reading, writing, and erasing electrical data, for example, an EEPROM.

  The EEPROM is provided on a floating gate electrode provided on the semiconductor layer, a second insulating film provided so as to cover the floating gate electrode, and the second insulating film via the first insulating film. A plurality of memory cells including a control gate are provided, and each memory cell is selected by a selection transistor, so that data can be written, read and erased. The first insulating film is formed of, for example, a thin insulating film called a tunnel insulating film having a thickness of 10 to 20 nm, and electrons are accumulated in the floating gate electrode when a current flows through the tunnel insulating film. It is possible.

Conventionally, the memory is externally attached to the electro-optical panel, and the electro-optical device on which the memory is mounted cannot be sufficiently reduced in size. Therefore, a technique is known in which a pixel portion, a drive circuit, and a memory are formed in the same substrate by forming TFTs using SOI technology, and the device is miniaturized (for example, Patent Document 1). reference).
JP 2001-326289 A

  By the way, the first insulating film functioning as the tunnel insulating film needs to be set to a film thickness through which the tunnel current flows satisfactorily. However, in the process disclosed in Patent Document 1, the tunnel insulating film constituting the memory cell and the gate insulating film constituting the TFT included in the pixel portion and the driver circuit are formed in the same process. The film thickness becomes equal. Therefore, in the TFT of the pixel portion, a tunnel current that passes through the gate insulating film flows, which may cause malfunction, and a reliable one cannot be obtained.

  The present invention has been made in view of such circumstances. An electro-optical device and an electro-optical device capable of forming a nonvolatile memory and a thin film transistor on the same substrate and operating both of them successfully. It is an object to provide a manufacturing method and an electronic device.

  In order to solve the above problems, an electro-optical device according to an embodiment of the present invention includes a pixel portion in which a plurality of pixels are arranged in a matrix, a driving circuit that drives the pixel portion, and a nonvolatile memory on the same substrate. A switching element made of a thin film transistor is provided in at least one of the pixel portion and the drive circuit, and the gate insulating film of the switching element includes a first insulating film, The non-volatile memory includes a semiconductor layer, a first insulating film, a floating gate electrode, and a third insulating film, and has a stacked structure with a second insulating film having a thickness larger than that of the first insulating film. A memory cell formed by stacking a film and a control gate electrode, wherein the third insulating film is formed to have a thickness larger than that of the first insulating film; Concavities and convexities are formed on the surface in contact with the third insulating film, and due to the concavities and convexities, the capacitance between the floating gate electrode and the control gate electrode is larger than the capacitance between the floating gate electrode and the semiconductor layer. It is characterized by being larger.

  According to this configuration, the tunnel insulating film constituting the memory cell is configured by the first insulating film, and the gate insulating film of the switching element provided in at least one of the pixel portion or the drive circuit is the first insulating film. It is comprised by the laminated film of a film | membrane and a 2nd insulating film. For this reason, when the gate insulating film and the tunnel insulating film have the same film thickness, the trouble that the tunnel current flows in the gate insulating film or the trouble that the tunnel current does not flow in the tunnel insulating film is prevented. Both of the memory cells can function well. Therefore, the electro-optical device provided with these has high reliability in which operation failure due to the above-described failure is prevented.

  In the electro-optical device of the present invention, irregularities are formed on the surface of the floating gate electrode in contact with the third insulating film, and the irregularities cause the capacitance between the floating gate electrode and the control gate electrode to be different from that of the floating gate electrode. It is larger than the capacity between the semiconductor layers. Therefore, if the potential difference between the control gate electrode and the semiconductor layer is constant, the potential difference between the floating gate electrode and the semiconductor layer increases, and the Fowler-Nordheim tunnel current ( FN current) easily flows. Therefore, it is possible to provide an electro-optical device that can perform writing and reading at a low voltage when writing and erasing data.

The floating gate electrode is preferably formed by a plurality of protrusions having a height of 10 to 100 nm formed in an island shape.
According to this configuration, a floating gate electrode having a small thickness can be formed. Therefore, disconnection or the like hardly occurs in the control gate electrode or the wiring layer formed on the floating gate electrode, and a highly reliable electro-optical device can be provided.

The third insulating film may be the same film as the second insulating film.
According to this configuration, the second insulating film is formed on the first insulating film and the floating gate electrode provided on the second semiconductor layer, and the second insulating film provided on the floating gate electrode. The film becomes the third insulating film. In this way, since the second insulating film and the third insulating film can be formed by a common process, manufacturing is facilitated.

  According to another aspect of the invention, there is provided a method for manufacturing an electro-optical device, comprising: a pixel portion in which a plurality of pixels are arranged in a matrix; a drive circuit that drives the pixel portion; and a nonvolatile memory on the same substrate. And at least one of the driving circuit and the driving circuit is provided with a switching element including a thin film transistor, and the nonvolatile memory includes a semiconductor layer, a floating gate electrode, and a control gate electrode stacked via an insulating film. A method of manufacturing an electro-optical device including a memory cell, comprising: forming a semiconductor film on the substrate; and patterning the semiconductor film to form a first semiconductor layer that constitutes the memory cell; and the switching Forming a second semiconductor layer constituting the element, and forming a first insulating film on the first semiconductor layer and the second semiconductor layer. A step of forming the floating gate electrode at a position overlapping with the first semiconductor layer on the first insulating film, and a position overlapping with the second semiconductor layer on the first insulating film. A second insulating film having a thickness larger than that of the first insulating film is formed, and a gate insulating film constituting the switching element is formed by the first insulating film and the second insulating film. A step of forming a gate electrode constituting the switching element at a position overlapping the second semiconductor layer on the second insulating film, and a third insulating film on the floating gate electrode. Forming the control gate electrode via the step, wherein in the step of forming the floating gate electrode, irregularities are formed on a surface of the floating gate electrode in contact with the third insulating film. By the irregularities, the capacitance between the floating gate electrode and the control gate electrode, characterized in that is larger than the capacitance between the semiconductor layer and the floating gate electrode.

  According to this method, the tunnel insulating film constituting the memory cell is configured by the first insulating film, and the gate insulating film of the switching element provided in at least one of the pixel portion or the drive circuit is the first insulating film. It is comprised by the laminated film of a film | membrane and a 2nd insulating film. For this reason, when the gate insulating film and the tunnel insulating film have the same film thickness, the trouble that the tunnel current flows in the gate insulating film or the trouble that the tunnel current does not flow in the tunnel insulating film is prevented. Both of the memory cells can function well. Therefore, the electro-optical device provided with these has high reliability in which operation failure due to the above-described failure is prevented.

  In the electro-optical device of the present invention, irregularities are formed on the surface of the floating gate electrode in contact with the third insulating film, and the irregularities cause the capacitance between the floating gate electrode and the control gate electrode to be different from that of the floating gate electrode. It is larger than the capacity between the semiconductor layers. Therefore, if the potential difference between the control gate electrode and the semiconductor layer is constant, the potential difference between the floating gate electrode and the semiconductor layer increases, and the Fowler-Nordheim tunnel current ( FN current) easily flows. Therefore, it is possible to provide an electro-optical device that can perform writing and reading at a low voltage when writing and erasing data.

The third insulating film can be formed by a process common to the second insulating film.
According to this method, the second insulating film is formed on the first insulating film and the floating gate electrode provided on the second semiconductor layer, and the second insulating film provided on the floating gate electrode. The film becomes the third insulating film. In this way, since the second insulating film and the third insulating film can be formed by a common process, manufacturing is facilitated.

  The floating gate electrode is made of a polysilicon film formed by laser annealing an amorphous silicon film, and the unevenness of the surface of the floating gate electrode is caused by the surface of the polysilicon film generated when the amorphous silicon film is laser annealed. It is desirable that the protrusions be formed using the protrusions.

  When the amorphous silicon film is irradiated with laser light, the amorphous silicon film is instantaneously melted and expands locally, and protrusions (ridges) are formed on the surface of the polysilicon film to relieve internal stress caused by this expansion. Is done. The protrusions are spontaneously formed during the cooling process of laser annealing, and the height and density (pitch) of the protrusions are uniform throughout the polysilicon film. In addition, since it is not necessary to perform special processing on the surface of the polysilicon film, the manufacturing process can be simplified, and an electro-optical device with high productivity is provided.

In the step of forming the floating gate electrode, it is preferable that the polysilicon film is etched back and the floating gate electrode is formed only by the projection of the polysilicon.
According to this method, a floating gate electrode having a small film thickness can be formed. Therefore, disconnection or the like hardly occurs in the control gate electrode or the wiring layer formed on the floating gate electrode, and a highly reliable electro-optical device can be provided.

The first semiconductor layer is made of a polysilicon film formed by laser annealing an amorphous silicon film, and in the step of forming the floating gate electrode, an amorphous silicon film formed on the first insulating film is formed. When the laser annealing is performed, it is preferable that the first semiconductor layer is simultaneously annealed.
According to this method, an electro-optical device provided with a high-quality memory cell can be provided.

An electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.
According to this configuration, a highly functional and highly reliable electronic device in which the nonvolatile memory is integrally formed on the electro-optic substrate can be provided.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below show some aspects of the present invention and do not limit the present invention. Moreover, in each drawing used for the following description, each layer and each member have a size that can be recognized on the drawing.

  FIG. 1 is a schematic plan view of a liquid crystal device 1 which is an example of an electro-optical device of the present invention. The liquid crystal device 1 is an active matrix type liquid crystal panel in which a liquid crystal layer is sandwiched between a TFT array substrate 10 and a counter substrate 20. On the TFT array substrate 10, a sealing material 52 is provided along the edge of the counter substrate 20, and a light shielding film 53 (peripheral parting) as a frame is provided in parallel to the inside thereof. A data line driving circuit (driving circuit) 201 and an external circuit connection terminal 202 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 52, and a scanning line driving circuit (driving circuit) 104 is provided. It is provided along one side adjacent to this one side.

  A region surrounded by the light shielding film 53 is provided with a pixel portion formed by a plurality of pixels G. The pixel portion is configured by arranging a plurality of pixels G in a matrix, and each pixel G is formed with a pixel electrode and a pixel TFT (switching element) for switching control of the pixel electrode. The TFT is driven by the data line driving circuit 201 and the scanning line driving circuit 104.

  A vertical conductive material 106 for providing electrical conduction between the TFT array substrate 10 and the counter substrate 20 is provided in at least one corner of the counter substrate 20. 1 is fixed to the TFT array substrate 10 by the sealing material 52, and a liquid crystal layer is sealed between the TFT array substrate 10 and the opposing substrate 20. Has been. An opening 52 a provided in the sealing material 52 shown in FIG. 1 is a liquid crystal injection port and is sealed by the sealing material 25.

  FIG. 2 is an equivalent circuit diagram of a plurality of pixels G formed in a matrix. Each pixel G is formed with a pixel electrode 9 and a pixel TFT 30 for controlling the switching of the pixel electrode 9. A data line 6 a for supplying an image signal from the data line driving circuit 201 is electrically connected to the source region of the pixel TFT 30, and a pixel electrode 9 is electrically connected to the drain region of the pixel TFT 30. In the pixel electrode 9, an image signal supplied from the data line 6 a is written at a predetermined timing by turning on the pixel TFT 30 that is a switching element for a certain period. An image signal of a predetermined level written in the liquid crystal through the pixel electrode 9 is held for a certain period with a common electrode (described later) formed on the counter substrate 20. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is provided in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.

  Returning to FIG. 1, the liquid crystal device 1 includes a memory controller circuit 112, an SRAM 113, and a side opposite to one side of the TFT array substrate 10 provided with the data line driving circuit (driving circuit) 201 and the external circuit connection terminal 202. A nonvolatile memory 110 is provided. The memory controller circuit 112 is a control circuit for controlling operations of storing and reading image data in the SRAM 113 and the nonvolatile memory 110. The SRAM 113 is provided for writing data at high speed. A DRAM may be provided in place of the SRAM 113, and the SRAM 113 is not particularly required if it is a non-volatile memory capable of high-speed writing.

  FIG. 3A is an equivalent circuit diagram of the nonvolatile memory 110, and FIG. 3B is a schematic cross-sectional view of the memory cell 110a and the selection TFT 111a constituting the nonvolatile memory 110. Although the nonvolatile memory 110 includes a plurality of memory cells, only two memory cells are illustrated in FIG. 3A for simplicity. FIG. 3B shows only a schematic configuration of one memory cell and one selection TFT shown in FIG. In this embodiment, an EEPROM (Electrically Erasable Programmable Read Only Memory) is adopted as the nonvolatile memory 110. The feature of the EEPROM is that writing, reading, and erasing can be performed every bit.

  As shown in FIG. 3A, the nonvolatile memory 110 has a circuit configuration in which selection TFTs 111a and 111b are arranged in series in the memory cells 110a and 110b. A nonvolatile memory having such a structure is called a NOR-type full-function EEPROM. In the present embodiment, the case where both the memory cells 110a and 110b and the selection TFTs 111a and 111b are n-channel TFTs will be described.

  As shown in FIG. 3B, the memory cell 110a has a structure in which a first insulating film 35, a floating gate electrode 36, a second insulating film 40, and a control gate electrode 60 are sequentially stacked on a semiconductor layer 33. It has become. The semiconductor layer 33 made of low-temperature polysilicon includes high-concentration n-type impurity regions 33a, 33d, 33e, and 33h, low-concentration n-type impurity regions 33b, 33c, 33f, and 33g, and an intrinsic semiconductor region (channel region) 33i. Is formed. A selection TFT 111a is formed adjacent to the right side of the memory cell 110a. The selection TFT 111 a has a structure in which a gate electrode 308 is provided on the gate insulating film 18 having a laminated structure of the first insulating film 35 and the second insulating film 37.

  In the memory cell 110a, a first capacitance is formed by the channel region 33i, the first insulating film 35, and the floating gate electrode 36, and a second capacitance is formed by the floating gate electrode 36, the second insulating film 40, and the control gate electrode 60. Is formed. Since the first capacitor and the second capacitor are connected in series, a large voltage can be applied between the channel region 33 i and the floating gate electrode 36 by increasing the second capacitor. As a result, a Fowler-Nordheim tunnel current (FN current) can be generated between the channel region 33 i and the floating gate electrode 36 at a low voltage.

  In the present embodiment, irregularities are formed on the surface of the floating gate electrode 36 on the second insulating film 40 side in order to increase the second capacitance. Specifically, the floating gate electrode 36 is formed by a plurality of protrusions with sharp tips, and the surface area of the floating gate electrode 36 is increased by the surface irregularities formed by the protrusions, thereby increasing the second capacitance. . Thus, a large voltage can be applied between the channel region 33i and the floating gate electrode 36, and data can be written or erased at a low voltage.

  In the nonvolatile memory 110 having the above configuration, the memory cell 110a realizes a memory function by injecting and releasing charges (mainly electrons) to the floating gate electrode. That is, 1-bit data is stored using the difference in threshold voltage between when the charge is accumulated in the floating gate electrode 36 and when it is not accumulated.

  When data is written to the memory cell 110a, the source line Sa and the bit line Ba are dropped to GND, and a positive high voltage (for example, 20V) is applied to the word line W. As a result, a Fowler-Nordheim tunnel current (FN current) flows between the floating gate electrode 36 and the channel region 33i, and charges are accumulated in the floating gate electrode 36 to perform writing. For other memory cells 110b in the same column, data is written by setting the voltage of the source line Sb and the bit line Bb to the same voltage as the word line W or sufficiently high so that no FN current flows. You can prevent it from being broken.

  When reading data, the source line Sa is dropped to GND, and a predetermined voltage (for example, 5 V) is applied to the word line W. Further, a positive voltage (for example, 5 V) is applied to the selection line V in order to turn on the selection TFT 111a. As a result, data stored in the memory cell can be read from the bit line Ba according to the state of the memory cell 110a.

  When erasing data, the source line Sa and the bit line Ba are dropped to GND, and a negative high voltage (for example, 20 V) is applied to the word line W. As a result, electrons accumulated in the floating gate electrode 36 are emitted to the channel region 33i by the Fowler-Nordheim tunnel current (FN current), and data is erased. For other memory cells 110b in the same column, the voltages of the source line Sb and the bit line Bb are set to a negative voltage that is the same as the negative high voltage applied to the word line W or sufficiently high so that no FN current flows. Thus, data can be prevented from being erased. As a result, data can be erased only in the memory cell 110a.

  In the above-described operation, all non-selected selection lines V may be set to 0V. Moreover, the value of the operating voltage described above is an example, and the value is not limited to that value.

  Here, when the potential difference between the control gate electrode 60 and the channel region 33i is constant at the time of data writing / erasing, if the capacitance between the floating gate electrode 36 and the control gate electrode 60 increases, the floating gate The potential difference between the electrode 36 and the control gate electrode 60 decreases, and the potential difference between the floating gate electrode 36 and the channel region 33i increases. As a result, the FN current easily flows between the floating gate electrode 36 and the channel region 33i.

  In other words, if the potential required for the FN current to flow between the floating gate electrode 36 and the channel region 33i is determined, the data write / erase is performed when the capacitance between the floating gate electrode 36 and the control gate electrode 60 increases. Thus, the potential difference between the floating gate electrode 36 and the channel region 33i can be reduced.

  Therefore, by increasing the capacitance between the floating gate electrode 36 and the control gate electrode 60, it becomes possible to reduce the potential difference between the control gate electrode 60 and the channel region 33i at the time of data writing / erasing. This can have a significant effect on conversion.

  FIG. 4 is a block diagram of the liquid crystal device 1. The liquid crystal device 1 receives an image signal, a clock signal, a synchronization signal, or the like via an FPC (flexible printed circuit board) 117. The FPC 117 is connected to the external circuit connection terminal 202 (see FIG. 1). The external circuit connection terminal 202 is electrically connected to the memory controller circuit 112 through a wiring (not shown) so that an image signal, a clock signal, a synchronization signal, or the like can be input to the memory controller circuit 112.

  In the liquid crystal device 1, for example, an image signal sent from an external input device such as a personal computer or a television receiving antenna is stored (stored) in the SRAM 113 for each frame, and the image signal is sequentially transferred to the pixels G by the memory controller circuit 112. Entered and displayed. The SRAM 113 stores image information for at least one frame displayed on the pixel G. For example, when a 6-bit digital signal is sent as an image signal, a memory capacity corresponding to at least the number of pixels × 6 bits is required. Further, the memory controller circuit 112 stores the image signal stored in the SRAM 113 in the non-volatile memory 110 or inputs the image signal stored in the non-volatile memory 110 to the pixel TFT 30 as necessary. An image can be displayed by applying a voltage between the electrode 9 and the common electrode to align the liquid crystal layer 50.

  Since the image data stored in the SRAM 113 and the nonvolatile memory 110 is a digital signal, a D / A converter or an A / D converter is formed on the TFT array substrate 10 as necessary.

  In the liquid crystal device 1, the image displayed on the pixel G is always stored in the SRAM 113, so that the image can be easily paused. Further, by storing the image signal stored in the SRAM 113 in the nonvolatile memory 110 or inputting the image signal stored in the nonvolatile memory 110 to the pixel G, for example, operations such as image recording and reproduction can be easily performed. Can be done.

  5 to 9 are cross-sectional process diagrams illustrating an example of a method for manufacturing the liquid crystal device 1. In the following manufacturing method, a polysilicon film formed by a low-temperature process is used as an active layer, and a memory cell and a selection TFT constituting the nonvolatile memory 110 provided on the TFT array substrate 10 and a pixel TFT 30 constituting the pixel G are used. Are formed on the same substrate. 5 to 9, the “memory cell formation region” is a region where the memory cell 110a is formed, and the “selection TFT formation region” is a region where the selection TFT 111a is formed.

First, as shown in FIG. 5A, a glass substrate is prepared as the substrate body 10A constituting the TFT array substrate 10 and washed with sulfuric acid. Then, under the temperature condition of the substrate temperature of about 150 ° C. to about 450 ° C., the base protective film 31 made of a silicon oxide film (SiO ₂ ) is formed on the surface of the substrate body 10A by the plasma CVD method. As the source gas at this time, for example, TEOS (tetraethoxysilane) and oxygen, or disilane and ammonia can be used.

  Next, an amorphous silicon film having a thickness of 50 nm to 75 nm is formed on the entire surface of the substrate body 10A by the plasma CVD method under the temperature condition of about 150 ° C. to about 450 ° C. without exposing the substrate body 10A to the outside air. 32a is formed. As the source gas at this time, for example, disilane or monosilane can be used. Further, a silicon oxide film is formed on the amorphous silicon film 32a, channel doping is performed on the amorphous silicon film 32a, and then the silicon oxide film is peeled off by wet etching.

  Then, as shown in FIG. 5B, the substrate body 10A is moved into the chamber of the laser annealing apparatus, the amorphous silicon film 32a is irradiated with laser light (laser annealing), and the amorphous silicon film 32a is crystallized. Change to a polysilicon film (semiconductor film) 32.

  Next, as illustrated in FIG. 5C, a resist mask M is formed on the surface of the polysilicon film 32 using a photolithography method, and the polysilicon film 32 is patterned using the resist mask M.

  FIG. 5D is a diagram showing a state in which the polysilicon film 32 is patterned into an island shape, and the first semiconductor layer 33 is formed in the memory cell region and the second semiconductor layer 34 is formed in the selection TFT formation region. After patterning the polysilicon film 32, the resist mask M is removed.

  Next, as shown in FIG. 5E, the first insulating film 35 made of silicon oxide is formed on the substrate body so as to cover the semiconductor layers 33 and 34 by, for example, TEOS-CVD, CVD, plasma CVD, or the like. Form on 10A. The first insulating film 35 forms a tunnel insulating film in the nonvolatile memory 110, and the film thickness is preferably set to about 10 to 20 nm.

  Next, as shown in FIG. 5F, an amorphous silicon film having a thickness of 30 nm to 50 nm is formed on the first insulating film 35 by plasma CVD. Then, the substrate body 10A is moved into the chamber of the laser annealing apparatus, the amorphous silicon film is irradiated with laser light (laser annealing), and the amorphous silicon film is crystallized to be changed to a polysilicon film (semiconductor film) 36a.

  When the amorphous silicon film is irradiated with laser light, depending on the conditions of laser annealing, fine projections are formed on the surface of the resulting polysilicon film 36a. For example, when an excimer laser is irradiated in a state where a natural oxide film of about 3 nm is formed on the surface of an amorphous silicon film, it is confirmed that fine protrusions having a height of 10 to 100 nm are formed on the surface of the polysilicon film. Yes. The interval (pitch) between the protrusions is 200 to 300 nm, although it depends on the irradiation condition of the laser beam. This is thought to be because the amorphous silicon film is instantaneously melted and locally expanded, and protrusions (ridges) are formed on the surface of the polysilicon film in order to relieve internal stress caused by this expansion. Yes. The protrusions are spontaneously formed during the cooling process of laser annealing, and the height and interval (density) of the protrusions are uniform throughout the polysilicon film.

  Next, the entire surface of the polysilicon film 36a is etched (etched back) using a mixed solution of hydrofluoric acid and nitric acid, and the underlying polysilicon film is removed leaving only the protrusions. Then, the memory cell formation region is masked, and the polysilicon protrusions in the other regions are removed. As a result, as shown in FIG. 6A, a floating gate electrode 36 made of a polysilicon protrusion having a height of 10 to 100 nm is formed in the memory cell formation region.

  Next, as shown in FIG. 6B, a second insulating film made of silicon oxide is formed on the substrate body 10A so as to cover the floating gate electrode 36 by, for example, TEOS-CVD, CVD, plasma CVD, or the like. 37 is formed. Here, in the present embodiment, the first insulating film 35 and the second insulating film 37 are laminated in a region excluding the floating gate electrode 36. Note that the thickness of the second insulating film 37 is preferably set so that the thickness of the stacked body of the first insulating film 35 and the second insulating film 37 is about 750 mm (75 nm). For example, when the first insulating film 35 is formed with a thickness of 10 nm, it is desirable to set the thickness of the second insulating film 37 to 650 mm.

Next, as shown in FIG. 6C, impurities are implanted into the semiconductor layers 33 and 34, and the N channel high concentration source region 33a, the N channel high concentration drain region 33d of the memory cell 110a, and the N for memory switching are used. A channel high concentration source region 33e, an N channel high concentration drain region 33h, and an N channel high concentration source region 34a and an N channel high concentration drain region 34d of the pixel TFT are formed. Specifically, using a resist mask M1 having a width wider than that of the floating gate electrode 36 and the gate electrode of the pixel TFT 30 formed by a process described later, a dopant of a group V element such as P is formed at a high concentration (for example, P ion At an acceleration voltage of 70 keV and a dose of 4 × 10 ¹⁵ / cm ² . Then, the resist mask M1 is removed by ashing, and scrub cleaning (brush cleaning) is performed.

  Next, as shown in FIG. 6D, a gate electrode forming material is formed by TEOS-CVD, CVD, plasma CVD, sputtering, or the like. In this embodiment, the gate electrode is formed by sequentially stacking TiN, Al, and Ti. Then, the gate electrode 39 constituting the pixel TFT 30 is formed on the second insulating film 37 by patterning the forming material. The nonvolatile memory according to the present embodiment has a configuration in which the selection TFT 111a is provided in the memory cell 110a as described above. Therefore, the gate electrode 39 of the pixel TFT 30 in the pixel portion is formed, and the gate electrode 38 constituting the selection TFT 111a is also formed on the substrate in the same process.

Next, as shown in FIG. 6E, impurities are implanted into the semiconductor layers 33 and 34, and the N channel low concentration source region 33b, the N channel low concentration drain region 33c of the memory cell 110a, and the N channel for memory switching. A low concentration source region 33f, an N channel low concentration drain region 33g, and an N channel low concentration source region 34b and an N channel low concentration drain region 34c of the pixel TFT 30 are formed. Specifically, a dopant of a group V element such as P is doped at a low concentration (for example, P ions are accelerated at a pressure of 70 keV and a dose of 6 × 10 ¹² / cm ² ).

  Next, as shown in FIG. 7A, the insulating films (first insulating film 35 and second insulating film 37) are etched using the gate electrodes 38 and 39 and the floating gate electrode 36 as a mask. . At this time, the insulating films other than the lower portions of the gate electrodes 38 and 39 and the floating gate electrode 36 are removed, and the semiconductor layers 33 and 34 are exposed. As a result, a tunnel insulating film is formed by the first insulating film 35 below the floating gate electrode 36. A gate insulating film 18 having a stacked structure of a first insulating film 35 and a second insulating film 37 is formed below the gate electrodes 38 and 39.

Next, as shown in FIG. 7B, a third insulating film 40 made of SiO ₂ , SiN, or the like is formed using, for example, TEOS-CVD, CVD, plasma CVD, sputtering, or the like. The third insulating film 40 forms a gate insulating film in the memory cell 110a, and the film thickness is preferably about several tens of nm. As the third insulating film 40, a film having a three-layer structure of an oxide film, a nitride film, and an oxide film may be employed.

  Next, the same Al as the formation material of the floating gate electrode 36 is formed on the third insulating film 40 as the formation material of the control gate electrode by, for example, TEOS-CVD method, CVD method, plasma CVD method, sputtering method or the like. . Note that the control gate electrode may be formed of a single-layer conductive film, but is preferably a stacked film of two layers or three layers as necessary. As a material for forming the floating gate, other than Al, a known conductive film can be used similarly to the floating gate electrode 36. In addition, when forming the control gate electrode forming material, a cleaning (scrub cleaning) step with a brush may be provided. Then, the control gate electrode 60 is formed on the third insulating film 40 by patterning the formation material of the control gate electrode using a photolithography method, as shown in FIG. Subsequently, a cover insulating film 61 for P channel region impurity implantation covering the control gate electrode 60 is formed on the third insulating film 40.

  Subsequently, as shown in FIG. 7E, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film is formed so as to cover the cover insulating film 61 by, for example, atmospheric pressure or low pressure CVD. An interlayer insulating film 62 made of, for example, is formed. The film thickness of the interlayer insulating film 62 is preferably about 500 to 1500 nm, and more preferably 800 nm. Thereafter, a hydrogenation process for stabilizing the polysilicon film is performed (dangling bond reduction).

  Subsequently, as shown in FIG. 8A, a contact hole is provided in a predetermined region of the interlayer insulating film 62, and the source electrode connected to the high concentration source region in the selection TFT 111a of the nonvolatile memory 110 through the contact hole. 63, and a drain electrode 64 connected to the high concentration drain region of the pixel TFT 30 is formed. Note that the source electrode 63 and the drain electrode 64 have a stacked structure in which TiN, Al, and Ti are sequentially stacked.

Subsequently, as shown in FIG. 8B, a passivation film 65 made of SiO ₂ is formed by, for example, a CVD method so as to cover the source electrode 63 and the drain electrode 64.

  Next, as shown in FIG. 8C, a planarizing film 66 made of acrylic is formed so as to cover the passivation film 65, and a contact hole exposing the drain electrode 64 is formed in the passivation film 65 by dry etching. Then, the pixel electrode 9 made of ITO connected to the drain electrode 64 is formed through the contact hole. Note that other wirings constituting the pixel TFT 30, a process for manufacturing a selection line, a bit line, a word line, etc. constituting the nonvolatile memory can be formed by a method similar to the conventional method, and detailed description thereof is omitted. To do.

  According to the electro-optical device of the present embodiment described above, the tunnel insulating film constituting the memory cell is configured by the first insulating film, and the gate insulating film of the pixel TFT is the first insulating film and the second insulating film. And a laminated film. Therefore, the trouble that the tunnel current flows in the gate insulating film when the gate insulating film and the tunnel insulating film are the same thickness, or the trouble that the tunnel current does not flow in the tunnel insulating film is prevented. Both of the memory cells can function well. Therefore, the electro-optical device provided with these has high reliability in which operation failure due to the above-described failure is prevented.

  In the electro-optical device according to the present embodiment, irregularities are formed on the surface of the floating gate electrode in contact with the second insulating film, and the irregularities cause the capacitance between the floating gate electrode and the control gate electrode to be changed. And larger than the capacitance between the semiconductor layer and the semiconductor layer. Therefore, if the potential difference between the control gate electrode and the semiconductor layer is constant, the potential difference between the floating gate electrode and the semiconductor layer increases, and the Fowler-Nordheim tunnel current ( FN current) easily flows. Therefore, it is possible to provide an electro-optical device that can perform writing and reading at a low voltage when writing and erasing data.

  Further, in the electro-optical device according to the present embodiment, the floating gate electrode is formed only by the polysilicon protrusion. Therefore, a floating gate electrode with a small film thickness can be formed, and disconnection or the like hardly occurs in the control gate electrode or wiring layer formed thereon. Further, since the floating gate electrode is formed by laser annealing amorphous silicon, the underlying semiconductor layer 33 is annealed by this laser annealing step, and a high-quality memory cell is provided.

  In this embodiment, the polysilicon film is etched back, and the floating gate electrode is formed only by the polysilicon protrusion. However, the floating gate electrode is not necessarily formed only from the protrusion, and a floating gate electrode having a structure in which the polysilicon film underlying the protrusion is left may be used. Also in this case, the capacitance between the floating gate electrode and the control gate electrode can be increased by the unevenness of the surface of the floating gate electrode, and the FN current can easily flow between the floating gate electrode and the channel region 33i. Is possible.

  In the present embodiment, the third insulating film 40 and the second insulating film 37 are formed in separate steps, and the control gate electrode 60 and the gate electrodes 38 and 39 are formed in separate steps. These steps can be formed by a common process. For example, by forming a conductive film on the second insulating film 37 in FIG. 6D and patterning the conductive film, the gate electrodes 38 and 39 and the control gate electrode can be formed at once. The subsequent steps are the same as those in FIG. According to this method, since the manufacturing process is simplified, an electro-optical device with high productivity can be provided.

  In the present embodiment, the pixel TFT 30 and the switching element constituting a part of the nonvolatile memory 110 are integrally formed on the substrate body 10A. However, the present invention is not limited to this. For example, not only the nonvolatile memory 110 but also the driving circuits 104 and 201 that drive the pixel portion, the SRAM 113, and the TFTs that constitute the memory controller circuit 112 may be formed in the same process. In this case, the manufacturing cost of the liquid crystal device 1 can be further reduced.

  In the present embodiment, the liquid crystal device (liquid crystal panel) is described as an example of the electro-optical device. However, the present invention is not limited to this, and other electro-optical devices such as an organic EL device, an inorganic EL device, The present invention can also be applied to plasma display devices, electrophoretic display devices, field emission display devices, and the like.

(Electronics)
FIG. 9 is a perspective view illustrating an overall configuration of a mobile phone 600 that is an example of an electronic apparatus. The mobile phone 600 includes a housing 601, an operation unit 602 provided with a plurality of operation buttons, and a display unit 603 that displays images, moving images, characters, and the like. The display unit 603 is equipped with the liquid crystal device 1 according to the present invention. As described above, since the highly reliable liquid crystal device 1 including the nonvolatile memory is provided, a highly reliable and high performance electronic device (mobile phone) 600 can be obtained.

  FIG. 10 is a schematic configuration diagram of a projection type liquid crystal display device (liquid crystal projector) which is another example of the electronic apparatus. The projection-type liquid crystal display device 1100 is configured as a projector using three liquid crystal modules including the liquid crystal device 1 as RGB light valves 100R, 100G, and 100B.

  In this projection type liquid crystal display device 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three primary colors of R, G, and B are obtained by three mirrors 1106 and two dichroic mirrors 1108. The light components are separated into corresponding light components R, G, and B (light separating means) and guided to the corresponding light valves 100R, 100G, and 100B (liquid crystal device 1 / liquid crystal light valve). At this time, since the optical component B has a long optical path, the light component B is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss.

  Then, the light components R, G, and B corresponding to the three primary colors respectively modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining unit) from three directions and are combined again, and then the projection lens. A color image is projected on a screen 1120 or the like via 1114.

  According to the projection type liquid crystal display device, since the liquid crystal device 1 of the present invention is used as the light valves 100R, 100G, and 100B, it is highly reliable and highly functional.

  As electronic devices, in addition to the mobile phone 600 and the projection type liquid crystal display device 1100, a multimedia-compatible personal computer (PC), an engineering work station (EWS), a pager, or a mobile phone, a word processor, a television set. And a viewfinder type or monitor direct view type video tape recorder, electronic notebook, electronic desk calculator, car navigation device, POS terminal, touch panel, and the like.

1 is a schematic plan view of a liquid crystal device which is an example of an electro-optical device. It is an equivalent circuit diagram of a plurality of pixels formed in a matrix. It is the equivalent circuit schematic and schematic sectional drawing of a non-volatile memory. It is a block diagram of a liquid crystal device. It is a figure which shows the manufacturing process of a liquid crystal device. FIG. 6 is a diagram illustrating manufacturing steps of the liquid crystal device, following FIG. 5. FIG. 7 is a diagram illustrating manufacturing steps of the liquid crystal device, following FIG. 6. FIG. 8 is a diagram illustrating manufacturing steps of the liquid crystal device, following FIG. 7. It is a schematic diagram of a cellular phone which is an example of an electronic device. It is the schematic of the projection type liquid crystal display device which is an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device (electro-optical device), 10A ... Substrate body (substrate), 18 ... Insulating film, 30 ... Pixel TFT (switching element), 32 ... Polysilicon film, 32a ... Amorphous silicon film, 33 ... Semiconductor layer, 34 ... Semiconductor layer, 35 ... First insulating film, 36 ... Floating gate electrode, 37 ... Second insulating film, 38 ... Gate electrode, 39 ... Gate electrode, 40 ... Third insulating film, 60 ... Control gate electrode, 104 ... Scanning line drive circuit (drive circuit), 110 ... Non-volatile memory, 111a, 111b ... Selection TFT (selection transistor), 202 ... Data line drive circuit (drive circuit), 600 ... Mobile phone (electronic device), 1100 ... Projection-type liquid crystal display device (electronic equipment), G ... pixel

Claims (7)

An electro-optical device including a pixel portion in which a plurality of pixels are arranged in a matrix, a drive circuit that drives the pixel portion, and a nonvolatile memory on the same substrate,
A switching element including a thin film transistor is provided in at least one of the pixel portion and the driving circuit, and a gate insulating film of the switching element is thicker than the first insulating film and the first insulating film. A laminated structure with a large second insulating film,
The nonvolatile memory includes a memory cell formed by stacking a semiconductor layer, a first insulating film, a floating gate electrode, a third insulating film, and a control gate electrode,
The third insulating film is formed larger in thickness than the first insulating film,
Concavities and convexities are formed on the surface of the floating gate electrode in contact with the third insulating film, and due to the concavities and convexities, a capacitance between the floating gate electrode and the control gate electrode is reduced between the floating gate electrode and the semiconductor layer. An electro-optical device characterized by being larger than the capacity between the two.   The electro-optical device according to claim 1, wherein the floating gate electrode is formed by a plurality of protrusions having a height of 10 to 100 nm formed in an island shape. A pixel portion in which a plurality of pixels are arranged in a matrix, a drive circuit that drives the pixel portion, and a nonvolatile memory are provided over the same substrate, and at least one of the pixel portion and the drive circuit And a non-volatile memory including a memory cell in which a semiconductor layer, a floating gate electrode, and a control gate electrode are stacked with an insulating film therebetween. A method,
Forming a semiconductor film on the substrate and patterning the semiconductor film to form a first semiconductor layer constituting the memory cell and a second semiconductor layer constituting the switching element;
Forming a first insulating film on the first semiconductor layer and the second semiconductor layer;
Forming the floating gate electrode at a position overlapping the first semiconductor layer on the first insulating film;
A second insulating film having a thickness greater than that of the first insulating film is formed at a position overlapping the second semiconductor layer on the first insulating film, and the first insulating film and the second insulating film are formed. A step of forming a gate insulating film constituting the switching element with the insulating film;
Forming a gate electrode constituting the switching element at a position overlapping the second semiconductor layer on the second insulating film;
Forming the control gate electrode on the floating gate electrode via a third insulating film,
In the step of forming the floating gate electrode, irregularities are formed on the surface of the floating gate electrode that is in contact with the third insulating film, and due to the irregularities, the capacitance between the floating gate electrode and the control gate electrode is An electro-optical device manufacturing method, wherein a capacitance between the floating gate electrode and the semiconductor layer is larger.   The floating gate electrode is made of a polysilicon film formed by laser annealing an amorphous silicon film, and the unevenness of the surface of the floating gate electrode is caused by the surface of the polysilicon film generated when the amorphous silicon film is laser annealed. The method of manufacturing an electro-optical device according to claim 3, wherein the protrusion is formed using a protrusion.   5. The method of manufacturing an electro-optical device according to claim 4, wherein, in the step of forming the floating gate electrode, the polysilicon film is etched back, and the floating gate electrode is formed only by the projection of the polysilicon. . The first semiconductor layer comprises a polysilicon film formed by laser annealing an amorphous silicon film,
5. The step of forming the floating gate electrode, wherein the first semiconductor layer is simultaneously annealed when laser annealing the amorphous silicon film formed on the first insulating film. 6. A method of manufacturing the electro-optical device according to 5.   An electronic apparatus comprising the electro-optical device according to claim 1.

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