KR101137259B1 - Tunneling field effect transistor for low power applications - Google Patents

Abstract

The present invention relates to a tunneling field effect transistor, and more particularly, by adopting a structure in which a source region and a channel region face each other, an area in which a tunneling current flows is increased to improve driving current as well as a tunneling junction thickness of the source and channel. The present invention relates to a tunneling field effect transistor that can be defined by the thickness of a very thin semiconductor film therebetween, which can enable a drastic change in driving current, and thus can be applied to low power and high efficiency electronic products.

Description

TUNNELING FIELD EFFECT TRANSISTOR FOR LOW POWER APPLICATIONS

The present invention relates to a tunneling field effect transistor, and more particularly, by adopting a structure in which a source region and a channel region face each other, an area in which a tunneling current flows is increased to improve driving current as well as a tunneling junction thickness of the source and channel. The present invention relates to a tunneling field effect transistor that can be defined by the thickness of a very thin semiconductor film therebetween, which can enable a drastic change in driving current, and thus can be applied to low power and high efficiency electronic products.

Tunneling Field Effect Transistors (TFETs) were first proposed at Hitachi in Japan and Cambridge University in the UK.However, in the 1990s, tunneling was not possible because the reduction of existing MOSFETs was inevitable and the energy problem was not serious. Transistors have not been widely studied.

However, in the 2000s, as the limit of MOSFET miniaturization was imminent and the energy problem became serious, the tunneling transistor research came into the spotlight as one solution.

This is because as the size of semiconductor devices decreases and performance increases, power consumption increases, and there is a need for developing devices to replace or supplement existing MOSFETs.

Conventional MOSFETs have a physical limitation that the subthreshold swing (SS) cannot be lowered below 60mV / dec at room temperature, and there is a fundamental problem that a significant performance degradation occurs when the driving voltage is lowered.

However, the tunneling field effect transistor controls the flow of electrons or holes in a tunneling scheme different from that of conventional MOSFETs, so that a small change in the input voltage (driving voltage) can lead to a large change in the output current.

This suggests that the change of ON / OFF state occurs very rapidly in accordance with the change of the gate voltage, and it means that the lower SS may be lower than the threshold voltage SS.

Therefore, the tunneling field effect transistor is expected to be able to operate normally even at a very low driving voltage of 1V or less. Therefore, the tunneling transistor can achieve similar performance to that of a conventional MOSFET while consuming less power. It is expected that semiconductor devices can be implemented.

The tunneling field effect transistor basically has a structure in which the source 220 / the drain 240 are formed of impurities having opposite polarities to both sides of the channel region 210, unlike the conventional MOSFET.

For example, in the case of an n-channel TFET, a source 220 is formed as a P + region and a drain 240 is formed as an N + region on both sides of the channel region 210 on a P-type, N-type, or intrinsic SOI substrate on the buried oxide film 100. Here, the P + region refers to a high concentration doped layer of P-type impurities, and the N + region refers to a high concentration doped layer of N-type impurities (hereinafter, the same).

In the above structure, when the + driving voltage is applied to the gate 400 on the gate insulating film 300 and the reverse bias voltage is applied to the source 220 and the drain 240, respectively, as shown in FIG. A junction having an energy band inclination is formed between the 210 and the source 220 so that a driving current I _ON due to quantum mechanical tunneling flows.

However, in the conventional tunneling field effect transistor, as shown in FIG. 3 in contrast to the present invention, an inversion layer or an accumulation layer formed in the channel region according to an increase in the gate voltage is P + or respectively. The tunneling junction is formed in a vertical contact with the junction plane of the N + region, so that the area of the tunneling junction where the tunneling occurs is narrow, and the thickness of the interband tunneling barrier depends on the gradual change of the depletion region of the pn junction. Therefore, there has been a problem that the current value is lower than the driving current of the conventional MOSFET.

Accordingly, the inventors of the present invention have a problem in that the tunneling field effect transistor has a direction in which a channel formed of an inversion layer or an accumulation layer contacts the junction plane of the P + or N + region, respectively. Recognizing that the area of the tunneling junction where tunneling occurs is narrow and the thickness of the interband tunneling barrier is dependent on the gradual change of the depletion region of the pn junction, while increasing the structure that can improve the tunneling junction area, It is an object of the present invention to provide a structure of a tunneling field effect transistor that can be applied to low power and high efficiency electronics by limiting the thickness of the tunneling barrier to a thickness less than or equal to a specific driving voltage.

In order to achieve the above object, the tunneling field effect transistor according to the present invention comprises a semiconductor substrate having a recessed portion; A semiconductor layer formed to a predetermined thickness on the recessed portion of the semiconductor substrate; A gate insulating film formed on the semiconductor layer; A gate formed on the gate insulating layer to fill the recessed portion; A semiconductor substrate including a P + region and an N + region formed on both sides of the gate, or having a mesa structure protruding from one side; A semiconductor layer formed on the semiconductor substrate with a predetermined thickness; A gate insulating film formed on the semiconductor layer; A gate formed on a sidewall of the semiconductor substrate on the gate insulating film; And a P + region and an N + region formed in the semiconductor substrate at both sides of the gate.

Here, the semiconductor layer is a semiconductor material of the same type as the semiconductor substrate, it is preferable that the channel is formed according to the voltage applied to the gate.

According to the present invention, a gate is formed to be in contact with at least one of a P + region and an N + region, and a gate insulating layer and a semiconductor layer interposed therebetween, so that channels formed in the semiconductor layer can be formed to face the source region (P + or N + region). Accordingly, the tunneling current flows to increase the driving current, and the tunneling junction thickness is defined as the thickness of the semiconductor layer between the source and the channel, thereby enabling a drastic change in the driving current.

1 is a cross-sectional view showing the basic structure of a conventional tunneling field effect transistor (n-channel TFET).
Figure 2 is when the n reverse bias, the gate to the source / drain in the channel TFET structure of 1 + voltage is applied to each of P + regions tunneling current in the tunneling junction between (source region) and the adjacent channel region (ON CURRENT: I _ON Is an energy band diagram showing).
3 is a conceptual diagram for comparing the operation principle of the tunneling field effect transistor according to the existing technology and the present invention.
4 and 6 are cross-sectional views each illustrating a structure of a tunneling field effect transistor according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Tunneling field effect transistor according to the present invention, unlike the conventional conventional structure as shown in Figure 1, basically, a semiconductor substrate, a gate formed between the gate insulating film on the semiconductor substrate, and the P + region and N + formed on both sides of the gate In a tunneling field effect transistor including a region, the gate is formed to be in contact with at least one of the P + region and the N + region and the gate insulating layer and a semiconductor layer connected to the semiconductor substrate therebetween.

More specifically, as shown in FIG. 4, the gate 40 is formed in the semiconductor substrate 22 on the buried oxide film 10 so as to contact both the P + region 22 and the N + region 24, and the gate 40. ) And the P + region 22 or the N + region 24 may have a structure in which a gate insulating layer 30 and a semiconductor layer 21 connected to the semiconductor substrate 20 are formed from a gate.

Here, the semiconductor substrate may be a bulk silicon substrate as well as an SOI substrate, and a conventional recessed gate process may be used to manufacture the structure.

However, the semiconductor layer 21 may be formed as a thin single crystal semiconductor film by epitaxially growing a semiconductor material of the same type as the semiconductor substrate 20.

However, the semiconductor layer 21 may be integrally connected with the same material as the semiconductor substrate 20.

According to the above configuration, a channel is formed in the semiconductor layer 21 in contact with the gate insulating layer 30 by the voltage applied to the gate 40, thereby greatly increasing the area through which the tunneling current flows. And the tunneling junction thickness can be limited to the thickness of the semiconductor layer between the source and the channel.

In FIG. 3, the structure of the present invention according to FIG. 4 is compared with that of the existing structure, and channels are formed in an inversion layer (when the semiconductor substrate and the semiconductor layer are p-type) with increasing gate voltage, and It shows intuitively how the direction comes into contact with the junction plane of the P + region (which becomes the source region when the semiconductor substrate and the semiconductor layer are p-type), and the strength of the tunneling current.

In addition, in FIG. 4, the semiconductor substrate 20 and the semiconductor layer 21 are made of a p-type semiconductor material to form the P + region 22 as a source region. However, the semiconductor substrate 20 and the semiconductor layer 21 are formed. Of course, the n-type semiconductor material and the N + region 24 can be operated as a source region.

Another specific aspect of the tunneling field effect transistor according to the present invention may be such that it has a cross section as shown in FIG. 5, which is different from FIG. 4, in which the recessed gate 40a region, the gate insulating layer 30a and the semiconductor layer surrounding the same are formed. It can be seen that 21a can each be rounded. In this case, the boundary between the source region facing the channel (the P + region 22a in the case of the n-channel element and the N + region 24a in the case of the p-channel element) is widened, resulting in an area in which the tunneling current flows rather than the structure of 4. There is an advantage that can be wider.

Meanwhile, as shown in FIG. 6, the N + region 24b is protruded to form a mesa structure, and then the gate 40b is in contact with the sidewall of the protruding N + region 24b and the gate insulating layer 30b and the semiconductor layer 21b. It can be formed on. In this case, the semiconductor substrate 20a and the semiconductor layer 21b may be made of an n-type semiconductor material to operate the N + region 24b as a source region.

Of course, the P + region 22b may be protruded instead of the N + region 24b and the P + region 22b may be operated as a source region using the semiconductor substrate 20a and the semiconductor layer 21b as p-type semiconductor materials.

Conventional sidewall processes and mesa structure formation processes can be used to fabricate the structures.

Then, the gates 40, 40a, and 40b shown in FIGS. 4 to 6 sandwich the semiconductor layers 21, 21a, and 21b with the gate insulating layers 30, 30a, and 30b interposed therebetween, or both. The three surfaces may have a double-gate structure and a triple-gate structure. In addition, although not shown in the drawing, a gate may be formed in a gate-all-around (GAA) structure surrounding the slope of the semiconductor layer with the gate insulating layer interposed therebetween.

As mentioned above, although preferred embodiments of the present invention have been described, those skilled in the art may perform various applications based on the above embodiments, and specific examples of other applications will be described. Omit.

10: buried oxide film BOX 20, 20a: semiconductor substrate
22, 22a, 22b: P + region 24, 24a, 24b: N + region
30, 30a, 30b: gate insulating film 40, 40a, 40b: gate

Claims (9)

A semiconductor substrate having a recessed portion;
A semiconductor layer formed to a predetermined thickness on the recessed portion of the semiconductor substrate;
A gate insulating film formed on the semiconductor layer;
A gate formed on the gate insulating layer to fill the recessed portion;
And a P + region and an N + region formed in the semiconductor substrate at both sides of the gate.
The method of claim 1,
The gate is a tunneling field effect transistor, characterized in that the gate insulating film and the semiconductor layer is surrounded in a round shape and contact the P + region and the N + region.
A semiconductor substrate having a mesa structure in which one side protrudes;
A semiconductor layer formed on the semiconductor substrate with a predetermined thickness;
A gate insulating film formed on the semiconductor layer;
A gate formed on a sidewall of the semiconductor substrate on the gate insulating film;
And a P + region and an N + region formed in the semiconductor substrate at both sides of the gate.
The method of claim 3, wherein
The P + region or the N + region protrudes,
And the gate is formed to contact a sidewall of the protruding P + region or the N + region.
The method according to any one of claims 1 to 4,
And the semiconductor layer is a semiconductor material of the same type as the semiconductor substrate, and a channel is formed according to a voltage applied to the gate.
The method of claim 5, wherein
And said semiconductor substrate is an SOI substrate or a bulk silicon substrate.
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