KR101746701B1 - 저항성 메모리에서의 비트 결함의 실시간 정정 - Google Patents
저항성 메모리에서의 비트 결함의 실시간 정정 Download PDFInfo
- Publication number
- KR101746701B1 KR101746701B1 KR1020167020441A KR20167020441A KR101746701B1 KR 101746701 B1 KR101746701 B1 KR 101746701B1 KR 1020167020441 A KR1020167020441 A KR 1020167020441A KR 20167020441 A KR20167020441 A KR 20167020441A KR 101746701 B1 KR101746701 B1 KR 101746701B1
- Authority
- KR
- South Korea
- Prior art keywords
- row
- bit
- array
- bank
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1695—Protection circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/814—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for optimized yield
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/150,559 | 2014-01-08 | ||
| US14/150,559 US9552244B2 (en) | 2014-01-08 | 2014-01-08 | Real time correction of bit failure in resistive memory |
| PCT/US2014/069984 WO2015105624A1 (en) | 2014-01-08 | 2014-12-12 | Real time correction of bit failure in resistive memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20160106091A KR20160106091A (ko) | 2016-09-09 |
| KR101746701B1 true KR101746701B1 (ko) | 2017-06-13 |
Family
ID=52293223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020167020441A Expired - Fee Related KR101746701B1 (ko) | 2014-01-08 | 2014-12-12 | 저항성 메모리에서의 비트 결함의 실시간 정정 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9552244B2 (enExample) |
| EP (1) | EP3092649B1 (enExample) |
| JP (1) | JP6126313B2 (enExample) |
| KR (1) | KR101746701B1 (enExample) |
| CN (1) | CN105917413B (enExample) |
| WO (1) | WO2015105624A1 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170132095A1 (en) * | 2014-03-28 | 2017-05-11 | Hewlett Packard Enterprise Development Lp | Data restoration |
| US9836349B2 (en) * | 2015-05-29 | 2017-12-05 | Winbond Electronics Corp. | Methods and systems for detecting and correcting errors in nonvolatile memory |
| US9484114B1 (en) * | 2015-07-29 | 2016-11-01 | Sandisk Technologies Llc | Decoding data using bit line defect information |
| US9933954B2 (en) * | 2015-10-19 | 2018-04-03 | Nxp Usa, Inc. | Partitioned memory having pipeline writes |
| JP2019045910A (ja) | 2017-08-29 | 2019-03-22 | 東芝メモリ株式会社 | 半導体記憶装置 |
| DE102018126051A1 (de) | 2018-01-12 | 2019-07-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | Neuartige Speichervorrichtung |
| US10643722B2 (en) | 2018-01-12 | 2020-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device |
| US11521697B2 (en) | 2019-01-30 | 2022-12-06 | STMicroelectronics International, N.V. | Circuit and method for at speed detection of a word line fault condition in a memory circuit |
| US11393532B2 (en) | 2019-04-24 | 2022-07-19 | Stmicroelectronics International N.V. | Circuit and method for at speed detection of a word line fault condition in a memory circuit |
| KR20230121611A (ko) | 2020-12-26 | 2023-08-18 | 인텔 코포레이션 | 시스템 메모리 신뢰성, 가용성 및 서비스 가능성(ras)을개선하기 위한 적응형 오류 정정 |
| CN116343892A (zh) * | 2021-12-24 | 2023-06-27 | 浙江驰拓科技有限公司 | 存储器硬失效位元的修复系统及修复方法 |
| JP7550895B2 (ja) * | 2023-02-02 | 2024-09-13 | ウィンボンド エレクトロニクス コーポレーション | 半導体装置およびウエアレベリング方法 |
| US20240403163A1 (en) * | 2023-05-31 | 2024-12-05 | Western Digital Technologies, Inc. | Error rate management in non-uniform memory arrays |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999463A (en) | 1997-07-21 | 1999-12-07 | Samsung Electronics Co., Ltd. | Redundancy fuse box and semiconductor device including column redundancy fuse box shared by a plurality of memory blocks |
| US20010054165A1 (en) | 2000-06-16 | 2001-12-20 | Fujitsu Limited | Memory device having redundant cells |
| JP2004030884A (ja) | 2002-05-01 | 2004-01-29 | Hewlett-Packard Development Co Lp | 磁気抵抗固体記憶素子における誤りを最小限にする方法 |
| US20050128830A1 (en) | 2003-12-11 | 2005-06-16 | Sony Corporation | Semiconductor memory device |
| US20080320346A1 (en) | 2007-06-25 | 2008-12-25 | Lin Jason T | Systems for reading nonvolatile memory |
| US20090132876A1 (en) | 2007-11-19 | 2009-05-21 | Ronald Ernest Freking | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks |
| JP2011008850A (ja) | 2009-06-24 | 2011-01-13 | Sony Corp | メモリ及び情報処理方法 |
| US8040743B2 (en) | 2008-09-30 | 2011-10-18 | Seagate Technology Llc | Data storage using read-mask-write operation |
| US8086913B2 (en) | 2008-09-11 | 2011-12-27 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US20120030441A1 (en) | 2010-07-29 | 2012-02-02 | Takahiro Yamashita | Semiconductor memory device detecting error |
| JP2012033222A (ja) | 2010-07-29 | 2012-02-16 | Toshiba Corp | 半導体記憶装置およびその制御方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2515097B2 (ja) * | 1985-10-08 | 1996-07-10 | 日本テキサス・インスツルメンツ 株式会社 | 半導体記憶装置 |
| JPH01165100A (ja) * | 1988-08-26 | 1989-06-29 | Hitachi Ltd | 半導体メモリ |
| US6879530B2 (en) | 2002-07-18 | 2005-04-12 | Micron Technology, Inc. | Apparatus for dynamically repairing a semiconductor memory |
| US7415640B1 (en) * | 2003-10-13 | 2008-08-19 | Virage Logic Corporation | Methods and apparatuses that reduce the size of a repair data container for repairable memories |
| US8032816B2 (en) | 2007-06-01 | 2011-10-04 | International Business Machines Corporation | Apparatus and method for distinguishing temporary and permanent errors in memory modules |
| US8839053B2 (en) | 2010-05-27 | 2014-09-16 | Microsoft Corporation | Error correcting pointers for non-volatile storage |
| US8467258B2 (en) | 2010-08-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for bit cell repair |
| US20120173921A1 (en) * | 2011-01-05 | 2012-07-05 | Advanced Micro Devices, Inc. | Redundancy memory storage system and a method for controlling a redundancy memory storage system |
| JP5377526B2 (ja) | 2011-01-13 | 2013-12-25 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP5204868B2 (ja) * | 2011-04-12 | 2013-06-05 | シャープ株式会社 | 半導体記憶装置 |
| KR20130049332A (ko) | 2011-11-04 | 2013-05-14 | 삼성전자주식회사 | 메모리 시스템 및 그것의 동작 방법 |
| US8996936B2 (en) * | 2011-12-08 | 2015-03-31 | Sandisk Technologies Inc. | Enhanced error correction in memory devices |
| US9110824B2 (en) * | 2012-06-08 | 2015-08-18 | Silicon Motion Inc. | Method, controller, and memory device for correcting data bit(s) of at least one cell of flash memory |
-
2014
- 2014-01-08 US US14/150,559 patent/US9552244B2/en active Active
- 2014-12-12 KR KR1020167020441A patent/KR101746701B1/ko not_active Expired - Fee Related
- 2014-12-12 WO PCT/US2014/069984 patent/WO2015105624A1/en not_active Ceased
- 2014-12-12 CN CN201480072470.7A patent/CN105917413B/zh active Active
- 2014-12-12 EP EP14824661.4A patent/EP3092649B1/en active Active
- 2014-12-12 JP JP2016543222A patent/JP6126313B2/ja not_active Expired - Fee Related
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999463A (en) | 1997-07-21 | 1999-12-07 | Samsung Electronics Co., Ltd. | Redundancy fuse box and semiconductor device including column redundancy fuse box shared by a plurality of memory blocks |
| US20010054165A1 (en) | 2000-06-16 | 2001-12-20 | Fujitsu Limited | Memory device having redundant cells |
| JP2004030884A (ja) | 2002-05-01 | 2004-01-29 | Hewlett-Packard Development Co Lp | 磁気抵抗固体記憶素子における誤りを最小限にする方法 |
| US20050128830A1 (en) | 2003-12-11 | 2005-06-16 | Sony Corporation | Semiconductor memory device |
| JP2005174462A (ja) | 2003-12-11 | 2005-06-30 | Sony Corp | 半導体記憶装置 |
| US20080320346A1 (en) | 2007-06-25 | 2008-12-25 | Lin Jason T | Systems for reading nonvolatile memory |
| US20090132876A1 (en) | 2007-11-19 | 2009-05-21 | Ronald Ernest Freking | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks |
| US8086913B2 (en) | 2008-09-11 | 2011-12-27 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
| US8040743B2 (en) | 2008-09-30 | 2011-10-18 | Seagate Technology Llc | Data storage using read-mask-write operation |
| JP2011008850A (ja) | 2009-06-24 | 2011-01-13 | Sony Corp | メモリ及び情報処理方法 |
| US20120030441A1 (en) | 2010-07-29 | 2012-02-02 | Takahiro Yamashita | Semiconductor memory device detecting error |
| JP2012033222A (ja) | 2010-07-29 | 2012-02-16 | Toshiba Corp | 半導体記憶装置およびその制御方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3092649A1 (en) | 2016-11-16 |
| CN105917413A (zh) | 2016-08-31 |
| CN105917413B (zh) | 2019-04-19 |
| JP2017502445A (ja) | 2017-01-19 |
| JP6126313B2 (ja) | 2017-05-10 |
| WO2015105624A1 (en) | 2015-07-16 |
| US9552244B2 (en) | 2017-01-24 |
| KR20160106091A (ko) | 2016-09-09 |
| US20150194201A1 (en) | 2015-07-09 |
| EP3092649B1 (en) | 2018-10-31 |
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