KR101563474B1 - 유연하고 확장가능한 메모리 아키텍쳐 - Google Patents

유연하고 확장가능한 메모리 아키텍쳐 Download PDF

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KR101563474B1
KR101563474B1 KR1020157014541A KR20157014541A KR101563474B1 KR 101563474 B1 KR101563474 B1 KR 101563474B1 KR 1020157014541 A KR1020157014541 A KR 1020157014541A KR 20157014541 A KR20157014541 A KR 20157014541A KR 101563474 B1 KR101563474 B1 KR 101563474B1
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memory
coupled
group
cubes
serially
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KR20150068494A (ko
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데이비드 알. 레스닉
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마이크론 테크놀로지, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
KR1020157014541A 2008-08-05 2009-08-04 유연하고 확장가능한 메모리 아키텍쳐 Active KR101563474B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/186,357 2008-08-05
US12/186,357 US8656082B2 (en) 2008-08-05 2008-08-05 Flexible and expandable memory architectures
PCT/US2009/004461 WO2010016889A2 (en) 2008-08-05 2009-08-04 Flexible and expandable memory architectures

Related Parent Applications (1)

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KR1020117005191A Division KR101584391B1 (ko) 2008-08-05 2009-08-04 유연하고 확장가능한 메모리 아키텍쳐

Publications (2)

Publication Number Publication Date
KR20150068494A KR20150068494A (ko) 2015-06-19
KR101563474B1 true KR101563474B1 (ko) 2015-10-26

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KR1020157014541A Active KR101563474B1 (ko) 2008-08-05 2009-08-04 유연하고 확장가능한 메모리 아키텍쳐
KR1020117005191A Active KR101584391B1 (ko) 2008-08-05 2009-08-04 유연하고 확장가능한 메모리 아키텍쳐

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KR1020117005191A Active KR101584391B1 (ko) 2008-08-05 2009-08-04 유연하고 확장가능한 메모리 아키텍쳐

Country Status (7)

Country Link
US (2) US8656082B2 (https=)
EP (1) EP2310943B1 (https=)
JP (2) JP5666445B2 (https=)
KR (2) KR101563474B1 (https=)
CN (2) CN102144223B (https=)
TW (2) TWI482171B (https=)
WO (1) WO2010016889A2 (https=)

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US20130019053A1 (en) * 2011-07-14 2013-01-17 Vinay Ashok Somanache Flash controller hardware architecture for flash devices
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US9569211B2 (en) * 2012-08-03 2017-02-14 International Business Machines Corporation Predication in a vector processor
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US9594724B2 (en) 2012-08-09 2017-03-14 International Business Machines Corporation Vector register file
US9298395B2 (en) 2012-10-22 2016-03-29 Globalfoundries Inc. Memory system connector
US8972782B2 (en) 2012-11-09 2015-03-03 International Business Machines Corporation Exposed-pipeline processing element with rollback
JP5985403B2 (ja) 2013-01-10 2016-09-06 株式会社東芝 ストレージ装置
US9244684B2 (en) 2013-03-15 2016-01-26 Intel Corporation Limited range vector memory access instructions, processors, methods, and systems
US9236564B2 (en) 2013-12-11 2016-01-12 Samsung Electronics Co., Ltd. Method and system for providing an engineered magnetic layer including Heusler layers and an amorphous insertion layer
US9934194B2 (en) 2013-12-20 2018-04-03 Rambus Inc. Memory packet, data structure and hierarchy within a memory appliance for accessing memory
US9558143B2 (en) * 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

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US6633947B1 (en) * 1998-09-16 2003-10-14 Intel Corporation Memory expansion channel for propagation of control and request packets
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Also Published As

Publication number Publication date
EP2310943B1 (en) 2015-04-08
TW201021048A (en) 2010-06-01
JP2011530736A (ja) 2011-12-22
CN102144223B (zh) 2014-11-26
WO2010016889A3 (en) 2010-05-14
KR101584391B1 (ko) 2016-01-21
TW201523628A (zh) 2015-06-16
WO2010016889A2 (en) 2010-02-11
US20100036994A1 (en) 2010-02-11
JP5820038B2 (ja) 2015-11-24
TWI482171B (zh) 2015-04-21
EP2310943A2 (en) 2011-04-20
US9348785B2 (en) 2016-05-24
TWI559323B (zh) 2016-11-21
US20140164667A1 (en) 2014-06-12
CN102144223A (zh) 2011-08-03
CN104281556A (zh) 2015-01-14
JP2015008011A (ja) 2015-01-15
CN104281556B (zh) 2019-11-08
KR20150068494A (ko) 2015-06-19
JP5666445B2 (ja) 2015-02-12
KR20110050497A (ko) 2011-05-13
US8656082B2 (en) 2014-02-18
EP2310943A4 (en) 2012-06-27

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