KR101467467B1 - 최적화된 비터비 디코더 및 gnss 수신기 - Google Patents
최적화된 비터비 디코더 및 gnss 수신기 Download PDFInfo
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- KR101467467B1 KR101467467B1 KR1020127024288A KR20127024288A KR101467467B1 KR 101467467 B1 KR101467467 B1 KR 101467467B1 KR 1020127024288 A KR1020127024288 A KR 1020127024288A KR 20127024288 A KR20127024288 A KR 20127024288A KR 101467467 B1 KR101467467 B1 KR 101467467B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
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- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP07119378 | 2007-10-26 | ||
| EP07119378.3 | 2007-10-26 | ||
| PCT/EP2008/064530 WO2009053490A2 (en) | 2007-10-26 | 2008-10-27 | Optimized viterbi decoder and gnss receiver |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020107011361A Division KR20100085131A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020137028253A Division KR20130124413A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20120120448A KR20120120448A (ko) | 2012-11-01 |
| KR101467467B1 true KR101467467B1 (ko) | 2014-12-02 |
Family
ID=40580136
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020127024288A Expired - Fee Related KR101467467B1 (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020137028253A Ceased KR20130124413A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020107011361A Ceased KR20100085131A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020117031504A Expired - Fee Related KR101129064B1 (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020117031502A Expired - Fee Related KR101127333B1 (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
Family Applications After (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020137028253A Ceased KR20130124413A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020107011361A Ceased KR20100085131A (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020117031504A Expired - Fee Related KR101129064B1 (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
| KR1020117031502A Expired - Fee Related KR101127333B1 (ko) | 2007-10-26 | 2008-10-27 | 최적화된 비터비 디코더 및 gnss 수신기 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8621335B2 (enExample) |
| EP (1) | EP2220771A2 (enExample) |
| JP (2) | JP5502739B2 (enExample) |
| KR (5) | KR101467467B1 (enExample) |
| CN (2) | CN101889401B (enExample) |
| WO (1) | WO2009053490A2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8270405B2 (en) | 2009-06-30 | 2012-09-18 | Intel Corporation | Multicast support on a switch for PCIe endpoint devices |
| US8694878B2 (en) * | 2011-06-15 | 2014-04-08 | Texas Instruments Incorporated | Processor instructions to accelerate Viterbi decoding |
| US9153990B2 (en) | 2012-11-30 | 2015-10-06 | Tesla Motors, Inc. | Steady state detection of an exceptional charge event in a series connected battery element |
| US9529048B2 (en) | 2012-11-30 | 2016-12-27 | Tesla Motors, Inc. | Transient detection of an exceptional charge event in a series connected battery element |
| US10496407B2 (en) * | 2017-12-21 | 2019-12-03 | Intel Corporation | Apparatus and method for adding packed data elements with rotation and halving |
| CN109993272B (zh) * | 2017-12-29 | 2019-12-06 | 北京中科寒武纪科技有限公司 | 卷积及降采样运算单元、神经网络运算单元和现场可编程门阵列集成电路 |
| GB202006748D0 (en) | 2020-05-07 | 2020-06-24 | Qinetiq Ltd | Decoder for a receiver |
| KR102418617B1 (ko) | 2020-10-13 | 2022-07-07 | 서울대학교산학협력단 | 염기 비율과 연속적 발생을 제한하는 dna 저장 부호화 방법, 프로그램 및 장치 |
| EP4109138A1 (en) | 2021-06-21 | 2022-12-28 | Electronics and Telecommunications Research Institute | Method and apparatus for transmitting and receiving characteristic information of gnss subframe |
| CN115499093B (zh) * | 2022-08-01 | 2024-05-24 | 北京北方联星科技有限公司 | 一种基于fec编码的sbas信号非译码帧同步方法 |
| CN117749199A (zh) * | 2024-02-20 | 2024-03-22 | 北京凯芯微科技有限公司 | 一种导航电文译码单元及方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006041616A (ja) * | 2004-07-22 | 2006-02-09 | Advantest Corp | ビタビ復号装置、方法、プログラム、記録媒体 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232973A (ja) * | 1996-02-28 | 1997-09-05 | Sony Corp | ビタビ復号器 |
| US6301314B1 (en) | 1996-10-24 | 2001-10-09 | Sony Corporation | Viterbi decoding apparatus and viterbi decoding method |
| JP3660361B2 (ja) * | 1997-10-31 | 2005-06-15 | エイ ティ アンド ティ ワイヤレス サービス インコーポレイテッド | 無線機器のための連結された空間符号の簡単な最尤検出 |
| US5912908A (en) * | 1997-11-21 | 1999-06-15 | Lucent Technologies Inc. | Method of efficient branch metric computation for a Viterbi convolutional decoder |
| US6272188B1 (en) * | 1997-11-24 | 2001-08-07 | Agere Systems Guardian Corp. | Single-cycle accelerator for extremun state search |
| US6029267A (en) * | 1997-11-25 | 2000-02-22 | Lucent Technologies Inc. | Single-cycle, soft decision, compare-select operation using dual-add processor |
| JPH11196007A (ja) * | 1997-12-25 | 1999-07-21 | Matsushita Electric Ind Co Ltd | ビタビ復号器 |
| US6256505B1 (en) * | 1998-05-28 | 2001-07-03 | Ericsson Lnc. | GSM transceiver unit equipped for time of arrival measurements |
| JP3419680B2 (ja) * | 1998-06-02 | 2003-06-23 | 三菱電機株式会社 | ビタビ復号装置 |
| JP2001060881A (ja) * | 1999-08-20 | 2001-03-06 | Fujitsu Ltd | パスメトリック正規化装置 |
| US6560749B1 (en) * | 2000-01-28 | 2003-05-06 | Nec Electronics, Inc. | Apparatus and method for implementing a decoder for convolutionally encoded symbols |
| DE10010238C2 (de) * | 2000-03-02 | 2003-12-18 | Infineon Technologies Ag | Verfahren zum Speichern von Pfadmetriken in einem Viterbi-Decodierer |
| US6788750B1 (en) * | 2000-09-22 | 2004-09-07 | Tioga Technologies Inc. | Trellis-based decoder with state and path purging |
| JP3984790B2 (ja) * | 2001-01-15 | 2007-10-03 | 日本電気株式会社 | ビタビ復号処理装置 |
| US6633856B2 (en) * | 2001-06-15 | 2003-10-14 | Flarion Technologies, Inc. | Methods and apparatus for decoding LDPC codes |
| US7661059B2 (en) * | 2001-08-06 | 2010-02-09 | Analog Devices, Inc. | High performance turbo and Viterbi channel decoding in digital signal processors |
| US7043682B1 (en) * | 2002-02-05 | 2006-05-09 | Arc International | Method and apparatus for implementing decode operations in a data processor |
| JP2003258650A (ja) * | 2002-03-06 | 2003-09-12 | Hitachi Kokusai Electric Inc | 最尤復号器 |
| US7248637B2 (en) * | 2003-06-11 | 2007-07-24 | Advanced Micro Devices, Inc. | Viterbi decoder utilizing partial backtracing |
| US7861146B2 (en) * | 2004-05-27 | 2010-12-28 | Panasonic Corporation | Viterbi decoding apparatus and Viterbi decoding method |
-
2008
- 2008-10-27 CN CN200880119377.1A patent/CN101889401B/zh not_active Expired - Fee Related
- 2008-10-27 WO PCT/EP2008/064530 patent/WO2009053490A2/en not_active Ceased
- 2008-10-27 KR KR1020127024288A patent/KR101467467B1/ko not_active Expired - Fee Related
- 2008-10-27 CN CN201410714995.8A patent/CN104601181B/zh not_active Expired - Fee Related
- 2008-10-27 KR KR1020137028253A patent/KR20130124413A/ko not_active Ceased
- 2008-10-27 KR KR1020107011361A patent/KR20100085131A/ko not_active Ceased
- 2008-10-27 KR KR1020117031504A patent/KR101129064B1/ko not_active Expired - Fee Related
- 2008-10-27 JP JP2010530479A patent/JP5502739B2/ja not_active Expired - Fee Related
- 2008-10-27 EP EP08842947A patent/EP2220771A2/en not_active Withdrawn
- 2008-10-27 KR KR1020117031502A patent/KR101127333B1/ko not_active Expired - Fee Related
- 2008-10-27 US US12/680,160 patent/US8621335B2/en not_active Expired - Fee Related
-
2013
- 2013-01-30 JP JP2013015211A patent/JP5694398B2/ja not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006041616A (ja) * | 2004-07-22 | 2006-02-09 | Advantest Corp | ビタビ復号装置、方法、プログラム、記録媒体 |
Non-Patent Citations (3)
| Title |
|---|
| Hui-Ling Lou, "Implementing the Viterbi Algorithm", IEEE Signal Processing Magazine, September 1995, pp.42-52. * |
| K. Y. Lin 외 1인, "A parallel Viterbi algorithm for decoding convolutional codes on SIMD machines", Proceedings of 35th Midwest Symposium on Circuits and Systems, 1권, August 1992, pp.361-364. * |
| W. Grass, "Higher performance and lower power enhancements to VLIW architectures", IEEE Workshop on Signal Processing Systems, September 2001, p.157. * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013138452A (ja) | 2013-07-11 |
| KR20130124413A (ko) | 2013-11-13 |
| EP2220771A2 (en) | 2010-08-25 |
| CN104601181A (zh) | 2015-05-06 |
| KR20120023143A (ko) | 2012-03-12 |
| US8621335B2 (en) | 2013-12-31 |
| CN101889401A (zh) | 2010-11-17 |
| WO2009053490A3 (en) | 2009-09-24 |
| JP5502739B2 (ja) | 2014-05-28 |
| KR101129064B1 (ko) | 2012-03-23 |
| US20100299583A1 (en) | 2010-11-25 |
| CN101889401B (zh) | 2014-12-31 |
| KR20120120448A (ko) | 2012-11-01 |
| WO2009053490A2 (en) | 2009-04-30 |
| KR20100085131A (ko) | 2010-07-28 |
| KR101127333B1 (ko) | 2012-03-29 |
| JP2011501596A (ja) | 2011-01-06 |
| JP5694398B2 (ja) | 2015-04-01 |
| CN104601181B (zh) | 2017-12-22 |
| KR20120014065A (ko) | 2012-02-15 |
| WO2009053490A9 (en) | 2011-03-10 |
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