KR101341373B1 - 공통의 기판에 의해 지지된 2 개 이상의 가공 반도체 구조를 포함하는 접합 반도체 구조의 형성 방법, 및 이러한 방법에 의해 형성된 반도체 구조 - Google Patents

공통의 기판에 의해 지지된 2 개 이상의 가공 반도체 구조를 포함하는 접합 반도체 구조의 형성 방법, 및 이러한 방법에 의해 형성된 반도체 구조 Download PDF

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Publication number
KR101341373B1
KR101341373B1 KR1020120033825A KR20120033825A KR101341373B1 KR 101341373 B1 KR101341373 B1 KR 101341373B1 KR 1020120033825 A KR1020120033825 A KR 1020120033825A KR 20120033825 A KR20120033825 A KR 20120033825A KR 101341373 B1 KR101341373 B1 KR 101341373B1
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KR
South Korea
Prior art keywords
semiconductor
substrate
material layer
layer
metallization layer
Prior art date
Application number
KR1020120033825A
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English (en)
Korean (ko)
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KR20120112270A (ko
Inventor
마리암 사다카
Original Assignee
소이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/077,364 external-priority patent/US8338294B2/en
Priority claimed from FR1153080A external-priority patent/FR2973943B1/fr
Application filed by 소이텍 filed Critical 소이텍
Publication of KR20120112270A publication Critical patent/KR20120112270A/ko
Application granted granted Critical
Publication of KR101341373B1 publication Critical patent/KR101341373B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020120033825A 2011-03-31 2012-04-02 공통의 기판에 의해 지지된 2 개 이상의 가공 반도체 구조를 포함하는 접합 반도체 구조의 형성 방법, 및 이러한 방법에 의해 형성된 반도체 구조 KR101341373B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/077,364 2011-03-31
US13/077,364 US8338294B2 (en) 2011-03-31 2011-03-31 Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
FR1153080A FR2973943B1 (fr) 2011-04-08 2011-04-08 Procédés de formation de structures semi-conductrices collées comprenant deux structures semi-conductrices traitées ou plus supportées par un substrat commun, et structures semi-conductrices formées par ces procédés
FRFR1153080 2011-04-08

Publications (2)

Publication Number Publication Date
KR20120112270A KR20120112270A (ko) 2012-10-11
KR101341373B1 true KR101341373B1 (ko) 2013-12-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120033825A KR101341373B1 (ko) 2011-03-31 2012-04-02 공통의 기판에 의해 지지된 2 개 이상의 가공 반도체 구조를 포함하는 접합 반도체 구조의 형성 방법, 및 이러한 방법에 의해 형성된 반도체 구조

Country Status (3)

Country Link
KR (1) KR101341373B1 (zh)
CN (1) CN102738026B (zh)
TW (1) TWI517226B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3373329B1 (en) * 2014-02-28 2023-04-05 LFoundry S.r.l. Integrated circuit comprising a laterally diffused mos field effect transistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020001937A1 (en) 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
US6946365B2 (en) 2000-12-08 2005-09-20 Commissariat A L'energie Atomique Method for producing a thin film comprising introduction of gaseous species
US7786571B2 (en) 2007-07-10 2010-08-31 Unimicron Technology Corporation Heat-conductive package structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2002108A (en) * 1931-12-24 1935-05-21 Hal G Child Exercising device
US5635761A (en) * 1994-12-14 1997-06-03 International Business Machines, Inc. Internal resistor termination in multi-chip module environments
JP4092890B2 (ja) * 2001-05-31 2008-05-28 株式会社日立製作所 マルチチップモジュール
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
TW569416B (en) * 2002-12-19 2004-01-01 Via Tech Inc High density multi-chip module structure and manufacturing method thereof
TWI251916B (en) * 2003-08-28 2006-03-21 Phoenix Prec Technology Corp Semiconductor assembled heat sink structure for embedding electronic components
US7371662B2 (en) * 2006-03-21 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a 3D interconnect and resulting structures
JP4956128B2 (ja) * 2006-10-02 2012-06-20 ルネサスエレクトロニクス株式会社 電子装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020001937A1 (en) 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
US6946365B2 (en) 2000-12-08 2005-09-20 Commissariat A L'energie Atomique Method for producing a thin film comprising introduction of gaseous species
US7786571B2 (en) 2007-07-10 2010-08-31 Unimicron Technology Corporation Heat-conductive package structure

Also Published As

Publication number Publication date
CN102738026A (zh) 2012-10-17
CN102738026B (zh) 2014-11-05
TWI517226B (zh) 2016-01-11
KR20120112270A (ko) 2012-10-11
TW201239970A (en) 2012-10-01

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