TW201239970A - Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods - Google Patents

Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods Download PDF

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TW201239970A
TW201239970A TW101104599A TW101104599A TW201239970A TW 201239970 A TW201239970 A TW 201239970A TW 101104599 A TW101104599 A TW 101104599A TW 101104599 A TW101104599 A TW 101104599A TW 201239970 A TW201239970 A TW 201239970A
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Taiwan
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layer
semiconductor
substrate
processed
semiconductor structure
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TW101104599A
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Chinese (zh)
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TWI517226B (en
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Mariam Sadaka
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Soitec Silicon On Insulator
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Priority claimed from US13/077,364 external-priority patent/US8338294B2/en
Priority claimed from FR1153080A external-priority patent/FR2973943B1/en
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Publication of TW201239970A publication Critical patent/TW201239970A/en
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Publication of TWI517226B publication Critical patent/TWI517226B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Description

201239970 六、發明說明： 【發明所屬之技術領域】 本發明之實施例一般而言係關於形成包含黏附至一共同底材之兩個 或更多半導體構造之半導體裝置之方法，以及應用此等方法所形成之半 導體裝置。 【先前技術】 兩個或更多半導體構造之三度空間集積（3D integration)可以替微 電子應用帶來許多好處。舉例而言，微電子元件之三度空間集積可以改進 電氣效能及電力消耗’同時減少裝置之底面積。相關資料可參見諸如P.201239970 VI. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to a method of forming a semiconductor device including two or more semiconductor structures adhered to a common substrate, and applying the methods The formed semiconductor device. [Prior Art] Three-dimensional integration of two or more semiconductor structures can bring many benefits to microelectronic applications. For example, a three-dimensional spatial accumulation of microelectronic components can improve electrical performance and power consumption while reducing the bottom area of the device. Related information can be found in such as P.

Garrou 等人所編之《The Handbook of 3D Integration》（Wiley-VCH 出版， 2008 年）。 半導體構造之三度空間集積可以透過以下方式或該些方式之組合而 達到：將一半導體晶粒附著至額外的一個或更多半導體晶粒（亦即晶粒對 晶粒（D2D))，將一半導體晶粒附著至一個或更多半導體晶圓（亦即晶 粒對晶圓（D2W))，以及將一半導體晶圓附著至額外的一個或更多半導 體晶圓（亦即晶圓對晶圓（W2W))。 通常的情況是，該些個別的半導體構造（例如晶粒或晶圓）可能相 §薄’很難以處理半導體構造的設備處理。因此，可以將所謂的「載體」 晶粒或晶圓附著至其中含有操作半導體裝置之主動及被動元件之實際半 導體構造上。該些載體晶粒或晶圓通常不包含有待形成之半導體裝置之任 何主動或被動元件。此等載體晶粒或晶圓在本說明書中稱為「載體底材」。 該些載體底材增加了該些半導體構造之整體厚度，並有利於處理設備處理 3 201239970 該些半導體構造（經由細細之·半導職造提供結構性支樓） 該些處理設備制於處理崎於該辨導_造之絲竭絲元件兮 些半導體構·包括轉製作於其上之—㈣體裝置之主動及被料 件。在本說明書令’此等半導體構造，其最終將包含有待製作於其上之^ 半導體裝置之絲及/或獅耕，或在製較餅最終將包含有待製作於 其上之-半導體裝置之主動及/或被動元件，稱為「装置 。 用於將一半導體構造黏附至另一半導體構造之黏附技術可以按不同 方式加以分類，-種方式為按一層中間材料是否提供於該兩個半導體構造 之間以將其黏附在-起而加以分類，第二種方式為按黏附界面是否允許電 子（亦即電流）通過該界面而加以分類。所謂的「直接黏附方法」係指在 兩個半導體構造之間建立直接的固體對固體化學鍵結以將其黏附在一 起’而無需在該些半導體構造間使用—中介之黏附材料將其黏附在一起之 方法。目前已發展出直接的金屬對金屬黏附方*，可將—第 -表面的金屬材料黏附至-第二半導體構造—表面的金屬材料。^ 直接的金屬對金屬黏附方法亦可以按照各方法操作時的溫度範圍加 以分類。例如’-些直接的金屬對金屬_方歧在相對高溫下進行，因 而造成黏附界面處之金屬材料至少有部分炼化。此等直接黏附製程可能不 適合用於黏附包含-個或更多裝置構造之已處理半導體構造，因其偏高之 溫度可能_早前形成之該钱置構造有不利影響。 「熱壓黏附」方法為在介於攝氏2⑻度（2⑻。c)及大約攝氏· 度（500。〇間之高溫下，通常為介於大約攝氏3〇〇度（3〇〇。〇及大約攝 氏400度（400。〇之間’於_黏附表面間施加壓力之直接黏附方法。 201239970 額外之直接黏附方法目則已發展出來，該些方法可以在攝氏2⑽度 (2〇〇。〇或更低之溫度下進行。對於在攝氏2〇〇度（2〇〇〇c)或更低之溫 度下進行之此等直接黏附製程，本說明書稱為「超低溫」直接黏附方法。 超低溫直接Μ方法可以麵仔轉除表面雜f及表面化合物（例如原生 氧化層）’以及經由在原子級尺度上增加兩録面職雜觸之面積而進 行。兩個表面間緊密接觸之面積通常經由以下方式達成：研磨該錄附表 面以降低其表面減至接近原子級尺度之練、於細表面間施加壓 力以造成雜變形、姐研磨該些_表面謂其施加壓力以制此種塑 性變形。 -些超低溫直接_方法可以不需在該錄附表面間之黏附界面施 加壓力，但在其他超低溫直接黏附綠中，可以在該些黏附表面間之黏附 界面施加壓力’以在該_界面達到合適__度。在本發明所屬之技 術領域巾，於婦軸表關施域力之超低溫直接_方法通常被稱為 「表面輔助義」或「湖」方法。因此，在本說明書中，「表面辅助黏 附」及「SAB」係指並包括在攝氏2〇〇度（2〇〇〇c)或更低之溫度下，將 -第-材料緊靠-第二材料，並在該錄喊關之黏附界面施加壓力， 以使該第-觀直接_至該第二材料之任何直接細製程。 載體底材通常利用黏著劑附著至裝置底材。類似的黏附方法也可以 用於將-半導體構造岭至另—半導體構造，該些半導體構造當中均包含 一個或更多轉體裝置之絲及/或被動元件。 半導體晶㈣有之電驗接可贿其所要連結之其他半導體構造之 電氣連接不匹配。-中介層（interp〇ser，亦即一額外構造）可以置於兩半 201239970 導體構ie間或任何半導體晶粒及—半導體封裝件之間 ，以重新佈線並使適 當的電氣連接對準。該中介層可以具有一個或更多導電線路及通孔，該些 線路及通孔侧於在該麵冑之半導體财賊錢當接觸。 【發明内容】 本發明之實施例可啸供形成含有由—共同底材承載之兩個或更多 半導體構k之半導n裝置之方法及触。-電祕接可以透麟共同底材 提供於該些轉體構拍其巾兩個或多個之間。本概要係為了以簡要形式 介紹—系列概念而提供，該些概念將於本發明之實施例中進-步詳細敘 述本概要之用思並非指出所主張專利標的之主要特點或基本特點，亦非 用於限制所主張專利標的之範圍。 在-些實施例巾’本發明包括形成-半導體裝置之方.依照此等 方法’可以提供-底材’該底材包括一層半導體材料在一層電氣絕緣材料 上。在與該層電氣絕緣材料相反之闕半導體材料第—面，可以將含有複 數個導電部件之第-金屬化層形餘該底材上。形成複數個晶圓間透通連 結使之至少部分穿過該底材。該些晶圓間透通連結至少其中之—可以穿過 a玄金屬化層及職半導㈣料。在無層半導體材料第—面相反之該層半 導體材料第二面，可以將含有複數料電部狀第二金屬化層碱於該底 材上。在由該底材承載於該層半導體材料第—面之—第—已處理半導體構 造，以及由該底材承載於該層半導體材料第一面之—第二已處理半導體構 造間，提供（例如形成）f過該第-金屬化層、該底材及該第二金屬化層 之一電氣路徑。 201239970 在額外之實施例中，本發明包括應用本說明書所述方法所形成之 半導體構造。舉例而言，在額外之實施例中，本發明包含半導體裝置， 其包括：包含一層半導體材料之一底材；該底材上之一第一金屬化層， 其位於該層半導體材料之第一面；以及該底材上之一第二金屬化層其 位於與該層半導體材料第一面相反之該層半導體材料第二面。複數個晶 圓間透通連結至少部分穿過該第一金屬化層及該底材之該層半導體材 料。一第一已處理半導體構造可以由該底材承載於該層半導體材料之第 一面，一第二已處理半導體構造亦可以由該底材承載於該層半導體材料 之第一面。至少一個電氣路徑可以從該第一已處理半導體構造，穿過該 第一金屬化層之一導電部件、該些晶圓間透通連結之一第一晶圓間透通 連結、該第二金屬化層之一導電部件，及該些晶圓間透通連結之一第二 晶圓間透通連結’延伸至該第二已處理半導體構造。 【實施方式】 本說明書提出之闡釋其用意並非對於任何特定材料、裝置、系統咬 方法之貫際意見，而僅是用來描述本發明實施例之理想化陳述。 本說明書所用之任何標題不應認定其用意為限制本發明實施例之範 圍’該範圍係由以下之申請專繼圍及其法律同等效力所界定。在任何特 定標題下所敘述之概念，通常亦適用於整份說明書之其他部分。 本說明書引用了-些參考資料，為了所有目的，該些參考資料之完 整揭露茲以此述及方式納入本說明書。此外，相對於本發明主張之專利標 201239970 的’該些引用之參考資料，不論本說明書如何描述其特點，均不予承認為 習知技術。 在本說明書中，「半導體裝置」一詞係指並包括含有一種或更多半 導體材料之任何裝置，將該裝置在功能上予以適當地集積成一電子或光電 之裝置或系統時，其能夠發揮一項或多項功能。半導體裝置包括，但不限 於，電子信號處理器、記憶裝置（例如隨機存取記憶體'動態 隨機存取記憶體（DRAM)、快閃記憶體等等）、光電裝置（例如發光二 極體、雷射二極體 '太陽能電池等等），以及包含在操作上彼此連結之兩 個或更多此等裝置之裝置。 在本說明書中，「半導體構造」一詞係指並包括製作一半導體襄置 期間所使贼形叙贿構造。半導體構造包括，舉例而言，晶粒和晶圓 (例如載縣讽Μ底材），叹含扣三妓财錢此集積之兩個 或更多晶粒及/或晶圓之組合或複合構造。半導體構造亦包括完全裝配之半 導體裝置，以及製作轉雜置_所形成之中間構造。 在本說明書中，「已處理半導體構造」一詞係指並包括含有至少已 ^形权-鐵更錢置财之任辨魏财。已處理料體構造為 +導體構狀ϋ。 在本說明書中，「黏附半導 起之_或更多半_造-何構造附著在- 構，心== 處理半導館構造之黏附侧構造亦為已處理半導趙構造。 已 8 201239970 在本說明書t，「裝置構造」—詞係指並包括—已處理半導體構造 之任何部分，該部分為、包含'或界定出—半導體裝置之_絲或被動元 件之至少-部分，辭導體裝置树形成於解導體構造之上或之中。舉 例而言’裝置構造包含積體電路之主動及被動元件，像是電晶體換能器、 電谷'電阻、導電線、導電通孔及導電接觸墊。 在本說明書t ’「晶圓間透通連結」或「谓」—觸指並包括穿 過一第-半導體構造至少-部分之任何導電通孔，其跨越該第一半導體構 造與-第二半導體構造間之—界面，以在該第—半導體構造與該第二半導 體構造間提供-構造上及/或電氣上之互連。在本發明所屬技術領域中，晶 圓間透通連結亦有其他名稱，像是「石夕導通孔（thr〇u細—㈣/底材 (throughsubstratevias) , ^TSV, , ^ a ®^L (through wafer vias)」或「TWVj。谓通常會在大致垂直於一半導體構造中該 些大致平坦之主要表面之—方向上（亦即平行於％軸之—方向上）穿 過該半導體構造。 在本說月曰中’主動表面」一詞用於和一已處理半導體構造有關 的情況時’係指並包括該已處理半導體構造之一曝露主要表面，該表面已 經過處理過’或將經過處理’以使—個或更多裝置構造形成於該已處理半 導體構造之曝露主要表面之中及/或之上。 在本說月曰中，金屬化層」—詞係指並包括一已處理半導體構造 之層’該層包含鴨、輸孔、輪咖其卜_個，其係 用於沿著-錢路徑之至少—部分料電流。 9 201239970 在本說明書中，「背表面J一詞用於和一已處理半導體構造有關的 情況時，係指並包括該已處理半導體構造之一曝露主要表面，其為與該已 處理半導體構造之-主動表面相反之-面。 在本說明書中，「三五族半導體材料」一詞係指並包括絕大部分含 有元素週期表中—種或更多ΙΠΑ族元素（B、ai、&、^及阳與—種或 更多VA族元素（N、p、As、％及执）之任何材料。 本發明之實施例包括形成半導體構造之方法及構造，更具體而言為 包含_半導體之料體，収形献等細半導麟造之方 法。 在―實知例中’所形成之晶圓間透通連結會穿過一絕緣體上半導 體（SeOI)底材之至少—部分，靖形成之—層或更多金屬化層會覆蓋該 eOI底材之至少一部分。已處理半導體構造（例如半導體裝置）可以由 5 底材之至^部分所承載’且該些已處理半導體構造（以及，選 擇性地，其他構造或底材）間之電氣路徑，可以利用該些金屬化層之導電 P牛及圓間透通連結而建立。本發明之該些方法及構造之實施例可 以供不同目的所採用，例如用於三度空間集積製程及形成三度空間集積構 造。 ,圖1呈現可以為本發明實施例所採用之一底材。該底材1〇〇包含相 田4之-層半導麟料1G4。在—些實施例巾該層半導體材料104可以 至少實質上為單晶半導體材料。 201239970 作為非限制性質之範例，該層半導體材料104可以包括單晶之石夕、 鍺，或—種三五族半導體材料，且可以為有摻雜或無摻雜。在一些實施例 中’該層半導體材料104可以包括半導體材料之一磊晶層。 在一些實施例中，該層半導體材料104之平均總厚度可以為大約i 微米（1 μπι)或更薄、大約500奈米（5〇〇啦）或更薄，或甚至大約 奈米（10nm)或更薄。 或者，該層半導體材料可以配置在一基底1〇6之上並由其承載。作 為非限制性質之範例，該基底1〇6可以包括-種或更多介電材料，像是一 種氧化物(例如氧化矽(Si〇2)或氧化鋁(A丨2〇3))、一種氮化物(例如 氮化石夕（Si3N4)或氮化棚⑽））料。在額外之實施例中，該基底ι〇6 可以包括辭導體材料’諸如上文關於該半導體材料丨⑽所述及者之任 何種。在一些實施例中，該基底1〇6也可以包括含有兩種或更多不同材 料之一多層構造。 在-些實施例中’該底材100可以包括本發明所屬技術領域中稱為 「絕緣體上半導體（SeOI)」類型之一底材。例如，該底材励可以包括 本發明所屬技術領域中稱為「絕緣體上石夕⑽）」類型之一底材。在此 等實把例_，一層電氣絕緣材料丨〇5可以配置在該層半導體材料與一 基底106之間。該電氣絕緣材料1〇5可以包括在本發明所屬技術領域中稱 為「埋置氧化物（BOX)」之一層。該電氣絕緣材料1〇5可以包括，例如， 一種陶紐料’像是-種氮化物（例如氮切或—魏化物（例 如二氧化矽⑽2)或氧她（執））。在—些實施例中，該層電氣絕 201239970 緣材料105之平均總厚度可以為大約！微米（1叫）或更薄、大約3〇〇奈 米（300nm)或更薄，或甚至大約1〇奈米〇〇nm)或更薄。 作為非限制性質之一範例，圖！所示之底材1〇〇可以應用本發明所 屬技術領域中稱為SMART_CUTrM製程者加以形成。舉例而言，如圖2所 不，一層相當厚之半導體材料104,可以被黏附至該層電氣絕緣材料1〇5之 -曝露主要表fir 1G7 1層相當厚之半導翻·料鮮之喊可以與有待提 供於該基底1G6上方之該層半導體材料1G4之_完全_，且該層半導 體材料104可以自該層相當厚之半導體材料财形成，並包括該層相當厚 之半導體材料104’之相對較薄之一部分。 在些貫把例中，一黏附材料（未顯示）可以用於將該層相當厚之 半導體材料104'黏附至該層電氣絕緣材料1()5之主要表面1〇7。此種黏附 材料可以包括，例如，氧化石夕、氮化石夕其中之一種或多種，及其混合物。 此種黏附材料可以形成或以其他方式提供於該層電氣絕緣材料1〇5與該層 相當厚之半導體材料104,之該些毗連表面其中之一或兩者，以增進兩者間 之黏附。 在一些實施例中，該層相當厚之半導體材料1〇4，可以在大約4〇〇〇c 或更低之溫度下，或甚至在大約350°C或更低之溫度下，黏附至該層電氣 絕緣材料105。但在其他實施例中’該黏附製程可以在更高之溫度下實施。 將s玄層相當厚之半導體材料104’黏附至該層電氣絕緣材料1〇5後， 該層相當厚之半導體材料1〇4'便可予以薄化，以形成圖丨中相當薄之半導 體層104。邊層相當厚之半導體材料1〇4’之一部分no可以從該層相當薄 12 201239970 • 之半導體材料104移除，而將該層相當薄之半導體材料104留在該層電氣 絕緣材料105之表面107上。 作為非限制性質之範例，SMART_CurrM製程可以用於將該層相當 厚之半導騎料贈之該部分11G無相#薄之半導體材料⑽該層電 氣絕緣材料105及該基底1〇6分離。此等製程詳述於諸如美國專利虹 39,484號（細年2月6日核發^Brud)、美國專利㈣调號（雇 年1〇月16曰核發予Aspar等人）、美國專利6,335,258號（2〇〇2年^月 1日核發予ASpar等人）、美國專利6756286號（2_年6月29日核發 予Μ〇Γί_等人）、美國專利_9,〇44號（2004年1〇月26日核發予 等人）’及美國專利6,946,365號（2005年9月20日核發予Aspar 等人）中’該些專利之完整揭露兹以此述及方式納人本說明書。 簡。之’複數個離子（例如氫離子、氦離子或惰性氣體離子其中之 一種或多種）可以沿著-離子植入平面112植入該層半導體材料ι〇4,。在 -些實施财’該些離子可以在騎半導珊料贈被細至該層電氣絕 緣材料105及該基底106之前，植入該層半導體材料财。 離子可以沿著實質上垂直於該層半導體材料财之一方向植入。如 本發明所屬齡倾巾所已知，該麟子植人騎半導體·财之深度 至少部分為該些離子植入該層半導體材料雜寺所帶能量之一函數。—般 而3 ’以較減量植人之離子，其植人深度相對贱，以較高能量植入之 離子，其植入深度相對較深。 離子可以以-預定能量植入該層半導體材料聯該預定能量係為 了將該些料狀簡料體材料104Ί理想深度而敎。齡離子可 3 13 201239970 ^在該層半導體材料_黏附至該層電氣絕緣材料Κ)5及該基底106之 則植入該層半導體材料鮮。作為一特定的非限制性質範例該離子植 入平面m可以酉己置在該層半導體材料财内距離該層半導體材料财 之表面有—深紅處，赠騎相當私半導騎料Κ)4之平均厚度落在 大約_奈米（_nm)至大請奈米⑽⑽）之範_。如本發 明所屬技術領域情6知，無可避免地，至対_些軒可能會被植入非 所需之深度，且作為從該層半導體材料之表面（例如在黏附前）至該 層半導體材料辦内-深度之函數，離子濃度之圖表可能會顯示大致為鐘 形（對稱或不對稱）之-曲線，該曲線在理想之植入深度處具有—最大值。 將離子植人該料導断料鮮後，該麟子便可以在該層半導體 材料104内界定出-離子植入平面112 (在圖2 _以虛線呈現）。該離子 植入平面112可以包括該層半導體材料廣内之一層或一區域其與該層 半導體材料鮮内帶有最高離子濃度之平面對準（例如以其為中心圍 繞）。該離子植入平面112可以在該層半導體材料财内界定出一弱化區 域’在-後續製程中，該層半導體材料财可以沿著該弱化區域剝離或裂 開。例如，可以對該層半_材料1〇4，加熱，以造成該層半導體材料贈 …著《亥離子植入平面112剥離或裂開。在一些實施例中，於該剝離製程期 間’該層半導體材料104’之溫度可以維持在大約4〇〇〇c或更低，或甚至大 約350。(：或更低。但在其他實施例中，該剝離製程可以在更高溫度下進 仃。或者，可以對該層半導體材料1〇4，施加機械力，以造成或協助該層半 導體材料104’沿著該離子植入平面112剝離。 201239970 在額外之實施例中，該層相當薄之半導體材料1〇4可以經由將該層 相當厚之半導體材料104,（例如平均厚度大於约1〇〇微米之一層）黏附至 該層電氣絕緣材料1()5及該基底106，接著從與該基底伽相反之一側將 該層相當厚之半導體材料财薄化，而提供於該層電氣絕緣材料1〇5及該 基底106之上。例如，可以從該層相當厚之半導體材料1〇4,之一曝露主要 表面移除材料，以使該層相當厚之半導體材料1〇4，薄化。例如，可以利用 -化學製程（例如-濕式或乾式化學_製程）、_機械製程（例如一研 磨或紙磨製程），經由-化學機械研磨（CMp)製程，將材料從該層相 S厚之半導體材料104之該曝露主要表面移除。在—些實施例中，此等製 程可以在大約400〇C或更低’或甚至大約35(rc或更低之溫度下進行。但 在其他實施例_，此等製程可以在更高溫度下進行。 在另外的實施例中，該層相當薄之半導體材料1〇4可以及避形成於 該層電氣絕緣材料105之表面1〇7上。舉例而言，圖丨之底材1〇〇可以經 由在該層電氣絕緣材料1〇5之表面1〇7上沉積諸如矽、多晶矽或非晶質矽 之半導體材料至一理想厚度而形成。在一些實施例中，該沉積製程可以在 大約400°C或更低，或甚至大約350。(：或更低之溫度下進行。舉例而言， 如本發明所屬技術領域中所已知，用於形成該層相當薄之半導體材料1〇4 之一低溫沉積製程可以運用一電漿增強化學氣相沉積製程而實施。但在其 他實施例中，該沉積製程可以在更高溫度下進行。 在一些實施例中’圖1之底材100可以包括一相當小之晶粒等級構 造。在其他實施例中，該底材100可以包括一相對較大之晶圓，該晶圓之 平均直徑為大約100毫米或更大、大約300毫米或更大，或甚至大約400 201239970 笔米或更大。在此等實施例中，複數個已處理半導體構造⑼可以製作在 〇底材00之不同區域之中及之上，如圖3之簡化綱要性圖解所示。該些 已處理半導體構造丨20可以以㈣的序列或格網狀湖在該底材1〇〇上。 利用該底材100製作該些已處理半導體構造W之方法之範例，兹 參考圖4及5描述如下。 參考圖4複數個電晶體122可以形成於該層半導體材料之選 疋區域之+及之上，該些歡區域對應於有待形成已處理半導體構造12〇 (圖3)之區域。該些電晶體122綱要性地呈現於圖4中。如本發明所屬 技術領域中所已知，該些電晶體122中的每一個皆包括—源極區及一沒極 區，由一通道區分隔。該些源極、汲極與通道區域可以形成於該層半導體 材料104中。一閘極構造可以形成於該層半導體材料1〇4上，垂直位於該 源極區及該汲極區間之通道區上方。雖然為了簡化起見，只有三個電晶體 122顯示於圖4中，但實際上每個已處理半導體構造120可以包括數千個、 數百萬個，甚至更多的電晶體122。 參考圖5 ’ 一第一金屬化層124可以形成在該層半導體材料1〇4與 該層電氣絕緣材料105相反之一第一面上。該第一金屬化層124包含複數 個導電部件126。該些導電部件126可以包括垂直延伸之導電通孔、水平 延伸之導電跡線及導電接觸墊的其中一個或多個。該些導電部件126中至 少有一些可以與該些電晶體122之對應部件有電氣接觸，像是該些電晶體 122之源極區、汲極區及閘極構造。該些導電部件126可以形成自並包括 一金屬。該第一金屬化層124可以在一逐層（layer-by-layer)製程中形成， 在該製程中，多個金屬層及介電材料125層交替沉積並組成圖案，以形成 201239970 該些導電部件126，該些導電部件丨26可以嵌在一介電材料125内並由該 介電材料所圍繞。該些導電部件126可以用於佈線或重分配從該些電晶體 122之不同主動元件之位置至其他遠端位置之電氣路徑。因此，在一些實 施例中，該第一金屬化層124可以包括本發明所屬技術領域中所稱之重分 配層（RDL)。 在圖5之實施例中’該些導電部件丨26係形成於該第一金屬化層124 中，在該底材100中該些電晶體122已形成之區域上方，該些區域通常稱 為主動區域，但並未在該底材1〇〇中不含任何電晶體122之其他區域上 方，該些區域通常稱為非主動區域。 圖6A至6F呈現圖6F所示之一黏附半導體構造之製作，該黏附半 導體構造包括由該底材100之一部分所承載之兩個或更多已處理半導體構 造（例如半導體裝置）。此外，該底材100之該部分係用於使該些已處理 半導體構造的其中兩個或多個之間透過該底材1〇〇之該部分而有一直接、 連續之電氣路徑。 本發明之該些實施例之方法可以利用圖5之已處理半導體構造12〇。 接著參考圖6A，一載體底材140可以選擇性地暫時黏附至圖5之已 處理半導體構造中該第一金屬化層124之一曝露主要表面128。該載體底 材140可以用於在後續製程中方便處理設備處理該半導體構造。 將該載體底材140黏附至該第一金屬化層124後，便可以移除該底 材100之該基底106及該層電氣絕緣材料1〇5，以形成圖6B所示之構造。 該底材100之該基底106及該層電氣絕緣材料1〇5可以利用一化學製程(例 17 201239970 如一濕式或乾式化學_製程）、_機械餘（例如—研麵紙磨製程）， 或經由一化學機械研磨（CMP)製程加以移除。 移除該基底106及該層電氣絕緣材料1〇5後，便可以形成複數個晶 圓間透通連結130使之至辦分穿職層半導解料1()4、至少部分穿過 介電材料125，並位於該主動裝置區域中，以形成圖6C所示之構造。該 些晶圓間透通連結130可以經由先侧穿過該層半導體材料1〇4、至少部 分穿過介電機125，且位於該絲裝置賊之洞孔或通孔織以一種 或更多導電材料（例如銅或銅之—合金）填充該些洞孔或通孔而形成；或 疋經由本發明所屬技術躺巾已知之任何其他方法形心例如，該些晶圓 間透通連結130的其巾-個❹個可加以形成並使之完全穿過該第一金屬 化層124及該層半導體材料104而延伸至該載體底材14〇。在用於形成多 個洞孔或通孔之-侧製程中’該載體底材14〇可以作為侧阻擔層使 用，該些職^或通孔最終觀-贼更多導電㈣填充而形成該些晶圓間 透通連結130。應注意的是’在本發明之一些實施例中，該些導電部件I% 亦可以在祕形成該些洞孔或通孔之__侧雜巾充當網阻擅層。 該些晶圓間透通連結130的至少其中一些可以接觸該第一金屬化層 124之該些導電部件126，從而與該些電晶體122之—個或更多主動裝置 部件有電氣接觸。 作為非限制性質之範例，-種或更多遮罩及_製程可以用於形成 該些洞孔或通孔，而一種無電電鍍製程及一種電解電鍍製程的其中之一或 更多可以用於將導電材料填入該些洞孔或通孔。在―些實施例中，用於形 成該些晶關透通連結13G之每-製程，包括形成該些舰或通孔及將導The Handbook of 3D Integration, edited by Garrou et al. (Wiley-VCH Publishing, 2008). The three-dimensional spatial accumulation of the semiconductor structure can be achieved by attaching a semiconductor die to an additional one or more semiconductor dies (ie, die-to-die (D2D)), A semiconductor die attaches to one or more semiconductor wafers (ie, die-to-wafer (D2W)), and attaches a semiconductor wafer to an additional one or more semiconductor wafers (ie, wafer-to-wafer Round (W2W)). It is often the case that the individual semiconductor structures (e.g., dies or wafers) may be relatively thin' difficult to handle with devices that process semiconductor construction. Thus, so-called "carrier" dies or wafers can be attached to the actual semiconductor construction in which the active and passive components of the semiconductor device are operated. The carrier dies or wafers typically do not contain any active or passive components of the semiconductor device to be formed. Such carrier dies or wafers are referred to herein as "carrier substrates." The carrier substrates increase the overall thickness of the semiconductor structures and facilitate processing of the device. 3 201239970 The semiconductor structures (providing structural branches through thin semi-conducting) are processed. Saki is in the process of making the wire and exhausting the components of the semiconductor structure, including the active and material parts of the (four) body device. In this specification, 'the semiconductor constructions, which will eventually contain the filaments and/or lions of the semiconductor device to be fabricated thereon, or the semiconductor device to be fabricated on the wafer will eventually contain the active semiconductor device to be fabricated thereon. And/or passive components, referred to as "devices. Adhesion techniques for adhering a semiconductor structure to another semiconductor structure can be classified in different ways, by whether a layer of intermediate material is provided to the two semiconductor structures. The two are classified by sticking them together, and the second way is to classify whether the bonding interface allows electrons (ie, current) to pass through the interface. The so-called "direct adhesion method" refers to two semiconductor structures. A method of establishing direct solid-to-solid chemical bonding to bond them together without the need to use an intervening adhesive material to adhere them together. A direct metal-to-metal adhesion* has been developed to adhere the first-surface metal material to the second semiconductor structure-surface metal material. ^ Direct metal-to-metal adhesion methods can also be classified according to the temperature range at which each method operates. For example, some direct metal-to-metal squash is carried out at relatively high temperatures, thereby causing at least partial refining of the metallic material at the adhesion interface. Such direct adhesion processes may not be suitable for adhering processed semiconductor structures containing one or more device configurations, as the high temperature may have an adverse effect on the structure previously formed. The "thermocompression bonding" method is at a temperature between 2 (8) degrees Celsius (2 (8).c) and about Celsius (500.), usually between about 3 degrees Celsius (3 〇〇. 〇 and about A direct adhesion method of applying pressure between the adhesion surfaces of 400 degrees Celsius (400 Å.) 201239970 Additional direct adhesion methods have been developed, which can be 2 (10) degrees Celsius (2 〇〇. Performed at low temperatures. For such direct adhesion processes at temperatures of 2 〇〇〇 C (2 ° C) or lower, this specification is referred to as the "ultra-low temperature" direct adhesion method. The ultra-low temperature direct enthalpy method can The facets are removed from surface impurities and surface compounds (eg, native oxide layers) and by increasing the area of the two-surface contact on the atomic scale. The area of intimate contact between the two surfaces is typically achieved by: Grinding the surface to reduce the surface to near the atomic scale, applying pressure between the fine surfaces to cause mis-deformation, and grinding the surface to apply pressure to make such plastic deformation. Some ultra-low temperature direct _ methods can not apply pressure on the adhesion interface between the recording surfaces, but in other ultra-low temperature direct adhesion green, pressure can be applied at the adhesion interface between the adhesion surfaces to achieve the right at the _ interface _ _ degree. In the technical field to which the present invention pertains, the ultra-low temperature direct method of the field of force is generally referred to as the "surface assisted" or "lake" method. Therefore, in the present specification, "surface assist" "Adhesive" and "SAB" mean and include - at -2 ° C (2 ° C) or lower, the - - material close to - the second material, and adhered to the record Pressure is applied to the interface to direct the first view to any direct fine process of the second material. The carrier substrate is typically attached to the device substrate using an adhesive. A similar adhesion method can also be used to laminate the semiconductor structure to Another semiconductor construction, wherein each of the semiconductor structures comprises one or more filaments and/or passive components of the rotating device. The semiconductor crystal (4) has an electrical connection that does not allow electrical connections to other semiconductor structures to be connected. Matching - an interposer (ie, an additional configuration) can be placed between the two halves of the 201239970 conductor or between any semiconductor die and semiconductor package to rewire and align the appropriate electrical connections The interposer may have one or more conductive lines and through holes, and the lines and through holes are in contact with the semiconductor thief in the face. [Invention] Embodiments of the present invention can be formed into a whistle The method and the contact of two or more semiconducting n devices of the semiconductor substrate are carried out by the common substrate, and the electroacupuncture can be provided by the common substrates of the translating body to form two or more tissues of the rotating body. This summary is provided to introduce a series of concepts in a simplified form, which will be described in detail in the embodiments of the present invention. The summary of the present invention does not indicate the main features or basic features of the claimed subject matter. Nor is it used to limit the scope of the claimed patents. In the present invention, the invention includes a method of forming a semiconductor device. According to such methods, a substrate can be provided. The substrate comprises a layer of semiconductor material on a layer of electrically insulating material. On the first side of the semiconductor material opposite the layer of electrically insulating material, a first metallization layer containing a plurality of electrically conductive members may be formed on the substrate. A plurality of inter-wafer via connections are formed to pass at least partially through the substrate. The inter-wafers are connected to at least one of them - through the a-metallization layer and the occupational semiconductor (four) material. On the second side of the layer of semiconductor material opposite the first side of the layerless semiconductor material, a second metallization layer comprising a plurality of electrical portions may be alkalized to the substrate. Provided between the first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material, and the second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material (eg Forming) an electrical path through the first metallization layer, the substrate, and the second metallization layer. 201239970 In additional embodiments, the invention includes a semiconductor construction formed using the methods described herein. For example, in an additional embodiment, the present invention comprises a semiconductor device comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate, the first of the layers of semiconductor material And a second metallization layer on the substrate positioned on a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material. A plurality of intercrystalline circles are interconnected to at least partially pass through the first metallization layer and the layer of semiconductor material of the substrate. A first processed semiconductor structure can be carried by the substrate on a first side of the layer of semiconductor material, and a second processed semiconductor structure can also be carried by the substrate on a first side of the layer of semiconductor material. At least one electrical path may be from the first processed semiconductor structure, through one of the first metallization layer conductive members, the inter-wafer via connections, one of the first inter-wafer via connections, the second metal One of the conductive layers of the layer, and one of the inter-wafer via connections, the second inter-wafer via junction ' extends to the second processed semiconductor structure. The present invention is not intended to be an intent to describe any particular material, device, or system biting method, but merely to describe an idealized embodiment of the present invention. The use of any headings in this specification is not intended to limit the scope of the embodiments of the invention. The scope is defined by the following application and its legal equivalents. The concepts described under any particular heading usually apply to the rest of the specification. The present specification is hereby incorporated by reference in its entirety in its entirety in its entirety in the extent of the disclosure of the disclosure. In addition, the reference to the above-referenced patents No. 201239970, the entire disclosure of which is hereby incorporated by reference in its entirety in its entirety herein in its entirety in the entireties in In the present specification, the term "semiconductor device" means and includes any device containing one or more semiconductor materials, which can function as a device or system that is functionally integrated into an electronic or optoelectronic device. Item or multiple functions. The semiconductor device includes, but is not limited to, an electronic signal processor, a memory device (eg, a random access memory 'DRAM), a flash memory, etc.), an optoelectronic device (eg, a light emitting diode, A laser diode 'solar cell, etc.', and a device containing two or more such devices that are operatively coupled to each other. In the present specification, the term "semiconductor construction" means and includes a thief-shaped narration structure during the manufacture of a semiconductor device. The semiconductor construction includes, for example, a die and a wafer (for example, a county-supplied substrate), and a combination of two or more crystal grains and/or wafers or a composite structure of the accumulation. . The semiconductor construction also includes a fully assembled semiconductor device and an intermediate structure formed by the fabrication of the miscellaneous. In this specification, the term "processed semiconductor structure" means and includes at least the right of the right to make a profit. The treated material is constructed as a +conductor structure. In this specification, "adhesive semi-conducting _ or more _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the present specification t, "device configuration" - the term means and includes - any portion of a processed semiconductor structure that contains, or defines - at least - a portion of a wire or passive component of a semiconductor device, a conductor device The tree is formed on or in the unconstructed conductor structure. For example, the device configuration includes active and passive components of the integrated circuit, such as a transistor transducer, a valley resistor, a conductive line, a conductive via, and a conductive contact pad. In the present specification, the term "through-wafer through" or "predicate"-contact refers to any conductive via that passes through at least a portion of a first-semiconductor structure across the first semiconductor structure and the second semiconductor. An interface between the structures to provide a structural and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical field to which the present invention pertains, there is also a different name for the inter-wafer transmission connection, such as "石夕导孔孔(thr〇u细-(四)/底物(throughsubstratevias), ^TSV, , ^ a ®^L ( Through wafer vias) or "TWVj." is generally passed through the semiconductor structure in a direction substantially perpendicular to the substantially flat major surfaces of a semiconductor structure (ie, parallel to the % axis). The term 'active surface' is used in the context of a semiconductor structure to refer to and includes one of the processed semiconductor structures that exposes the major surface that has been treated or will be processed. 'In order to have one or more device configurations formed in and/or on the exposed major surface of the processed semiconductor structure. In the present disclosure, the metallization layer" refers to and includes a processed semiconductor. The layer of construction 'this layer contains the duck, the hole, the wheel, which is used for at least part of the current along the path of the money. 9 201239970 In this specification, the term "back surface J is used for And a processed semiconductor structure In the relevant case, it refers to and includes one of the treated semiconductor structures exposing the main surface, which is opposite to the active surface of the processed semiconductor structure. In the present specification, "three-five semiconductor materials" Words refer to and include most of the elements of the Periodic Table of the Elements (B, ai, &, ^ and yang and or more VA elements (N, p, As, % and Any of the materials of the present invention include methods and structures for forming a semiconductor structure, and more particularly, a method comprising a semiconductor body, a thin semiconductor structure, etc. The resulting inter-wafer via junction will pass through at least a portion of a semiconductor-on-insulator (SeOI) substrate, and the layer or layers of metallization will cover at least a portion of the eOI substrate. A semiconductor structure (eg, a semiconductor device) can be carried by the 5 substrate to the portion and the electrical path between the processed semiconductor structures (and, optionally, other structures or substrates), can be utilized Floor The conductive P-bovine and the circle are connected by a through-connection. The embodiments of the method and structure of the present invention can be used for different purposes, for example, for a three-dimensional spatial accumulation process and a three-dimensional spatial accumulation structure. The substrate may be a substrate used in the embodiment of the present invention. The substrate 1 includes a phase 4 semiconductor layer 1G4. In some embodiments, the semiconductor material 104 may be at least substantially a single crystal semiconductor material. 201239970 As an example of a non-limiting property, the layer of semiconductor material 104 may comprise a single crystal, a bismuth, or a tri-five semiconductor material, and may be doped or undoped. In some embodiments' The layer of semiconductor material 104 can comprise an epitaxial layer of one of the semiconductor materials. In some embodiments, the average thickness of the layer of semiconductor material 104 can be about i microns (1 μm) or less, about 500 nanometers (5 inches) or less, or even about nanometers (10 nm). Or thinner. Alternatively, the layer of semiconductor material can be disposed over and carried by a substrate 1〇6. As an example of non-limiting properties, the substrate 1 6 may include one or more dielectric materials such as an oxide (eg, yttrium oxide (Si〇2) or aluminum oxide (A丨2〇3)), one A nitride (for example, a nitride (Si3N4) or a nitride (10)) material. In an additional embodiment, the substrate ι 6 may comprise a conductor material such as any of those described above with respect to the semiconductor material (10). In some embodiments, the substrate 1 6 may also comprise a multilayer construction comprising one or two different materials. In some embodiments, the substrate 100 may comprise a substrate referred to in the art as a "Semiconductor-on-Second (SeOI)" type of art. For example, the substrate excitation may include one of the types referred to in the art of the present invention as "on insulator (10)". Here, a layer of electrically insulating material 丨〇5 may be disposed between the layer of semiconductor material and a substrate 106. The electrically insulating material 1〇5 may comprise a layer referred to as "embedded oxide (BOX)" in the technical field to which the present invention pertains. The electrically insulating material 1〇5 may comprise, for example, a ceramic material such as a nitride (e.g., a nitrogen cut or a -vete (e.g., cerium oxide (10) 2) or oxygen (s). In some embodiments, the average total thickness of the layer of electrical material 201239970 edge material 105 may be approximately! Micron (1) or thinner, about 3 nanometers (300 nm) or less, or even about 1 nanometer 〇〇 nm) or thinner. As an example of an unrestricted nature, the map! The substrate 1 shown can be formed using a process known as the SMART_CUTrM process in the art to which the present invention pertains. For example, as shown in Figure 2, a relatively thick layer of semiconductor material 104 can be adhered to the layer of electrical insulating material 1〇5-exposure main table fir 1G7 1 layer is quite thick half-turned The semiconductor material 1G4 may be formed from the semiconductor material 1G4 to be provided over the substrate 1G6, and the semiconductor material 104 may be formed from a relatively thick semiconductor material of the layer, and include a relatively thick semiconductor material 104'. Relatively thin one part. In some examples, an adhesive material (not shown) can be used to adhere the relatively thick semiconductor material 104' to the major surface 1'7 of the layer of electrically insulating material 1()5. Such an adhesive material may include, for example, one or more of oxidized stone, cerium nitride, and a mixture thereof. Such an adhesive material may be formed or otherwise provided to the layer of electrically insulating material 1 〇 5 and the layer of semiconductor material 104 which is relatively thick, one or both of the contiguous surfaces to enhance adhesion therebetween. In some embodiments, the layer of relatively thick semiconductor material 1 〇 4 can be adhered to the layer at a temperature of about 4 〇〇〇 c or less, or even at a temperature of about 350 ° C or lower. Electrical insulation material 105. However, in other embodiments the adhesion process can be carried out at higher temperatures. After adhering the relatively thick semiconductor material 104' to the layer of electrical insulating material 1〇5, the relatively thick semiconductor material 1〇4' can be thinned to form a relatively thin semiconductor layer in the pattern. 104. A portion of the relatively thick semiconductor material 1〇4' can be removed from the relatively thin semiconductor material 104, and the relatively thin semiconductor material 104 is left on the surface of the layer of electrically insulating material 105. 107 on. As an example of a non-limiting property, the SMART_CurrM process can be used to separate the layer of relatively thick semi-conductive material from the portion of the 11G phaseless semiconductor material (10) and the layer of electrically insulating material 105 and the substrate 1〇6. These processes are detailed in, for example, U.S. Patent No. 39,484 (issued on February 6th of the fine year ^Brud), U.S. Patent (four) tune (issued from Aspar et al.), U.S. Patent 6,335,258 (2) 〇〇 2 years ^ month 1 issued to ASpar et al.), US patent 6756286 (issued to Μ〇Γί_ et al. on June 29, 2), US patent _9, 〇 44 (2004) The full disclosure of these patents is hereby incorporated by reference in its entirety to the entire disclosure of the entire disclosure of the entire disclosure of the disclosure of the disclosure of the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the entire disclosure of simple. The plurality of ions (e.g., one or more of a hydrogen ion, a helium ion, or an inert gas ion) can be implanted along the ion implantation plane 112 to implant the layer of semiconductor material ι4. In the case of some implementations, the ions may be implanted in the semiconductor material before the semi-conductive material is applied to the layer of electrically insulating material 105 and the substrate 106. The ions can be implanted in a direction substantially perpendicular to one of the layers of semiconductor material. As is known in the age of the present invention, the depth of the lining of the lining of the semiconductor is at least partly a function of the energy carried by the ions implanted in the semiconductor material. In general, 3' implanted human ions with a reduced amount of implants with relatively deep implants, ions implanted at higher energies, and their implantation depth is relatively deep. The ions may implant the layer of semiconductor material at a predetermined energy in conjunction with the predetermined energy system to 将该 the desired material body material 104 to a desired depth. The aged ion can be 3 13 201239970 ^ in the layer of semiconductor material _ adhered to the layer of electrical insulating material Κ 5) and the substrate 106 is implanted into the layer of semiconductor material fresh. As a specific example of non-limiting properties, the ion implantation plane m can be placed in the semiconductor material of the layer. The surface of the semiconductor material has a deep red color, and the rider is quite a private semi-guided bicycle. The average thickness falls within the range of approximately _ nanometer (_nm) to large nanometer (10) (10). As is known in the art to which the present invention pertains, it is inevitable that 些 some may be implanted at an undesired depth and as a surface from the layer of semiconductor material (e.g., prior to adhesion) to the layer of semiconductor The material's internal-depth function, the chart of ion concentration may show a roughly bell-shaped (symmetric or asymmetrical)-curve with a maximum at the ideal implant depth. After the ions are implanted into the material, the lining can define an ion implantation plane 112 in the layer of semiconductor material 104 (shown in phantom in Figure 2). The ion implantation plane 112 can include a layer or region of the layer of semiconductor material that is aligned (e.g., centered about) with the plane of the layer of semiconductor material having the highest ion concentration. The ion implantation plane 112 can define a weakened region in the layer of semiconductor material. In the subsequent process, the layer of semiconductor material can be stripped or cracked along the weakened region. For example, the layer _ material 1 〇 4 may be heated to cause the layer of semiconductor material to be detached or delaminated. In some embodiments, the temperature of the layer of semiconductor material 104' during the stripping process can be maintained at about 4 〇〇〇 c or less, or even about 350. (: or lower. However, in other embodiments, the stripping process may be performed at a higher temperature. Alternatively, a mechanical force may be applied to the layer of semiconductor material 1 to 4 to cause or assist the layer of semiconductor material 104. 'Split along the ion implantation plane 112. 201239970 In an additional embodiment, the layer of relatively thin semiconductor material 1 〇 4 may pass through the layer of relatively thick semiconductor material 104 (eg, an average thickness greater than about 1 〇〇) One layer of micron) is adhered to the layer of electrical insulating material 1() 5 and the substrate 106, and then the semiconductor material of a relatively thick layer is thinned from one side opposite to the substrate gamma, and is provided to the layer of electrical insulating material. 1 〇 5 and above the substrate 106. For example, the primary surface removal material may be exposed from one of the relatively thick layers of semiconductor material 1 〇 4 to make the layer of relatively thick semiconductor material 1 〇 4 thin. For example, the material can be made from the layer S by a chemical process (eg, wet or dry chemistry process, _ mechanical process (eg, a grinding or paper milling process), via a chemical mechanical polishing (CMp) process. Semiconductor The exposure of the material 104 is primarily surface removed. In some embodiments, such processes can be performed at a temperature of about 400 〇 C or less, or even about 35 (rc or less), but in other embodiments _ These processes can be performed at higher temperatures. In other embodiments, the relatively thin layer of semiconductor material 1〇4 can be formed on the surface 1〇7 of the layer of electrically insulating material 105. For example, The substrate 1 〇〇 can be formed by depositing a semiconductor material such as tantalum, polysilicon or amorphous germanium on the surface 1〇7 of the layer of electrically insulating material 1〇5 to a desired thickness. In some embodiments The deposition process can be carried out at a temperature of about 400 ° C or less, or even about 350 ° (or lower). For example, as is known in the art to which the present invention pertains, the layer is formed. A relatively thin semiconductor material, a low temperature deposition process, can be implemented using a plasma enhanced chemical vapor deposition process, but in other embodiments, the deposition process can be performed at higher temperatures. In some embodiments 'The substrate of Figure 1 100 can include a relatively small grain grade configuration. In other embodiments, the substrate 100 can include a relatively large wafer having an average diameter of about 100 mm or greater, about 300 mm or Larger, or even about 400 201239970 pen meters or larger. In these embodiments, a plurality of processed semiconductor structures (9) can be fabricated in and on different regions of the 〇 substrate 00, as shown in the simplified outline of FIG. The processed semiconductor structure 20 may be in the sequence of (d) or a grid-like lake on the substrate. An example of a method for fabricating the processed semiconductor structures W using the substrate 100 is shown. Referring to Figures 4 and 5, the following description can be made with reference to Figures 4 and 5. A plurality of transistors 122 can be formed on and above the selected regions of the layer of semiconductor material corresponding to the semiconductor structure to be formed. 3) The area. The transistors 122 are outlined in Figure 4. As is known in the art, each of the transistors 122 includes a source region and a non-polar region separated by a channel region. The source, drain and channel regions may be formed in the layer of semiconductor material 104. A gate structure may be formed on the layer of semiconductor material 1〇4, vertically above the source region and the channel region of the drain region. Although only three transistors 122 are shown in FIG. 4 for simplicity, in practice each processed semiconductor structure 120 can include thousands, millions, or even more transistors 122. Referring to Fig. 5', a first metallization layer 124 may be formed on one of the first faces of the layer of semiconductor material 1〇4 opposite the layer of electrically insulating material 105. The first metallization layer 124 includes a plurality of conductive features 126. The conductive features 126 can include one or more of vertically extending conductive vias, horizontally extending conductive traces, and conductive contact pads. At least some of the conductive members 126 are in electrical contact with corresponding components of the transistors 122, such as the source regions, the drain regions, and the gate structures of the transistors 122. The electrically conductive members 126 can be formed from and include a metal. The first metallization layer 124 can be formed in a layer-by-layer process. In the process, a plurality of metal layers and a dielectric material 125 are alternately deposited and patterned to form 201239970. The component 126, the conductive features 26 can be embedded in and surrounded by a dielectric material 125. The electrically conductive members 126 can be used to route or redistribute electrical paths from the locations of the different active components of the transistors 122 to other remote locations. Thus, in some embodiments, the first metallization layer 124 can comprise a heavy distribution layer (RDL) as referred to in the art to which the present invention pertains. In the embodiment of FIG. 5, the conductive members 26 are formed in the first metallization layer 124. Above the regions where the transistors 122 have been formed in the substrate 100, the regions are generally referred to as active. The regions, but not the other regions of the substrate 1 that do not contain any of the transistors 122, are often referred to as inactive regions. Figures 6A through 6F illustrate the fabrication of one of the bonded semiconductor structures shown in Figure 6F, which includes two or more processed semiconductor structures (e.g., semiconductor devices) carried by a portion of the substrate 100. Moreover, the portion of the substrate 100 is used to provide a direct, continuous electrical path between two or more of the processed semiconductor structures through the portion of the substrate 1〇〇. The method of the embodiments of the present invention may utilize the processed semiconductor construction 12 of FIG. Referring next to Figure 6A, a carrier substrate 140 can be selectively temporarily adhered to the exposed semiconductor structure of Figure 5 in which one of the first metallization layers 124 exposes the major surface 128. The carrier substrate 140 can be used to facilitate handling of the semiconductor construction by a processing device in a subsequent process. After the carrier substrate 140 is adhered to the first metallization layer 124, the substrate 106 of the substrate 100 and the layer of electrically insulating material 1〇5 can be removed to form the configuration shown in FIG. 6B. The substrate 106 of the substrate 100 and the layer of electrical insulating material 1〇5 may utilize a chemical process (Example 17 201239970 such as a wet or dry chemical process), _ mechanical remainder (for example, a research paper grinding process), or It is removed via a chemical mechanical polishing (CMP) process. After removing the substrate 106 and the layer of electrical insulating material 1〇5, a plurality of inter-wafer through-connections 130 can be formed to make the through-layer semi-conductive material 1()4, at least partially pass through Electrical material 125 is located in the active device region to form the configuration shown in Figure 6C. The inter-wafer via junctions 130 may pass through the layer of semiconductor material 1〇4 via the front side, at least partially through the dielectric motor 125, and the holes or vias of the wire device are woven with one or more conductive layers. Materials (such as copper or copper-alloy) are formed by filling the holes or through holes; or by any other method known in the art to which the present invention pertains, for example, the inter-wafer-through connection 130 Towels can be formed and extend completely through the first metallization layer 124 and the layer of semiconductor material 104 to the carrier substrate 14A. In the side process for forming a plurality of holes or through holes, the carrier substrate 14 can be used as a side resist layer, and the holes or the through holes finally form a conductive (four) filling to form the The inter-wafer is transparently connected 130. It should be noted that in some embodiments of the present invention, the conductive members 1% may also serve as mesh barriers in the side of the holes or through holes. At least some of the inter-wafer via bonds 130 may contact the conductive features 126 of the first metallization layer 124 to make electrical contact with one or more active device components of the transistors 122. As an example of non-limiting properties, one or more masks and processes may be used to form the holes or vias, and one or more of an electroless plating process and an electrolytic plating process may be used for A conductive material fills the holes or through holes. In some embodiments, each of the processes for forming the pass-through connections 13G includes forming the ships or vias and guiding

S 201239970 電材料填入该些洞孔或通孔，均可以在大約4〇〇(>c或更低，或甚至35〇〇c 或更低之溫度Tit行。但在其他實關巾，此等製程可以在以溫度下進 灯。例如，«些實酬巾’當銅可以在用卿絲些晶關透通連結之 後段（back-endofline，BEOL)製程中使用時，其溫度不可超過大約4〇〇〇c， 另一種情況為，在某些實施例中，當鋁可以在用於形成該些晶圓間透通連 結之BE0L製程中使用時，其溫度可以超過大約4〇〇〇c。 參考圖6D，在移除該基底106及該層電氣絕緣材料1〇5，並界定出 該些洞孔或通扎後，-第二金屬化層154便可以形成於該層半導體材料 04之第一面，6玄第一面為其上已有該第一金屬化層124形成之該層半 導體材料104之第一面之相反面。相對於圖6入至6(：之角度，圖6D之角 度是倒轉的，因為該構造可能會被倒轉，以利該第二金屬化層154形成於 該層半導體材料104之第二面。 β玄第一金屬化層154與該第一金屬化層124類似，亦包含複數個導 電部件156。該些導電部件156可以包括垂直延伸之導電通孔、水平延伸 之導電跡線及導電接觸墊的其中一個或多個。該些導電部件I%中至少有 些可以與§玄些晶圓間透通連結130有電氣接觸，從而與該第一金屬化層 124之導電部件126及該些電晶體122之主動區域，像是源極區、汲極區 及閘極構造’亦有電氣接觸。該些導電部件156可以形成自並包括一金屬。 如同該第一金屬化層124’該第二金屬化層154可以在一逐層製程中形 成，例如藉由眾所周知的鑲嵌犁程，在該製程中，多個金屬層及介電材料 層父替沉積並纟且成圖案，以形成該些導電部件156，該些導電部件I%可 以嵌在一介電材料内並由該介電材料所圍繞。該些導電部件156可以用於S 201239970 Electrical materials filled into the holes or through holes, can be Tit at about 4 〇〇 (> c or lower, or even 35 〇〇 c or lower). But in other real tights, These processes can be used to enter the lamp at a temperature. For example, when the copper can be used in a back-end of line (BEOL) process, the temperature must not exceed Approximately 4 〇〇〇c, in another case, in some embodiments, when aluminum can be used in the BEOL process for forming the inter-wafer via connections, the temperature can exceed about 4 〇〇〇. c. Referring to FIG. 6D, after the substrate 106 and the layer of electrical insulating material 1〇5 are removed and the holes or openings are defined, a second metallization layer 154 may be formed on the layer of semiconductor material 04. On the first side, the first side of the sixth side is opposite to the first side of the layer of semiconductor material 104 formed by the first metallization layer 124. The angle is shown in FIG. 6 to 6 (: angle The angle of 6D is reversed because the configuration may be reversed to facilitate formation of the second metallization layer 154 in the layer half. The second side of the body material 104. The β-first metallization layer 154 is similar to the first metallization layer 124 and also includes a plurality of conductive members 156. The conductive members 156 may include vertically extending conductive vias and horizontal extensions. One or more of the conductive traces and the conductive contact pads. At least some of the conductive features I% may be in electrical contact with the inter-wafer via junction 130, and thus the first metallization layer 124 The conductive member 126 and the active regions of the transistors 122, such as the source region, the drain region and the gate structure, also have electrical contact. The conductive members 156 may be formed and include a metal. Like the first metal The second metallization layer 154 may be formed in a layer-by-layer process, for example, by a well-known inlay plowing process in which a plurality of metal layers and dielectric material layers are deposited and formed. Patterning to form the conductive members 156, the conductive members 1% can be embedded in and surrounded by a dielectric material. The conductive members 156 can be used for

S 19 201239970 佈線或重分配從該些晶圓間透通連結130露出之位置穿過該層半導體材料 1〇4之第二面至其他遠端位置之魏路徑。因此，在—些實施例中，該第 -金屬化層154可以包括树騎似術領域愤稱之重分配層⑽ 此外，如圖6D所示，該第二金屬化層】54之該些導電部件i56之 其中一些可以透職第二金屬化層154，在該些晶關透通連結I%曝露 於"玄層半導體材料HM之第二面的其_兩個或更多端面間，提供直接、連 續之一電氣連接。 圖6E呈現該半導體構造再次被倒轉，以使該第二金屬化層154位於 該半導體構造之底部（從圖6D之角度而言）。形成該第二金屬化層154 之該些導電部件156後，便可以將該第一金屬化層124中多個部分之介電 材料⑵移除。該第一金屬化層以中有待移除之區域可以包括在該些非 主動區域巾之介電材料125，脚在沒有主練置之該些區域中之介電材 料125。該介電材料125可以經由諸如乾式侧（例如反麟子钱刻）或 濕式姓刻之-姓刻製程加以移除。為了移除該已處理半導體構造之非主動 區域中之’丨電材料125 ’可以將圖6D所示之該已處理構造從該載體底材 140 >刀離’並使之附著至額外之一載體（未顯示）。該額外健可以附著 至邊第—金屬化層。在該介電材料125從該已處理半導體構造之該些 非主動區域移除後n金屬化廣154之該些通孔⑼'便會露出，如圖 6E所呈現。 將。P刀之"電材料125移除並露出通孔156'後，便可以將圖犯之 已處理半導體構造切割為晶粒。此外，該晶粒可以為經過電氣測試並利用 凸塊技術钱在_封魏上之已純品（KGD)。接著抑朗微凸塊S 19 201239970 Wiring or redistribution passes from the second side of the layer of semiconductor material 1〇4 to the other remote location. Therefore, in some embodiments, the first metallization layer 154 may include a redistribution layer (10) in the field of tree riding. In addition, as shown in FIG. 6D, the second metallization layer 54 is electrically conductive. Some of the components i56 may pass through the second metallization layer 154, and provide between the two or more end faces of the second side of the thin layer semiconductor material HM. Direct, continuous electrical connection. Figure 6E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of Figure 6D). After the conductive features 156 of the second metallization layer 154 are formed, portions of the dielectric material (2) in the first metallization layer 124 can be removed. The area of the first metallization layer to be removed may include dielectric material 125 in the non-active area, and the dielectric material 125 in the areas where the feet are not disposed. The dielectric material 125 can be removed via a process such as a dry side (e.g., a reverse slap money) or a wet type singularity. In order to remove the 'tantalum material 125' in the inactive region of the processed semiconductor construction, the processed structure shown in FIG. 6D can be removed from the carrier substrate 140 > and attached to one of the additional ones. Carrier (not shown). This extra bond can be attached to the edge-metallization layer. The vias (9)' of the n-metallization 154 are exposed after the dielectric material 125 is removed from the inactive regions of the processed semiconductor structure, as shown in Figure 6E. will. After the P-knives " electrical material 125 is removed and the vias 156' are exposed, the processed semiconductor structures that have been fabricated can be cut into dies. In addition, the die can be electrically tested and utilizes bump technology to clean the product (KGD). Then suppress the microbumps

S 20 201239970 (miCr〇-bump)技術將額外之晶粒（糊_或不同之魏性或使用類似 或不同之技術製作）堆疊在圖6E之中介層頂部，在該些主動裝置（亦即 主動區域）及非主動裝置（亦即非主動區域）上方。 應注意的是’本發明之實施例所採用之一絕緣體上石夕（s〇I)中介層， 有助於以具有成本•式提供匹配該中介層及裝置封裝體間之電氣 佈線普遍所需之扇出（或重分g&)層。而縮小封裝佈線以匹配裝置佈線之 常見做法則會大幅增加該裝置封裝體之成本。此外，該s〇I中介層提供了 非主動區域’該些區域可以雜賴似或關技術製作之其他晶粒（或其 他晶粒堆疊）堆疊並使其透過相同之電氣佈線連結至該封裝體。 因此，詳言之，在該處理過程之此一階段，一個或更多已處理半導 體構造120已縻％形成於該底材1〇〇之該層半導體材料1〇4 (亦即該底材 100之餘留部分）之上及之中，如圖6E所呈現。此等已處理半導體構造 120係由該層半導體材料104所承載。該一個或更多已處理半導體構造12〇 可以包括’舉例而言，電子信號處理器、電子記憶裝置，及/或光電裝置（例 如發光二極體、雷射二極體、太陽能電池等等）。 參考圖6F，額外之一個或更多已處理半導體構造，像是該已處理半 導體構造160A及該已處理半導體構造16〇B，可以於該層半導體材料1〇4 之第一面，在構造上及電氣上耦合至晶圓間透通連結13()之該些曝露端面 及該些通孔156'，以形成圖6F所示之黏附半導體構造。額外之該些已處 理半導體構造160A ' 160B可以與及祕形成於該層半導體材料1〇4之上及 之中之已處理半導體構造12〇由該層半導體材料1〇4之一共同面所承載。S 20 201239970 (miCr〇-bump) technology stacks additional dies (either paste or different singularity or using similar or different techniques) on top of the interposer of Figure 6E, in which the active devices (ie active Above the area) and the non-active device (ie the inactive area). It should be noted that one of the insulator-on-insulator layers used in the embodiments of the present invention helps to provide a common cost-matching electrical wiring between the interposer and the device package. Fan out (or re-divide g&) layers. The common practice of reducing package routing to match device wiring can significantly increase the cost of the device package. In addition, the sII interposer provides inactive regions that can be stacked with other dies (or other die stacks) that are fabricated or fabricated into technology and bonded to the package through the same electrical wiring. . Thus, in detail, at this stage of the process, one or more processed semiconductor structures 120 have been formed in the layer of semiconductor material 1〇4 of the substrate 1 (ie, the substrate 100) Above and in the remaining part, as shown in Figure 6E. These processed semiconductor structures 120 are carried by the layer of semiconductor material 104. The one or more processed semiconductor structures 12A may include, by way of example, an electronic signal processor, an electronic memory device, and/or an optoelectronic device (eg, a light emitting diode, a laser diode, a solar cell, etc.) . Referring to FIG. 6F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A and the processed semiconductor structure 16A, may be on the first side of the layer of semiconductor material 1〇4, in construction And the exposed end faces and the vias 156' electrically coupled to the inter-wafer via junction 13() to form the bonded semiconductor structure shown in FIG. 6F. The additional processed semiconductor structures 160A' 160B may be bonded to the processed semiconductor structure 12 formed on and in the layer of semiconductor material 1 〇 4 and carried by one of the layers of semiconductor material 1 〇 4 .

S 21 201239970 每個額外之已處理半導體構造160A、160B皆可包括一半導體裝置， 像疋一電子彳§號處理器、一電子記憶裝置，及/或一光電裝置（例如一發光 二極體、一雷射二極體、一太陽能電池等等）^作為非限制性質之一範例， #猶成之已處理半導體構造12〇可吨括—電子信號處理n裝置，而每 個額外之已處理半導體構造160A、160B皆可包括一電子記憶裝置、一發 光二極體、一雷射二極體，及一太陽能電池至少其中之一。 在一些實施例中，額外之該些已處理半導體構造16〇A、16〇B之導 電部件’像是導電墊’可以利用諸如導電焊接微凸塊或微球162，在構造 上及電氣上耦合至個別之晶圓間透通連結13〇及通孔156，如本發明所屬 技術領域中所已知。此外，額外之該些已處理半導體構造16〇A及16〇b 可包括以如前述之本發明之方法所製作之中介層及電氣佈線構造。 經由使額外之該些已處理半導體構造160A、16〇B在電氣上輕合至 該些晶圓間透通連結130及通孔156'，一個或更多電氣路徑便可以提供於 該已處理半導體構造120與每個額外之已處理半導體構造16〇A、16〇b之 間，該些電氣路徑連續穿過該第一金屬化層124、該底材1〇〇之餘留部分 (亦即經由該些晶圓間透通連結130及通孔156'穿過該層半導體材料 1〇4)，及该第二金屬化層154。此等電氣路徑可以用於在該些已處理半導 體構造120 ' 160A、160B之間傳遞電子信號及/或電力。因此，該些已處 理半導體構造120、160A、160B可加以設計及組構使之如單一半導體封 裝裝置般一起操作。 同樣如圖6F所示’該第二金屬化層154之導電部件⑼可以在構造 上及電氣上耦合至另一較高等級構造，像是另一底材17〇，之導電部件。S 21 201239970 Each additional processed semiconductor structure 160A, 160B can include a semiconductor device, such as an electronic device, an electronic memory device, and/or an optoelectronic device (eg, a light emitting diode, A laser diode, a solar cell, etc.) as an example of a non-limiting property, #犹成的处理半导体结构12〇可括-electronic signal processing n device, and each additional processed semiconductor Each of the structures 160A, 160B can include an electronic memory device, a light emitting diode, a laser diode, and at least one of a solar cell. In some embodiments, additional conductive features such as conductive pads of the processed semiconductor structures 16A, 16B may be structurally and electrically coupled using, for example, conductive solder microbumps or microspheres 162. The individual inter-wafer via connections 13 and vias 156 are known in the art to which the present invention pertains. In addition, the additional processed semiconductor structures 16A and 16B may include interposers and electrical wiring structures fabricated by the method of the present invention as described above. One or more electrical paths may be provided to the processed semiconductor by electrically attaching the additional processed semiconductor structures 160A, 16B to the inter-wafer via junctions 130 and vias 156'. Between the structure 120 and each of the additional processed semiconductor structures 16A, 16B, the electrical paths continue through the first metallization layer 124, the remaining portion of the substrate 1 (ie, via The inter-wafer via junctions 130 and vias 156 ′ pass through the layer of semiconductor material 1 4 ) and the second metallization layer 154 . These electrical paths can be used to transfer electronic signals and/or power between the processed semiconductor structures 120' 160A, 160B. Thus, the processed semiconductor structures 120, 160A, 160B can be designed and organized to operate as a single semiconductor package. Also as shown in Fig. 6F, the conductive member (9) of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration, such as another substrate, a conductive member.

S 22 201239970 該底材no可以包括，舉例*言，一有機印刷電路板亦可以包括—封裝 等級底材。該第一金屬化層之該些導電部件Ms可以利用諸如導電焊 接凸塊或焊接球172，在構造上及魏均合至該底材17()之導電部件， 如本發明所屬技術領域巾所已知。電氣路徑亦可以經由該第—金屬化層 124、該些晶關透通連結13G、該第二金屬化層154至該額外底材17〇 之導電部件’而提供_些已處理半導體構造12Q、藤、麵之間， 此等額外之電氣路徑亦可以用於在該些已處理半導體構造之間傳遞電力 及/或電子信號。 圖7A至7F與圖6A至6F類似，係用於呈現本發明之方法之額外實 _該一方法可以用於形成一黏附半導體構造，該黏附半導體構造包含 由圖5之構造所承載之兩個或更多已處理半導體構造。但在圖7A至π 之實施例中，該底材100之該層電氣絕緣材料105並未如圖6A至6F之實 施例般在麵雜巾被鎌。圖7A至7F之方法之触大絲言與上文有 關圖6A至证所述者相同，因此前文已述及之細節不再於下文重複。 本發明之額外實_之方法可以再次使用如圖Μ所呈現之一已處 理半導體構造120。 如圖7B所示’一載體底材14〇可以選擇性地暫時黏附至該第一金 屬化層m之-曝露主要表面128。將該載體底材⑽黏附至該第一金屬 化層124後，該底材〗⑻之基底1〇6便可以從該構造移除，留下該層半導 體材義及該層電氣絕緣材細。複數個晶_通連結耐以形 成並使之穿過該第-金屬化層m、該層半導體材_及該層電氣絕緣 材料’卿成圖7C所示之構造4此等方法中，該載體底材， 3 23 201239970 以在用於开峨多個洞孔《通孔之一姓刻t程中作為侧阻擋vf使用，該些 洞孔或通孔最終將以—種或更多導電材料填充以形成該些晶圓間透通連 結 130 〇 參考圖7D，一第二金屬化層154可以形成於該層半導體材料1〇4之 第面上方’該第二面為其上已有該第一金屬化層124形成之該層半導體 材料104之第一面之相反面。換言之，該第二金屬化層154可以形成於該 層電氣絕緣材料105之上。相對於圖7A至7C之角度，圖7D之角度是倒 轉的，因為該構造可能會被倒轉，以利該第二金屬化層154之形成。該第 金屬化層154與該第-金屬化層I〗4類似，亦包含複數個導電部件156, 如本說明書所述。 圖7E呈現該半導體構造再次被倒轉，以使該第二金屬化層丨54位於 該半導體構造之底部（從圖7D之角度而言）。如圖7E所示，該第一金 屬化層124之多個部分及該載體底材14〇可予以移除。例如，該第一金屬 化層124覆蓋住該層半導體材料1〇4但不包含任何電晶體122 #區域可予 以移除，亦即將介電材料125從該已處理半導體構造之非主動區域移除。 該介電材料125可以經由諸如乾式餘刻（例如反應離子侧）或濕式侧 之-侧製程純移除。為了移除該已處理半導體構造之非主動區域中之 介電材料125，可以將圖7D所示之該已處理構造從該載體底材14〇分離， 並使之附著至額狀-麵（未顯示）。鞠外載體可_著至該第二金 屬化層154。在該介電材料125從該已處理半導體構造之該些非主動區域 移除後’該第二金屬化層154之通孔156'便會露出，如圖疋所呈現。S 22 201239970 The substrate no may include, for example, an organic printed circuit board may also include a package grade substrate. The conductive members Ms of the first metallization layer may utilize conductive members such as conductive solder bumps or solder balls 172, which are structurally and uniformly bonded to the substrate 17 (), as known in the art to which the present invention pertains. . The electrical path may also provide some processed semiconductor structures 12Q via the first metallization layer 124, the crystal clear via bonds 13G, the second metallization layer 154 to the conductive features of the additional substrate 17〇, Between the vines and the faces, such additional electrical paths can also be used to transfer electrical and/or electronic signals between the processed semiconductor structures. Figures 7A through 7F are similar to Figures 6A through 6F and are used to present additional methods of the present invention. The method can be used to form an adherent semiconductor construction comprising two of the structures carried by the configuration of Figure 5. Or more processed semiconductor constructions. However, in the embodiment of Figures 7A through π, the layer of electrically insulating material 105 of the substrate 100 is not collapsed in the face as in the embodiment of Figures 6A through 6F. The touch of the method of Figures 7A through 7F is the same as that described above with respect to Figure 6A, so that the details already described above are not repeated below. The additional method of the present invention can again be used to process the semiconductor structure 120 as shown in FIG. As shown in Fig. 7B, a carrier substrate 14A can be selectively temporarily adhered to the exposed main surface 128 of the first metallization layer m. After the carrier substrate (10) is adhered to the first metallization layer 124, the substrate 1〇6 of the substrate (8) can be removed from the structure, leaving the layer of semiconductor material and the layer of electrical insulation material thin. a plurality of crystal-to-pass bonds are formed to pass through the first metallization layer m, the layer of semiconductor material, and the layer of electrical insulating material 'the structure 4 shown in FIG. 7C, the carrier Substrate, 3 23 201239970 to be used as a side barrier vf in the opening of a plurality of holes, one of the through holes, which will eventually be filled with one or more conductive materials To form the inter-wafer via junctions 130, referring to FIG. 7D, a second metallization layer 154 may be formed over the first surface of the layer of semiconductor material 1-4. The metallization layer 124 forms the opposite side of the first side of the layer of semiconductor material 104. In other words, the second metallization layer 154 can be formed over the layer of electrically insulating material 105. The angle of Fig. 7D is reversed relative to the angles of Figs. 7A through 7C because the configuration may be reversed to facilitate the formation of the second metallization layer 154. The first metallization layer 154 is similar to the first metallization layer I4 and also includes a plurality of conductive features 156, as described herein. Figure 7E shows that the semiconductor construction is again inverted such that the second metallization layer 54 is at the bottom of the semiconductor construction (from the perspective of Figure 7D). As shown in Figure 7E, portions of the first metallization layer 124 and the carrier substrate 14" can be removed. For example, the first metallization layer 124 covers the layer of semiconductor material 1〇4 but does not include any transistor 122. The region can be removed, that is, the dielectric material 125 is removed from the inactive region of the processed semiconductor structure. . The dielectric material 125 can be removed purely via a side process such as a dry residue (e.g., reactive ion side) or a wet side. To remove the dielectric material 125 in the inactive region of the processed semiconductor structure, the processed structure shown in FIG. 7D can be separated from the carrier substrate 14 and attached to the frontal-surface (not display). The outer support can be directed to the second metallization layer 154. The via 156' of the second metallization layer 154 is exposed after the dielectric material 125 is removed from the inactive regions of the processed semiconductor structure, as shown in FIG.

S 24 201239970 在該處理過程之此一階段，一個或更多已處理半導體構造12〇已及 政形成於該底材100餘留部分之該層半導體材料104之上及之中。圖7E 之已處理半導體構造可加以切割為晶粒（且該載體可予以移除）。此外， 該晶粒可以為經過電氣測試並利用凸塊技術安裝在一封裝體上之已知良 品（KGD)。接著’可以使用微凸塊技術將額外之晶粒（利用類似或不同 之功能性或使用類似或不同之技術製作）堆疊在圖7E之中介層頂部，在 D玄些主動裝置（亦即主動區域）及非主動裝置（亦即非主動區域）上方。 參考圖7F，額外之一個或更多已處理半導體構造，像是該已處理半 導體構造160A及該已處理半導體構造16〇B，可以於該層半導體材料1〇4 之第一面，在構造上及電氣上耦合至晶圓間透通連結13〇之該些曝露端面 及该些通孔156'，以形成圖7F所示之黏附半導體構造。 由使額外之3玄些已處理半導體構造16〇a、i6〇B在電氣上耗合至 該些晶圓間透通連結13G及通孔156'，—個或更多電氣路徑便可以提供於 该已處理轉ft構造12〇與每麵狀已處理半導麵造16QA、麵之 間’趟電氣路徑連續穿過該第一金屬化層124、該底材100之餘留部分 (亦即經由該些晶圓間透通連結13Q及通孔156穿過該層半導體材料 及該層電氣絕緣材料105)，及該第二金屬化層154。此等電氣路徑可以 用於在δ亥些已處理半導體構造120、160A、160B之間傳遞電力及/或電子 信號。 同樣如圖7F所示，該第二金屬化層154之導電部件156可以在構造 上及電氣上耗合至另—較高等級構造，像是另—底材Μ，之導電部件。 電氣路匕亦可以經由該第一金屬化層124、該些晶圓間透通連結⑽、該 25 201239970 第二金屬化層154至該額外底材丨70之導電部件’而提供於該些已處理半 導體構造120、160A、160B之間，此等額外之電氣路徑亦可以用於在該 些已處理半導體構造之間傳遞電力及/或電子信號。 在本發明之方法之更多其他實施例中，該第一金屬化層124可以在 非對應於有#原地形成已處理半導體構造之區域中包含額外之導電部件 126，而該第一金屬化層之此等區域不必在處理過程中予以移除。 舉例而言，® 8與圖5類似，其呈現一第一金屬化層124,，該金屬 化層可以形成在該層半導體材料1〇4與該層電氣絕緣材料1〇5相反之一第 一面上。在圖8之實施例中’多個導電部件126形成於該第一金屬化層124, 中，在s玄底材100中電晶體122已形成之區域上方，而額外之導電部件126 則形成於該底材100中不包含任何電晶體122之其他區域上方。 圖9A至9F呈現形成一黏附半導體之方法，該些方法如同前文參考 圖6A至6F所述者’但係使用圖8所示含有該第一金屬化層124,之構造， 而非圖5所示之構造。圖9A至9F之方法之製程大致而言與上文有關圖 6A至6F所敘述者相同，因此前文已述及之細節不再於下文重複。 參考圖9A，複數個晶圓間透通連結130可以形成並使之穿過該第一 金屬化層124'及該層半導體材料1〇4而延伸至該層電氣絕緣材料1〇5。在 此等方法中，該層電氣絕緣材料1〇5可以在用於形成多個洞孔或通孔之一 蝕刻製程中作為蝕刻阻擋層使用，該些洞孔或通孔最終將以一種或更多導 電材料填充以形成該些晶圓間透通連結130。 如圖9B所示’形成穿過該第一金屬化層124,及該層半導體材料1〇4 之該些晶圓間透通連結13〇後，一載體底材14〇可以選擇性地暫時黏附至S 24 201239970 At this stage of the process, one or more processed semiconductor structures 12 are formed over and in the layer of semiconductor material 104 remaining in the remainder of the substrate 100. The processed semiconductor construction of Figure 7E can be diced into dies (and the carrier can be removed). In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Then, you can use the microbump technology to stack additional dies (made with similar or different functionalities or using similar or different techniques) on top of the interposer of Figure 7E, in the D-active device (ie active area) ) and above the non-active device (ie, the inactive area). Referring to FIG. 7F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A and the processed semiconductor structure 16A, may be on the first side of the layer of semiconductor material 1〇4, in construction. And the exposed end faces and the vias 156' electrically coupled to the inter-wafer via junctions 13B to form the bonded semiconductor structure shown in FIG. 7F. By electrically consuming the additional three processed semiconductor structures 16A, i6〇B to the inter-wafer via junctions 13G and vias 156', one or more electrical paths may be provided. The treated ft structure 12〇 and each of the processed semi-conducting surfaces are 16QA, and the 'an electrical path continuously passes through the first metallization layer 124 and the remaining portion of the substrate 100 (ie, via The inter-wafer via junctions 13Q and vias 156 pass through the layer of semiconductor material and the layer of electrically insulating material 105), and the second metallization layer 154. These electrical paths can be used to transfer power and/or electronic signals between the processed semiconductor structures 120, 160A, 160B. As also shown in Figure 7F, the conductive features 156 of the second metallization layer 154 can be structurally and electrically constrained to another, higher grade construction, such as another substrate, a conductive component. The electrical circuit can also be provided through the first metallization layer 124, the inter-wafer transparent connection (10), the 25 201239970 second metallization layer 154 to the conductive member of the additional substrate 丨 70 Between the semiconductor structures 120, 160A, 160B, these additional electrical paths can also be used to transfer power and/or electronic signals between the processed semiconductor structures. In still other embodiments of the method of the present invention, the first metallization layer 124 may include additional conductive features 126 in regions that do not correspond to the in situ formation of the processed semiconductor structure, and the first metallization These areas of the layer do not have to be removed during processing. For example, the ® 8 is similar to FIG. 5 and presents a first metallization layer 124, which may be formed on the layer of semiconductor material 1〇4 opposite to the layer of electrical insulating material 1〇5. On the surface. In the embodiment of FIG. 8, a plurality of conductive features 126 are formed in the first metallization layer 124, above the region where the transistor 122 has been formed in the smectic substrate 100, and additional conductive features 126 are formed in The substrate 100 does not contain any other areas of the transistor 122 above it. 9A through 9F illustrate a method of forming an adhesion semiconductor, which is as described above with reference to FIGS. 6A through 6F', but using the configuration of the first metallization layer 124 shown in FIG. 8, instead of FIG. The structure of the display. The process of the method of Figures 9A through 9F is generally the same as that described above with respect to Figures 6A through 6F, and thus the details already described above are not repeated below. Referring to FIG. 9A, a plurality of inter-wafer via junctions 130 may be formed and extend through the first metallization layer 124' and the layer of semiconductor material 1〇4 to the layer of electrically insulating material 1〇5. In such methods, the layer of electrically insulating material 1〇5 can be used as an etch stop in an etching process for forming a plurality of holes or vias, which will eventually be one or more A plurality of electrically conductive materials are filled to form the inter-wafer via junctions 130. As shown in FIG. 9B, after the first metallization layer 124 is formed, and the inter-wafer is transparently connected to the semiconductor material 1〇4, a carrier substrate 14〇 can be selectively temporarily adhered. to

S 26 201239970 該第一金屬化層124,之一曝露主要表面128。將該載體底材140黏附至該 第一金屬化層124’後，該底材1〇〇之基底106及該層電氣絕緣材料1〇5便 可以從該般鎌，訂該層半導鼎料104崎細9C鮮之構造。 應注意的是，圖9C所呈烬之半導體構造亦可以以另一種方法加以 製作：將圓8之半導體構造安裝在一載體底材上，並透過研磨及磨光其中 之種或夕種，將該層半導體材料1〇4及該層電氣絕緣材料1〇5移除。後 續製程可以界定出穿過半導體層1(M並伸進該第—金屬化層124、之該些晶 圓間透通連結13〇。 參考圖9D, —第二金屬化層154可以形成於該層半導體材料1〇4之 第一面，該第二面為其上已有該第一金屬化層124，形成之該層半導體材 料104之第一面之相反面。相對於圖9a至9C之角度，圖9d之角度是倒 轉的’因為該構造可能會被娜，以利該第二金屬化層154之形成。該第 一金屬化層154與該第一金屬化層124,類似，亦包含複數個導電部件156, 如前文所述。 圖9E呈現該半導體構造再次被倒轉，以使該第二金屬化層154位於 "亥半導體構造之底部（從圖9E之角度而言）。如g 9E所示，該載體底材 140可予以移除。惟該第一金屬化層124，覆蓋住該層半導體材料⑴*但不 包含任何電晶體122的區域可以不必如騎述之實蘭般予以移除。在該 處理過程之此-隨，-贼更乡已處理轉雜造12G e^猶成於該 底材100餘留部分之該層半導體材料104之上及之中。 在該處理過程之此-階段，圖犯之已倾半導體構造可加以切割為 晶粒（且該載體可予以移除）。此外，該晶粒可以為經過電氣測試並利用 ff3- 27 201239970 凸塊技術安裝在-封裝體上之已知良品（KGD)。接著，可以使用微凸塊 技術將額外之BaB粒（糊齡或不肖之功紐或棚触或不狀技術製 作）堆疊在圖9E之中介層頂部，在該些主動裝置（亦即主動區域）及非 主動裝置（亦即非主動區域）上方。 因此’詳言之’參考圖9F，額外之一個或更多已處理半導體構造， 像是該已處理半導體構造祖、該已處理半導體構造腦，及一已處理 半導體構造160C，可以在構造上及電氣上於該第一金屬化層124,之該曝 露主要表面耗合至晶圓間透通連結13〇之該些曝露端面，以形成圖卯所 示之黏附半導體構造，外之已處理半導體構造觀可以包括前述與額 外之该些已處理半導體構造隐及娜有關之任何類型之已處理半導 體構造。以此方式組構後，電氣路徑便可以透過該第一金屬化層124，'該 些晶圓間透通連結13G，及該第二金屬化層154，提供於該些已處理半導 體構造120、職、160B、160C之間，該些電氣路徑可以用於在該些已 處理半導體構造間傳遞電力及/或電子信號。 同樣如圖9F所示’該第二金屬化層154之導電部件156可以如前所 述’在構造上及電氣上輕合至另一較高等級構造，像是另一底材Μ，之 導電部件。電氣路《可雖_—金屬化層以,、該些_透通連 結no、該第二金屬化層154至該額外底材17〇之導電部件提供於祕 已處理半導體構造120、舰、_、咖之間，此等額外之電氣路徑 亦可以用於在該些已處理轉體構造之間傳遞電力及/或電子信號。 圖胤謂呈現形成-_半導體之方法該些方法如同前文灸 考圖Μ至7F所述者，但舰_ 8所示含有該第—金屬化層軟構 3 28 201239970 造，而非圖5所示之構造。圖10A至l〇F之方法之製程大致而言與上文有 關圖6A至6F及7A至7F所敘述者相同，因此前文已述及之細節不再於 下文重複。 參考圖10A，複數個晶圓間透通連結13〇可以形成並使之穿過該第 一金屬化層124’、該層半導體材料1〇4、該層電氣絕緣材料1〇5而延伸至 該基底106。在此等方法中’該基底ι〇6可以在用於形成多個洞孔或通孔 之一蝕刻製程中作為蝕刻阻擋層使用，該些洞孔或通孔最終將以一種或更 多導電材料填充以形成該些晶圓間透通連結13〇。 如圖10B所示’形成穿過該第一金屬化層124，、該層半導體材料1〇4 及該層電氣絕緣測105之該些·間透通連結13〇後，—麵底材14〇 可以選擇性崎雜附至該帛―錢化層124，之—曝露主要表面128。將 該載體底材M0黏附至該第一金屬化層124,後，該底材謂之基底便 可以從該構造移除，留下該層半導體材料104及該層電氣絕緣材料1〇5以 形成圖10C所示之構造。 應注意的是，圖10C所呈現之半導體構造亦可以以另一種方法加以 製作將圖8之半導體構造安裝在一載體底材上，並透過研磨及磨光其中 之種或夕種’將該層半導體材料1〇4移除。後續製程可以界定出穿過該 層電氣，邑緣材料105及該半導體層1〇4並伸進該第-金屬化層124'之該些 晶圓間透通連結13〇。 HDD，—第二金屬化層154可以形成於該層半導體材料川4 ，4第二面為其上已有該第一金屬化層124,形成之該層半導體 材料104之第―而+上 田之相反面。換言之’該第二金屬化層154可以形成在與S 26 201239970 The first metallization layer 124, one of which exposes the major surface 128. After the carrier substrate 140 is adhered to the first metallization layer 124', the substrate 106 of the substrate 1 and the layer of electrical insulating material 1〇5 can be ordered from the layer. 104 fine texture of 9C fresh. It should be noted that the semiconductor structure shown in FIG. 9C can also be fabricated by another method: mounting the semiconductor structure of the circle 8 on a carrier substrate, and by grinding and polishing the species or the species, The layer of semiconductor material 1〇4 and the layer of electrically insulating material 1〇5 are removed. Subsequent processes may define through the semiconductor layer 1 (M and extend into the first metallization layer 124, the inter-wafer via junctions 13A. Referring to FIG. 9D, a second metallization layer 154 may be formed thereon. a first side of the layer of semiconductor material 1-4, the second side having the first metallization layer 124 thereon, the opposite side of the first side of the layer of semiconductor material 104 formed. Relative to Figures 9a through 9C Angle, the angle of Figure 9d is inverted 'because the configuration may be Na to facilitate the formation of the second metallization layer 154. The first metallization layer 154 is similar to the first metallization layer 124, and also includes A plurality of conductive features 156, as previously described. Figure 9E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the "Hei semiconductor construction (from the perspective of Figure 9E). As shown in Fig. 9E, the carrier substrate 140 can be removed. However, the first metallization layer 124, the region covering the layer of semiconductor material (1)* but not including any of the transistors 122 may not have to be Removed. In the process of this - with, - thief has been processed in the township 12G e^ is still on and in the layer of semiconductor material 104 remaining in the substrate 100. At this stage of the process, the patterned semiconductor structure can be cut into grains (and The carrier can be removed. In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using ff3- 27 201239970 bump technology. Next, microbump technology can be used to add The BaB particles (made by the age of the paste or the shackles or the shackles) are stacked on top of the interposer of Figure 9E, in the active devices (ie active regions) and inactive devices (ie, inactive regions). Therefore, referring to FIG. 9F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure progenitor, the processed semiconductor construction brain, and a processed semiconductor structure 160C, may be Structurally and electrically connected to the first metallization layer 124, the exposed main surface is taken up to the exposed end faces of the inter-wafer via junctions 13〇 to form an adhesive semiconductor structure as shown in FIG. deal with The conductor construction concept can include any of the types of processed semiconductor structures described above in connection with the additional processed semiconductor structures. In this manner, the electrical path can pass through the first metallization layer 124. The inter-wafer via junctions 13G, and the second metallization layer 154 are provided between the processed semiconductor structures 120, 160B, 160C, and the electrical paths can be used in the processed semiconductor structures The power and/or electronic signals are transmitted between. Similarly, as shown in FIG. 9F, the conductive member 156 of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration as described above. It is another substrate, a conductive part. The electrical circuit "may be provided by the metallization layer, the _through connection no, the second metallization layer 154 to the additional substrate 17 导电 conductive component provided in the secret processed semiconductor structure 120, ship, _ Between the coffee and the coffee, these additional electrical paths can also be used to transfer electrical and/or electronic signals between the processed swivel configurations. Figure 呈现 形成 形成 形成 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The structure of the display. The processes of the methods of Figures 10A through 10F are generally the same as those described above with respect to Figures 6A through 6F and 7A through 7F, and thus the details already described above are not repeated below. Referring to FIG. 10A, a plurality of inter-wafer via junctions 13A may be formed and extended through the first metallization layer 124', the layer of semiconductor material 1〇4, and the layer of electrically insulating material 1〇5. Substrate 106. In these methods, the substrate ι 6 can be used as an etch barrier in an etching process for forming a plurality of holes or vias, which will eventually be one or more conductive materials. Filling to form the inter-wafer via junctions 13A. As shown in FIG. 10B, 'the formation of the first metallization layer 124, the layer of the semiconductor material 1〇4, and the layer of the electrical insulation 105 are connected to each other, and the surface substrate 14〇 It can be selectively attached to the 帛-money layer 124, which exposes the main surface 128. The carrier substrate M0 is adhered to the first metallization layer 124, and then the substrate is said to be removed from the substrate, leaving the layer of semiconductor material 104 and the layer of electrically insulating material 1〇5 to form The configuration shown in Fig. 10C. It should be noted that the semiconductor structure shown in FIG. 10C can also be fabricated in another method. The semiconductor structure of FIG. 8 is mounted on a carrier substrate, and the layer or layer is polished and polished. The semiconductor material 1〇4 is removed. Subsequent processes may define such inter-wafer via connections 13 through the layer of electrical, germanium edge material 105 and the semiconductor layer 1〇4 and extending into the first metallization layer 124'. HDD, a second metallization layer 154 may be formed on the second surface of the layer of semiconductor material 4, 4 on which the first metallization layer 124 is present, and the first layer of the semiconductor material 104 is formed - and Ueda The opposite side. In other words, the second metallization layer 154 can be formed in

S 29 201239970 該層半導體材料104相反之該層電氣絕緣材料1〇5之一面上。相對於圖 10A至10C之角度，圖10D之角度是倒轉的，因為該構造可能會被倒轉， 以利該第二金屬化層154之形成。該第二金屬化層154與該第—金屬化層 124'類似，亦包含複數個導電部件156，如前文所述。 圖10E呈現該半導體構造再次被倒轉，以使該第二金屬化層154位 於該半導體構造之底部（從圖舰之角度而言）。如圖赃所示，該載體 底材140可予以移除。惟該第一金屬化層124，覆蓋住該層半導體材料耿 但不包含任何電晶體122的區域可以不必如前文參考0 6A至6F及7A至 7F所述之實施例般予轉除。在該輕雕之此—階段，—個或更多已 處理半導體構造120已·形成於該底材廳餘留部分之該層半導體材料 104之上及之中。 在該處理過程之此-階段，圖顺之已處理半導體構造可加以切割 為晶粒。此外，該晶粒可以為經過電氣測試並利用凸塊技術安裝在一封裝 體上之已知良品（KGD)。接著，可以使用微凸塊技術將額外之晶粒（利 用類似或不同之功能性紐用類似或不同之技術製作）堆疊在_ i呢之中 介層頂部，在該些主動裝置（亦即主動區域）及非主動裝置（亦即非主動 區域）上方。 因此’詳言之’參考圖10F，額外之一個或更多已處理半導體構造， 像是該已處理半導體構造16GA、該已處理半導體構造16QB，及該已處理 半導體構造脈’可以在構造上及魏上於雜—金屬化層124,之該曝 路主要表面搞合至晶圓間透通連結13〇之該些曝露端面，以形成圖.所 不之黏附半導體構造。這樣，電氣路徑便可以透過料-金屬化層124,、S 29 201239970 This layer of semiconductor material 104 is on the opposite side of the layer of electrically insulating material 1〇5. The angle of Fig. 10D is reversed relative to the angles of Figs. 10A through 10C because the configuration may be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124' and also includes a plurality of conductive features 156 as previously described. Figure 10E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of the ship). As shown in Figure ,, the carrier substrate 140 can be removed. However, the first metallization layer 124, the region overlying the layer of semiconductor material 耿 but not including any of the transistors 122 may not necessarily be removed as in the prior embodiments with reference to Figures 6A through 6F and 7A through 7F. At this stage of the sculpting, one or more processed semiconductor structures 120 have been formed on and in the layer of semiconductor material 104 remaining in the remainder of the substrate. At this stage of the process, the processed semiconductor structure can be cut into grains. In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Next, additional bumps (made with similar or different functionalities using similar or different techniques) can be stacked on top of the interposer using the microbumping technique, in the active devices (ie active regions) ) and above the non-active device (ie, the inactive area). Thus, with reference to FIG. 10F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 16GA, the processed semiconductor structure 16QB, and the processed semiconductor structure pulse can be constructed and Wei Shangyu-metallization layer 124, the main surface of the exposure is applied to the exposed end faces of the inter-wafer transparent connection 13〇 to form a bonded semiconductor structure. In this way, the electrical path can pass through the material-metallization layer 124,

S 30 201239970 該些晶_透通連結13G及該第二金屬化層丨54，提供於該些已處理半導 體構造120、160A、刪、160C之間，該些電氣路徑可以用於在該些已 處理半導體構造間傳遞電力及/或電子信號。 同樣如圖10F所示’該第二金屬化層154之導電部件156可以如前 所述’在構造上及電氣上齡至另_較高等級構造，像是另—底材17〇， 之導電部件。電氣路徑亦可以經由該第一金屬化層m,'該些晶圓間透通 連結130、該第二金屬化層154至該額外底材17〇之導電部件，而提供於 該些已處理半導體構造12G、職、職、職之間此等額外之電氣 路徑亦可㈣於在該些已處理半導體構造之間傳遞電力及/或電子信號。 在上述該些實施射，麟之該些已纽半♦體触16QA、16〇B、 160C之導電部件（譬如導電墊）係糊該些導電微凸塊或微球i62，而在 構U上及電氟上輕合至該些晶圓間透通連結及13〇，。同樣地該第二 金屬化層154之導電部件156係利用導電凸塊或導電球172，而在構造上 及電氣上耦合至該額外底材170之導電部件。在本發明之額外實施例中， 額外之e亥些已處理半導體構造160A、160B、160C之導電部件可以使用金 屬對金屬直接黏附製程，在構造上及電氣上耦合至該些晶圓間透通連結 130。同樣地，該第二金屬化層154之導電部件156可以使用金屬對金屬 直接黏附製程，而在構造上及電氣上耦合至該額外底材17〇之導電部件。 應注意的是，與本說明書中所述之微凸塊技術相較，直接黏附方法具有縮 減之接合間距（bonding pitch)且可以應用於本發明之額外實施例中。此 種縮減之接合間距可以允許在該些黏附裝置構造之間有較高之輸入/輸出 (I/O)密度。 31 201239970 舉例而言’圖11 1現_ 1()F類似之一黏附半導體構造之實施例， 但在圖11中使用了金屬對金屬直接黏附製程，以將額外之該些已處理半 導體構造160A、160B、160C之冑電部件黏附至該些晶圓間透通連結13〇， 並將該第二金屬化層154之導電部件156黏附至該額外底材17()之導電部 件。此等直接黏附製程亦可以用於形成如圖6F、7F及9F所示之黏附半導 體構造。 在本發明之一些實施例中，該些金屬對金屬直接黏附製程可以在低 於大約400T之溫度下，或甚至低於大約35〇。(：之溫度下施行，以避免對 該些已處理半導體構造120、160A、160B、160C中的任何裝置構造造成 熱損壞。在一些實施例中’該些黏附製程可以包括一超低溫直接黏附製 程’亦可以包括一表面輔助直接黏附製程，如先前於本說明書中所界定之 該些製程。 作為另一範例’圖12呈現與圖7F類似之一黏附半導體構造之實施 例’但在圖12中使用了氧化物對氧化物直接黏附製程，以將額外之該些 已處理半導體構造160A、160B黏附至該電氣絕緣材料層105。如同在圖 11中’一金屬對金屬直接黏附製程可以用於將該第二金屬化層154之導電 部件156黏附至該額外底材170之導電部件。類似於前文參考圖7A至7F 所述但略有修改之方法可以用於形成圖12之黏附半導體構造。例如，要 形成圖12之黏附半導體構造，該第一金屬化層124之多個部分可以如前 文參考圖7E所述之方式加以移除。但該些製程亦可以用於移除該層半導 體材料104在此等區域中之多個部分，以露出該層電氣絕緣材料105 (其 可以形成使之包含一種氧化物）。然後，額外之該些已處理半導體構造S 30 201239970 The crystal-transparent junctions 13G and the second metallization layer 丨54 are provided between the processed semiconductor structures 120, 160A, ED, 160C, and the electrical paths can be used for the Processing electrical and/or electronic signals between semiconductor structures. Similarly, as shown in FIG. 10F, the conductive member 156 of the second metallization layer 154 can be constructed as described above in terms of construction and electrical age to another level, such as another substrate. component. The electrical path may also be provided to the processed semiconductor via the first metallization layer m, 'the inter-wafer via junction 130, the second metallization layer 154 to the conductive component of the additional substrate 17〇 The additional electrical paths between the 12G, the job, the job, and the job may also be (4) to transfer power and/or electronic signals between the processed semiconductor structures. In the above-mentioned implementations, the conductive components (such as conductive pads) of the 16QA, 16〇B, and 160C of the linings of the linings are affixed to the conductive microbumps or microspheres i62, and on the U And the electric fluorine is lightly coupled to the inter-wafer through-connection and 13〇. Similarly, the conductive features 156 of the second metallization layer 154 are electrically and mechanically coupled to the conductive features of the additional substrate 170 using conductive bumps or conductive balls 172. In additional embodiments of the present invention, additional conductive components of the processed semiconductor structures 160A, 160B, 160C may be metal-to-metal direct adhesion processes, structurally and electrically coupled to the wafers. Link 130. Similarly, the conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to the conductive features of the additional substrate 17 using a metal-to-metal direct adhesion process. It should be noted that the direct adhesion method has a reduced bonding pitch as compared to the microbump technique described in this specification and can be applied to additional embodiments of the present invention. This reduced joint spacing allows for a higher input/output (I/O) density between the adhesive device configurations. 31 201239970 For example, 'Figure 11 1 _ 1 () F is similar to an embodiment of a bonded semiconductor construction, but a metal-to-metal direct adhesion process is used in Figure 11 to add additional processed semiconductor structures 160A The electrical components of 160B, 160C are adhered to the inter-wafer via junctions 13 and the conductive features 156 of the second metallization layer 154 are adhered to the conductive features of the additional substrate 17 (). These direct adhesion processes can also be used to form an adherent semiconductor construction as shown in Figures 6F, 7F and 9F. In some embodiments of the invention, the metal to metal direct adhesion processes can be at temperatures below about 400 T, or even below about 35 Torr. The temperature is applied to avoid thermal damage to any of the fabricated semiconductor structures 120, 160A, 160B, 160C. In some embodiments, the adhesion processes may include an ultra-low temperature direct adhesion process. A surface assisted direct adhesion process, such as those previously defined in this specification, may also be included. As another example, FIG. 12 presents an embodiment of an adhesive semiconductor construction similar to that of FIG. 7F but used in FIG. An oxide-to-oxide direct adhesion process to adhere additional of the processed semiconductor structures 160A, 160B to the layer of electrically insulating material 105. As in Figure 11, a metal-to-metal direct adhesion process can be used to The conductive features 156 of the second metallization layer 154 are adhered to the conductive features of the additional substrate 170. A method similar to that described above with reference to Figures 7A through 7F but with minor modifications may be used to form the bonded semiconductor construction of Figure 12. For example, To form the bonded semiconductor construction of Figure 12, portions of the first metallization layer 124 can be removed as previously described with reference to Figure 7E. The processes can also be used to remove portions of the layer of semiconductor material 104 in such regions to expose the layer of electrically insulating material 105 (which can be formed to include an oxide). Then, additional Processed semiconductor construction

S 32 201239970 160A、160B便可以在氧化物對氧化物直接黏附之一製程中，直接黏附至 該電氣絕緣材料層105。此外，就至少有待與額外之該些已處理半導體構 造160A、160B連結之該些晶圓間透通連結130而言，其形成可以在額外 之該些已處理半導體構造160A、160B於氧化物對氧化物直接黏附之一製 程中黏附至該電氣絕緣材料層105之後，及該第二金屬化層154形成之 前。於該直接黏附製程之後形成該些晶圓間透通連結13〇，可以改進建立 於該些晶圓間透通連結130和與其耦合之額外之該些已處理半導體構造 160A、160B之個別導電部件間之電氣連接之品質。 在本發明之一些實施例中，該氧化物對氧化物直接黏附製程可以在 低於大約400T之溫度下，或甚至低於大約350〇C之溫度下施行，以避免 對該些已處理半導體構造120、160A、160B中的任何裝置構造造成熱損 壞。在一些實施例中，該些黏附製程可以包括一超低溫直接黏附製程，亦 可以包括一表面輔助直接黏附製程，如先前於本說明書中所界定之該此製 程。 類似之氧化物對氧化物直接黏附製程亦可以用於形成如圖6F、卯 及10F所示之黏附半導體構造。 本發明之該些實施例可用於在由一 SeOI類型之底材之至少一部分 所承載之多個已處理半導體構造間提供直接、連續之電氣路徑，該些電氣 路徑僅穿過同樣由該SeOI類型之底材之至少該部分所承載之導電部件 (例如導電墊、跡線及通孔），而不會穿過附著至該SeOI類型底材之至 少一部分之另一較高等級底材，像是該額外底材17〇，之任何部分。此等 電氣路徑較先前已知之組構更短，並可以改進信號速度及/或電源效率。 33 201239970 本發明額外之非限制性質示範性實施例敘述如下： 實施例1:一種形成一半導體裝置之方法，該方法包括：提供一底 材，該底材包括在一層電氣絕緣材料上之一層半導體材料；在該底材上與 該層電氣絕緣材料相反之該層半導體材料之一第一面，形成包含複數個導 電部件之一第一金屬化層；形成複數個晶圓間透通連結使之至少部分穿過 該底材’且形成該些晶圓間透通連結中至少一個晶圓間透通連結，使之穿 過該金屬化層及該層半導體材料；在該底材上與該層半導體材料之第一面 相反之該層半導體材料之一第二面，形成包含複數個導電部件之一第二金 屬化層；以及在由該底材承載於該層半導體材料之第一面之一第一已處理 半導體構造以及由該底材承載於該層半導體材料之第一面之一第二已處 理半導體構造間，提供連續穿過該第一金屬化層、該底材，及該第二金屬 化層之一電氣路徑。 實施例2:如實施例1之方法，其中提供該底材包括選定該底材使 之包含一絕緣體上半導體（SeOI)底材。 實施例3 :如實施例2之方法，其中選定該底材使之包含一絕緣體 上半導體（SeOI)底材包括選定該底材使之包含一絕緣體上矽（s〇l)底 材》 實施例4 :如實施例丨至3中任一項之方法，其中該層半導體材料 具有之平均總厚度為大約1微米或更薄，且其中該層電氣絕緣材料包括一 層氧化物材料，該層氧化物材料具有之平均總厚度為大約3〇〇nm或更薄。 實施例5 :如實施例丨至4中任一項之方法，其中形成該些晶圓間 透通連結中至少一個晶圓間透通連結使之穿過該金屬化層及該層半導體S 32 201239970 160A, 160B can be directly adhered to the electrically insulating material layer 105 in a process in which the oxide is directly adhered to the oxide. In addition, at least the inter-wafer via junctions 130 to be coupled to the additional processed semiconductor structures 160A, 160B may be formed in addition to the processed semiconductor structures 160A, 160B in an oxide pair. After the adhesion of the layer of electrically insulating material 105 to one of the processes of direct adhesion of oxide, and before the formation of the second metallization layer 154. Forming the inter-wafer via connections 13A after the direct adhesion process, the individual conductive features of the inter-wafer via junctions 130 and the additional processed semiconductor structures 160A, 160B coupled thereto can be modified. The quality of the electrical connection between the two. In some embodiments of the invention, the oxide-to-oxide direct adhesion process can be performed at temperatures below about 400 T, or even below about 350 ° C, to avoid processing the processed semiconductor structures. Any device configuration in 120, 160A, 160B causes thermal damage. In some embodiments, the adhesion processes can include an ultra-low temperature direct adhesion process, and can also include a surface assisted direct adhesion process, as previously defined in this specification. A similar oxide-to-oxide adhesion process can also be used to form an adherent semiconductor structure as shown in Figures 6F, 卯 and 10F. Embodiments of the present invention can be used to provide a direct, continuous electrical path between a plurality of processed semiconductor structures carried by at least a portion of a SeOI type substrate, the electrical paths only passing through the same type of SeOI At least a portion of the substrate carries conductive features (eg, conductive pads, traces, and vias) without passing through another higher level substrate attached to at least a portion of the SeOI type substrate, such as The extra substrate is 17 inches, any part of it. These electrical paths are shorter than previously known and can improve signal speed and/or power efficiency. 33 201239970 Additional non-limiting properties of the invention Exemplary embodiments are described below: Embodiment 1: A method of forming a semiconductor device, the method comprising: providing a substrate comprising a layer of semiconductor on a layer of electrically insulating material a first surface of one of the plurality of conductive members on the substrate opposite to the layer of electrically insulating material, forming a first metallization layer comprising a plurality of conductive members; forming a plurality of inter-via transparent connections Passing at least partially through the substrate 'and forming at least one inter-wafer via-through connection between the inter-wafer vias to pass through the metallization layer and the layer of semiconductor material; and the layer on the substrate a second side of one of the layers of semiconductor material opposite the first side of the semiconductor material, forming a second metallization layer comprising one of a plurality of conductive features; and one of the first sides of the semiconductor material carried by the substrate a first processed semiconductor structure and carried by the substrate between one of the first processed semiconductor structures of the first side of the layer of semiconductor material to provide continuous passage through the first metallization layer The substrate, and an electrical path of the second metallization layer. Embodiment 2: The method of Embodiment 1, wherein providing the substrate comprises selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate. Embodiment 3: The method of Embodiment 2, wherein the substrate is selected to comprise a semiconductor-on-insulator (SeOI) substrate comprising: selecting the substrate to comprise an insulator slab substrate. The method of any one of embodiments 3 to 3, wherein the layer of semiconductor material has an average total thickness of about 1 micron or less, and wherein the layer of electrically insulating material comprises a layer of oxide material, the layer of oxide The material has an average total thickness of about 3 〇〇 nm or less. The method of any one of embodiments 4 to 4, wherein at least one of the inter-wafer via connections is formed to pass through the metallization layer and the semiconductor layer

34 S 201239970 一個晶圓間透通連結使之穿 材料更包括形成該些晶圓間透通連結中至少一 過該層電氣絕緣材料。34 S 201239970 An inter-wafer via-bonding material for forming a material further includes forming at least one of the inter-wafer via connections.

，其更包括在該層半導 第二已處理半導體構造 至少其中之一黏附至該底材。 實施例7 .如實施例6之方法， 其中在該層半導體材料之第一面將 該第-已處群導體構造麟第二已處理铸體構造至少其中之一黏附 至該底材包括於金騎金屬直接軸之—製程中，在低於大約彻。c之一 個溫度或多個溫度下，將鱗-已處理半導體構造及該第二已處理半導體 構造至少其中之一直接黏附至該底材。And further comprising bonding at least one of the semiconducting second processed semiconductor structures to the substrate. The method of embodiment 6, wherein at least one of the first processed group conductor structure and the second processed cast structure is adhered to the substrate on the first side of the layer of semiconductor material, the gold is included in the gold Riding a metal direct shaft - in the process, at less than about. At least one of the scale-processed semiconductor construction and the second processed semiconductor construction is directly adhered to the substrate at one or more temperatures.

至少其中之一#%形成於該底材上。 實施例9 :如實施例1至8中任-項之方法，其中提供—電氣路徑 更包括組構該電氣路徑使之穿過該第一金屬化層之至少一個導電部件、穿 過該金屬化層及該層半導體材料之該些晶圓間透通連結之至少一個晶圓 間透通連結、該第二金屬化層之至少-個導電部件，及該些晶圓間透通連 結之至少另一個晶圓間透通連結。 實施例10 :如實施例1至9中任-項之方法，其更包括在構造上及 電氣上將該第二金屬化層之至少一個導電部件連結至另一底材之一個導 電部件。 35 201239970 實施例11:如實施例1至10中任-項之方法，其更包括從由—電 子信號處理器裝置…電子記憶裝置電磁輪射發射器裝置，及一電磁 轉射接收器裝颜構权f合中’各_定辦—已處料導體構造及該 第二已處理半導體構造。 實施例12:如實施例11之方法，其更包括：選定該第-已處理半 導體構造使之包括—電子銳處理器裝置；及敎鱗二已處理半導體構 造使之包括-電子記憶裝置、-發光二極體、_雷射二極體，及一太陽能 電池至少其中之一。 實施例π -半導體構造，其包括：_底材，其包括一層半導體材 料’該底材上之一第一金屬化層’其位於該層半導體材料之一第一面；該 底材上之-第二金>1化層’其位於與該層半導體材料之第-面相反之該層 半導體材料之一第二面；複數個晶圓間透通連結，其至少部分穿過該第一 金屬化層及該底材之該層半導體材料；-第―已處理半導體構造，由該底 材承載於該層半導·料之第-面；以及—第二已處理半導體構造，由該 底材承載於該層半導體材料之第-面；其中—電氣路徑從該第一已處理半 導體構造穿過該第一金屬化層之一導電部件、該些晶圓間透通連結之一第 一晶圓間透通連結、該第二金屬化層之一導電部件，及該些晶圓間透通連 結之一第一晶圓間透通連結，延伸至該第二已處理半導體構造。 實施例14 :如實施例13之半導體構造，其中該底材包括一絕緣體 上半導體（SeOI)底材。 實施例15 :如實施例14之半導體構造，其中該絕緣體上半導體 (SeOI)底材包括一絕緣體上矽（s〇i)底材。At least one of #% is formed on the substrate. The method of any of embodiments 1 to 8, wherein providing - the electrical path further comprises structuring the electrical path through the at least one electrically conductive member of the first metallization layer, through the metallization And at least one inter-via transparent connection between the layer and the wafer of the semiconductor material, at least one conductive component of the second metallization layer, and at least another through-wafer connection between the wafers A wafer is connected through the gap. The method of any of embodiments 1 to 9, further comprising structurally and electrically joining the at least one electrically conductive member of the second metallization layer to one of the electrically conductive members of the other substrate. 35. The method of any of embodiments 1 to 10, further comprising: applying an electronic transmitter device, an electronic memory device, an electromagnetic wheel transmitter device, and an electromagnetic relay device The construction of the conductor structure and the second processed semiconductor structure. Embodiment 12: The method of Embodiment 11, further comprising: selecting the first processed semiconductor structure to include an electronic sharp processor device; and the scaled processed semiconductor structure to include an electronic memory device, At least one of a light emitting diode, a laser diode, and a solar cell. Embodiment π -a semiconductor construction comprising: a substrate comprising a layer of a semiconductor material 'one of the first metallization layers' on the first side of the layer of semiconductor material; on the substrate - a second gold >1 layer' is located on a second side of one of the layers of semiconductor material opposite the first side of the layer of semiconductor material; a plurality of wafers are transparently coupled to each other at least partially through the first metal And a layer of semiconductor material of the substrate; a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material; and a second processed semiconductor structure from the substrate Carrying a first surface of the semiconductor material of the layer; wherein the electrical path is from the first processed semiconductor structure through one of the conductive features of the first metallization layer, and the first wafer is transparently connected between the wafers An inter-via connection, a conductive member of the second metallization layer, and one of the inter-wafer via connections are transparently connected to the first wafer and extend to the second processed semiconductor structure. Embodiment 14: The semiconductor construction of Embodiment 13, wherein the substrate comprises a semiconductor-on-insulator (SeOI) substrate. Embodiment 15: The semiconductor construction of Embodiment 14, wherein the semiconductor-on-insulator (SeOI) substrate comprises an insulator s(i) substrate.

S 36 201239970 實施例16 :如實施例14或15之半導體構造，其中該層半導體材料 具有大約1微米或更薄之平均總厚度。 實施例17 :如實施例14至16中任一項之半導體構造，其中該些晶 圓間透通連結令至少一個晶圓間透通連結至少部分穿過該Se〇I底材之一 層電氣絕緣材料。 實施例18 :如實施例13至π中任一項之半導體構造，其中該第一 已處理半導體構造及該第二已處理半導體構造至少其巾之—在該層半導 體材料之第一面被黏附至該底材。 實施例19 :如實施例18之半導體構造，其中該第一已處理半導體 構&及该第二已處理半導體構造至少其中之—之—金屬部件被直接黏附 至該些晶圓間透通連結中至少一個晶圓間透通連結。 實施例20 :如實施例13至19中任一項之半導體構造，其令該電氣 路徑在該第-已處理半導體構造及該第二已處理半導體構造之間連續延 伸，穿過該底材、該第一金屬化層，及該第二金屬化層。 實施例21 :如實施例13至20中任一項之半導體構造，其中該第二 金屬化層之至少一個導電部件在電氣上耦合至另一底材之—導電部件。 實施例22 :如實施例13至21中任一項之半導體構造，其中該第一 已處理半導體構造及該第二已處理半導體構造巾的每__個皆包括—電 信號處理器裝置、一電子記憶裝置、一電磁輻射發 ，及—電磁輻 射接收器裝置其中之一。 實施例23 :如實施例 ™脚’Μ:該第—已處理半導 體構造包括-電子信號處㈣裝置；以及該第二已處理半導體構造勺&S 36 201239970 Embodiment 16: The semiconductor construction of Embodiment 14 or 15, wherein the layer of semiconductor material has an average total thickness of about 1 micron or less. The semiconductor structure of any one of embodiments 14 to 16, wherein the inter-wafer via bonds electrically insulate at least one inter-wafer via junction at least partially through a layer of the Se〇I substrate material. The semiconductor construction of any one of embodiments 13 to π, wherein the first processed semiconductor construction and the second processed semiconductor construction are at least a towel-attached to the first side of the layer of semiconductor material To the substrate. Embodiment 19: The semiconductor construction of embodiment 18, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is directly adhered to the inter-wafer transparent connection At least one of the wafers is transparently connected. Embodiment 20: The semiconductor construction of any of embodiments 13 to 19, wherein the electrical path extends continuously between the first processed semiconductor construction and the second processed semiconductor construction, through the substrate, The first metallization layer and the second metallization layer. The semiconductor construction of any one of embodiments 13 to 20, wherein the at least one electrically conductive member of the second metallization layer is electrically coupled to the electrically conductive member of the other substrate. Embodiment 22: The semiconductor construction of any one of embodiments 13 to 21, wherein each of the first processed semiconductor construction and the second processed semiconductor construction tissue comprises an electrical signal processor device, An electronic memory device, an electromagnetic radiation, and one of electromagnetic radiation receiver devices. Embodiment 23: As in the embodiment TM foot 'Μ: the first processed semiconductor structure includes - an electronic signal (4) device; and the second processed semiconductor construction scoop &

37 S 201239970 電子記憶裝置、-發光二極體、-雷射二極體，及—太陽能電池至少其中 之一。 上述之本發明示範性實施例並不會限制本發明之範圍。這些實施例 僅為本發明實施例之範例’本發日雜由所附之中請專利細及其法律同等 效力所界定。任何等同之實施例均屬於本發明之範_。對熟悉本發明所 屬技術領域者而言，除本說明書所示及所述者外，對於本揭露之各種修 改’例如替換所述該些元件之有用組合，將因本說明書之敛述而變棚而 易見。此等修改例亦落在所附之申請專利之範圍内。本說明書所用之標題 僅為清楚·及便於理解啸供，·標舰骑關町之㈣專利範 圍。 【圖式簡單說明】 藉由參照町詳纟錢所關式，可更充分了解本發明之實施 例，其中： 圖1為-絕緣體上半導體（Se0I)底材之簡化截面圖，該底材可以 為本發明之方法之實施例所採用； 圖2為一簡化截面圖，其呈現一種可以用於製作圖！之驗底材之 方法； 圖3為圖丨之SeOI底材之簡化俯視圖，其綱要性地呈現該底材上有 複數個已處理半導體構造； 圖4為一簡化截面圖’其綱要性地呈現複數個電晶體形成於圖1之 SeOI底材之一層半導體材料之中及之上；37 S 201239970 Electronic memory device, - light-emitting diode, - laser diode, and - at least one of solar cells. The above described exemplary embodiments of the invention do not limit the scope of the invention. These examples are merely examples of embodiments of the invention, which are defined by the accompanying patents and their legal equivalents. Any equivalent embodiment is within the scope of the invention. For those skilled in the art to which the present invention pertains, various modifications of the present disclosure, such as replacing the useful combinations of the elements, will be circumscribed by the present specification. And easy to see. Such modifications are also intended to fall within the scope of the appended claims. The title used in this manual is only for the sake of clarity and ease of understanding of the whistle, and the patent scope of the standard ship. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present invention can be more fully understood by reference to the details of the drawings, wherein: FIG. 1 is a simplified cross-sectional view of a semiconductor-on-insulator (Se0I) substrate, which may be It is used as an embodiment of the method of the present invention; FIG. 2 is a simplified cross-sectional view showing one that can be used to make a drawing! Figure 3 is a simplified top view of the SeOI substrate of the figure, which outlines a plurality of processed semiconductor structures on the substrate; Figure 4 is a simplified cross-sectional view of the schematic a plurality of transistors are formed in and on a layer of semiconductor material of the SeOI substrate of FIG. 1;

S 38 201239970 圖5為一簡化截面圖，其呈現一第一金屬化層形成於該些電晶體上 方及圖1之SeOI底材之該層半導體材料之第一面； 圖6A至6F係用於呈現本發明之方法之實施例，該些方法可以用於 形成一構造’該構造包含由圖5之底材所承載之兩個或更多已處理半導體 構造，該些方法並可用於在電氣上互連該些已處理半導體構造至少其中兩 個； 圖6A呈現晶圓間透通連結之製作，該些晶圓間透通連結穿過該第一 金屬化層及圖5所示之SeOI底材之該層半導體材料； 圖6B呈現在該第一金屬化層與該&〇1底材相反之一面，一載體底 材被黏附至該第一金屬化層； 圖6C呈現該SeOI底材之一部分被移除，以在與該載體底材相反之 一面露出穿過該底材之該些晶圓間透通連結； 圖6D呈現在該SeOI底材之該層半導體材料與該第一金屬化層相反 之一面，一第二金屬化層形成於該層半導體材料上； 圖6E呈現該載體底材及圖6D所示構造之其他部分被移除； 圖6F呈現在該SeOI底材之該層半導體材料第一面上，額外之已處 理半導體構造被黏附至圖6E之構造並在電氣上與其耦合，該圖更呈現在 該SeOI底材之該層半導體材料第二面上，該半導體構造與另一底材之點 附及電氣輕合； 圖7A至7F與圖6A至6F類似’係用於呈現本發明之方法之飞外實 施例，該些方法可以用於形成-構造，其包含_ 5之底材所承載之兩個 或更多已處理半導體構造’該些方法並可以用於在電氣上連择节此已〆S 38 201239970 FIG. 5 is a simplified cross-sectional view showing a first metallization layer formed over the transistors and a first side of the layer of semiconductor material of the SeOI substrate of FIG. 1; FIGS. 6A to 6F are used for Embodiments of the method of the present invention are presented, which may be used to form a construction comprising two or more processed semiconductor structures carried by the substrate of Figure 5, which methods may be used electrically Interconnecting at least two of the processed semiconductor structures; FIG. 6A illustrates fabrication of inter-wafer via connections through the first metallization layer and the SeOI substrate shown in FIG. Figure 6B shows a carrier substrate bonded to the first metallization layer on the opposite side of the first metallization layer from the & 1 substrate; Figure 6C shows the SeOI substrate a portion is removed to openly connect the wafers through the substrate on a side opposite the carrier substrate; FIG. 6D presents the layer of semiconductor material on the SeOI substrate and the first metallization On the opposite side of the layer, a second metallization layer is formed on the layer Figure 6E shows the carrier substrate and other portions of the configuration shown in Figure 6D removed; Figure 6F shows the additional processed semiconductor structure adhered to the first side of the layer of semiconductor material of the SeOI substrate The structure of FIG. 6E is electrically coupled thereto, and the figure is further presented on the second side of the layer of semiconductor material of the SeOI substrate, the semiconductor structure being electrically coupled with the point of another substrate; FIG. 7A to 7F is similar to FIGS. 6A through 6F' is an off-the-shelf embodiment for presenting the method of the present invention, which may be used in a formation-construction comprising two or more processed semiconductors carried by a substrate of _5 Construct 'these methods and can be used to electrically select the section

39 S 201239970 半導體構造至少其中兩個，其中該SeOI底材之m赞緣材料並未在 處理過程中被移除； 圖8與圖5類似，其呈現一第一金屬化層形成於該些電晶體上方及 圖1之Sea底材之該層半導體材料之第一面，包括其上並無電晶體形成 之SeOI底材區域； 圖9A至9F與圖6A至6F類似，係用於呈現本發明之方法之額外實 施例’該些方法可以用於形成—構造，其包含_ 8之構造所承載之兩個 或更多已纽半導體财，触;5·法並可以麟在魏上義該些已處理 半導體構造至少其中兩個’其中該線底材之—層電氣絕緣材料在處理 過程中被移除； 圖10A至10F與圖9A至9F類似，係用於呈現本發明之方法之額外 實施例’該些方法可關於形成—構造，其包含由圖8之構造所承載之兩 個或更多已處理半導體構造，該些方法並可以祕在電氣上連結該些已處 理半導體構造至少其中兩個，其中該Se0I底材之—層電氣絕緣材料並未 在處理過程中被移除； 圖11為一已處理半導體構造之簡化截面圖，該已處理半導體構造與 圖10F所呈現者類似’但本圖呈現多個已處理半導體構造在該底材 之第-面直雛附至-第-金屬化層，且另—底材在該Se〇I底材之第二 面直接黏附至一第二金屬化層；以及 圖12為一已處理半導體構造之簡化截面圖，該已處理半導體構造 與圖7F所呈現者類似，但本圖呈現多個已處理半導體構造直接黏附在該39 S 201239970 Semiconductor construction of at least two of which the m-like material of the SeOI substrate is not removed during processing; Figure 8 is similar to Figure 5, showing a first metallization layer formed on the electricity The first side of the layer of semiconductor material above the crystal and the Sea substrate of FIG. 1 includes a SeOI substrate region having no crystals formed thereon; FIGS. 9A through 9F are similar to FIGS. 6A through 6F and are used to present the present invention. Additional embodiments of the method 'These methods can be used for forming-constructing, which comprises two or more of the semiconductors carried by the structure of _8, and the touches of the semiconductors; Constructing at least two of the layers of the electrical insulation material of the wire substrate are removed during processing; FIGS. 10A through 10F are similar to FIGS. 9A through 9F and are used to present additional embodiments of the method of the present invention. The methods may be related to a formation-construction comprising two or more processed semiconductor structures carried by the configuration of FIG. 8, and the methods may be electrically connected to at least two of the processed semiconductor structures, wherein The bottom of the Se0I The layer-to-layer electrical insulating material is not removed during processing; Figure 11 is a simplified cross-sectional view of a processed semiconductor structure similar to that presented in Figure 10F' but with multiple Processing the semiconductor structure to be attached to the first-metallization layer on the first side of the substrate, and the other substrate directly adhering to the second metallization layer on the second side of the Se〇I substrate; 12 is a simplified cross-sectional view of a processed semiconductor structure similar to that presented in FIG. 7F, but showing a plurality of processed semiconductor structures directly attached thereto.

SeOI底材之第一面，且另一底材在該Se〇I底材之第二面直接黏附至一 金屬化屉。 201239970 【主要元件符號說明】 100、170 底材 104半導體材料 105電氣絕緣材料 106基底 107、128主要表面 110半導體材料之一部分 112離子植入平面 120、160A、160B已處理半導體構造 122電晶體 124第一金屬化層 125介電材料 126、156導電部件 130透通連結 140載體底材 154第二金屬化層 156’通孔 162微凸塊或微球 172凸塊或焊接球The first side of the SeOI substrate, and the other substrate is directly adhered to a metallization drawer on the second side of the Se〇I substrate. 201239970 [Description of main component symbols] 100, 170 Substrate 104 Semiconductor material 105 Electrical insulating material 106 Substrate 107, 128 Main surface 110 One part of semiconductor material Part 112 Ion implantation plane 120, 160A, 160B Processed semiconductor structure 122 Transistor 124 A metallization layer 125 dielectric material 126, 156 conductive member 130 is transparently bonded 140 carrier substrate 154 second metallization layer 156' through hole 162 microbump or microsphere 172 bump or solder ball

S 41S 41

Claims (1)

201239970 七、申請專利範圍： 1. -種形成-半導體裝置之方法，其包括： 提供一底材，該賴包括在1電氣職材料上之-層半導體材 料； 在該底材上與該層魏絕緣材料相反之該層半導體材料之一第一 面形成包含複數個導電部件之一第一金屬化層； 形成複數個晶關魏連結使之至少部分穿過該，且形成該些 晶圓間透通連結中至少-個晶圓間透通連結，使之穿過該金屬化層及該 層半導體材料； 在該底材上與該層半導體材料之第—面相反之該層半導體材料之 一第二面，形成包含複數個導電部件之一第二金屬化層；以及 在由該底材承載於該層半導體材料之第一面之一第一已處理半導 體構造以及由該底材承載於該層半導體材料之第一面之一第二已處理半 導體構造間’提供連續穿過該第一金屬化層'該底材，及該第二金屬化 層之一電氣路徑。 2. 如申請專利範圍第1項之方法，其中形成該些晶圓間透通連結 中至少一個晶圓間透通連結使之穿過該金屬化層及該層半導體材料更包 括形成該些晶圓間透通連結中至少一個晶圓間透通連結使之穿過該層電 氣絕緣材料》 S 42 201239970 第_ =糾㈣第1項之方法，其更包括在該層轉體材料之 至少其 ，將該第—已處理半導體構造及該第二已處理半導體構造 中之一黏附至該底材。 4. 如申請專利範圍第3項之方法，其中在該層半導體材料之第一 面將該第—已處理半導體構造及該第二已處理半導體構造至少其中之一 黏附至該缝包括於金屬對金屬直接雜之—製程巾，在低於大約 4〇〇〇C之-個溫度❹個溫度下，將該第一已處理半導體構造及該第二 已處理半導體構造至少其中之—直接黏附至該底材。 5. 如申請專利範圍第1項之方法，其更包括在該層半導體材料之 第-面’將該第—已處理铸體構造及該第二已處理半導體構造至少其 中之一#尨形成於該底材上。 ' 6. 如申請專利範圍第i項之方法，其中提供一電氣路徑更包括組 構該電氣路做之穿職第-驾化層之至少—料電部件、穿過該金 屬化層及該層半導體材料之該些晶關透通連結之至少—個晶圓間透通 連結、該第二金屬化層之至少-個導電部件，及該些晶圓間透通連結之 至少另一個晶圓間透通連結。 7. 如申請專利範圍第1項之方法，其更包括在構造上及電氣上將 該第二金屬化層之至少-個導電部件連結至另—底材之—個導電部件。 43 201239970 8, 如申請專利麵1項之方法，其更包括從由-電子信號處理 器裝置一電子記憶裝置一電磁輻射發射器裝置，及—電磁輻射接收 器裝置成之集合中，各別選定該第—已處理半導體構造及該第二已 處理半導體構造。 9. 如申請專利範圍第8項之方法其更包括 、疋該第-已處理半導體構造使之包括—電子信號處理器裝置；及 選定該第二已處理半導體構造使之包括—電子記憶裝置、一發光二 極體、-f射二極體’及__太陽能電池至少其中之一。 10· —半導體構造，其包括·· 一底材，其包括一層半導體材料； 該底材上之一第—金屬化層，其位於該層半導體材料之一第一面； 該底材上之一第二金屬化層，其位於與該層半導體材料之第一面相 反之該層半導體材料之—第二面； 複數個晶圓間透通連結，其至少部分穿過該第一金屬化層及該底材 之該層半導體材料； 一第一已處理半導體構造，由該底材承載於該層半導體材料之第一 面；以及 一第二已處理半導體構造，由該底材承載於該層半導體材料之第一 201239970 其t一電氣路徑從該第-已處理半導體構造穿過該第一金屬化層 之-導電部件、該些晶圓·通連結之—第—晶圓間透通連結該第二 金屬化層之-導電部件，及該些_透通連結之_第二_透通連 結，延伸至該第二已處理半導體構造。 11.如申雜_第1〇項之半導體構造，其中該底材包括一絕緣 體上半導體（SeOI)底材。 如申明專利範圍第11項之半導體構造其中該些晶圓間透通連 結中至少-觀關透通連結至少部分穿過該驗減之—層電氣絕 緣材料。 13.如申料利細第1G項之半物構造，其_-已處理半導 體構造及該第二已處理半導體構造至少其中之-在該層半導體材料之第 一面被黏附至該底材。 14.如申請專利範圍第13項之半導體構造，其中該第-已處理半導 體構造及該第二已處理铸體構造至少其巾之—之―金屬轉被直接黏 附至該些晶關透通連結中至少_個晶圓間透通連結。 15.如申明專麻圍第1〇項之半導體構造，其中該電氣路經在該第 已處理半導體構&及該第—已處理半導體構造之間連續延伸，穿過該 底材、該第-金屬化層’及該第二金屬化層。 45 201239970 16. 如申請專利範圍第10項之半導體構造，其中該第二金屬化層之 至少一個導電部件在電氣上耦合至另一底材之一導電部件。 17. 如申請專利範圍第10項之半導體構造，其中該第一已處理半導 體構造及該第二已處理半導體構造中的每一個皆包括一電子信號處理器 裝置、一電子記憶裝置、一電磁輻射發射器裝置，及一電磁輻射接收器 裝置其中之一。 18. 如申請專利範圍第17項之半導體構造，其中： 該第一已處理半導體構造包括一電子信號處理器裝置；以及 該第二已處理半導體構造包括一電子記憶裝置、一發光二極體、一 雷射二極體，及一太陽能電池至少其中之一。 46 S201239970 VII. Patent application scope: 1. A method for forming a semiconductor device, comprising: providing a substrate comprising: a layer of semiconductor material on an electrical service material; and the layer on the substrate a first surface of one of the plurality of conductive materials opposite to the insulating material is formed to include a first metallization layer of a plurality of conductive members; forming a plurality of crystal bonds to at least partially pass therethrough, and forming the inter-wafer through Passing through at least one of the wafers through the metallization layer and the layer of semiconductor material; on the substrate, one of the layers of the semiconductor material opposite to the first surface of the layer of semiconductor material Forming a second metallization layer comprising one of a plurality of electrically conductive members; and forming a first processed semiconductor structure on the first side of the layer of semiconductor material carried by the substrate and carrying the layer on the layer A second processed semiconductor structure of the first side of the semiconductor material 'provides a continuous path through the first metallization layer' of the substrate, and one of the second metallization layers. 2. The method of claim 1, wherein forming at least one of the inter-wafer via bonds through the metallization layer and the layer of semiconductor material further comprises forming the crystals a method of interconnecting at least one of the inter-wafer vias through the layer of electrically insulating material. S 42 201239970 § ==(4) Item 1, further comprising at least one of the layers of the rotating material Adhesion of one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate. 4. The method of claim 3, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is adhered to the slit on the first side of the layer of semiconductor material to be included in the metal pair a metal direct hybrid-process towel that adheres at least one of the first processed semiconductor structure and the second processed semiconductor structure directly to the temperature at a temperature of less than about 4 〇〇〇C Substrate. 5. The method of claim 1, further comprising forming at least one of the first processed cast structure and the second processed semiconductor structure on the first side of the layer of semiconductor material On the substrate. 6. The method of claim i, wherein providing an electrical path further comprises configuring at least the electrical component of the electrical driving circuit to pass through the metallization layer and the layer At least one inter-wafer via connection of the plurality of crystal-transparent connections of the semiconductor material, at least one conductive component of the second metallization layer, and at least another inter-wafer via which the inter-wafer is transparently connected Through the link. 7. The method of claim 1, further comprising structurally and electrically connecting at least one of the electrically conductive members of the second metallization layer to the other electrically conductive member of the substrate. 43 201239970 8, the method of claim 1, further comprising selecting from the group consisting of: an electronic signal processor device, an electronic memory device, an electromagnetic radiation transmitter device, and an electromagnetic radiation receiver device The first processed semiconductor structure and the second processed semiconductor structure. 9. The method of claim 8, further comprising: the first processed semiconductor structure comprising: an electronic signal processor device; and the second processed semiconductor structure selected to include an electronic memory device, At least one of a light-emitting diode, a -f emitter, and a solar cell. a semiconductor structure comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate, the first side of the layer of semiconductor material; one of the substrates a second metallization layer on a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material; a plurality of inter-wafer via connections that at least partially pass through the first metallization layer and a layer of semiconductor material of the substrate; a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material; and a second processed semiconductor structure carried by the substrate on the layer of semiconductor First material 201239970, wherein the electrical path from the first processed semiconductor structure through the first metallization layer - the conductive member, the wafers The conductive members of the two metallization layers, and the second through-connections of the through-connections, extend to the second processed semiconductor structure. 11. The semiconductor construction of claim 1, wherein the substrate comprises a semiconductor-on-insulator (SeOI) substrate. A semiconductor construction according to claim 11 wherein at least the through-through junction of the inter-wafer via junctions at least partially passes through the layer of electrically insulating material. 13. The semi-structure of claim 1G, wherein at least one of the processed semiconductor structure and the second processed semiconductor structure is adhered to the substrate on a first side of the layer of semiconductor material. 14. The semiconductor construction of claim 13, wherein the first processed semiconductor structure and the second processed cast structure are at least a metal-to-metal bond of the towel directly bonded to the crystal-transparent connection At least _ one wafer is transparently connected. 15. The semiconductor structure of claim 1, wherein the electrical path extends continuously between the first processed semiconductor structure and the first processed semiconductor structure, through the substrate, the first a metallization layer' and the second metallization layer. The semiconductor construction of claim 10, wherein the at least one electrically conductive component of the second metallization layer is electrically coupled to one of the electrically conductive components of the other substrate. 17. The semiconductor construction of claim 10, wherein each of the first processed semiconductor structure and the second processed semiconductor structure comprises an electronic signal processor device, an electronic memory device, an electromagnetic radiation One of a transmitter device and an electromagnetic radiation receiver device. 18. The semiconductor construction of claim 17, wherein: the first processed semiconductor structure comprises an electronic signal processor device; and the second processed semiconductor structure comprises an electronic memory device, a light emitting diode, A laser diode, and at least one of a solar cell. 46 S
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