KR101288116B1 - An Array Substrate of Poly-Silicon Liquid Crystal Display Device and the method for fabricating thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a polysilicon liquid crystal display device having improved device performance and reliability by lowering a resistance of a gate wiring, and a manufacturing method thereof.

A feature of the present invention is characterized by further comprising an ITO pattern which also serves as a redundancy pattern in the gate wiring in order to lower the resistance of the gate wiring with high resistance.

Description

An array substrate for a polysilicon liquid crystal display device and a method for manufacturing the same

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display;

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3 is a plan view showing unit pixels of an array substrate for a polysilicon liquid crystal display according to a first embodiment of the present invention;

4A to 4G and FIGS. 5A to 5G are cross-sectional views taken along line IV-IV and V-V of FIG. 3 and shown in a process sequence.

6A to 6D and FIGS. 7A to 7D are cross-sectional views illustrating unit pixels of an array substrate for a polysilicon liquid crystal display according to a second exemplary embodiment of the present invention. In detail, lines IV-IV and V-V of FIG. Cross-sectional view showing the process sequence by cutting each.

Description of the Related Art [0002]

100: transparent substrate 120: gate wiring

125 gate electrode 130 data wiring

132: source electrode 134: drain electrode

141: polysilicon layer 170: pixel electrode

190: Redundancy pattern CH2: Drain contact hole

CH3, CH4: first and second gate contact holes T: thin film transistor

P: pixel area

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a bottom gate type polysilicon liquid crystal display device having improved device performance and reliability, and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for the use of portable information media, research and commercialization of lightweight thin-film flat panel display devices, which replace the existing display device, the Cathode Ray Tube (CRT) It is done.

In particular, active driving liquid crystal display devices have become mainstream in such flat panel displays. In an active driving liquid crystal display device, a thin film transistor is used as a switching element to change the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one unit pixel.

Among them, Liquid Crystal Display Device (LCD) is the most widely used, replacing the cathode ray tube (CRT) for mobile image display devices because of its excellent image quality, light weight, thinness, and low power consumption. It is being developed in various ways such as a monitor of a notebook computer.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. The liquid crystal panel may include a color filter substrate and an array substrate bonded together with a predetermined space, and the two It consists of the liquid crystal layer injected between the board | substrates.

In this case, the array substrate includes a plurality of gate wires arranged in one direction at a predetermined interval, a plurality of data wires crossing in a direction perpendicular to the gate wires, and each of the gate wires and data wires defined to cross each other. A plurality of pixel electrodes formed in a matrix form in each pixel area, and a plurality of thin film transistors that are switched by signals of the gate lines and transfer the signals of the data lines to each pixel electrode, are provided.

Here, it may be classified according to the silicon layer used as the active layer of the thin film transistor, which may be divided into a method of using amorphous silicon as an active layer and a polysilicon as an active layer.

The active layer using polysilicon has a carrier mobility of about 10 to 100 times faster than amorphous silicon, so that a driving circuit can be made on a substrate, and thus it is advantageous to use it as a switching element of a high resolution panel.

Accordingly, liquid crystal display devices using polysilicon as the active layer have been recognized as a technology for realizing next generation high performance intelligent display systems.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

1 and 2, a selected one of conductive metal groups such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo) and copper (Cu) is deposited on the transparent substrate 10, When the pattern is formed, the gate line 20 and the gate electrode 25 extending from the gate line 20 are formed in one direction.

The gate insulating layer 45 is formed on the entire upper surface of the substrate 10 on which the gate wiring and the electrodes 20 and 25 are formed, selected from a group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

Next, an active layer 40 and an ohmic contact layer 41 overlapping the gate electrode 25 and a portion of the gate insulating layer 45 are stacked on the gate insulating layer 45.

In this case, the active layer 40 is made of pure amorphous silicon, and the ohmic contact layer 41 is made of impurity amorphous silicon, respectively.

The active and ohmic contact layers 40 and 41 may be formed by plasma enhanced chemical vapor deposition (PECVD).

Depositing one or more selected from the group of conductive metals such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and copper (Cu) on the active and ohmic contact layers 40 and 41, When a drain metal layer (not shown) is formed and patterned, the drain metal layer (not shown) intersects with the gate line 20 to define a pixel area P and extends from the data line 30. The source electrode 32 and the drain electrode 34 spaced apart from each other are configured.

Here, the ohmic contact layer 41 exposed between the source and drain electrodes 32 and 34 is removed to expose the active layer 40.

In this case, the thin film transistor T includes the gate electrode 25, the active and ohmic contact layers 40 and 41, and the source and drain electrodes 32 and 34.

In addition, the passivation layer 55 is formed on the entire upper surface of the substrate 10 on which the source and drain electrodes 32 and 34 are formed, selected from a group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

Next, a pixel electrode 70 in contact with the drain electrode 34 is formed in the pixel region P through the drain contact hole CH1 exposing a portion of the drain electrode 34.

As described above, a conventional array substrate for a liquid crystal display device can be manufactured through the above-described process.

However, when the thin film transistor T used in the conventional array substrate for a liquid crystal display device is formed of amorphous silicon, it is difficult to manufacture a liquid crystal display device having a high speed response due to the low mobility of the carrier.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and by forming a polysilicon that can improve device characteristics through a magnetic field crystallization method, a bottom gate type polysilicon liquid crystal display device having a gate electrode formed at the bottom thereof can be manufactured. Can be.

In addition, an object of the present invention is to fabricate an array substrate for a liquid crystal display device having a high speed response by further forming a redundancy pattern connected in parallel with the resistance of the gate wiring.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes a substrate, a gate wiring formed in one direction on the substrate, a gate electrode extending from the gate wiring, and a perpendicular intersection with the gate wiring. A data line configured to extend in a direction, and a source electrode extending from the data line and a drain electrode spaced apart from the data line;

A semiconductor layer including a polysilicon layer, an amorphous silicon layer, and an ohmic contact layer interposed between the gate electrode and the source and drain electrodes, and a pixel electrode contacting the drain electrode through a drain contact hole; And a redundancy pattern for lowering resistance in contact with the gate wiring.

In this case, the gate electrode and the wiring is a high heat-resistant high resistance metal including molybdenum (Mo), molybdenum alloy (MoW) and chromium (Cr) is used, the pixel electrode and the redundancy pattern is a transparent conductive metal in the same layer Characterized in that consists of.

The redundancy pattern includes a transparent conductive metal and a low resistance metal, and the redundancy pattern overlaps the gate wiring and is configured in the same direction.

Here, the polysilicon layer is configured through a magnetic field crystallization process method, and the redundancy pattern serves as a repair function of the gate wiring.

According to a first aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: preparing a substrate, forming a gate wiring and a gate electrode on the substrate in one direction; Forming a gate insulating film on the substrate on which the gate electrode and the gate wiring are formed;

Forming a semiconductor layer in which an island-shaped polysilicon layer, an amorphous silicon layer, and an ohmic contact layer are stacked on the gate insulating layer corresponding to the gate electrode, data wiring on the substrate on which the semiconductor layer is formed, and Forming a source electrode extending from the data line, a drain electrode spaced apart from the data line, a pixel electrode in contact with the drain electrode, and a redundancy pattern in contact with the gate line.

And exposing the polysilicon layer by sequentially removing the ohmic contact layer and the amorphous silicon layer, which are exposed between the source and drain electrodes, and exposing the data wiring and the drain and electrode on a substrate on which the source and drain electrodes are formed. The method may further include forming a passivation layer having a part of an electrode, a drain contact hole exposing a part of each of the gate lines, and a plurality of gate contact holes.

In this case, the gate electrode and the wiring is a high heat-resistant high resistance metal including molybdenum (Mo), molybdenum alloy (MoW) and chromium (Cr) is used, the redundancy pattern is in contact with the gate wiring, the gate It overlaps with wiring and is formed in the same one direction, It is characterized by the above-mentioned.

The redundancy pattern serves as a repair function of a gate wiring, and the pixel electrode and the redundancy pattern include indium tin oxide (ITO) and indium zinc oxide (IZO).

In the forming of the island-shaped polysilicon layer, forming a pure amorphous silicon layer on the entire surface of the substrate on which the gate insulating layer is formed, and transferring the substrate on which the pure amorphous silicon layer is formed to a magnetic field crystallization process chamber. And heating the interior of the chamber to within a range of 500 ^° C. to 1000 ^° C .;

After fixing the substrate to the stage, aligning the first and second magnets on the top and bottom spaced apart from this, and crystallization by applying an alternating magnetic field through the first and second magnets to form a polysilicon layer And patterning it into an island shape.

In this case, the first and second magnets are characterized in that the scan proceeds.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including preparing a substrate, forming a gate wiring and a gate electrode on the substrate, and Forming a gate insulating film on the electrode and the wiring, and forming a semiconductor layer in which an island-shaped polysilicon layer, an amorphous silicon layer, and an ohmic contact layer are stacked on the gate insulating film corresponding to the gate electrode;

Forming a data line, a spaced source electrode and a drain electrode on the substrate on which the semiconductor layer is formed, a pixel electrode formed of a transparent conductive metal in contact with the drain electrode, and a transparent conductive metal in contact with the gate wiring And forming a redundancy pattern in which the low-resistance metal is stacked.

The method may further include exposing the polysilicon layer by sequentially removing the ohmic contact layer and the amorphous silicon layer that are exposed between the source and drain electrodes, and the drain on the substrate on which the data line and the source and drain electrodes are formed. The method may further include forming a passivation layer having a part of an electrode, a drain contact hole exposing a part of each of the gate lines, and a plurality of gate contact holes.

The low resistance metal is selected from the group of conductive metals including aluminum (Al) and aluminum alloy (AlNd).

The forming of the pixel electrode and the redundancy pattern simultaneously may include forming the transparent conductive metal layer, the low resistance metal layer in order, and applying a photoresist thereon to form a photoresist layer. Arranging a mask configured to have a transflective portion at a portion where the pixel electrode is to be formed and a cutoff portion at a portion where the redundancy pattern is to be formed, and a portion except for the transmissive portion;

The photoresist layer corresponding to the blocking portion remains as it is, and the photoresist layer corresponding to the transflective portion is in a lowered state through the process of exposing and developing the upper portion spaced apart from the mask. Removing all of the photoresist layer, and removing all of the low-resistance metal layer and the transparent conductive metal layer below that are exposed corresponding to the transmission part by using the remaining photoresist layer as a mask;

Ashing the remaining photoresist layer, the photoresist layer corresponding to the blocking portion is in a lowered state, and the photoresist layer corresponding to the transflective portion is all removed; and the remaining photoresist layer is removed. Using the mask as a mask, removing only the exposed low resistance metal layer to form a redundancy pattern in which the pixel electrode made of the transparent conductive metal, the transparent conductive metal and the low resistance metal are laminated, and removing the remaining photoresist layer. It includes a step.

Hereinafter, a polysilicon liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

--- First Embodiment ---

3 is a plan view illustrating unit pixels of an array substrate for a polysilicon liquid crystal display according to a first exemplary embodiment of the present invention.

As shown in the drawing, the gate line 120 and the gate electrode 125 extending from the gate line 120 are formed in one direction on the transparent substrate 100.

A data line 130, a source electrode 132 extending from the data line 130, and a drain electrode 134 spaced apart from each other are formed in a direction perpendicular to the gate line 120.

Here, an area defined by the gate line 120 and the data line 130 intersecting with each other is referred to as a pixel area P.

A thin film transistor T is formed at a portion where the gate line 120 and the data line 130 cross each other, wherein the thin film transistor T is a gate electrode 125 and source and drain electrodes 132 and 134. And a polysilicon layer 141, an amorphous silicon layer (not shown), and an ohmic contact layer (not shown) interposed therebetween.

In this case, the semiconductor layer is formed by including the polysilicon layer 141, an amorphous silicon layer, and an ohmic contact layer (not shown).

Here, the polysilicon layer 141 is exposed between the source electrode 132 and the drain electrode 134, and the exposed portion becomes an active channel.

The pixel electrode 170, which is in contact with the drain electrode 134 and the drain contact hole CH2, is formed in the pixel region P.

In addition, the gate wiring 120 formed in one direction and the redundancy pattern 190 contacted through the plurality of contact holes CH3 and CH4 are overlapped to correspond to the gate wiring 120.

By forming the polysilicon layer 141 through the magnetic field crystallization process method in the above-described configuration, it can have excellent device performance and reliability, and is connected in parallel with the gate wiring 120 by the same material as the pixel electrode 170. By further configuring the redundancy pattern 190 to be characterized in that the resistance of the gate wiring 120 can be lowered.

As a result, an integrated circuit can be realized and a high-speed response can be produced, whereby a high-quality liquid crystal display device can be manufactured.

Hereinafter, a method of manufacturing an array substrate for a polysilicon liquid crystal display according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

4A to 4G and FIGS. 5A to 5G are cross-sectional views taken along line IV-IV and V-V of FIG. 3 and shown in a process sequence.

As shown in FIGS. 4A and 5A, one or more materials selected from the group of conductive metals are deposited on the transparent substrate 100 and patterned to form the gate wiring 120 and the gate wiring 120 in one direction. ) To form a gate electrode 125.

Here, the conductive metal is a high resistance metal, such as molybdenum (Mo), molybdenum alloy (MoW) and chromium (Cr). The reason is that the process using the magnetic field crystallization method which proceeds to the subsequent process usually proceeds to a high temperature process close to 700 ^o C, it is impossible to use aluminum (Al) and aluminum alloy (AlNd), a low resistance material that is susceptible to high temperature Because.

Next, a gate insulating layer is formed by depositing one selected from a group of inorganic insulating materials such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire upper surface of the substrate 100 on which the gate wiring 120 and the gate electrode 125 are formed. 145 is formed.

4B and 5B, a first pure amorphous silicon layer 141a is formed on the substrate 100 on which the gate insulating layer 145 is formed.

Next, as shown in FIGS. 4C to 5C, the substrate 100 on which the first pure amorphous silicon layer (141a of FIG. 4B) is formed is transferred to the magnetic field crystallization process chamber 195.

The magnetic field crystallization process chamber 195 is performed in a high temperature atmosphere of about 500 ^° C. to 1000 ^° C., and the substrate 100 having the first pure amorphous silicon layer (141a of FIG. 4B) formed therein. It is characterized by generating an alternating magnetic field (AMF) in spaced upper and lower portions.

Next, the substrate 100 on which the first pure amorphous silicon layer 141a of FIG. 4B is transferred to the magnetic crystallization chamber 195 is fixed to a stage (not shown), and spaced apart from the upper and lower magnets. align (magnet: 185, 186), respectively. In this case, the upper and lower magnets 185 and 186 may be scanned.

Therefore, after making the inside of the chamber 195 in a high temperature atmosphere, the vertical alternating magnetic field (AMF) is applied using the upper and lower magnets 185 and 186.

Through this vertical alternating magnetic field (AMF), crystallization proceeds gradually to the first pure amorphous silicon layer (141a of FIG. 4B), and the first pure amorphous silicon layer of the entire substrate 100 is scanned (FIG. 4B). 141a is crystallized to form the polysilicon layer 141.

When explaining the principle of the alternating magnetic field (AMF), the main energy source of crystallization is heat, the alternating magnetic field (AMF) plays a secondary role. At this time, a current is induced inside the first pure amorphous silicon layer (141a of FIG. 4B) by the alternating magnetic field (AMF), and the joule heat is generated by the induced internal current, thereby further accelerating crystallization. The alternating magnetic field (AMF) is applied to move the atoms to promote crystallization.

Next, as shown in FIGS. 4D and 5D, a second pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are stacked on the substrate 100 on which the polysilicon layer 141 is formed. The polysilicon layer 141, the amorphous silicon layer, and the ohmic contact layers 142 and 143 are formed by patterning the polysilicon layer 141.

Accordingly, the semiconductor layer 140 is formed by including the polysilicon layer 141, the amorphous silicon layer, and the ohmic contact layers 142 and 143.

As shown in FIGS. 4E and 5E, a conductive metal such as molybdenum (Mo), molybdenum alloy (MoW), aluminum alloy (AlNd), chromium (Cr), and the like on the substrate 100 on which the semiconductor layer 140 is formed. And depositing one or more selected from the group, patterning the data line 130 perpendicularly to the gate line 120, the source electrode 132 extending from the data line 130, and A spaced drain electrode 134 is formed.

Next, the ohmic contact layer 143 exposed between the source electrode 132 and the drain electrode 134 and the active layer 142 below are sequentially removed to expose the polysilicon layer 141. This part is used as a channel ch.

As shown in FIGS. 4F and 5F, silicon nitride (SiNx), silicon oxide (SiO ₂ ), and the like are formed on the entire upper surface of the substrate 100 where the data line 130 and the source and drain electrodes 132 and 134 are formed. The passivation layer 155 is formed of one selected from the group of inorganic insulating materials or one selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin.

Next, the protective layer 155 corresponding to each of the drain electrode 134 and the gate line 120 is removed to form the drain contact hole CH2 and the plurality of gate contact holes CH3 and CH4, respectively. .

Next, as shown in FIGS. 4G and 5G, indium tin oxide (ITO) is formed on the passivation layer 155 including the drain contact hole CH2 and the plurality of gate contact holes CH3 and CH4. One selected from the group of transparent conductive metals including and indium zinc oxide (IZO) is deposited and patterned to form a pixel electrode 170 in contact with the drain electrode 134 in the pixel region P. Referring to FIG.

At the same time, the redundancy pattern 190, which is in contact with the gate wiring 120 through the plurality of gate contact holes CH3 and CH4, overlaps the gate wiring 120 to be formed in one direction.

As described above, the array substrate for the polysilicon liquid crystal display device can be manufactured through the above-described process.

Therefore, in the present invention, the device performance and reliability can be secured by forming the polysilicon layer by the magnetic field crystallization process method, and the resistance of the gate wiring can be lowered through a redundancy pattern configured in parallel with the gate wiring.

Through this, problems such as signal delay can be prevented, and thus an array substrate for a liquid crystal display device of high quality can be manufactured.

In addition, disconnection of the gate wiring can be repaired.

At this time, although the resistance of ITO (or IZO) is generally higher than that of the conductive metal material in the above-described process, when configured in parallel with the gate wiring, the resistance of the ITO // Gate parallel wiring is higher than that of the gate wiring. The total resistance is lower.

If this is expressed as an equation,

to be. However, since the resistance of ITO (or IZO) generally has a higher resistance than the conductive metal material, there is a limit to lowering the total resistance even in parallel configuration.

Hereinafter, a method of further lowering the total resistance of the gate wiring will be described with reference to the accompanying drawings.

--- Second Embodiment ---

The second embodiment of the present invention is a somewhat modified version of the first embodiment, and duplicate description thereof will be omitted.

The second embodiment of the present invention is in plan view, similar to the first embodiment, and description thereof is to be avoided. In the first embodiment, after the data wiring and the source and drain electrodes are formed, the step No. 100 is shown in the figure. Add them.

In the second embodiment of the present invention, a low resistance conductive metal is further formed on the ITO to further lower the total resistance of the gate wiring.

6A to 6D and FIGS. 7A to 7D are cross-sectional views taken along lines IV-IV and V-V of FIG. 3 and shown in the order of process, and are indicated by lines VI-VI and X-VIII.

As shown in FIGS. 6A and 7A, silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be formed on the entire upper surface of the substrate 200 on which the data line 230 and the source and drain electrodes 232 and 234 are formed. The protective film 255 is formed by one selected from the group of inorganic insulating materials or one selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin.

Next, the protective layer 255 corresponding to each of the drain electrode 234 and the gate line 220 is removed to form the drain contact hole CH5 and the plurality of gate contact holes CH6 and CH7, respectively. .

6B and 7B, indium-tin-oxide (ITO) and indium- are formed on the passivation layer 255 including the drain contact hole CH5 and the plurality of gate contact holes CH6 and CH7. One selected from the group of transparent conductive metals including zinc oxide (IZO) and one or more selected from the group of low resistance metals are sequentially deposited to form a transparent conductive metal layer 270a and an opaque conductive metal layer 270b. Then, a photoresist layer 280 is laminated and formed thereon.

Next, the halftone mask 295 is aligned with the substrate 200 on which the photoresist layer 280 is formed.

The halftone mask 295 is a mask composed of a transmissive part AA, a blocking part CA, and a transflective part BA. The halftone mask 295 forms a blocking part corresponding to the gate area G, and a part of the pixel electrode to be formed is The transflective part BA is constituted, except for the part that constitutes the transmissive part AA.

Next, when the exposure and development processes are performed on the upper part spaced apart from the mask 295, the photoresist layer 280 corresponding to the transmissive part AA is completely removed and the transmissive part BA corresponds to the transmissive part BA. The photoresist layer 280 is in a lowered state, and the photoresist layer 280 corresponding to the blocking part CA is present as it is.

Then, using the remaining photoresist layer 280 as a mask, all of the exposed opaque conductive metal layer 270b and the lower transparent conductive metal layer 270a are removed.

As shown in FIGS. 6C and 7C, when the remaining photoresist layer 280 is deposited, the height of the photoresist layer 280 corresponding to the blocking part CA is lowered. The photoresist layer 280 corresponding to the transflective portion BA is completely removed.

Subsequently, using the remaining photoresist layer 280 as a mask, only the opaque conductive metal layer 270b exposed corresponding to the semi-transmissive portion BA is removed to expose the transparent conductive metal layer 270a.

Thereafter, as shown in FIGS. 6D and 7D, the remaining photoresist layer 280 is removed by a strip process.

Through the above-described process, the pixel electrode 270 in contact with the drain electrode 234 and the drain contact hole CH5 is formed of a transparent conductive metal.

At the same time, the redundancy pattern 290 contacting the gate line 220 and the plurality of gate contact holes CH6 and CH7 is a double layer in which a transparent conductive metal and an opaque conductive metal are stacked. The gate wiring 220 ) And overlaps with each other.

Although only the halftone mask has been described in the above-described process, the same result can be obtained by using the slit mask. In this case, the slit mask is to form a desired pattern by controlling the transmission amount according to the slit by using diffraction exposure.

As described above, the array substrate for the polysilicon liquid crystal display according to the second embodiment of the present invention can be manufactured through the above-described process.

In this case, by further forming a low resistance metal on the redundancy pattern made of ITO (or IZO) in the above-described process, the total resistance can be further lowered.

If this is expressed as an equation,

to be. Therefore, as described above, by configuring the redundancy pattern with a double layer made of a transparent conductive metal and a low resistance metal, it is possible to actively cope with the high speed response by further lowering the total resistance of the gate wiring.

Accordingly, in the present invention, by forming the polysilicon layer by the magnetic field crystallization process method, device characteristics and reliability can be ensured, and signal delay can be prevented by lowering the resistance of the gate wiring.

In the present invention, the polysilicon layer can be formed by the magnetic field crystallization process method, the device characteristics and reliability can be improved, the resistance of the gate wiring can be lowered, and problems such as signal delay can be prevented.

Accordingly, an integrated circuit can be implemented, and an array substrate for a high quality liquid crystal display device can be manufactured by preventing signal delay.

In addition, when a defect such as disconnection occurs in the gate wiring, the redundancy pattern has a function of repair, thereby improving the production yield.

Claims (19)

A substrate; A gate wiring formed on the substrate in one direction and a gate electrode extending from the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; A semiconductor layer on the gate insulating layer and corresponding to the gate electrode, the semiconductor layer including a polysilicon layer, an amorphous silicon layer, and an ohmic contact layer; A data line positioned on the gate insulating layer and crossing the gate line; A source electrode on the semiconductor layer, the source electrode extending from the data line and the drain electrode spaced apart from the source electrode; A protective layer having the data line, the source electrode, the drain electrode, a drain contact hole exposing the drain electrode, and a gate contact hole exposing the gate wire; A pixel electrode on the protective layer and in contact with the drain electrode through the drain contact hole; A redundancy pattern on the protective layer and in contact with the gate line through the gate contact hole And a plurality of pixel electrodes. The method of claim 1, And the gate electrode and the gate wiring are made of a high resistance metal having high heat resistance, including molybdenum (Mo), molybdenum alloy (MoW), and chromium (Cr). The method of claim 1, And the pixel electrode and the redundancy pattern are made of a transparent conductive metal in the same layer. The method of claim 1, The redundancy pattern is a liquid crystal display device array substrate, characterized in that the transparent conductive metal and low resistance metal is laminated. The method according to any one of claims 1 to 4, And said redundancy pattern overlaps said gate wiring and is configured in the same direction as said gate wiring. The method of claim 1, And the polysilicon layer is formed through a magnetic field crystallization process method. Claim 7 has been abandoned due to the setting registration fee. The method of claim 1, And the redundancy pattern serves as a repair function of the gate wiring. Preparing a substrate; Forming a gate wiring and a gate electrode on the substrate in one direction; Forming a gate insulating film on the substrate on which the gate electrode and the gate wiring are formed; Forming a semiconductor layer in which an island-shaped polysilicon layer, an amorphous silicon layer, and an ohmic contact layer are stacked on the gate insulating layer corresponding to the gate electrode; Forming a data line, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode on a substrate on which the semiconductor layer is formed; Forming a protective layer covering the data line, the source electrode, the drain electrode, a drain contact hole exposing the drain electrode, and a gate contact hole exposing the gate wire; Forming a pixel electrode in contact with the drain electrode through the drain contact hole and a redundancy pattern in contact with the gate wiring through the gate contact hole on the protective layer; And a plurality of pixel electrodes formed on the substrate. delete 9. The method of claim 8, And the gate electrode and the gate wiring are made of a high resistance metal having high heat resistance, including molybdenum (Mo), molybdenum alloy (MoW), and chromium (Cr). 9. The method of claim 8, And said redundancy pattern overlaps said gate wiring and is formed in the same direction as said gate wiring. Claim 12 is abandoned in setting registration fee. 9. The method of claim 8, And said redundancy pattern serves as a repair function of said gate wiring. 9. The method of claim 8, The pixel electrode and the redundancy pattern include indium tin oxide (ITO) and indium zinc oxide (IZO). 9. The method of claim 8, In the forming of the island-like polysilicon layer, Forming a pure amorphous silicon layer on the entire surface of the substrate on which the gate insulating film is formed; Transferring the substrate on which the pure amorphous silicon layer is formed to a magnetic field crystallization process chamber; Heating the interior of the chamber to a range within 500 ^° C. and 1000 ^° C .; Fixing the substrate to a stage, and then aligning the first and second magnets on top and bottom spaced therefrom; Applying an alternating magnetic field through the first and second magnets to perform crystallization to form a polysilicon layer, and patterning it in an island shape And a plurality of pixel electrodes formed on the substrate. Claim 15 is abandoned in the setting registration fee payment. 15. The method of claim 14, The first and second magnets are manufactured by a scanning method, characterized in that the array substrate for a liquid crystal display device. Preparing a substrate; Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the gate electrode and the gate wiring; Forming a semiconductor layer in which an island-shaped polysilicon layer, an amorphous silicon layer, and an ohmic contact layer are stacked on the gate insulating layer corresponding to the gate electrode; Forming a data line, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode on a substrate on which the semiconductor layer is formed; Forming a protective layer covering the data line, the source electrode, the drain electrode, a drain contact hole exposing the drain electrode, and a gate contact hole exposing the gate wire; Forming a redundancy pattern in which the pixel electrode is in contact with the drain electrode through the drain contact hole and is formed of a transparent conductive metal, and the transparent conductive metal and the low resistance metal are in contact with the gate wiring through the gate contact hole. And a plurality of pixel electrodes formed on the substrate. The method according to any one of claims 8 to 16, And removing the ohmic contact layer and the amorphous silicon layer sequentially exposed between the source and drain electrodes to expose the polysilicon layer. 17. The method of claim 16, The low resistance metal is selected from the group of conductive metals including aluminum (Al) and aluminum alloy (AlNd). 17. The method of claim 16, Simultaneously forming a redundancy pattern with the pixel electrode, Forming a transparent resistive metal layer and a low resistance metal layer in order on the protective layer, and then applying a photoresist thereon to form a photoresist layer; Arranging a mask on the spaced upper portion of the photoresist layer, a portion of which the pixel electrode is to be formed is a transflective portion and a portion of which the redundancy pattern is to be formed is a blocking portion; The photoresist layer corresponding to the blocking portion remains as it is, and the photoresist layer corresponding to the transflective portion is in a lowered state through the process of exposing and developing the upper portion spaced apart from the mask. Removing all of the photoresist layer; Using the remaining photoresist layer as a mask, removing all of the low-resistance metal layer and the transparent conductive metal layer exposed below the transparent portion; Ashing the remaining photoresist layer so that the photoresist layer corresponding to the blocking portion is in a lowered state, and all the photoresist layers corresponding to the transflective portion are removed; Removing only the exposed low resistance metal layer by using the remaining photoresist layer as a mask to form a redundancy pattern in which the pixel electrode made of the transparent conductive metal and the transparent conductive metal and the low resistance metal are stacked; Removing the remaining photoresist layer And a plurality of pixel electrodes formed on the substrate.

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