KR101277937B1 - LCD and drive method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of reducing horizontal crosstalk by dividing a plurality of common electrodes of a liquid crystal display panel and applying common voltages electrically separated from each other to the divided common electrodes. will be.

In the liquid crystal display according to the present invention, a plurality of common electrode groups are formed to form an electric field and face each other and are electrically separated from the pixel electrodes supplied with the data voltage in the effective display area. A liquid crystal display panel to which common electrodes are commonly connected; A plurality of common voltage signal wirings formed in a dummy area in the liquid crystal display panel positioned outside the effective display area of the liquid crystal display panel so as to be connected to the plurality of common electrode groups one-to-one; A common voltage generator for generating a common voltage; Differentially amplifying a feedback common voltage having a swing value fed back from one or more of the common electrodes of the liquid crystal display panel and the common voltage from the common voltage generator at a variable amplification ratio and supplying them to the plurality of common voltage signal lines; A common voltage compensator; And a timing controller configured to control an amplification ratio of the common voltage compensator according to the swing value of the feedback common voltage.

Description

Liquid crystal display and driving method thereof

1 is a view schematically showing a liquid crystal display device in a general IPS mode.

2 is a diagram showing the structure of common voltage signal wiring;

3A is a view showing a specific pattern displayed by the dot inversion driving method.

FIG. 3B is a drive waveform diagram for the specific pattern shown in FIG. 3A. FIG.

4 is a waveform diagram illustrating that the common voltage is shaken in the positive direction or the negative direction in units of a horizontal period (H).

5 and 6 are views for explaining horizontal crosstalk in a peripheral screen extending in a horizontal direction by a specific pattern in a liquid crystal display panel driven by a dot inversion method.

7 is a waveform diagram illustrating that the distortion of the common voltage is intensified toward the bottom of the liquid crystal display panel.

8 is a configuration diagram of a liquid crystal display according to an embodiment of the present invention.

9 is a diagram illustrating a liquid crystal display panel of FIG. 8.

FIG. 10 is a circuit diagram illustrating a common voltage compensator of FIG. 8. FIG.

11 and 12 are circuit diagrams illustrating an example of the negative feedback resistor of FIG. 10.

13A and 13B are waveform diagrams of common voltages in a liquid crystal display panel according to an exemplary embodiment of the present invention.

14 is a block diagram of a liquid crystal display according to another embodiment of the present invention.

15 is a schematic view of a gate integrated part of a liquid crystal display according to another exemplary embodiment of the present invention.

16 is a view for explaining an example of a switching operation of a common voltage output buffer;

17A to 17C are diagrams for describing in detail a switching operation of the second buffer array of FIG. 15 according to a gate shift clock;

18 is a waveform diagram of a common voltage in a liquid crystal display panel according to another exemplary embodiment of the present invention.

Description of the Related Art

110 and 210: liquid crystal display panels 120 and 220: data driver

130 and 230: gate driver 140 and 240: timing controller

150, 250: common voltage generator 160: common voltage compensator

162: inverted amplifier 164: buffer

232: gate integrated section 234: shift register block

236: level shifter block 238: output buffer block

238-1: first buffer array 238-2: second buffer array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof. In particular, horizontal crosstalk is reduced by dividing a plurality of common electrodes of a liquid crystal display panel and applying common signals electrically separated from each other to the divided common electrodes. The present invention relates to a liquid crystal display device and a driving method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned at the intersections of the gate lines and the data lines. Each of the liquid crystal cells is provided with pixel electrodes and a common electrode for applying an electric field. Each of the pixel electrodes is connected to one of the data lines via a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line. Accordingly, the liquid crystal array between the pixel electrode and the common electrode is changed according to the pixel voltage signal for each liquid crystal cell, thereby adjusting the light transmittance so that the liquid crystal display panel displays an image.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signal, that is, the gate signal to the gate lines, to sequentially drive the liquid crystal cells on the liquid crystal display panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode.

Such liquid crystal display devices are roughly classified into twisted nematic (TN) mode in which a vertical electric field is applied and in plane switch (IPS) mode in which a horizontal electric field is applied according to the direction of the electric field driving the liquid crystal.

The TN mode is a mode in which the liquid crystal is driven by a vertical electric field between the pixel electrode and the common electrode disposed opposite to each other on the upper and lower substrates, and has a large aperture ratio but a narrow viewing angle. The IPS mode is a mode in which a liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on the lower substrate, and has a large viewing angle, but a small aperture ratio.

FIG. 1 is a diagram schematically showing a liquid crystal display device in a general IPS mode, and FIG. 2 is a diagram illustrating a structure of a common voltage signal line.

The liquid crystal display of the IPS mode shown in FIG. 1 includes a thin film transistor TFT formed at each intersection of a plurality of data lines DLm and gate lines GLn, a thin film transistor TFT, and a common voltage line VcomLn. And a liquid crystal cell connected between each other.

The gate lines GLn and the data lines DLm cross each other. The plurality of common voltage signal lines VcomL1 to VcomLn are arranged side by side alternately with the gate lines GL0 to GLn-1 (not shown). The gate lines GLn supply a scan signal, and the data lines DLm supply a data signal. The common voltage signal lines VcomL1 to VcomLn supply a reference voltage to each liquid crystal cell. To this end, the common voltage signal lines VcomL1 to VcomLn are commonly connected to the common voltage signal wiring 20 formed on the left and right sides of the liquid crystal display panel 40 as shown in FIG. 2. The thin film transistor TFT causes the liquid crystal cell to charge a data signal from any one of the data lines DLm in response to a scan signal from any one of the gate lines GLn. The liquid crystal cell Clc includes a liquid crystal capacitor including a pixel electrode Ep and a common electrode Ec formed side by side on the lower substrate. The pixel electrode Ep is connected to the thin film transistor TFT, and the common electrode Ec is connected to any one of the common voltage signal lines VcomL1 to VcomLn. The liquid crystal cell includes a storage capacitor Cst formed at an overlapping portion of the pixel electrode Ep and the previous gate line with an insulating layer therebetween. The storage capacitor Cst maintains the data signal charged in the liquid crystal capacitor for one frame. The liquid crystal cell realizes gradation by adjusting the light transmittance by varying the arrangement state of the liquid crystal having dielectric anisotropy according to the charged data signal.

The liquid crystal display device is driven in an inversion method in which the polarity of the data signal is inverted at regular intervals to prevent deterioration and afterimage of the liquid crystal cell. Inversion methods include a dot inversion method, a line inversion method, and a frame inversion method.

The frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. The line inversion method inverts the polarities of the data signals supplied to the liquid crystal cells in line (low line or column line) units and inverts them in frame units. The dot inversion method inverts the data signals supplied to the liquid crystal cells in dot units and inverts them in frame units. Among them, the dot inversion method has an advantage of providing an image of excellent image quality compared to other methods. However, the dot inversion driving method has a disadvantage in that the horizontal crosstalk phenomenon occurs when the specific pattern shown in FIG. 3A is displayed, thereby degrading the image quality.

3A is a view showing a specific pattern displayed by the dot inversion driving method, and FIG. 3B is a driving waveform diagram for the specific pattern shown in FIG. 3A.

Each of the liquid crystal cells illustrated in FIG. 3A corresponds to each of the red, green, and blue liquid crystal cells (R, G, and B). The red, green, and blue liquid crystal cells R, G, and B are arranged side by side in a stripe shape. The liquid crystal cells R, G, and B are driven in a dot inversion manner, and thus polarities of data signals between adjacent liquid cells in the horizontal and vertical directions are inverted.

Here, the liquid crystal cells R, G, and B display a specific pattern, that is, a vertical stripe pattern, in which white gray (for example, 255 gray) and black gray alternate in a column line unit in a normal black mode. To this end, as illustrated in FIG. 3B, the i-th horizontal line Hi has the polarity of the data signal Vd_255 corresponding to 255 gray and the data signal Vd_0 corresponding to black gray based on the common voltage Vcom. Alternately supplied. In addition, as shown in FIG. 3B, the i + 1 th horizontal line Hi + 1 also has a data signal Vd_255 corresponding to 255 gray and a data signal Vd_0 corresponding to black gray as shown in FIG. 3B. Are alternately supplied with different polarities. Here, the data signal Vd supplied to the i + 1 th horizontal line Hi + 1 has a polarity opposite to that of the data signal Vd supplied to the i th horizontal line Hi.

In this case, since the average level of the data signal supplied to the i-th horizontal line Hi is larger in the positive polarity than in the negative polarity based on the common voltage Vcom, the common voltage Vcom signal is shown in FIG. 4. Is swinged in the positive direction by a capacitor coupling effect with the positive data signal. In addition, since the average level of the data signal supplied to the i + 1th horizontal line Hi + 1 is larger in the negative polarity than in the positive polarity based on the common voltage Vcom, the common voltage ( The Vcom) signal is swinged in the negative direction by a capacitor coupling effect with the negative data signal. When the data signal for displaying a specific pattern is supplied in a horizontal unit, the common voltage Vcom is in the positive direction or the negative direction in units of the horizontal period H as shown in FIG. 4 according to the average level of the data signal. The swinging phenomenon occurs. The common voltage Vcom swing phenomenon also affects the peripheral screen extending in the horizontal direction as shown in FIG. 5 to generate horizontal crosstalk in the peripheral screen.

FIG. 5 is a diagram for describing horizontal crosstalk in a peripheral screen extending in a horizontal direction by a specific pattern in a liquid crystal display panel driven by a dot inversion method.

Referring to FIG. 5, when a window B displaying a vertical stripe pattern, which is a specific pattern, is floated on a portion of the liquid crystal display panel image display unit 60, a horizontal cross having a vertical stripe shape is formed in the peripheral screen C extending in the horizontal direction of the window B. It can be seen that the torque pattern is generated. This is because the common voltage fluctuates toward the positive or negative polarity according to the average level of the data signal in units of horizontal periods even in the peripheral screen due to the vertical stripe pattern displayed in the window B. FIG.

For example, when the average level of the data signal in the i-th horizontal line Hi is large due to the vertical stripe pattern displayed in the window B, the common voltage swings toward the positive polarity. The swing of the common voltage level affects the i-th horizontal line Hi extending to the outside of the window B as shown in FIG. 6. In FIG. 6, the voltage difference between the positive data signal Vdo and the common voltage Vcom is relatively relatively due to the common voltage Vcom swinging toward the positive polarity in the odd-numbered liquid crystal cell in which the positive data signal Vdo is charged. As it shrinks, it looks darker in normal black mode. In contrast, in the even-numbered liquid crystal cell in which the negative data signal Vde is charged, the voltage difference between the negative data signal Vde and the common voltage Vcom is relatively increased by the common voltage Vcom swinging toward the positive polarity. It will look brighter.

In addition, when the average level of the data signal is negative in the i + 1th horizontal line Hi + 1 due to the vertical stripe pattern displayed in the window B, the common voltage swings toward the negative polarity. This ripple of the common voltage level is affected as shown in FIG. 6 in the i + 1th horizontal line Hi + 1 extending to the outside area of the window B. FIG. In FIG. 6, the voltage difference between the negative data signal Vdo and the common voltage Vcom is relative to the odd-numbered liquid crystal cell in which the negative data signal Vdo is charged due to the common voltage Vcom swinging toward the negative side. As it is reduced to, it will appear darker in normal black mode. In contrast, in the even-numbered liquid crystal cell in which the positive data signal Vde is charged, the voltage difference between the positive data signal Vde and the common voltage Vcom is relatively increased by the common voltage Vcom swinging toward the negative polarity. As it gets brighter.

As a result, even when data signals of the same gray level are applied to the regions A and C except for the window B, the common voltage swing phenomenon caused by the vertical stripe pattern displayed on the window B affects the peripheral region C in the horizontal direction of the window B. As described above, the luminance difference occurs between the odd-numbered liquid crystal cell and the even-numbered liquid crystal cell in the "C" region. As a result, as shown in FIG. 5, horizontal crosstalk patterns such as vertical stripes are generated in the peripheral area C of the window B, thereby degrading image quality.

This horizontal crosstalk phenomenon is caused by an increase in line resistance of the common voltage signal lines as well as the common voltage signal line 20 as the display data is positioned in the "D" direction (the lower direction of the liquid crystal display panel) as shown in FIG. Is caused more severely. This is because the current component of the common voltage signal decreases in proportion to the increase in the line resistance of the common voltage signal lines and the common voltage signal wiring 20, so that the common voltage signal is as much as the average of the data signal. This is because the swing is large depending on the level.

If a line on glass (LOG) method is used in which a plurality of signal lines including a common voltage signal wiring are mounted on a lower substrate for thinning of a liquid crystal display device, the common voltage signal wiring and a common voltage are used. Since the overall line length for the voltage signal line increases by that much, the above problem becomes larger.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of preventing horizontal crosstalk caused by a decrease in the current component of a common signal charged according to the position of the display data on the liquid crystal display panel.

In order to achieve the above object, the liquid crystal display according to the exemplary embodiment of the present invention has a plurality of common electrode groups that form an electric field and are electrically separated from each other in the effective display area to face pixel electrodes supplied with a data voltage. A liquid crystal display panel having a plurality of common electrodes connected to each of the common electrode groups; A plurality of common voltage signal wirings formed in a dummy area in the liquid crystal display panel positioned outside the effective display area of the liquid crystal display panel so as to be connected to the plurality of common electrode groups one-to-one; A common voltage generator for generating a common voltage; Differentially amplifying a feedback common voltage having a swing value fed back from one or more of the common electrodes of the liquid crystal display panel and the common voltage from the common voltage generator at a variable amplification ratio and supplying them to the plurality of common voltage signal lines; A common voltage compensator; And a timing controller configured to control an amplification ratio of the common voltage compensator according to the swing value of the feedback common voltage.

The feedback common voltage is formed on one side of the liquid crystal display panel and fed back from a feedback dedicated line connected to any one or more of the common electrodes.

The timing controller may include an analog-digital converter configured to convert the swing value of the feedback common voltage into a digital signal; And a memory for storing an amplification factor control signal corresponding to the swing value of the feedback common voltage converted into the digital signal as a look-up table.

The common voltage compensator may include an inverting amplifier configured to generate a common voltage compensation signal by inverting and amplifying the feedback common voltage based on the common voltage in response to the amplification rate control signal; And a buffer unit connected to an output terminal of the inversion amplifier unit to stabilize the common voltage compensation signal.

The inverting amplifier may include a plurality of negative feedbacks in which a combined resistance value is determined according to an inverting input terminal to which the feedback common voltage is input through a series connected capacitor and a resistor, a non-inverting input terminal to which the common voltage is input, and the amplification rate control signal. And a differential amplifier comprising an output terminal connected to the inverting input terminal through resistors.

The negative feedback resistors are connected in series with each other between the inverting input terminal and the output terminal; And a plurality of switch elements connected in parallel one-to-one with each of the negative feedback resistors and switched according to the digital logic value of the amplification rate control signal to switch current flow through the negative feedback resistors.

One side of the negative feedback resistors is commonly connected in parallel to the inverting input terminal; A plurality of one-to-one serial connection with each of the negative feedback resistors between the other side of the negative feedback resistors and the output terminal and switched according to a digital logic value of the amplification rate control signal to switch current flow through the negative feedback resistors. It further comprises a switch element of.

According to another exemplary embodiment of the present invention, a thin film transistor is formed at an intersection of a plurality of gate lines and a plurality of data lines in an effective display area, and forms an electric field opposite to pixel electrodes supplied with a data voltage. A liquid crystal display panel including a plurality of common electrodes for supplying a common signal to the common electrodes and having a plurality of common electrode lines separated in one-to-one correspondence with the gate lines; A common voltage generator configured to generate a charging common signal supplied to the common electrode lines corresponding to the activated liquid crystal cells and a maintenance common signal supplied to the remaining common electrode lines corresponding to the deactivated liquid crystal cells; The scan signal is sequentially supplied to the gate line to select the activated liquid crystal cells, and the common electrode for charging is supplied to the common electrode line connected to the common electrode of the activated liquid crystal cells, while the deactivated The remaining common electrode lines connected to the common electrodes of the liquid crystal cells may include a gate driver configured to supply the holding common signal having a current component different from that of the charging common signal; And a timing controller for controlling the gate driver.

The timing controller designates a time period during which the gate of the thin film transistor is turned on and indicates a shift of the scan signal, a gate output signal for controlling the output of the gate driver, and the plurality of scans. A gate start pulse is generated to indicate a point in time at which the first scan signal is generated.

The gate driver includes a plurality of gate integrated units.

The gate integrated part may include: a shift register connected in a dependent manner and including a plurality of stages sequentially generating an output in response to any one of the gate start pulse and a previous output and the gate shift clock; A level shifter for adjusting a swing width of output signals of the shift register; A first buffer array including a plurality of buffers connected between the output terminals of the level shifter and the gate lines; And a plurality of buffers connected between the output terminals of the common voltage generator and the common electrodes and switching between the charging common signal and the sustain common signal in response to the gate shift clock. Equipped.

The current component of the charging common signal is larger than the current component of the holding common signal.

According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device having a plurality of common electrodes forming an electric field facing pixel electrodes supplied with a data voltage in an effective display area of the liquid crystal display panel may include a common voltage. Generating; The dummy area in the liquid crystal display panel is disposed outside the effective display area of the liquid crystal display panel so as to divide the plurality of common electrodes into a plurality of common electrode groups electrically separated from each other, and to be connected one-to-one to the plurality of common electrode groups. Supplying the common voltage to a plurality of common voltage signal lines formed in the plurality of common voltage signals; Receiving a feedback of a common voltage having a swing value from at least one of the common electrodes of the liquid crystal display panel; Generating an amplification rate control signal according to a swing value of the feedback common voltage; And differentially amplifying the feedback common voltage and the common voltage from the common voltage generator in response to the amplification rate control signal and supplying the plurality of common voltage signal lines.

According to another exemplary embodiment of the present invention, thin film transistors are formed in an intersection area of a plurality of gate lines and a plurality of data lines in an effective display area of a liquid crystal display panel, and an electric field is formed to face pixel electrodes supplied with a data voltage. A driving method of a liquid crystal display device having a plurality of common electrodes for supplying a common signal to the common electrodes and having a plurality of common electrode lines separated in one-to-one correspondence with the gate lines is provided. Generating a common signal for charging supplied to the common electrode lines corresponding to the cells and a maintenance common signal supplied to the remaining common electrode lines corresponding to the deactivated liquid crystal cells; Generating a control signal to drive the gate line; Selecting the activated liquid crystal cells by sequentially supplying a scan signal to the gate line in response to the control signal; And the common signal for charging is supplied to the common electrode line connected to the common electrode of the activated liquid crystal cells, while the common signal for charging is provided to the remaining common electrode lines connected to the common electrodes of the liquid crystal cells that are deactivated. And supplying the holding common signal having a current component different from that of the holding unit.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 18.

8 to 13b illustrate one embodiment of the present invention.

FIG. 8 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 9 is a diagram illustrating the liquid crystal display panel of FIG. 8.

Referring to FIG. 8, the liquid crystal display device of the present invention includes a liquid crystal display panel 110 and a liquid crystal display panel 110 including a plurality of common electrode groups G-Ec1 to G-Eck, which are electrically separated from each other. A data driver 120 for driving the data lines DL1 to DLm of the LCD, a gate driver 130 for driving the gate lines GL0 to GLn of the liquid crystal display panel 110, a data driver 120, and Generation of a common voltage for controlling the driving timing of the gate driver 130 and generating a common voltage Vcom supplied to the liquid crystal display panel 110 and a timing controller 140 for generating an amplification rate control signal. The inverted amplification factor of the feedback common voltage Vcom-F / B fed back from the liquid crystal display panel 110 based on the common voltage Vcom in accordance with the amplification rate control signal Φ is adjusted differently. A common voltage compensator 160 for generating compensation signals Vcom1 'to Vcomk', A plurality of common voltage signal wirings CL1 to CLk are provided to supply the common voltage compensation signals Vcom1 'to Vcomk' to each of the plurality of common electrode groups G-Ec1 to G-Eck.

The liquid crystal display panel 110 includes a plurality of common electrode groups G-Ec1 to G-Eck that are electrically separated from each other, and a plurality of common voltage signal wirings formed on one side of a dummy region located outside the effective display region. CL1 to CLk). In addition, as shown in FIG. 9, the liquid crystal display panel 110 includes a thin film transistor TFT formed at an intersection of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. Liquid crystal cells Clc connected to any one of the thin film transistor TFT and the plurality of common voltage signal lines VcomL1 to VcomLn and arranged in a matrix form.

The plurality of common electrode groups G-Ec1 to G-Eck are formed on the liquid crystal display panel 110 to be electrically separated from each other. Each common electrode group G-Ec receives a common voltage compensation signal Vcom 'for compensating for the swing of the common voltage Vcom and the common voltage Vcom through a plurality of common voltage signal lines VcomL. . For example, as illustrated in FIG. 9, when the liquid crystal display panel having a resolution of 1024 × 768 includes six common electrode groups G-Ec, the first to sixth common electrode groups G-Ec1. To G-Ec6) through the common voltage signal lines VcomL1 to VcomL128, VcomL129 to VcomL256, VcomL257 to VcomL384, VcomL389 to VcomL512, VcomL513 to VcomL640, and VcomL641 to VcomL768, respectively. The signal Vcom 'is supplied. The common voltage signal lines for supplying the common voltage Vcom and the common voltage compensation signal Vcom 'to the same common electrode group are commonly connected to each other through corresponding common voltage signal lines.

 The plurality of common voltage signal lines CL1 to CLk are electrically separated from one side of the dummy area positioned outside the effective display area of the liquid crystal display panel 110. The plurality of common voltage signal wirings CL1 to CLk correspond to each of the plurality of common electrode groups G-Ec1 to G-Eck in a one-to-one manner to supply a common voltage and a common voltage compensation signal. To this end, common voltage signal lines of the same common electrode group G-Ec are commonly connected to a corresponding common voltage signal line. For example, in FIG. 9, the first to sixth common voltage signal lines CL1 to CL6 may be common voltage signal lines belonging to the first to sixth common electrode groups G-Ec1 to G-Ec6, respectively. Common voltage and common voltage compensation signals are supplied to the VcomL1 through VcomL128, VcomL129 through VcomL256, VcomL257 through VcomL384, VcomL389 through VcomL512, VcomL513 through VcomL640, and VcomL641 through VcomL768.

As described above, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of liquid crystal displays are formed separately from one side of the dummy region of the liquid crystal display panel 110, unlike all common electrodes are commonly connected to one common voltage signal line. Common voltage signal wirings CL1 to CLk and a plurality of common electrode groups G-Ec1 to G-Eck supplied with a common voltage and a common voltage compensation signal electrically connected to each other in a one-to-one correspondence. As a result, the difference between the common voltage signal wiring and the line resistance of the common voltage signal lines according to the vertical position of the liquid crystal display panel 110 is significantly reduced, so that the position of the display data in the conventional liquid crystal display panel is far from the data driver 120. As the current component of the common voltage signal being charged decreases, the swing width of the common voltage is increased.

The plurality of common voltage signal lines VcomL1 to VcomLn are arranged side by side alternately with the gate lines GL0 to GLn-1. The gate lines GL1 to GLn supply a scan signal to the liquid crystal cell Clc, and the data lines DL1 to DLm supply a data signal to the liquid crystal cell Clc. The common voltage signal lines VcomL1 to VcomLn supply a common voltage and a common voltage compensation signal to each liquid crystal cell Clc. To this end, the common voltage signal lines VcomL1 to VcomLn are divided into a plurality of blocks G-Ec1 to G-Eck, and common voltage signal lines belonging to the same block are connected to the corresponding common voltage signal lines CL1 to CLk. Common connection. The thin film transistor TFT causes the liquid crystal cell to charge a data signal from any one of the data lines DL1 to DLm in response to a scan signal from one of the gate lines GL1 to GLn. The liquid crystal cell Clc includes a liquid crystal capacitor including a pixel electrode Ep and a common electrode Ec formed side by side on the lower substrate. The pixel electrode Ep is connected to the thin film transistor TFT, and the common electrode Ec is connected to any one of the common voltage signal lines VcomL1 to VcomLn. The liquid crystal cell Clc includes a storage capacitor Cst formed at an overlapping portion of the pixel electrode Ep and the front gate line with an insulating layer therebetween. The storage capacitor Cst maintains the data signal charged in the liquid crystal capacitor for one frame.

The timing controller 140 relays the digital video data R, G, and B from the system (not shown) and supplies the data to the data driver 120. The timing controller 140 controls the gate control signal GDC and the data driver 120 to control the gate driver 130 using the vertical / horizontal synchronization signals V and H and the clock signal CLK. The amplification ratio control signal Φ for controlling the data control signal DDC and the inverted amplification ratio of the common voltage compensator 160 is generated. In addition, the timing controller 140 analog-to-digital converts the feedback common voltage Vcom-F / B and generates an amplification rate control signal.

The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

The amplification rate control signal Φ is a digital signal for controlling the inversion amplification rate of the feedback common voltage Vcom-F / B fed back from the liquid crystal display panel 110. The amplification rate control signal? Varies in size depending on the size of the liquid crystal display panel, the degree of distortion of the common voltage in the liquid crystal display panel, and the like. The timing controller 140 includes a memory (not shown) to generate an amplification rate control signal Φ corresponding to the swing value of the digitally converted feedback common voltage Vcom-F / B. For this purpose, a swing value of the digitally converted feedback common voltage Vcom-F / B and an amplification control signal Φ corresponding thereto are stored in the form of a lookup table.

The data driver 120 converts the digital data signal from the timing controller 140 into an analog data signal according to the data control signal DDC so that every one horizontal period in which the gate high signal is supplied to the gate lines GL1 to GLn. The analog data signal for one horizontal line is supplied to the data lines DL1 to DLm.

The gate driver 130 sequentially supplies scan signals to the gate lines GL1 to GLn in response to the gate control signal GDC from the timing controller 140.

The common voltage generator 150 receives a high potential power voltage from a power supply (not shown) to generate a common voltage Vcom to compensate for the common voltage signal wirings CL1 to CLk and common voltage compensation of the liquid crystal display panel 110. Supply to the unit 160.

The common voltage compensator 160 provides a feedback common voltage Vcom-F / fed back from the feedback dedicated line F / BL of the liquid crystal display panel 110 based on the common voltage Vcom according to the amplification rate control signal Φ. The inversion amplification ratio of B) is adjusted differently to generate common voltage compensation signals Vcom1 'to Vcomk', and are supplied to common voltage signal wirings CL1 to CLk. When the feedback common voltage Vcom-F / B fed back from the liquid crystal display panel 110 is driven in the dot inversion method as described above in the related art problem, the feedback common voltage Vcom-F / B is horizontal due to the effect of capacitor coupling with the data signal. It swings in the positive direction or the negative direction in the period H. In addition, as the common voltage signal line VcomL farther from the data driver 120, the current component of the common voltage supplied thereto gradually decreases due to an increase in the line resistance of the common voltage signal wiring, and thus is supplied to the corresponding liquid crystal cell. The voltage swings up and down more significantly than the common voltage supplied to the liquid crystal cell relatively close to the data driver 120 (see FIG. 7). In order to stabilize the common voltage, the position of the display data is first moved to the data driver 120. It is necessary to prevent the charging current component of the common voltage from decreasing as it is farther away from the circuit, so that the common voltage has a constant swing width regardless of the up and down positions of the display data. Next, regardless of the up and down positions of the display data, the common voltage having a constant swing width must be stabilized to be close to the DC component through the compensation signal from the common voltage compensator 160. In order to ensure that the common voltage has a constant swing width irrespective of the up and down positions of the display data, the liquid crystal display according to the exemplary embodiment of the present invention has a plurality of common electrode groups G-Ec1 to electrically divided as described above. G-Eck). In addition, the present invention stabilizes the common voltage having a constant swing width close to the DC component through the common voltage compensation signals Vcom1 'to Vcomk' from the common voltage compensator 160 regardless of the vertical position of the display data. The liquid crystal display according to the exemplary embodiment includes a common voltage compensator 160. The common voltage compensator 160 will be described in detail with reference to FIGS. 10 to 12.

FIG. 10 is a circuit diagram illustrating a common voltage compensator of a liquid crystal display according to an exemplary embodiment, and FIGS. 11 and 12 are circuit diagrams illustrating an example of the negative feedback resistor of FIG. 10.

10 to 12, the common voltage compensator 160 of the liquid crystal display according to the exemplary embodiment includes an inverting amplifier 162 and a buffer 164.

The inverting amplifier 162 receives the feedback dedicated line F / BL based on the common voltage Vcom from the common voltage generator 150 in response to the amplification rate control signal Φ from the timing controller 140. The common voltage compensation signals Vcom1 'to Vcomk' are generated by inverting and amplifying the feedback common voltages Vcom-F / B. The common voltage compensation signals Vcom1 'to Vcomk' are the same in magnitude and opposite in phase to the feedback common voltages Vcom-F / B.

The inverting amplifier 162 has an inverting input terminal (-) to which the feedback common voltage (Vcom-F / B) is input through a capacitor (C) and a resistor (R) connected in series, and a ratio at which the common voltage (Vcom) is input. And a differential amplifier (Amp) comprising an inverting input terminal (+) and an output terminal connected to the inverting input terminal (-) through the negative feedback resistor (Rf). Here, the DC noise component included in the feedback common voltage Vcom-F / B is removed by the capacitor C connected in series with the resistor R to the inverting input terminal node ni of the differential amplifier Amp. . In addition, the negative feedback resistor Rf connected to the inverting input terminal node ni of the differential amplifier Amp and the output terminal node no to the resistor R connected to the inverting input terminal node ni of the differential amplifier Amp. The inverse amplification factor of the differential amplifier (Amp) is determined by the ratio of Rf / R. The resistor R has a fixed value, but the negative feedback resistor Rf has a value that is varied by the timing controller 140. The negative feedback resistor Rf may be configured as shown in FIGS. 11 and 12. 11 and 12 show negative feedback resistance circuits when the amplification rate control signal Φ of the timing controller 140 is 4 bits, and each bit of the amplification rate control signal Φ corresponds to D1 to D4. do. As illustrated, the combined resistance values of the first to fourth negative feedback resistors Rf1 to Rf4 may correspond to the first to fourth switches S1 to D4 in response to the amplification rate control signals D1 to D4 from the timing controller 140. S4) is determined by switching. The 4-bit digital signals D1 to D4 are embedded in a memory (not shown) in the timing controller 140 at 16 different values according to the swing width of the common voltage in the liquid crystal display panel. Each of the first to fourth switches S1 to S4 closes the switch when the logic value of the digital signal corresponding thereto is "1", and opens the switch when "0" corresponds to the first to fourth negative feedback resistors Rf1 to S4. The combined resistance value of Rf4) is varied. The negative feedback resistance circuit may be configured differently according to the size of the liquid crystal display panel, the degree of distortion of the common voltage in the liquid crystal display panel, and the like. For example, when the amplification rate control signal .phi. Is set to 6 bits, the negative feedback resistance circuit may be composed of six negative feedback resistors and six switches.

The buffer unit 164 is connected to the output node node no of the inverting amplifier 162 to stabilize the common voltage compensation signals Vcom1 'to Vcomk' which are outputs of the inverting amplifier 162, thereby allowing the liquid crystal display panel 110 to be stabilized. Are supplied to common voltage signal wirings CL1 to CLk. The common voltage compensation signals Vcom1 'to Vcomk' minimize the swing width of the common voltage.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention includes a plurality of common electrode groups G-Ec1 to G-Eck electrically divided and driven to display data on the liquid crystal display panel 110. Minimize the line resistance difference between the signal lines (common voltage supply signal lines) according to the up and down positions of the. Accordingly, as the display data is positioned below the liquid crystal display panel 110, the charging current component of the common voltage is prevented from being reduced, and as shown in FIG. 13A, the vertical position of the display data in the liquid crystal display panel 110 is reduced. Regardless, the common voltage swings with a constant swing width. The liquid crystal display according to the exemplary embodiment of the present invention cancels the swing component by supplying a common voltage compensating signal having the same magnitude and opposite phase to the common voltage swinging with the swing width, thereby canceling the swing component. As described above, the common voltage is kept close to the DC component regardless of the position of the display data. As a result, horizontal crosstalk due to the swing of the common voltage is prevented.

14 to 18 show another embodiment of the present invention.

14 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 14, a liquid crystal display according to another exemplary embodiment of the present invention may include a liquid crystal display panel 210 and a data driver 220 for driving data lines DL1 to DLm of the liquid crystal display panel 210. And a common voltage generator 250 for generating the charging common voltage Vcom-C and the holding common voltage Vcom-H, and the gate lines GL0 to GLn of the liquid crystal display panel 210. In addition, the gate driver 230 and the data driver 220 for selectively outputting the charging common voltage Vcom-C and the sustaining common voltage Vcom-H in response to the gate shift clock GSC. A timing controller 240 for controlling the driving timing of the gate driver 230 is provided.

The liquid crystal display panel 210 includes common voltage signal lines VcomL1 to VcomLn and a plurality of gates that are formed to be parallel to each other and electrically separated from each of the plurality of gate lines GL0 to GLn-1. The thin film transistor TFT formed at the intersection of the lines GL1 to GLn and the data lines DL1 to DLm, and the thin film transistor TFT and the plurality of common voltage signal lines VcomL1 to VcomLn, respectively. And liquid crystal cells Clc connected to any one of them and arranged in a matrix form.

The gate lines GL0 to GLn and the data lines DL1 to DLm cross each other. The common voltage signal lines VcomL1 to VcomLn are alternately arranged in parallel with the gate lines GL0 to GLn-1, and the common voltage signal lines VcomL1 to VcomLn are electrically separated from each other. Is formed. The gate lines GL1 to GLn supply a scan signal to each liquid crystal cell Clc, and the data lines DL1 to DLm supply a data signal to each liquid crystal cell Clc. The common voltage signal lines VcomL1 to VcomLn supply a common voltage to each liquid crystal cell Clc. To this end, the common voltage signal lines VcomL1 to VcomLn receive the charging or maintaining common voltages Vcom-C and Vcom-H that are synchronized with the gate shift clock GSC from the gate driver 230. The thin film transistor TFT allows the data signal from any one of the data lines DL1 through DLm to be charged in the liquid crystal cell Clc in response to a scan signal from any one of the gate lines GL1 through GLn. The liquid crystal cell Clc includes a liquid crystal capacitor including a pixel electrode Ep and a common electrode Ec formed side by side on the lower substrate. The pixel electrode Ep is connected to the thin film transistor TFT, and the common electrode Ec is connected to any one of the common voltage signal lines VcomL1 to VcomLn. The liquid crystal cell Clc includes a storage capacitor Cst formed at an overlapping portion of the pixel electrode Ep and the front gate line with an insulating layer interposed therebetween. The storage capacitor Cst maintains the data signal charged in the liquid crystal capacitor for one frame.

The timing controller 240 relays the digital video data R, G, and B from the system (not shown) and supplies the data to the data driver 220. In addition, the timing controller 240 uses the vertical / horizontal synchronization signals V and H and the clock signal CLK to control the gate control signal GDC and the data driver 220 to control the gate driver 230. It generates a data control signal (DDC) for controlling. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

The data driver 220 converts the digital data signal from the timing controller 240 into an analog data signal according to the data control signal DDC, so that every one horizontal period in which the gate high signal is supplied to the gate lines GL1 to GLn. The analog data signal for one horizontal line is supplied to the data lines DL1 to DLm.

The common voltage generator 250 receives a high potential power voltage from a power supply unit (not shown) to generate a common common voltage Vcom-C and a common common voltage Vcom-H of the same magnitude, thereby generating a gate driver. 230).

The gate driver 230 sequentially supplies scan signals to the gate lines GL1 to GLn in response to the gate control signal GDC from the timing controller 240. In addition, the gate driver 230 selectively applies the charging common voltage Vcom-C and the maintaining common voltage Vcom-H to the common voltage signal lines VcomL1 to VcomLn in response to the gate shift clock GSC. Supply. That is, the gate driver 230 supplies the charging common voltage Vcom-C to the common voltage signal line corresponding to the gate line to which the scan signal is supplied, and the maintenance common voltage Vcom- to the other common voltage signal line. Supply H). To this end, the gate driver 230 includes a plurality of gate integrated units 232 configured as shown in FIG. 15. The number of gate integrated units 232 included in the gate driver 230 depends on the resolution of the liquid crystal display panel and the number of output channels of the integrated circuit. For example, in a liquid crystal display panel having a resolution of 1024 × 768, when the output channel number of the gate integrated part is 128, the number of the gate integrated parts 232 included in the gate driver 230 is six, and the gate integrated parts are provided. When the number of negative output channels is 256, the number of gate integrators 232 included in the gate driver 230 is three. Hereinafter, any one gate integrator 232 included in the gate driver 230 will be described with reference to FIG. 15.

15 is a view schematically illustrating a gate integrated part of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 15, a gate integrated unit 232 of a liquid crystal display according to another exemplary embodiment includes a shift register block 234, a level shifter block 236, and an output buffer block 238.

The shift register block 234 has a plurality of stages S1 to Si that are cascaded. The shift register block 234 is one horizontal period from the first stage S1 to the i-th stage Si in response to the gate start pulse GSP and the gate shift clock GSC supplied from the timing controller 240. The shifted shift output signals Vs1 to Vsi are sequentially output.

The level shifter block 236 includes a plurality of level shifters L / S1 to L / Si to correspond one-to-one with the plurality of shift registers S1 to Si. The plurality of level shifters L / S1 to L / Si are shift output signals Vs1 to Vsi respectively output from the stages S1 to Si in response to a gate output signal GOE supplied from the timing controller 240. ) Is converted into scan signals Vg1 to Vgi swinging between the gate low voltage Vgl and the gate high voltage Vgh and supplied to the output buffer block 238. Here, the gate high voltage Vgh is a voltage above the threshold voltage of the TFTs of the liquid crystal display panel 210, that is, the gate-on voltage, and the gate low voltage Vgl is below the threshold voltage of the TFTs. That is, the gate-off voltage.

The output buffer block 238 includes a first buffer array 238-1 for outputting a scan signal and a second buffer array 238-2 for outputting a common voltage.

The first buffer array 238-1 includes a plurality of scan signal output buffers B1 to Bi to correspond one-to-one with the plurality of level shifters L / S1 to L / Si. The first buffer array 238-1 buffers the scan signals Vg1 to Vgi from the level shifter block 236 through a plurality of scan signal output buffers B1 to Bi, and gates them at one horizontal period. The lines GL1 to GLi are sequentially supplied.

The second buffer array 238-2 includes a plurality of common voltage output buffers BC1 to BCi. The plurality of common voltage output buffers BC1 to BCi may be charged with the common voltage Vcom-C for the charge from the common voltage generator 250 in response to the gate shift clock GSC from the timing controller 240. The common voltage Vcom-H is selectively output. Among the plurality of common voltages Vcom1 to Vcomi that are output, one common voltage that is output in synchronization with the scan signal is output as the charging common voltage Vcom-C, and the other common voltages are the maintenance common voltage Vcom-C. H) is output. To this end, the switching element SW for switching the non-inverting input terminal (+) of each of the common voltage output buffers BC1 to BCi in response to the gate shift clock to output the charging common voltage Vcom-C. Is connected. For example, as illustrated in FIG. 16, the j-th gate shift clock GSCj from the timing controller 240 to supply the scan signal Vgj to the j (1 <j <i) th gate line GLj. ), The switching element SW of the j-th common voltage output buffer BCj outputs the non-inverting input terminal (+) of the j-th common voltage output buffer BCj and the charging common voltage Vcom-C. The terminal A is switched to be connected. The switching element SW of the other common voltage output buffer maintains the state in which the non-inverting input terminal (+) of the common voltage output buffer BCj and the output terminal B of the maintenance common voltage Vcom-H are connected. . Accordingly, the charging common voltage Vcom-C output through the j-th common voltage output buffer BCj is larger than the holding common voltage Vcom-H output through the other common voltage output buffers. Has This is because the charging common voltage Vcom-C has the same voltage value as the maintenance common voltage Vcom-H, but the load resistance value is very small. As described in the problem of the prior art, the swing width of the common voltage charged in the common voltage signal line is closely related to the current component of the common voltage during charging. As the line resistance of the common voltage signal line increases, the current component of the common voltage decreases during charging, and accordingly, the common voltage swings larger due to the influence of capacitor coupling with the data signal. . Therefore, the liquid crystal display according to another exemplary embodiment of the present invention has a second buffer such that the current component of the common voltage Vcom-C for charging is much larger than the current component of the common voltage Vcom-H as described above. By configuring the array 238-2, the swing width of the common voltage to be charged can be greatly reduced. Hereinafter, the operation of the second buffer array 238-2 will be described in more detail with reference to FIGS. 17A to 17C.

17A illustrates a connection relationship between the second buffer array 238-2 while the first gate shift clock GSC1 is generated from the timing controller 240 so that the scan signal Vg1 is supplied to the first gate line GL1. Indicates. As described above, only the switching element SW of the first common voltage output buffer BC1 is switched to be connected to the output terminal A of the charging common voltage Vcom-C in response to the first gate shift clock GSC1. . Accordingly, the non-inverting input terminal of the first common voltage output buffer BC1 is connected to the output terminal A of the common voltage Vcom-C for charging, while the non-inverting input terminals of the other common voltage output buffers are used for holding. Common connection is made to the output terminal B of the common voltage Vcom-H. As a result, the charging common voltage Vcom-C output through the first common voltage output buffer BC1 has a larger current component than the holding common voltage Vcom-H output through the other common voltage output buffers. Therefore, the swing width of the common voltage charged in the first common voltage signal line VcomL1 is greatly reduced.

FIG. 17B illustrates the second buffer array 238-2 while the j-th gate shift clock GSCj is generated from the timing controller 240 to supply the scan signal Vgj to the j-th gate line GLj. Indicates a connection relationship. As described above, only the switching element SW of the j-th common voltage output buffer BCj is connected to the output terminal A of the charging common voltage Vcom-C in response to the j-th gate shift clock GSCj. Switching. Accordingly, the non-inverting input terminal of the j-th common voltage output buffer BCj is connected to the output terminal A of the charging common voltage Vcom-C, while the non-inverting input terminals of the other common voltage output buffers are maintained. The common terminal is connected to the output terminal B of the common voltage Vcom-H. As a result, the charging common voltage Vcom-C output through the j-th common voltage output buffer BCj is larger than the holding common voltage Vcom-H output through the other common voltage output buffers. Therefore, the swing width of the common voltage charged in the j-th common voltage signal line VcomLj is greatly reduced.

FIG. 17C illustrates the second buffer array 238-2 while the i-th gate shift clock GSCi is generated from the timing controller 240 to supply the scan signal Vgi to the i-th gate line GLi. Indicates a connection relationship. As described above, only the switching element SW of the i-th common voltage output buffer BCi is connected to the output terminal A of the charging common voltage Vcom-C in response to the i-th gate shift clock GSCi. Switching. Accordingly, the non-inverting input terminal of the i-th common voltage output buffer BCi is connected to the output terminal A of the charging common voltage Vcom-C, while the non-inverting input terminals of the other common voltage output buffers are maintained. The common terminal is connected to the output terminal B of the common voltage Vcom-H. As a result, the charging common voltage Vcom-C output through the i-th common voltage output buffer BCi is larger than the maintenance common voltage Vcom-H output through the other common voltage output buffers. Since the component has a component, the swing width of the common voltage charged in the i-th common voltage signal line VcomLi is greatly reduced.

As described above, in the liquid crystal display according to another exemplary embodiment, the common voltage signal lines VcomL1 to VcomLn are connected to the plurality of gate lines, unlike all common electrodes are commonly connected to one common voltage signal line. GL0 to GLn-1) are formed so as to alternate with each other and electrically separated from each other. As a result, the difference in the line resistance of the common voltage signal lines and the like depending on the vertical position of the liquid crystal display panel 210 is greatly reduced, so that the position of the display data in the conventional liquid crystal display panel is farther from the data driver 220. The current component of the common voltage signal to be charged is gradually reduced, thereby increasing the swing width of the common voltage to be charged.

Furthermore, the liquid crystal display according to another exemplary embodiment of the present invention allows the common voltage signal line corresponding to the gate line to which the scan signal is supplied to be supplied with a charging common voltage having a relatively large current component in response to the gate shift clock. The remaining common voltage signal line is supplied with a holding common voltage having a relatively small current component, thereby significantly reducing the swing width of the charged common voltage as shown in FIG. Regardless of this, it should be kept close to the DC component. As a result, horizontal crosstalk due to the swing of the common voltage is prevented.

On the other hand, the technical idea according to another embodiment of the present invention is a line on glass (hereinafter referred to as LOG) for mounting a plurality of signal lines including a common voltage signal wiring on the lower substrate in order to reduce the thickness of the liquid crystal display device It is also applicable to the case of employing the method.

As described above, the liquid crystal display and the driving method thereof according to the present invention divide the common voltage signal lines of the liquid crystal display panel into a plurality of blocks, and common voltages separated from each other by blocks are divided into the divided common voltage signal lines. By being applied, the charging current component of the common voltage is prevented from being reduced according to the position of the display data in the liquid crystal display panel so that the common voltage swings with a constant swing width regardless of the position of the display data. In addition, horizontal crosstalk due to the swing of the common voltage may be prevented by supplying a common voltage compensation signal having the same magnitude and opposite phase to the swinging common voltage to cancel the swing component.

In addition, the liquid crystal display and the driving method thereof according to the present invention are formed so that the common voltage signal lines are alternately formed in parallel with each of the plurality of gate lines and electrically separated from each other. The common voltage signal line corresponding to the gate line to which the scan signal is supplied is supplied with a charging common voltage having a relatively large current component in response to the gate shift clock, and the other common voltage signal line is relatively small. By supplying a common common voltage having a current component, it is possible to significantly reduce the swing width of the common voltage being charged to prevent horizontal crosstalk due to the swing of the common voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, although the embodiments of the present invention have been described using the IPS mode as an example, the technical spirit of the present invention is not limited thereto, and the FFS (Field) disclosed in the applications Nos. 2004-0049955, 2004-0050214, etc. previously filed by the present applicant. It is also applicable to Fringe Switching mode. In addition, the technical idea of the present invention is applicable not only to the case of driving by the dot inversion method but also to the case of driving by all inversion methods. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (17)

In the effective display area, a plurality of common electrode groups are formed to form an electric field facing the pixel electrodes supplied with the data voltage and are electrically separated from each other, and each of the common electrode groups has a plurality of common electrodes connected in common. panel; A plurality of common voltage signal wirings formed in a dummy area in the liquid crystal display panel positioned outside the effective display area of the liquid crystal display panel so as to be connected to the plurality of common electrode groups one-to-one; A common voltage generator for generating a common voltage; A common voltage differentially amplifies the feedback common voltage fed back from any one or more of the common electrodes of the liquid crystal display panel and the common voltage from the common voltage generator at a variable amplification ratio to supply the plurality of common voltage signal lines. Compensation unit; And And a timing controller configured to control an amplification ratio of the common voltage compensator in accordance with a swing value of the feedback common voltage. The method of claim 1, And the feedback common voltage is formed on one side of the liquid crystal display panel and fed back from a feedback dedicated line connected to any one or more of the common electrodes. The method of claim 2, The timing controller, An analog-digital converter for converting the swing value of the feedback common voltage into a digital signal; And And a memory for storing an amplification factor control signal corresponding to the swing value of the feedback common voltage converted into the digital signal into a look-up table. The method of claim 3, wherein The common voltage compensator, An inverting amplifier for differentially amplifying the common voltage and the feedback common voltage in response to the amplification rate control signal to generate a common voltage compensation signal opposite to the swing feedback common voltage; And And a buffer unit connected to an output terminal of the inverting amplifier unit to stabilize the common voltage compensation signal. 5. The method of claim 4, The inversion amplifier, The inversion is input through an inverting input terminal through which the feedback common voltage is input through a capacitor and a resistor connected in series, a non-inverting input terminal through which the common voltage is input, and a plurality of negative feedback resistors whose synthetic resistance value is determined according to the amplification rate control signal. And a differential amplifier comprising an output terminal connected to an input terminal. 6. The method of claim 5, The negative feedback resistors are connected in series with each other between the inverting input terminal and the output terminal; And a plurality of switch elements connected in parallel with each of the negative feedback resistors one-to-one and switched according to a digital logic value of the amplification rate control signal to switch current flow through the negative feedback resistors. Device. 6. The method of claim 5, One side of the negative feedback resistors is commonly connected in parallel to the inverting input terminal; A plurality of one-to-one serial connection with each of the negative feedback resistors between the other side of the negative feedback resistors and the output terminal and switched according to a digital logic value of the amplification rate control signal to switch current flow through the negative feedback resistors. The liquid crystal display device further comprises a switch element. In the effective display area, a plurality of common electrodes are formed at the intersections of the plurality of gate lines and the plurality of data lines, and a plurality of common electrodes are formed to face the pixel electrodes supplied with the data voltage. A liquid crystal display panel supplying a common signal to the common electrodes and having common electrode lines which are separated into a plurality of one-to-one correspondences with the gate lines; A common voltage generator configured to generate a charging common signal supplied to the common electrode lines corresponding to the activated liquid crystal cells and a maintenance common signal supplied to the remaining common electrode lines corresponding to the deactivated liquid crystal cells; The scan signal is sequentially supplied to the gate line to select the activated liquid crystal cells, and the common electrode for charging is supplied to the common electrode line connected to the common electrode of the activated liquid crystal cells, while the deactivated The remaining common electrode lines connected to the common electrodes of the liquid crystal cells may include a gate driver configured to supply the holding common signal having a current component different from that of the charging common signal; And And a timing controller for controlling the gate driver. 9. The method of claim 8, The timing controller, A gate shift clock indicating a time for turning on the gate of the thin film transistor and indicating a shift of the scan signal, a gate output signal for controlling the output of the gate driver, and a first one of the plurality of scan signals. And a gate start pulse indicative of the timing of generation of the scan signal. The method of claim 9, Wherein the gate driver comprises: A liquid crystal display device comprising a plurality of gate integrated parts. 11. The method of claim 10, The gate integration unit, A shift register that is cascaded and includes a plurality of stages that sequentially generate an output in response to one of the gate start pulse and a previous output and the gate shift clock; A level shifter for adjusting a swing width of output signals of the shift register; A first buffer array including a plurality of buffers connected between the output terminals of the level shifter and the gate lines; And A second buffer array including a plurality of buffers connected between the output terminals of the common voltage generator and the common electrodes and switching between the charging common signal and the sustain common signal in response to the gate shift clock; Liquid crystal display characterized in that. 9. The method of claim 8, And a current component of the charging common signal is larger than a current component of the holding common signal. A driving method of a liquid crystal display device comprising a plurality of common electrodes forming an electric field facing pixel electrodes supplied with a data voltage in an effective display area of the liquid crystal display panel, Generating a common voltage in the common voltage generator; The dummy area in the liquid crystal display panel is disposed outside the effective display area of the liquid crystal display panel so as to divide the plurality of common electrodes into a plurality of common electrode groups electrically separated from each other, and to be connected one-to-one to the plurality of common electrode groups. Supplying the common voltage to a plurality of common voltage signal lines formed in the plurality of common voltage signals; Receiving a feedback of a common voltage having a swing value from at least one of the common electrodes of the liquid crystal display panel; Generating an amplification rate control signal according to a swing value of the feedback common voltage; And And differentially amplifying the feedback common voltage and the common voltage from the common voltage generator in response to the amplification rate control signal and supplying them to the plurality of common voltage signal lines. 14. The method of claim 13, Generating the amplification rate control signal, Converting a swing value of the feedback common voltage into a digital signal; And And reading out an amplification factor control signal from a lookup table using the digital signal as a read address. 14. The method of claim 13, And buffering the stabilized signal to stabilize the differentially amplified signal. In the effective display area of the liquid crystal display panel, thin film transistors are formed at intersections of a plurality of gate lines and a plurality of data lines, and a plurality of common electrodes are formed to form an electric field facing pixel electrodes supplied with a data voltage. And supplying a common signal to the common electrodes and having a plurality of common electrode lines corresponding to the gate lines in a one-to-one manner. Generating a common signal for charging supplied to the common electrode line corresponding to the activated liquid crystal cells and a maintenance common signal supplied to the remaining common electrode lines corresponding to the deactivated liquid crystal cells; Generating a control signal to drive the gate line; Selecting the activated liquid crystal cells by sequentially supplying scan signals to the gate lines in response to the control signal; And The charging common signal is supplied to the common electrode line connected to the common electrode of the activated liquid crystal cells, while the remaining common electrode lines connected to the common electrodes of the deactivated liquid crystal cells are connected to the charging common signal. And supplying said holding common signal having a different current component. 17. The method of claim 16, And the current component of the charging common signal is greater than the current component of the holding common signal.

Images