KR101389252B1 - Liquid Crystal Display and Driving Method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of improving display quality.

The liquid crystal display includes liquid crystal cells in which a plurality of data lines and a plurality of gate lines intersect and are arranged in a matrix form, and the common electrodes of the liquid crystal cells are formed in parallel with the data lines at one side and the other short side thereof, respectively. A liquid crystal display panel having first and second common voltage supply wirings commonly connected to the light emitting diodes and divided into a plurality of horizontal block units; And generating a first regulated common voltage whose level is varied in units of one horizontal block period so as to change the level of the common voltage between adjacent horizontal blocks of the liquid crystal display panel. And a regulated common voltage generation circuit for generating a second regulated common voltage at which the level thereof is varied in units of the one horizontal block period and supplying the second common voltage supply wiring to the second common voltage supply wiring. The first and second regulated common voltages have the same phase or have different phases within the first horizontal block period, and the level variable width of the second regulated common voltage between the highest level and the lowest level is It is equal to the level variable width of the first adjustment common voltage.

 Ion, Polarization, Stain, Common Voltage, Variable, Horizontal Block

Description

[0001] The present invention relates to a liquid crystal display and a driving method thereof,

The present invention relates to a liquid crystal display device and a driving method thereof capable of improving display quality.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal. Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment and the like. Particularly, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is capable of actively controlling a switching element, which is advantageous for a moving image.

As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is mainly used as shown in FIG.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital video data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The data voltage is charged in the liquid crystal cell Clc. For this purpose, the gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst1. It is connected to one electrode. A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst1 charges a data voltage applied from the data line DL when the TFT is turned on to maintain a constant voltage of the liquid crystal cell Clc. When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc are changed in arrangement by the electric field between the pixel electrode and the common electrode to modulate the incident light.

However, when a direct current voltage is applied to the liquid crystal layer of the liquid crystal display device for a long time, negatively charged ions move in the same motion vector direction and positively charged ions move in the opposite direction along the polarity of the electric field applied to the liquid crystal. As it moves toward, it becomes polarized, and as time passes, the amount of negatively charged ions increases and the amount of positively charged ions increases. As the accumulation amount of ions increases, the alignment film deteriorates, and as a result, the alignment characteristics of the liquid crystal deteriorate. Therefore, if a DC voltage is applied to the liquid crystal display for a long time, unevenness appears in the displayed image, and the unevenness increases as time passes. In order to improve such spots, a method of developing a liquid crystal material having a low dielectric constant or improving an alignment material or an alignment method has been attempted. However, such a method requires much time and expense to develop materials, and lowering the dielectric constant of the liquid crystal may cause another problem that the driving characteristic of the liquid crystal is deteriorated. Experimentally found that the time of appearance of the stain due to the polarization and accumulation of ions is faster the more impurities ionized in the liquid crystal layer and the larger the acceleration factor. The acceleration factor is temperature, time, direct current driving of the liquid crystal, and the like. Therefore, spots appear faster as the temperature is applied or the longer the DC voltage of the same polarity is applied to the liquid crystal layer, the worse it becomes. Moreover, stains are different in form or extent of panels of the same model produced through the same manufacturing line, and thus cannot be solved only by new material development or process improvement methods.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which improves the display quality by suppressing spots caused by polarization and accumulation of ions by varying the level of common voltage between adjacent horizontal blocks of the liquid crystal display panel. To provide.

Another object of the present invention is to improve the display quality by suppressing unevenness caused by polarization and accumulation of ions by varying the level of common voltage between adjacent horizontal blocks of the liquid crystal display panel and for a predetermined frame period. It is to provide a driving method.

In order to achieve the above object, the liquid crystal display according to the embodiment of the present invention includes a plurality of liquid crystal cells in which a plurality of data lines and a plurality of gate lines are intersected and arranged in a matrix form, respectively, on one side and the other short side thereof. A liquid crystal display panel formed in parallel with data lines and having first and second common voltage supply wirings connected to common electrodes of the liquid crystal cells and divided into a plurality of horizontal block units; And generating a first regulated common voltage whose level is varied in units of one horizontal block period so as to change the level of the common voltage between adjacent horizontal blocks of the liquid crystal display panel. And a regulating common voltage generating circuit for generating a second regulating common voltage whose level is varied in units of said one horizontal block period and supplying it to said second common voltage supply wiring. The first and second regulated common voltages have the same phase or have different phases within the first horizontal block period, and the level variable width of the second regulated common voltage between the highest level and the lowest level is It is equal to the level variable width of the first adjustment common voltage.

Each of the first and second regulated common voltages applied to the same horizontal block within the one horizontal block period is fixed to any one of a plurality of levels in every frame.

When the first and second regulated common voltages are in phase, the levels of the first and second regulated common voltages are equal to each other within the first horizontal block period.

When the first and second regulated common voltages are in phase, the levels of the first and second regulated common voltages are symmetrical with respect to the DC common voltage corresponding to the black gray level within the first horizontal block period.

Each of the first and second regulated common voltages applied to the same horizontal block within the one horizontal block period is varied in stages in units of a plurality of predetermined frame periods.

When the first and second adjustment common voltages are in phase, the levels of the first and second adjustment common voltages are equal to each other within the first horizontal block period of the same frame period.

When the first and second regulated common voltages are in phase, the level of the first and second regulated common voltages within the first horizontal block period of the same frame period is based on the DC common voltage corresponding to the black gray level. Are symmetrical to each other.

According to an exemplary embodiment of the present invention, a plurality of data lines and a plurality of gate lines may be intersected and arranged in a matrix. Each of the liquid crystal cells may be formed in parallel with the data lines at one side and the other short side. A driving method of a liquid crystal display device having first and second common voltage supply wirings commonly connected to common electrodes and having a liquid crystal display panel divided into a plurality of horizontal blocks includes horizontally adjacent to each other of the liquid crystal display panel. In order to change the level of the common voltage between the blocks, a first regulated common voltage whose level is varied in units of one horizontal block period is generated and supplied to the first common voltage supply wiring, and the first horizontal block period is Generating a second regulated common voltage whose level varies in units and supplying it to the second common voltage supply wiring; And applying a first regulated common voltage from the first common voltage supply line to the common electrodes of the liquid crystal cells in common, and simultaneously applying a second regulated common voltage from the second common voltage supply line to the liquid crystal cells. Applying in common to the common electrodes; The first and second regulated common voltages have the same phase or have different phases within the first horizontal block period, and the level variable width of the second regulated common voltage between the highest level and the lowest level is It is equal to the level variable width of the first adjustment common voltage.

The liquid crystal display device and the driving method thereof according to the present invention disperse the directivity and intensity of the electric field vector formed in the liquid crystal layer by the frame period even when a constant data voltage for a long time is applied to the liquid crystal cell (Clc), even within the same frame period. By dispersing in units of horizontal blocks and in units of horizontal formation positions of the liquid crystal cell even in the same frame period and the same horizontal block, the phenomenon of polarization and accumulation of ions can be suppressed and the display quality can be greatly increased.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 7. FIG.

Referring to FIG. 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and an adjusting common voltage generating circuit ( 14).

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines DL and n gate lines GL.

Data lines DL, gate lines GL, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, but the in-plane switching (IPS) mode and the fringe field switching (FFS) mode In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. The common electrode 2 is commonly connected to the first common voltage supply wiring 21 formed on the left short side of the liquid crystal display panel 10 and the second common voltage supply wiring 22 formed on the right short side of the liquid crystal display panel 10. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The liquid crystal display panel 10 is divided into k (2 ≦ k ≦ n) horizontal block units, and receives common voltages of different levels between neighboring horizontal blocks. One horizontal block includes n / k horizontal lines.

The timing controller 11 receives timing signals such as a data enable signal (DE), a dot clock (CLK), etc. from an external system board to adjust the operation timing of the data driver circuit 12 and the gate driver circuit 13. Generate control signals (GDC, DDC) for controlling.

The gate timing control signal GDC for controlling the operation timing of the gate driving circuit 13 is a gate start pulse (GSP) indicating a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. Is a timing control signal input to the shift register in the gate driving circuit 13 to sequentially shift the gate start pulse GSP. The gate shift clock signal Gate is generated with a pulse width corresponding to the ON period of the TFT. Shift Clock: GSC), and a Gate Output Enable Signal (GOE) indicating the output of the gate driving circuit 13.

The data timing control signal DDC for controlling the operation timing of the data driving circuit 12 is supplied to the data driving circuit 12 in the data driving circuit 12 based on the rising or falling edge, The source output enable signal SOE for indicating the output of the data driving circuit 12 and the data voltage of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 10 A polarity control signal POL indicating the polarity, and the like.

In addition, the timing controller 11 rearranges the digital video data RGB input from the external system board to the data driving circuit 12 according to the resolution of the liquid crystal display panel 10.

The data driving circuit 12 based on the gamma reference voltages GMA from the gamma reference voltage generator (not shown) in response to the data control signal DDC from the timing controller 11. The analog gamma compensation voltage is converted into an analog gamma compensation voltage, and the analog gamma compensation voltage is supplied to the data lines DL of the liquid crystal display panel 10 as a data voltage. To this end, the data driving circuit 12 stores a shift register for sampling the clock signal, a register for temporarily storing the digital video data RGB, and one line of data in response to a clock signal from the shift register. A latch for simultaneously outputting data for a line, a digital / analog converter for selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to a digital data value from the latch, and a positive / negative gamma A plurality of data drive ICs include a multiplexer for selecting a data line DL to which analog data converted by voltage is supplied, and an output buffer connected between the multiplexer and the data line DL.

The gate driving circuit 13 sequentially supplies scan pulses for selecting the horizontal line of the liquid crystal display panel 10 to which the data voltage is supplied to the gate lines GL. To this end, the gate driving circuit 13 is connected between a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell Clc, and between the level shifter and the gate line GL. It consists of a plurality of gate drive ICs each including an output buffer.

The regulating common voltage generation circuit 14 includes a first regulating common whose level is varied in units of one horizontal block period 1THB in order to change the level of the common voltage between neighboring horizontal blocks of the liquid crystal display panel 10. The second regulated common voltage MVcom2 that generates a voltage MVcom1 and supplies the same to the first common voltage supply wiring 21 of the liquid crystal display panel 10 and changes its level in units of one horizontal block period 1THB. ) Is supplied to the second common voltage supply wiring 22 of the liquid crystal display panel 10.

Here, one horizontal block period 1THB is a total time taken for all of the n / k horizontal lines to be scanned, assuming that n / k horizontal lines are included in one horizontal block of the liquid crystal display panel 10. it means. The first and second regulated common voltages MVcom1 and MVcom2 respectively supplied to the common electrodes in the same horizontal block via the first and second common voltage supply wirings 21 and 22 have the same phase, or They can have different phases. In addition, the number of levels of the regulated common voltage, which is variable in units of one horizontal block period 1THB, may be two or more, and the level variable width of the second regulated common voltage MVcom2 between the highest level and the lowest level may be the first. It is equal to the level variable width of the adjustment common voltage MVcom1. Meanwhile, each of the levels of the first and second regulated common voltages MVcom1 and MVcom2 applied to the same horizontal block during one horizontal block period 1THB may be fixed to a specific level in all frames as shown in FIGS. 3 and 5. As shown in FIG. 6, the level may be varied step by step at predetermined time intervals (eg, 200 frames).

FIG. 3 shows an example of the first and second regulated common voltages MVcom1 and MVcom2 supplied to the common electrodes in the horizontal block via the first and second common voltage supply wirings 21 and 22, respectively.

Referring to FIG. 3, the levels of the first and second regulated common voltages MVcom1 and MVcom2 vary between the first level LV1 and the second level LV2 in units of one horizontal block period 1THB. They are supplied in phase with each other. The first level LV1 has a potential lower than the DC common voltage Vcom_DC corresponding to the black gray level by a predetermined value, while the second level LV2 has a potential higher than the DC common voltage Vcom_DC by a predetermined value. . Accordingly, since the level of the common voltage between the adjacent horizontal blocks of the liquid crystal display panel 10 is different, even if a constant data voltage for a long time is applied to the liquid crystal cell Clc, the directionality and intensity of the electric field vector formed in the liquid crystal layer Is distributed in units of horizontal blocks. Through the dispersion of the directionality and the intensity of the electric field vector, staining caused by polarization and accumulation of ions is suppressed.

On the other hand, the first and second regulated common voltages MVcom1 and MVcom2 may have more than two variable levels. For example, as shown in FIG. 4A, the first and second regulated common voltages MVcom1 and MVcom2 are the first level LV1 in units of one horizontal block period 1THB. The level may vary step by step between the third and third levels LV3, and the level between the first and fifth levels LV1 through LV5 in units of one horizontal block period 1THB as shown in FIG. 4B. This may vary in stages.

FIG. 5 shows another example of the first and second regulated common voltages MVcom1 and MVcom2 supplied to the common electrodes in the corresponding horizontal block via the first and second common voltage supply wirings 21 and 22, respectively.

Referring to FIG. 5, the level of the first and second regulated common voltages MVcom1 and MVcom2 varies between the first level LV1 and the second level LV2 in units of one horizontal block period 1THB. They are supplied in opposite phases. In other words, when the first regulated common voltage MVcom1 is supplied to the first level LV1 within a horizontal block period HBLk-1, the second regulated common voltage MVcom2 is supplied to the second level LV2. Next, when the first regulated common voltage MVcom1 is supplied to the second level LV2 within the horizontal block period HBLk, the second regulated common voltage MVcom2 is supplied to the first level LV1. Here, the first level LV1 has a potential lower than the DC common voltage Vcom_DC corresponding to the black gray level by a predetermined value, while the second level LV2 has a potential higher than the DC common voltage Vcom_DC by a predetermined value. Has Accordingly, the level of the common voltage applied to the common electrode of the liquid crystal cell Clc depends not only on the adjacent horizontal blocks of the liquid crystal display panel 10 but also depending on the formation position of the corresponding liquid crystal cell Clc within the same horizontal block. Will be different. For example, assuming the liquid crystal cell Clc formed in the first horizontal block HBL1, when the liquid crystal cell Clc is positioned on the first common voltage supply wiring 21, it is relatively first adjusted common voltage. Due to the strong influence of MVcom1, a common voltage having a potential higher than the DC common voltage Vcom_DC is supplied to the common electrode of the liquid crystal cell Clc, whereas the liquid crystal cell Clc is supplied with the second common voltage supply wiring 22. In the case of a biased position, a common voltage having a potential lower than the DC common voltage Vcom_DC is supplied to the common electrode of the liquid crystal cell Clc due to the strong influence of the second regulated common voltage MVcom2. On the other hand, when the liquid crystal cell Clc is positioned at the center of the first and second common voltage supply wirings 21 and 22, the first and second regulated common voltages MVcom1 and MVcom2 are canceled with each other, thereby providing a DC common voltage. A common voltage having the same potential as Vcom_DC is supplied to the common electrode of the liquid crystal cell. Accordingly, even when a constant data voltage for a long time is applied to the liquid crystal cell Clc, the directivity and intensity of the electric field vector formed in the liquid crystal layer are dispersed in units of horizontal blocks, and the horizontal formation position of the liquid crystal cell even in the same horizontal block. Will be distributed in units. Through the dispersion of the directionality and the intensity of the electric field vector, staining caused by polarization and accumulation of ions is suppressed.

The first and second regulated common voltages MVcom1 and MVcom2 may have more than two variable levels. In addition, the phase difference between the first and second regulated common voltages MVcom1 and MVcom2 is not limited to 180 ° (inverse phase) but may have another phase difference (eg, 90 °).

6 and 7 show another example of the first and second regulated common voltages MVcom1 and MVcom2 supplied to the common electrodes in the corresponding horizontal block via the first and second common voltage supply wirings 21 and 22, respectively. An example is shown.

Each of the levels of the first and second regulated common voltages MVcom1 and MVcom2 applied to the same horizontal block is predetermined as shown in FIG. 6, unlike FIG. 3 and FIG. 5, which are fixed at any particular level in all frames. The level varies in stages for a certain time (for example, 200 frames). For example, each of the first and second regulated common voltages MVcom1 and MVcom2 applied to the same horizontal block may have five levels of multisteps S0 to S4 that are sequentially changed every 200 frames between 0 to 4 levels LV0 to LV4. It can be composed of). Of course, the period of the 200 frame period may vary depending on the model.

The first regulated common voltage MVcom1 is supplied to the same horizontal block in multi-steps S0 to S4 that are supplied at different levels between neighboring horizontal blocks in the same frame as shown in FIG. do. The second regulated common voltage MVcom2 is supplied to the same horizontal block in multi-steps S0 to S4 that are supplied at different levels between neighboring horizontal blocks in the same frame as shown in FIG. do. The second regulated common voltage MVcom2 may be supplied in phase with the first regulated common voltage MVcom1 as described in the first column line C1, and as described in the second column line C2. It can be supplied out of phase with the regulated common voltage MVcom1. Here, the in-phase of the zeroth step S0 is the zero-step S0 and its inverse phase is the fourth step S4, and the in-phase of the first step S1 is the first step S1 and its inverse. The phase is the third step S3, the in-phase and inverted phases of the second step S2 are the second step S2, and the in-phase of the third step S3 is the third step S3, and its inverse. The phase is the first step S1, the in-phase of the fourth step S4 is the fourth step S4 and its antiphase is the zero step S0. As shown in FIG. 6, a phase difference of 180 ° occurs between the steps forming the antiphase. On the other hand, unlike the description of the column lines C1 and C2, the second regulated common voltage MVcom2 may be supplied in a phase different from that of the first regulated common voltage MVcom1. Accordingly, even when a constant data voltage for a long time is applied to the liquid crystal cell Clc, the directivity and intensity of the electric field vector formed in the liquid crystal layer are dispersed in units of frame periods, and in units of horizontal blocks even within the same frame period. In addition, within the same frame period and the same horizontal block, the liquid crystal cells are dispersed in units of horizontal formation positions. Through the dispersion of the directionality and the intensity of the electric field vector, staining caused by polarization and accumulation of ions is suppressed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is an equivalent circuit diagram of a pixel of a general liquid crystal display device.

2 is a block diagram of a liquid crystal display according to an embodiment of the present invention.

3 is a view showing an example of first and second regulated common voltages supplied in common phase to common electrodes in a corresponding horizontal block via first and second common voltage supply wirings;

4A is a diagram illustrating a case where three levels of the first and second regulated common voltages varying in stages are three;

4B is a diagram illustrating a case where the number of levels of the first and second regulated common voltages varying in stages is five;

FIG. 5 is a diagram illustrating an example of first and second regulated common voltages supplied to the common electrodes in a corresponding horizontal block in phase out from each other via first and second common voltage supply wirings. FIG.

FIG. 6 is a diagram showing that the levels of each of the first and second regulated common voltages applied to the same horizontal block in one horizontal block period are varied stepwise in units of a plurality of predetermined frame periods.

7 is a diagram showing levels of first and second regulated common voltages for horizontal blocks and frames.

Description of the Related Art

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14: regulating common voltage generating circuit 21: first common voltage supply wiring

22: second common voltage supply wiring

Claims (10)

And a plurality of data lines and a plurality of gate lines intersecting and arranged in a matrix form, each of which is formed in parallel with the data lines at one side and the other short side thereof and is commonly connected to common electrodes of the liquid crystal cells. A liquid crystal display panel having first and second common voltage supply wirings and divided into a plurality of horizontal blocks; And In order to change the level of the common voltage between the adjacent horizontal blocks of the liquid crystal display panel, a first adjustment common voltage whose level is varied in units of one horizontal block period is generated and supplied to the first common voltage supply wiring. And a second common common voltage which generates a second regulated common voltage whose level varies in units of the first horizontal block period, and supplies the second common common voltage supply wiring to the second common voltage supply wiring. The first and second regulated common voltages have the same phase or have different phases within the first horizontal block period, and the level variable width of the second regulated common voltage between the highest level and the lowest level is And a level variable width of the first adjustment common voltage. The method of claim 1, And each of the first and second regulated common voltages applied to the same horizontal block within the one horizontal block period is fixed to any one of a plurality of levels in every frame. The method of claim 2, And the level of the first and second regulated common voltages is equal to each other within the first horizontal block period when the first and second regulated common voltages are in phase. The method of claim 2, When the first and second regulated common voltages are in reverse phase, the levels of the first and second regulated common voltages are symmetrical with respect to the DC common voltage corresponding to the black gray level within the first horizontal block period. A liquid crystal display device. The method of claim 1, And each of the first and second adjustment common voltages applied to the same horizontal block within the one horizontal block period is varied in stages in units of a plurality of predetermined frame periods. 6. The method of claim 5, And when the first and second adjustment common voltages are in phase, the levels of the first and second adjustment common voltages are equal to each other within the first horizontal block period of the same frame period. 6. The method of claim 5, When the first and second regulated common voltages are in phase, the level of the first and second regulated common voltages within the first horizontal block period of the same frame period is based on the DC common voltage corresponding to the black gray level. Liquid crystal display characterized in that they are symmetrical to each other. And a plurality of data lines and a plurality of gate lines intersecting and arranged in a matrix form, each of which is formed in parallel with the data lines at one side and the other short side thereof and is commonly connected to common electrodes of the liquid crystal cells. A driving method of a liquid crystal display device comprising a liquid crystal display panel having first and second common voltage supply wirings and divided into a plurality of horizontal blocks. In order to change the level of the common voltage between the adjacent horizontal blocks of the liquid crystal display panel, a first adjustment common voltage whose level is varied in units of one horizontal block period is generated and supplied to the first common voltage supply wiring. And generating a second regulated common voltage whose level varies in units of the first horizontal block period and supplying the second common voltage supply wiring to the second common voltage supply wiring; And The first common common voltage from the first common voltage supply line is commonly applied to the common electrodes of the liquid crystal cells, and the second common common voltage from the second common voltage supply line is common to the liquid crystal cells. Applying in common to the electrodes; The first and second regulated common voltages have the same phase or have different phases within the first horizontal block period, and the level variable width of the second regulated common voltage between the highest level and the lowest level is And a level variable width of the first adjustment common voltage. 9. The method of claim 8, And each of the first and second regulated common voltages applied to the same horizontal block within the one horizontal block period is fixed at any one of a plurality of levels in every frame. 9. The method of claim 8, And a level of each of the first and second adjustment common voltages applied to the same horizontal block within the one horizontal block period is varied stepwise in units of a plurality of predetermined frame periods.

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