KR101264719B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of reducing the number of data lines and thus reducing manufacturing cost and power consumption.

A liquid crystal display according to the present invention is formed for each region defined by a plurality of data lines and gate lines, and a plurality of colors in which three colors are repeatedly arranged in the direction of the data line and the same color is arranged in the direction of the gate line. A liquid crystal panel having pixel cells, a gate embedded circuit formed in the liquid crystal panel to supply a gate-on voltage to gate lines, and driving the gate embedded circuit and inverted in the data line unit and inverted in the frame unit And a flexible printed circuit connecting the liquid crystal panel to an external driving system, and a driving integrated circuit mounted on the liquid crystal panel to supply an image signal to the data lines.

Integrated circuit, liquid crystal panel, pixel cell, polarity, image signal

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a schematic view of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a block diagram schematically illustrating the driving integrated circuit shown in FIG. 1. FIG.

FIG. 3 is a diagram showing a data signal aligned by the signal controller shown in FIG. 2; FIG.

4 is a waveform diagram illustrating a driving waveform of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a schematic view of a liquid crystal display according to a second exemplary embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

100: liquid crystal panel 102: lower substrate

104: upper substrate 110: pixel cell

112: thin film transistor 114: pixel electrode

120: embedded circuit circuit 130: drive integrated circuit

200: flexible printed circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display which can reduce manufacturing cost and power consumption by reducing the number of data lines.

In general, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

To this end, a liquid crystal display device includes a liquid crystal panel including liquid crystals injected between two glass substrates and switching elements for switching signals supplied to the pixel cells and the pixel cells arranged in a matrix form, and a liquid crystal panel. A driving circuit unit for driving and a back light unit for irradiating light to the liquid crystal panel is configured.

In recent years, the number of signal lines or the number of circuit components of a liquid crystal panel has been reduced, so that a thin, light and inexpensive liquid crystal display device has been developed. Accordingly, in Korean Patent Laid-Open Publication No. 2003-39972, a single integrated driving chip for driving a liquid crystal display panel is mounted in the peripheral area of the display area, thereby reducing the process time and the defective rate required for mounting the chip, and in addition, the overall size. An on-glass single chip liquid crystal display that can reduce the number of pixels has been proposed.

However, the on-glass single chip liquid crystal display has the following problems.

First, since each pixel has a vertical stripe structure in which pixels of a color constituting a unit pixel are arranged in a horizontal direction (gate line direction) of the liquid crystal display panel, a large number of data lines supplying image signals to the liquid crystal display panel is disadvantageous. have.

Second, since the size of the integrated driving chip increases due to the increase in the number of data lines, there is a problem in that it cannot be applied to anything other than a small liquid crystal display panel (for example, a resolution of 360 × 160).

Third, there is a disadvantage that an additional circuit such as a selection circuit is required to reduce the number of data lines.

Fourth, the charging time of the pixel data is reduced by time-dividing analog pixel data into a plurality of data lines by using a selection circuit during the active period of the gate line, and the resolution of the liquid crystal display panel is designed in consideration of the charging time of the pixel data. There is a problem that must be done.

Fifth, there is a problem that power consumption is high by inverting the analog pixel data output from each channel of the integrated driving chip in units of horizontal lines.

Accordingly, in order to solve the above problems, the present invention is to provide a liquid crystal display device that can reduce the number of data lines to reduce the manufacturing cost and power consumption.

In addition, the present invention provides a liquid crystal display device capable of improving image quality.

According to an exemplary embodiment of the present invention, an LCD includes an area defined by m data lines (where m is a natural number) and n (where n is a natural number) gate lines. A liquid crystal panel having a plurality of pixel cells formed each time and having three colors repeatedly arranged in the direction of the data line and having the same color disposed in the direction of the gate line, and a gate-on voltage applied to the gate lines. A gate integrated circuit to be supplied, a driving integrated circuit mounted on the liquid crystal panel to drive the gate embedded circuit and to supply an image signal which is inverted in units of data lines and inverted in units of frames to the data lines; And a flexible printed circuit connecting the liquid crystal panel to an external driving system.

According to another exemplary embodiment of the present invention, a liquid crystal display device is formed for each region defined by m (where m is a natural number) data lines and n (where n is a natural number) gate lines, and a direction of the data line is defined. A liquid crystal panel having a plurality of pixel cells in which three colors are repeatedly arranged and the same color is arranged in a direction of a gate line, a gate embedded circuit formed in the liquid crystal panel and supplying a gate-on voltage to the gate lines; A driving integrated circuit mounted on the liquid crystal panel to drive the gate embedded circuit and to supply an image signal of a color corresponding to each sub period to the data lines by dividing one horizontal section into a plurality of sections; It characterized in that it comprises a flexible printed circuit for connecting to an external drive system.

According to another exemplary embodiment of the present invention, a liquid crystal display device is formed for each region defined by m (where m is a natural number) data lines and n (where n is a natural number) gate lines, and a direction of the data line is defined. A liquid crystal panel having a plurality of pixel cells in which three colors are repeatedly arranged and the same color is arranged in a direction of a gate line, a gate embedded circuit formed in the liquid crystal panel and supplying a gate-on voltage to the gate line, A drive integrated circuit mounted on the liquid crystal panel to drive a gate embedded circuit and to supply an image signal to the data lines, and a flexible printed circuit connecting the liquid crystal panel to an external driving system. It features.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display according to the first exemplary embodiment of the present invention is formed for each region defined by the plurality of data lines DL and the gate lines GL, and the direction of the data line (vertical direction). The liquid crystal panel 100 includes a plurality of pixel cells 110, in which three colors are repeatedly arranged and the same color is arranged in a direction of a gate line (horizontal direction), and gate lines are formed on the liquid crystal panel 100. The gate integrated circuit 120 driving the GL and the driving integrated circuit 130 mounted on the liquid crystal panel 100 to drive the gate embedded circuit 120 and supply image signals to the data lines DL. And a flexible printed circuit 200 attached to the liquid crystal panel 100 and connecting the liquid crystal panel 100 to an external driving system (not shown).

The liquid crystal panel 100 includes a lower substrate 102 and an upper substrate 104 bonded together to face each other, a spacer (not shown) for maintaining a constant cell gap between the two substrates 102 and 104, and a spacer. It is configured to include a liquid crystal layer (not shown) filled in the liquid crystal space provided.

The lower substrate 102 includes a display region corresponding to the upper substrate 104 and a non-display region excluding the display region.

In the display area of the lower substrate 102, a plurality of data lines DL formed in parallel in the first direction to have a predetermined distance, and a plurality of data lines DL formed in parallel in the second direction crossing the first direction to have a predetermined distance. And a pixel cell 110 formed in each region defined by the gate line GL and the plurality of data lines DL and the gate lines GL. In this case, the data lines DL to which the image signal is supplied are formed to have a smaller number than the gate lines GL to which the gate on voltage is supplied.

Each of the pixel cells 110 includes a thin film transistor 112 connected to a gate line GL and a data line DL, and a pixel electrode 114 connected to the thin film transistor 112.

The thin film transistor 112 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the pixel electrode 114. In this case, each of the thin film transistors 112 is disposed in a staggered form along the data line DL. That is, the thin film transistors 112 of each of the two pixel cells 112 adjacent to each other vertically along the data line DL are connected to different data lines DL. Accordingly, each of the thin film transistors 112 connected to the odd-numbered gate lines GL2n-1 supplies the image signals from the first to mth data lines DL1 to DLm to the pixel electrodes 114, and is even. Each of the thin film transistors 112 connected to the first gate line GL2n supplies an image signal from the second to m + 1th data lines DL2 to DLm + 1 to each pixel electrode 114.

The length of the short side parallel to the data line DL is formed to be shorter than the long side parallel to the gate line GL. Accordingly, the pixel electrode 114 has a horizontal stripe shape.

The gate embedded circuit 120 connected to each of the plurality of gate lines GL is formed in the non-display area of the lower substrate 102, and the driving integrated circuit 130 is mounted.

The upper substrate 104 includes a color filter, a common electrode, a light shielding layer, and the like. Here, the common electrode may be formed on the lower substrate 102 according to the liquid crystal formed on the liquid crystal layer.

In the color filter, a red (R) color filter, a green (G) color filter, and a blue (B) color filter are repeatedly formed in the direction of the data line DL and have the same color along the direction of the gate line GL. do.

The common electrode may be formed on the entire surface of the upper substrate 104 to face the pixel electrode 114 to form a vertical electric field in the liquid crystal layer, or may be formed in a line shape. The common electrode may be formed on the lower substrate 102 to be parallel to the pixel electrode 114 to form a horizontal electric field in the liquid crystal layer.

The light shielding layer is formed on the upper substrate 104 so as to overlap with the remaining region except for the opening region overlapping the pixel electrode 114.

The pixel cells of red (R), green (G), and blue (B) in which the red (R) color filter, the green (G) color filter and the blue Thereby forming a unit pixel.

The flexible printed circuit 200 is provided in the non-display area of the lower substrate 102 and attached to the pad portion. The flexible printed circuit 200 transmits the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the driving system to the driving integrated circuit 130.

The driving integrated circuit 130 is mounted on an integrated circuit mounting unit in which a plurality of input / output pads are formed in a non-display area of the lower substrate 102. Accordingly, each of the plurality of input / output bumps provided in the driving integrated circuit 130 is mounted to be electrically connected to each of the input / output pads of the integrated circuit mounting unit.

The driving integrated circuit 130 uses one of the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the flexible printed circuit 200 to determine one horizontal section corresponding to one period of the horizontal synchronization signal Hsync. A gate driving signal and a data control signal for driving by dividing into first to third sub-sections are generated.

In addition, the driving integrated circuit 130 aligns the source data signal Data with the red data R, the green data G, and the blue data B corresponding to each of the first to third sub-sections, and then the analog signal. The image signal is converted into an in image signal and supplied to the data lines DL.

To this end, the driving integrated circuit 130 may include the signal relay 310, the first power generator 320, the clock generator 322, the reference voltage setting unit 324, and the second as shown in FIG. 2. The power generator 326, the common voltage generator 328, the signal controller 330, the control signal generator 340, the booster circuit 350, the gray voltage generator 360, and the data converter 380 It is configured to include.

The signal relay 310 relays the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the flexible printed circuit 200 to the signal controller 330.

The clock generator 322 generates a clock for driving the first and second power generators 326.

The first power generator 320 generates the first power source, that is, the first and second power sources, according to the clock supplied from the clock generator 322, using the input power Vin supplied from the flexible printed circuit 200, To generate voltages VSP and VSN. The passive elements such as the resistor 210, the capacitors 220 and the inductors 230 mounted on the flexible printed circuit 200 are electrically connected to the first power source 320 through the power signal lines 321a, 321b and 321c, And is used to bias the first and second reference voltages VSP and VSN generated by the first power generation unit 320 or to set an optional function of the driving integrated circuit 130. [

The second power generator 326 may generate a second power source, ie, a second power source, required to drive the liquid crystal panel 100 using the first and second reference voltages VSP and VSN generated by the first power generator 320. The first and second driving voltages Vdd and Vss, the integrated circuit driving voltage Vcc, the gate on voltage Von, and the gate off voltage Voff are generated.

The reference voltage setting unit 324 sets the levels of the first and second reference voltages VSP and VSN supplied from the first power generator 320 to the gray voltage generator 360.

The common voltage generator 328 uses the first and second driving voltages Vdd and Vss supplied from the second power generator 326 through the passive element of the flexible printed circuit 200 to form the liquid crystal panel 100. Generates a common voltage to be supplied to the common electrode. In this case, the flexible printed circuit 200 may include a common voltage variable part (not shown) for varying the common voltage Vcom generated by the common voltage generator 328 using at least one of a resistor and a capacitor (not shown). It is configured to include.

The signal controller 330 controls driving of the signal relay 310 and controls internal circuit blocks of the driving integrated circuit 130.

In addition, as illustrated in FIG. 3, the signal controller 330 aligns the source data signal Data supplied from the signal relay 310 to be suitable for driving the liquid crystal panel 100, and arranges the data RGB. Is supplied to the data converter 380.

In detail, the signal controller 330 may include the red data R and the green data G so that the source data signal Data of the one horizontal section supplied from the signal relay 310 corresponds to each of the first to third sub-sections. ) And blue data (B).

In addition, the signal controller 330 converts the aligned red data R to odd-numbered data lines DL1, among the first to m-th data lines DL1 to DLm, during the first sub-section 1ST of one horizontal section. Rearranges the odd-numbered red data RO1 to ROm / 2 to be supplied to the DL3 to DLm-1 and the even-numbered red data RE1 to REm / 2 to be supplied to the even-numbered data lines DL2 and DL4 to DLm. .

Subsequently, the signal controller 330 converts the aligned green data G into even-numbered data among the second to m + 1 data lines DL2 to DLm + 1 during the second sub-section 2ST of one horizontal section. The odd green data GO1 to GOm / 2 to be supplied to the lines DL2 and DL4 to DLm and the even green data GE1 to GEm / to be supplied to the odd data lines DL3 to DLm + 1. Rearrange to 2).

Similarly, the signal controller 330 may arrange the aligned blue data B among the odd-numbered data lines DL1, among the first to m-th data lines DL1 to DLm, during the third sub-section 3ST of one horizontal section. Rearranges the odd blue data BO1 to BOm / 2 to be supplied to the DL3 to DLm-1 and the even blue data BE1 to BEm / 2 to be supplied to the even data lines DL2 and DL4 to DLm. .

The signal control unit 330 also supplies the control signal generation unit 340 with the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the signal relay unit 310.

The control signal generator 340 uses the at least one of the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the signal controller 330 to control the data control signals DST, DSC, DOE, and DPS and the gate driving signal ( RVst, RCLK1 to RCLKi).

The data control signals DST, DSC, DOE, and DPS include a data start signal DST, a data shift clock DSC, a data output signal DOE, and a data polarity signal for controlling the data converter 380. DPS). Here, the control signal generator 340 supplies image signals having different polarities to adjacent data lines DL and inverts the polarities of the image signals supplied to the data lines DL in at least one frame unit. To generate a data polarity signal (DPS). That is, the control signal generator 340 inverts the polarity of the image signal in data line units and generates a data polarity signal DSP of a column inversion method that inverts the data signal in at least one frame unit.

The gate driving signals RVst and RCLK1 to RCLKi include the gate start signal RVst for driving the gate embedded circuit 120 and the first to i th clock signals RCLK1 to RCLKi. At this time, each of the first to i th clock signals RCLK1 to RCLKi is sequentially delayed in phase so as to have a pulse width for turning on the thin film transistor in each sub-section. In addition, the first to i th clock signals RCLK1 to RCLKi may be any one of two phases, four phases, six phases, eight phases, and ten phases, depending on the gate embedded circuit 120.

The booster circuit 350 is provided with the gate driving signals RVst and RCLK1 supplied from the control signal generator 340 using the gate-on voltage Von and the gate-off voltage Voff supplied from the second power generator 326. To the voltage level of RCLKi). Here, the gate on voltage Von is a voltage for turning on the thin film transistor 112 of each pixel cell 110, and the gate off voltage Voff is a voltage for turning off the thin film transistor 112. . The booster circuit 350 supplies the boosted gate drive signals Vst and CLK1 to CLKi to the gate embedded circuit 120 through the gate drive signal transmission line 140 formed in the non-display area of the lower substrate 102. do.

The gray voltage generator 360 divides the first and second reference voltages VSP and VSN supplied from the first power generator 320 to generate a plurality of gray voltages, and supplies them to the data converter 380. . Here, the plurality of gray voltages generate 2 ^N gray voltages of positive polarity (+) and gray voltages of negative polarity (−) when the source data signal Data is N bits.

The data converter 380 includes a shift register 381, a latch 383, a digital-analog converter 385, a buffer 387, and a selector 389.

The shift register 381 sequentially shifts the data start signal DST according to the data shift clock DSC supplied from the control signal generator 340 to generate the shift signal SS. In this case, the shift register 381 may be a bidirectional shift register driven in both directions according to the direction signal supplied from the signal controller 330.

The latch unit 383 sequentially latches the data (RGB) of one horizontal line supplied from the signal controller 330 in accordance with the shift signal SS supplied from the shift register 381. The latch unit 383 supplies the data (RData) for one horizontal line latched in accordance with the data output signal DOE supplied from the control signal generating unit 340 to the digital-analog converter 385.

The digital-analog converter 385 analogizes the latched data RData supplied from the latch unit 383 using the plurality of positive and negative gray voltages supplied from the gray voltage generator 360. The signal is converted into positive and negative image signals PVS and NVS as signals. At this time, the digital-analog converter 385 selects one gray voltage corresponding to the gray value of the data RData latched from the plurality of positive gray voltages as the positive image signal PVS and at the same time a plurality of gray level voltages. One gray voltage corresponding to the gray value of the data RData latched in the negative gray voltages is selected as the negative image signal NVS.

The buffer unit 387 uses the first and second driving voltages Vdd and Vss supplied from the first power generator 320 through the passive element of the flexible printed circuit 200 to form a positive and negative image. Each of the signals PVS and NVS is buffered. At this time, the buffer unit 387 amplifies and outputs each of the positive and negative image signals PVS and NVS in consideration of the load of the data line DL.

The selector 389 selects the positive or negative image signals PVS and NVS supplied from the buffer unit 387 according to the data polarity signal DPS supplied from the control signal generator 340, and selects the first to first to third signals. The data lines DL are supplied to the data lines DL through the m + 1th output channel. At this time, the polarity of the image signal selected and output by the selector 389 is inverted in the unit of the output channel according to the data polarity signal DPS and in the unit of the frame.

In FIG. 1, the gate embedded circuit 120 is formed in the non-display area of the lower substrate 102 to be connected to each of the plurality of gate lines GL together with the process of forming the thin film transistor 112. The gate embedded circuit 120 generates a gate-on voltage for each sub-section according to the boosted gate driving signals Vst and CLK1 to CLKi supplied from the driver integrated circuit 130, and sequentially generates the gate-on voltage to the gate lines GL. To supply. In this case, the driving integrated circuit 130 receives the gate driving signals Vst and CLK1 to CLKi boosted through the plurality of gate driving signal transmission lines 140 formed in the non-display area of the lower substrate 102. Supplies).

4 is a waveform diagram illustrating a driving waveform of the liquid crystal display according to the first exemplary embodiment of the present invention.

Referring to FIG. 4, the driving of the liquid crystal display according to the first exemplary embodiment of the present invention will be described as follows.

First, odd-numbered data lines DL_odd of the first to m-th data lines DL1 to DLm are synchronized with the gate-on voltage supplied to the first gate line GL1 in the first sub-section of the first horizontal period. The red image signal R + of positive polarity (+) is supplied to the red image signal R− of negative polarity (−) to the even-numbered data lines DL_even. Accordingly, odd-numbered pixel cells 110 of each pixel cell 110 of the first horizontal line display a red image corresponding to the positive red image signal R +, and even-numbered pixel cells 110 are negative. A red image corresponding to the red image signal R- of polarity is displayed.

Subsequently, in the second sub-section of the first horizontal section, the odd-numbered data line among the second to m + 1 data lines DL2 to DLm + 1 is synchronized with the supply of the gate-on voltage to the second gate line GL2. The green image signal G + is supplied to the field DL_odd and the negative green image signal G− is supplied to the even-numbered data lines DL_even. Accordingly, the odd-numbered pixel cells 110 of the pixel cells 110 of the second horizontal line display the green image corresponding to the negative green image signal G- and the even-numbered pixel cells 110. Indicates a green image corresponding to the positive green image signal G +. At this time, the image signals displayed in the pixel cells 110 of the first and second horizontal lines adjacent to each other have different polarities.

Subsequently, in the third sub-section of the first horizontal section, the odd-numbered data lines DL_odd of the first to m-th data lines DL1 to DLm are synchronized with the gate-on voltage supplied to the third gate line GL3. The positive blue image signal B + is supplied and the negative blue image signal B- is supplied to the even-numbered data lines DL_even. Accordingly, the odd-numbered pixel cells 110 of the pixel cells 110 of the third horizontal line display a blue image corresponding to the positive blue image signal B +, and the even-numbered pixel cells 110 may be A blue image corresponding to the negative blue image signal B- is displayed. At this time, the image signals displayed in the pixel cells 110 of the second and third horizontal lines adjacent to each other have different polarities.

In the first horizontal section divided into the first to third subdivisions, one color image is displayed by mixing red, green, and blue images sequentially by each subdivision.

Similarly, one color image is displayed in each pixel cell of each horizontal section after the first horizontal section in the same manner as the first horizontal section. In the next frame, the polarity of the image signal is reversed as described above.

Accordingly, the liquid crystal display according to the second exemplary embodiment of the present invention includes the pixel cells 110 arranged one by one in the direction of the data line DL so that the liquid crystal display according to the second embodiment of the present invention may be arranged in a column inversion manner from the driver integrated circuit 130. The polar pattern of the image signal supplied to the pixel cells 110 is displayed as a polar pattern of the one dot inversion method.

5 is a schematic view of a liquid crystal display according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display according to the second exemplary embodiment of the present invention has the same form as the liquid crystal display according to the first exemplary embodiment of the present invention except for the arrangement of the pixel cells 110. Have

Accordingly, in the liquid crystal display according to the second exemplary embodiment of the present invention, descriptions of other configurations except for the arrangement structure of the pixel cells 110 will be replaced with the above description.

The pixel cells 110 are alternately connected to two adjacent data lines along the direction of the data line. That is, each pixel cell 110 connected to a 4k-3 (where k is a natural number) gate line is connected to an adjacent left data line, and each pixel cell 110 connected to a 4k-2 gate line is It is connected to an adjacent left data line. On the other hand, each pixel cell 110 connected to the 4k-th gate line is connected to the adjacent right data line, and each pixel cell 110 connected to the 4k-th gate line is connected to the adjacent right data line. .

In addition, an image signal is supplied from the driver integrated circuit 130 to data lines connected to each pixel cell 110. In this case, the polarity of the image signal is inverted for each data line and inverted in at least one frame unit.

Accordingly, the liquid crystal display according to the second exemplary embodiment of the present invention includes the pixel cells 110 arranged in a staggered manner along the direction of the data line DL so that the liquid crystal display according to the second embodiment of the present invention may be arranged in a column inversion manner from the driving integrated circuit 130. The polar pattern of the image signal supplied to the pixel cells 110 is displayed as a polar pattern of the vertical two dot inversion method. In this case, in the vertical two-dot inversion polarity pattern, the polarity of the image signal is inverted in units of two pixel cells along the direction of the data line, and the polarity of the image signal is inverted in units of the data line.

As a result, the liquid crystal display according to the second exemplary embodiment of the present invention displays a column inversion image signal output from the driving integrated circuit 130 on the liquid crystal panel 100 in a vertical two dot inversion manner. Image quality defects such as dot flicker can be improved. In addition, the liquid crystal display according to the second exemplary embodiment of the present invention improves the charging time of each pixel cell 110 by inverting the polarity of the image signal output from the driving integrated circuit 130 in at least one frame unit. The image quality can be improved by improving the delay characteristic of the image signal.

As described above, the liquid crystal display according to the exemplary embodiments of the present invention has a horizontal stripe structure in which each pixel cell is arranged in a vertical direction so that the number of data lines is reduced to 1/3 so that not only the small liquid crystal display device. It can also be applied to a medium-size liquid crystal display.

Meanwhile, in the above-described liquid crystal display according to the exemplary embodiments of the present invention, the pixel cells 110 are alternately arranged one by one or two in the direction of the data line DL, but the present invention is not limited thereto. In consideration of this, at least three may be staggered along the direction of the data line DL.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

The liquid crystal display according to the exemplary embodiment of the present invention as described above provides the following effects.

First, by driving a liquid crystal panel with one driving integrated circuit and incorporating a driving integrated circuit into a liquid crystal panel, the unit cost can be reduced and the thickness of the liquid crystal display device can be minimized.

Second, the power consumption can be reduced by inverting the polarity of the image signal in the data line unit and in the frame unit.

Third, the image quality can be improved by minimizing the polarity change of the image signal to secure the charging time of the image signal.

Fourth, since the pixel cells are arranged in the horizontal direction, the number of data lines is reduced to 1/3, so that the pixel cells can be applied not only to the small liquid crystal display but also to the medium liquid crystal display.

Fifth, it is possible to reduce the unit cost of the flexible printed circuit by minimizing the size of the flexible printed circuit by driving the liquid crystal panel using only one integrated circuit.

Sixth, gate driver integrated circuits, gate flexible printed circuits, and gate printed circuit boards can be removed by incorporating a gate driver for driving the gate lines into the liquid crystal panel.

Seventh, the manufacturing process of the liquid crystal panel, the process of mounting the driving integrated circuit, and the process of attaching the flexible printed circuit are manufactured to simplify the manufacturing process and minimize the defect rate.

Eighth, image quality defects such as dot flicker can be improved by displaying a column inversion type image signal supplied to the liquid crystal panel in a vertical two dot inversion manner.

Ninth, the polarity of the image signal output from the driving integrated circuit is inverted by at least one frame unit, thereby improving charging time of each pixel cell and improving delay quality of the image signal, thereby improving image quality.

Claims (15)

It is formed for each area defined by m (where m is a natural number) data lines and n (where n is a natural number) gate lines, and three colors are repeatedly arranged in the direction of the data line and the direction of the gate line. A liquid crystal panel having a plurality of pixel cells in which the same colors are arranged; A gate embedded circuit formed in the liquid crystal panel and supplying a gate-on voltage to gate lines; The data lines may be configured to drive the gate embedded circuit and to divide one horizontal section into a plurality of sections so that the image signal of a color corresponding to each sub section is inverted in the data line unit and inverted in at least one frame unit. A driving integrated circuit mounted on the liquid crystal panel for supplying to the liquid crystal panel; A flexible printed circuit connecting the liquid crystal panel to an external driving system; The driving integrated circuit, A signal relay unit for relaying a source data signal and a synchronization signal from the driving system through the flexible printed circuit; A first power generating unit for generating a first power source, A second power generator for generating a second power using the first power source, A common voltage generator supplying a common voltage to the liquid crystal panel using the second power supply; A signal controller for aligning the source data signal supplied from the signal relay to be suitable for driving the liquid crystal panel and controlling the inside of the driving integrated circuit; A control signal generator for generating a gate driving signal and a data control signal for driving the gate embedded circuit using the synchronization signal supplied through the signal controller; A boosting circuit for boosting the voltage level of the gate driving signal using the second power supply and supplying the voltage to the gate embedded circuit; A gradation voltage generator for generating a plurality of gradation voltages using the first power source, And a data converter which converts the sorted data signal supplied from the signal controller into the image signal using the plurality of gray voltages according to the data control signal. delete delete The method of claim 1, Each pixel cell has a stripe structure in which a long side parallel to the gate line is longer than a short side parallel to the data line. 5. The method of claim 4, And at least one pixel cell is alternately connected to adjacent data lines along a direction of the data line. 6. The method of claim 5, The pixel cells are alternately connected one by one to adjacent data lines. The pixel cells connected to the odd-numbered gate lines are connected to an adjacent left data line, And the pixel cells connected to an even-numbered gate line are connected to an adjacent right data line. 6. The method of claim 5, The pixel cells are alternately connected to each other by adjacent data lines. Each pixel cell connected to a 4k-3 (where k is a natural number of 1 to n / 4) th gate line is connected to an adjacent left data line, Each pixel cell connected to the 4k-2th gate line is connected to an adjacent left data line, Each pixel cell connected to the 4k-1th gate line is connected to an adjacent right data line, And each pixel cell connected to a 4kth gate line is connected to an adjacent right data line. delete The method of claim 1, The driving integrated circuit, A clock generator for generating a clock for driving the first and second power generators; And a level setting unit which sets a voltage level of the first power supplied from the first power generation unit and supplies the voltage level to the gray level voltage generation unit. The method of claim 9, The signal controller divides one horizontal section into first to third subdivisions, and aligns the source data signal of the first horizontal section with data of first to third colors so as to correspond to each subdivision. Liquid crystal display. 11. The method of claim 10, The signal control unit, Rearranging the aligned data such that the image signal is supplied to first to m-th data lines in the sub-section in which the odd-numbered gate line is driven, And rearranging the sorted data such that the image signal is supplied to second to m + 1th data lines in the sub-section in which the even-numbered gate line is driven. The method of claim 1, The data converter, A shift register for generating a shift signal, A latch unit for latching the aligned data signal according to the shift signal; A digital-to-analog converter for converting the latched data signal into positive and negative image signals using the plurality of gray voltages; A buffer unit for buffering the positive and negative image signals; And a selector for selecting the positive and negative image signals according to the data polarity signals supplied from the control signal generator and supplying the positive and negative image signals to the data lines through a plurality of output channels. . 13. The method of claim 12, And the control signal generator generates the data polarity signal for inverting the polarity of the image signal output from the selector in units of the output channel and inverting the polarity in units of at least one frame. The method of claim 1, And the flexible printed circuit includes a passive element including at least one of a resistor, a capacitor, and an inductor for biasing the first power supply or for an optional function of the driving integrated circuit. 15. The method of claim 14, The flexible printed circuit may include a common voltage varying part including at least one of a resistor and a capacitor for varying the common voltage.

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