CN111312192A - Drive circuit and liquid crystal display - Google Patents
Drive circuit and liquid crystal display Download PDFInfo
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- CN111312192A CN111312192A CN202010253217.9A CN202010253217A CN111312192A CN 111312192 A CN111312192 A CN 111312192A CN 202010253217 A CN202010253217 A CN 202010253217A CN 111312192 A CN111312192 A CN 111312192A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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Abstract
The application provides a driving circuit and a liquid crystal display, adjacent two sub-pixels in the same column of sub-pixels are respectively connected with a first type data line and a second type data line, adjacent two sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line, the polarity of a first type data signal input into the first type data line is opposite to that of a second type data signal input into the second type data line, so that a point inversion driving mode when the liquid crystal display displays is realized, the picture flicker phenomenon is improved, the longitudinal signal crosstalk is avoided, and meanwhile, the power consumption required by a driving chip is reduced.
Description
Technical Field
The present disclosure relates to liquid crystal display technologies, and particularly to a driving circuit and a liquid crystal display.
Background
In recent years, with the rapid development of the semiconductor Display industry, new technologies such as Low Temperature PolySilicon (LTPS), Active Matrix Organic Light emitting diode (AM-OLED), Micro-diode (Micro-LED), etc. have threatened Liquid Crystal Displays (LCD) in the middle and small size fields, but LCD still occupies an unmovable position in the large size Display field due to its mature technology and manufacturing process. Liquid crystal displays have become the mainstream display technology in the market today due to their advantages of high brightness, long lifetime, wide viewing angle, and large size.
At present, a panel architecture simplification technology is adopted to save the number of source driving chips, so as to reduce the manufacturing cost of a large-size liquid crystal display, which is one of the methods for further improving the competitiveness of the liquid crystal display. As shown in fig. 1, which is a schematic structural diagram of a driving circuit of a conventional liquid crystal display, the polarities of driving electrical signals input by 3 adjacent data lines are the same, and the sub-pixels in the same column are connected to the same data line, which may cause the problem of image flicker and crosstalk deterioration.
Disclosure of Invention
The present disclosure provides a driving circuit and a liquid crystal display, wherein the driving circuit can improve the flicker and the vertical crosstalk of electrical signals when the liquid crystal display is displaying, and reduce the power consumption required by the driving chip.
In order to achieve the above object, the present application provides a driving circuit for a liquid crystal display, where the driving circuit is configured to drive a plurality of sub-pixels arranged in an array to emit light, and the driving circuit includes:
the data line structure comprises a plurality of first-type data lines arranged in parallel and a plurality of second-type data lines arranged in parallel with the first-type data lines, wherein one second-type data line is arranged between any two adjacent first-type data lines;
two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line;
the data signals transmitted by each first type data line are first type data signals, and the data signals transmitted by each second type data line are second type data signals;
the polarity of the first type of data signal is opposite to the polarity of the second type of data signal.
In the above driving circuit, the driving circuit further comprises a demultiplexer, the demultiplexer comprises a first input terminal and a first output terminal, each of the first input terminals corresponds to at least two of the first output terminals to transmit the first type data signals loaded into each of the first input terminals to at least two of the first output terminals, each of the second input terminals corresponds to at least two of the second output terminals to transmit the second type data signals loaded into each of the second input terminals to at least two of the second output terminals, each of the first output terminals is connected to one of the first type data lines to output the first type data signals to the first type data lines, and each of the second output terminals is connected to one of the second type data lines to output the second type data signals to the second type data lines.
In the above driving circuit, each of the first input terminals corresponds to three of the first output terminals, and each of the second input terminals corresponds to three of the second output terminals.
In the above driving circuit, the demultiplexer further includes a first type switch and a second type switch, the first type switch is disposed between each of the first input terminals and each of the first output terminals, and the second type switch is disposed between each of the second input terminals and each of the second output terminals.
In the above driving circuit, the first type switch and the second type switch are both P-type thin film transistors or n-type thin film transistors.
A liquid crystal display, the liquid crystal display includes a driving circuit, the driving circuit is used for driving a plurality of sub-pixels arranged in an array to emit light, the driving circuit includes:
the data line structure comprises a plurality of first-type data lines arranged in parallel and a plurality of second-type data lines arranged in parallel with the first-type data lines, wherein one second-type data line is arranged between any two adjacent first-type data lines;
two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line;
the data signals transmitted by each first type data line are first type data signals, and the data signals transmitted by each second type data line are second type data signals;
the polarity of the first type of data signal is opposite to the polarity of the second type of data signal.
In the above liquid crystal display, the driving circuit further comprises a demultiplexer, the demultiplexer comprising a first input terminal and a first output terminal, each of the first input terminals corresponds to at least two of the first output terminals to transmit the first type data signals loaded into each of the first input terminals to at least two of the first output terminals, each of the second input terminals corresponds to at least two of the second output terminals to transmit the second type data signals loaded into each of the second input terminals to at least two of the second output terminals, each of the first output terminals is connected to one of the first type data lines to output the first type data signals to the first type data lines, and each of the second output terminals is connected to one of the second type data lines to output the second type data signals to the second type data lines.
In the above liquid crystal display, each of the first input terminals corresponds to three of the first output terminals, and each of the second input terminals corresponds to three of the second output terminals.
In the above-mentioned liquid crystal display, the demultiplexer further includes a first type switch and a second type switch, the first type switch is disposed between each of the first input terminals and each of the first output terminals, and the second type switch is disposed between each of the second input terminals and each of the second output terminals.
In the above liquid crystal display, the first type of switch and the second type of switch are both P-type thin film transistors or n-type thin film transistors.
Has the advantages that: the application provides a driving circuit and a liquid crystal display, adjacent two sub-pixels in the same column of sub-pixels are respectively connected with a first type data line and a second type data line, adjacent two sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line, the polarity of a first type data signal input into the first type data line is opposite to that of a second type data signal input into the second type data line, so that a point inversion driving mode during display is realized, the picture flicker phenomenon is improved, the longitudinal signal crosstalk is avoided, and meanwhile, the power consumption required by a driving chip is reduced.
Drawings
FIG. 1 is a diagram of a driving circuit of a conventional LCD;
FIG. 2 is a diagram of a driving circuit of a liquid crystal display according to a first embodiment of the present application;
FIG. 3 is a diagram of a driving circuit of a liquid crystal display according to a second embodiment of the present application;
fig. 4 is a timing diagram of the driving circuit shown in fig. 3.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Please refer to fig. 2, which is a diagram illustrating a driving circuit of a liquid crystal display according to a first embodiment of the present application. The driving circuit 100 is used for driving a plurality of sub-pixels arranged in an array to emit light. The sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R, the green sub-pixel G and the blue sub-pixel B are sequentially arranged in columns, one red sub-pixel R, one green sub-pixel G and one blue sub-pixel B form one pixel, and the pixels are repeatedly arranged in the row direction. The red light emitted by the red sub-pixel R, the green light emitted by the green sub-pixel G and the blue light emitted by the blue sub-pixel B jointly realize color picture display.
Each sub-pixel comprises a pixel circuit, liquid crystal and a color film layer. The pixel circuit controls the liquid crystal deflection state under the action of the input scanning signal and data signal. The color film layer comprises a red photoresist, a blue photoresist and a green photoresist, and is used for filtering light. The pixel circuits of each sub-pixel are the same, and the sub-pixels share a liquid crystal layer and are divided into a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B according to different light resistances included in the sub-pixels. Each sub-pixel corresponds to a pixel circuit, the pixel circuit at least comprises a switch TFT and a pixel capacitor electrically connected with the switch TFT, and after the switch TFT is turned on, the pixel capacitor is charged to apply voltage to the liquid crystal after the switch TFT is turned off, so that the sub-pixel emits light in a preset time period.
The driving circuit 100 includes a plurality of first type data lines arranged in parallel and a plurality of second type data lines arranged in parallel with the first type data lines. A second-type data line is arranged between any two adjacent first-type data lines, and a first-type data line is arranged between any two adjacent second-type data lines, namely the first-type data lines and the second-type data lines are alternately arranged in parallel. The data signals transmitted by each first type data line are first type data signals, and the data signals transmitted by each second type data line are second type data signals. The polarity of the first type of data signal is opposite to the polarity of the second type of data signal. For example, the first type of data signal is a positive polarity voltage, and the second type of data signal is a negative polarity voltage. The driving circuit 100 further includes a plurality of scan lines disposed in parallel, and the plurality of scan lines disposed in parallel perpendicularly intersect the first-type data lines and the second-type data lines.
A sub-pixel is arranged in a region enclosed by two adjacent scanning lines, one first-type data line and a second-type data line adjacent to the first-type data line. One end of each sub-pixel is connected with the scanning line to load scanning signals, and the other end of each sub-pixel is connected with one of the first type data line or the second type data line to input the first type data signals or the second type data signals. The sub-pixels in the same row are connected with the same scanning line. Two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line.
Specifically, as shown in fig. 2, the first type data lines include a data line L11, a data line L12, and a data line L13, and the second type data lines include a data line L21, a data line L22, and a data line L23, wherein the data line L11, the data line L21, the data line L12, the data line L22, the data line L13, and the data line L23 are arranged in parallel from left to right. A column of red sub-pixels R is disposed between the data line L11 and the data line L21, a column of green sub-pixels G is disposed between the data line L21 and the data line L12, a column of blue sub-pixels B is disposed between the data line L12 and the data line L22, a column of red sub-pixels R is disposed between the data line L22 and the data line L13, a column of green sub-pixels G is disposed between the data line L13 and the data line 23, and a column of blue sub-pixels B is disposed on a side of the data line L23 away from the data line L13. The scanning lines comprise a scanning line Gn, a scanning line Gn +1, a scanning line Gn +2 and a scanning line Gn +3 which are sequentially arranged from top to bottom. The same row of sub-pixels are all connected to the same scan line (Gn, Gn +1, Gn +2, and Gn +3), two adjacent red sub-pixels in the same column of red sub-pixels are respectively connected to the first type data line and the second type data line adjacent to the first type data line, for example, two adjacent red sub-pixels R in the same column of red sub-pixels R are respectively connected to the data line L11 and the data line L21, two adjacent red sub-pixels R in the same column of red sub-pixels R are respectively connected to the data line L22 and the data line L13, and the same column of green sub-pixels G and the same column of blue sub-pixels B are the same, which will not be described in detail herein. Two adjacent sub-pixels in the same row of sub-pixels are respectively connected to the first type data line and the second type data line adjacent to the first type data line, for example, the red sub-pixel R in one pixel is connected to the data line L11, and the green sub-pixel G in the pixel is connected to the data line L21.
The first data signal is a positive voltage, so that the data line L11, the data line L12, and the data line L13 input a positive voltage to the sub-pixels connected thereto, and the second data signal is a negative voltage, so that the data line L21, the data line L22, and the data line L23 input a negative voltage to the sub-pixels connected thereto. When the pixel circuit is composed of a switch TFT and a pixel capacitor connected with the drain electrode of the switch TFT, the grid electrode of the switch TFT is connected with the scanning line, the source electrode of the switch TFT is connected with the first type data line or the second type data line, and the liquid crystal is connected with the pixel capacitor in parallel. When a certain row of sub-pixels is scanned, scanning pulses enable all the switch TFTs on the row to be conducted, meanwhile, the first-class data lines or the second-class data lines apply voltages corresponding to the first-class data signals or voltages corresponding to the second data signals to the liquid crystal, namely, pixel capacitors connected in parallel with the liquid crystal are charged, after the row is scanned, all the switch TFTs are in an open circuit state, the pixel capacitors drive the liquid crystal, the liquid crystal maintains a deflection state under the action of the voltages of the pixel capacitors, and color pictures with different light and shade are displayed through color film filtering until next frame scanning comes.
Because two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, after a certain row of sub-pixels are scanned, voltage signals with opposite polarities are input into any two adjacent sub-pixels on the row of sub-pixels; because two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, after two adjacent rows of sub-pixels are scanned, two adjacent sub-pixels in the same column of sub-pixels input voltage signals with opposite polarities, namely, a point inversion driving mode during macroscopic display is realized, the image flicker phenomenon is improved, and the problem of longitudinal signal crosstalk is solved. In addition, compared with the prior art that the polarity of the voltage input to the same data line is periodically changed within the time of one frame of picture to realize the dot inversion, the dot inversion driving effect of macroscopic lighting is realized by matching the column inversion with the pixel inversion, and the voltage input to the same data line within the time of one frame of picture is kept unchanged, so that the energy consumption required by a driving chip is lower.
In the present embodiment, the driving circuit further includes a demultiplexer 101, and the demultiplexer 101(DEMUX circuit) can reduce the number of output lines of the driving chip for outputting the data signal. The demultiplexer includes first input terminals I1, first output terminals O1, second input terminals I2, and second output terminals O2, each of the first input terminals I1 corresponds to at least two first output terminals O1 to transmit the first type data signals loaded by each of the first input terminals I1 to at least two first output terminals O1, each of the second input terminals I2 corresponds to at least two second output terminals O2 to transmit the second type data signals loaded by each of the second input terminals I2 to at least two second output terminals O2, each of the first output terminals O1 is connected to one first type data line to output the first type data signals to the first type data line, and each of the second output terminals O2 is connected to one second type data line to output the second type data signals to the second type data line. Each first input I1 alternates with each second input I2.
In the present embodiment, each first input terminal I1 corresponds to three first output terminals O1, each second input terminal I2 corresponds to three second output terminals O2, three first output terminals O1 corresponding to the same first input terminal I1 are respectively connected to three adjacent first-type data lines (a data line L11, a data line L12, and a data line L13), and three second output terminals O2 corresponding to the same second input terminal I2 are respectively connected to three adjacent second-type data lines (a data line L21, a data line L22, and a data line L23). Each of the first input terminals I1 and each of the second input terminals I2 is connected to a driving chip (not shown) such that the first type data signal and the second type data signal output from the driving chip are output to the first input terminal I1 and the second input terminal I2, respectively. It is to be understood that each first input I1 may correspond to six first outputs O1, and each second input I2 may correspond to six second outputs O2.
Please refer to fig. 3, which is a diagram illustrating a driving circuit of a liquid crystal display according to a second embodiment of the present application. The driving circuit 100 shown in fig. 3 is substantially similar to the driving circuit 100 shown in fig. 2, except that the demultiplexer 101 further includes a first type switch K1 and a second type switch K2, the first type switch K1 is disposed between each first input terminal I1 and each first output terminal O1, and the second type switch K2 is disposed between each second input terminal I2 and each second output terminal O2.
The first type of switch K1 is used for controlling the transmission of the first type of data signals from the first input terminal I1 to the first output terminal O1, and the second type of switch K2 is used for controlling the transmission of the second type of data signals from the second input terminal I2 to the second output terminal O2. The first type switch K1 and the second type switch K2 are both a P-type thin film transistor and an n-type thin film transistor. Specifically, the first switch K1 and the second switch K2 are both P-type thin film transistors.
The multiplexer further comprises control lines for controlling the on and off states of the first type of switch K1 and the second type of switch K2, each control line being connected to the first type of switch K1 and the second type of switch K2. Specifically, the control line includes a first control line SW1, a second control line SW2 and a third control line SW3, the first control line SW1 is connected to a first switch K1 for controlling the data line L11 and a second switch K2 for controlling the data line L22, so as to control the first data signal inputted from the data line L11 and the second data signal inputted from the data line L22 to be written into the corresponding sub-pixel, and the working principle of the second control line SW2 and the working principle of the third control line SW3 are the same, which is not described in detail herein.
Please refer to fig. 4, which is a timing diagram of the driving circuit shown in fig. 3. When a scan signal is loaded on a scan line Gn, the sub-pixels connected to the scan line Gn are all turned on, a first control line SW1 loads a control signal so that a first type switch K1 and a second type switch K2 connected to a first control line SW1 are turned on, a first type data signal and a second type data signal are respectively transmitted to a first output terminal O1 and a second output terminal O2, the first output terminal O1 and the second output terminal O2 respectively output a first type data signal in a data line L11 and a second type data signal in a data line L22 are written to two red sub-pixels, a second control line SW2 loads a control signal so that the second type data signal in the data line L21 and the first type data signal in the data line L13 are written to two green sub-pixels, a third control line SW3 loads a control signal so that the first type data signal in the data line L13 and the second type data signal in the data line L23 are loaded to two blue sub-pixels, therefore, after the scanning line Gn is loaded with the scanning signal, the polarities of any two adjacent sub-pixels in the same row of sub-pixels connected with the scanning line Gn are opposite; when the scanning line Gn +1 loads a scanning signal, the sub-pixels connected with the scanning line Gn +1 are all turned on, the first control line SW1 loads a control signal so that the second type of data signal in the data line L22 is written into the blue sub-pixel B, the second control line SW2 loads a control signal so that the second type of data signal in the data line L21 and the first type of data signal in the data line L13 are written into the two red sub-pixels, and the third control line SW3 loads a control signal so that the first type of data signal in the data line L12 and the second type of data signal in the data line L23 are written into the two blue sub-pixels, so that one of the first type of data signal and the second type of data signal is written into two adjacent sub-pixels in the same column of sub-pixels, and on the whole, the driving circuit realizes the dot inversion driving during the macro lighting.
The present application further provides a liquid crystal display, the liquid crystal display includes a driving circuit, the driving circuit is used for driving the sub-pixels arranged in a plurality of arrays to emit light, the driving circuit includes:
the data line structure comprises a plurality of first-type data lines arranged in parallel and a plurality of second-type data lines arranged in parallel with the first-type data lines, wherein one second-type data line is arranged between any two adjacent first-type data lines;
two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and a second data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and a second data line adjacent to the first type data line;
the data signals transmitted by each first-class data line are first-class data signals, and the data signals transmitted by each second-class data line are second-class data signals;
the polarity of the first type of data signal is opposite to the polarity of the second type of data signal.
The driving circuit further comprises a multiplexer, wherein the multiplexer comprises first input ends, first output ends, second input ends and second output ends, each first input end corresponds to at least two first output ends so as to transmit the first type data signals loaded by each first input end to at least two first output ends, each second input end corresponds to at least two second output ends so as to transmit the second type data signals loaded by each second input end to at least two second output ends, each first output end is connected with one first type data line so as to output the first type data signals to the first type data line, and each second output end is connected with one second type data line so as to output the second type data signals to the second type data line.
Each first input terminal corresponds to three first output terminals, and each second input terminal corresponds to three second output terminals.
The multi-path output selector also comprises a first type switch and a second type switch, wherein the first type switch is arranged between each first input end and each first output end, and the second type switch is arranged between each second input end and each second output end.
The first type switch and the second type switch are both P-type thin film transistors or n-type thin film transistors.
In the liquid crystal display provided by the embodiment of the application, the adjacent two sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line, the adjacent two sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and the polarities of the first type data signal input to the first type data line and the second type data signal input to the second type data line are opposite, so that a point inversion driving mode during display of the liquid crystal display is realized, the picture flicker phenomenon is improved, the longitudinal signal crosstalk is avoided, and the power consumption required by a driving chip is reduced.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A driving circuit for a liquid crystal display, the driving circuit for driving a plurality of sub-pixels arranged in an array to emit light, the driving circuit comprising:
the data line structure comprises a plurality of first-type data lines arranged in parallel and a plurality of second-type data lines arranged in parallel with the first-type data lines, wherein one second-type data line is arranged between any two adjacent first-type data lines;
two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line;
the data signals transmitted by each first type data line are first type data signals, and the data signals transmitted by each second type data line are second type data signals;
the polarity of the first type of data signal is opposite to the polarity of the second type of data signal.
2. The driver circuit of claim 1, further comprising a demultiplexer, the multi-output selector comprises first input ends, first output ends, second input ends and second output ends, wherein each first input end corresponds to at least two first output ends so as to transmit the first type data signals loaded by each first input end to at least two first output ends, each second input end corresponds to at least two second output ends so as to transmit the second type data signals loaded by each second input end to at least two second output ends, each first output end is connected with one first type data line so as to output the first type data signals to the first type data line, and each second output end is connected with one second type data line so as to output the second type data signals to the second type data line.
3. The driving circuit according to claim 2, wherein each of the first input terminals corresponds to three of the first output terminals, and each of the second input terminals corresponds to three of the second output terminals.
4. The driving circuit of claim 3, wherein the demultiplexer further comprises a first type switch and a second type switch, the first type switch being disposed between each of the first input terminals and each of the first output terminals, and the second type switch being disposed between each of the second input terminals and each of the second output terminals.
5. The driving circuit according to claim 4, wherein the first type of switch and the second type of switch are both P-type thin film transistors or n-type thin film transistors.
6. A liquid crystal display, comprising a driving circuit for driving a plurality of sub-pixels arranged in an array to emit light, the driving circuit comprising:
the data line structure comprises a plurality of first-type data lines arranged in parallel and a plurality of second-type data lines arranged in parallel with the first-type data lines, wherein one second-type data line is arranged between any two adjacent first-type data lines;
two adjacent sub-pixels in the same column of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line, and two adjacent sub-pixels in the same row of sub-pixels are respectively connected with the first type data line and the second type data line adjacent to the first type data line;
the data signals transmitted by each first type data line are first type data signals, and the data signals transmitted by each second type data line are second type data signals;
the polarity of the first type of data signal is opposite to the polarity of the second type of data signal.
7. The liquid crystal display of claim 6, wherein the driving circuit further comprises a demultiplexer, the multi-output selector comprises first input ends, first output ends, second input ends and second output ends, wherein each first input end corresponds to at least two first output ends so as to transmit the first type data signals loaded by each first input end to at least two first output ends, each second input end corresponds to at least two second output ends so as to transmit the second type data signals loaded by each second input end to at least two second output ends, each first output end is connected with one first type data line so as to output the first type data signals to the first type data line, and each second output end is connected with one second type data line so as to output the second type data signals to the second type data line.
8. The liquid crystal display of claim 7, wherein each of the first input terminals corresponds to three of the first output terminals, and each of the second input terminals corresponds to three of the second output terminals.
9. The lcd of claim 8, wherein the demultiplexer further comprises a first type switch and a second type switch, the first type switch being disposed between each of the first input terminals and each of the first output terminals, and the second type switch being disposed between each of the second input terminals and each of the second output terminals.
10. The liquid crystal display of claim 9, wherein the first type of switch and the second type of switch are both P-type thin film transistors or n-type thin film transistors.
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| CN202010253217.9A CN111312192A (en) | 2020-04-02 | 2020-04-02 | Drive circuit and liquid crystal display |
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| CN202010253217.9A CN111312192A (en) | 2020-04-02 | 2020-04-02 | Drive circuit and liquid crystal display |
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Application publication date: 20200619 |