KR101184775B1 - Semiconductor light emitting element and manufacturing method thereof - Google Patents

Abstract

The semiconductor light emitting element LE1 includes a multilayer structure LS for generating light. The multilayer structure includes a plurality of stacked compound semiconductor layers 3-8 and has first and second main surfaces 61 and 62 opposing each other. The first electrode 21 is disposed on the first main surface, and the second electrode 31 is disposed on the second main surface. On the first main surface, a film 10 made of silicon oxide is also formed to cover the first electrode. The glass plate 1, which is optically transparent to light generated by the multilayer structure, is fixed to the multilayer structure through a film made of silicon oxide.

Description

Semiconductor light emitting device and its manufacturing method {SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF}

TECHNICAL FIELD This invention relates to a semiconductor light emitting element and its manufacturing method.

In recent years, with the increase of the drive frequency of a CPU (for example, 10 GHz or more), the optical interconnection technique which transmits the signal in a system apparatus and between apparatuses by light is attracting attention. In this optical interconnection technology, optical semiconductor elements such as semiconductor light receiving elements and semiconductor light emitting elements are used.

Japanese Unexamined Patent Application Publication No. 2-128481 which includes a substrate and a plurality of compound semiconductor layers laminated on one main surface of the substrate, and emits light from the other main surface of the substrate. , Japanese Patent Laid-Open No. 10-200200, and Japanese Patent Laid-Open No. 11-46038. In such a semiconductor light emitting device, a portion located below the light emitting region of the substrate is partially thinned, and a portion having a substrate thickness is formed so as to surround the portion. The first object is to prevent optical signal degradation or loss due to light absorption of the substrate. A second object is to prevent the semiconductor light emitting element from being damaged or damaged when the semiconductor light emitting element is installed on the external substrate by wire bonding or bump bonding.

However, in the above-described semiconductor light emitting device, there is a part which maintains the thickness of the substrate. Therefore, there is a limit in miniaturization of the semiconductor light emitting device. In particular, in the case where a plurality of light emitting portions are provided in parallel to form a light emitting element array, it is difficult to narrow the pitch between the light emitting portions, so that the size of the light emitting element array is inevitably large.

An object of the present invention is to provide a semiconductor light emitting device having sufficient mechanical strength and capable of miniaturization, and a method of manufacturing the same.

The semiconductor light emitting device according to the present invention includes a plurality of compound semiconductor layers laminated, and has first and second main surfaces facing each other, and is disposed on the first main surface of the multilayer structure and the multilayer structure that generate light. The first electrode, the second electrode disposed on the second main surface of the multilayer structure, the film formed on the first main surface of the multilayer structure so as to cover the first electrode, and made of silicon oxide, and the multilayer structure The glass substrate which is optically transparent with respect to the produced | generated light, and was fixed to the multilayer structure through the film | membrane which consists of silicon oxide is provided.

Even if the plurality of compound semiconductor layers included in the multilayer structure is made thin, the mechanical strength of the multilayer structure is maintained by the glass substrate. Moreover, since it is not necessary to form the part which kept the board | substrate thickness like the prior art mentioned above, miniaturization of an element is easy.

Since the silicon oxide can be fused to glass, the multilayer structure and the glass substrate can be bonded to each other without using an adhesive. Therefore, the light emitted from the multilayer structure can reach the glass substrate without being absorbed by the adhesive.

The film made of silicon oxide preferably has a flat surface in contact with the glass substrate. Since the unevenness | corrugation by a 1st electrode is eliminated by the film | membrane which consists of silicon oxide, a glass substrate can be easily and reliably adhere | attached to the 1st main surface of a multilayer structure through the film | membrane which consists of silicon oxide.

In addition, the multilayer structure includes a first conductive type contact layer, a first distributed Bragg reflector (DBR) layer of a first conductive type, a first cladding layer of an first conductive type, an active layer, and a first stacked type as a plurality of compound semiconductor layers. The second cladding layer of the second conductivity type and the second DBR layer of the second conductivity type may be included. The multilayer structure may have a multilayer region partially comprising a contact layer, a first DBR layer, a first clad layer, an active layer, and a second clad layer, and a current confinement region surrounding the multilayer region and insulated or semi-insulated. do. In this case, a surface light emitting semiconductor light emitting element can be obtained.

The semiconductor light emitting element according to the present invention may further include a first pad electrode disposed on the second main surface of the multilayer structure and a through wiring penetrating through the multilayer structure. The first electrode may include a wiring electrode electrically connected to a portion included in the multilayer region of the contact layer, and the wiring electrode may be electrically connected to the first pad electrode through the through wiring. The second electrode may include a second pad electrode electrically connected to the second DBR layer. Since the first pad electrode and the second pad electrode are arranged on the side opposite to the light exit surface, the semiconductor light emitting element can be easily installed.

The semiconductor light emitting element according to the present invention may further include bump electrodes disposed on the first pad electrode and the second pad electrode, respectively.

The multilayer structure may have a plurality of multilayer regions arranged side by side.

The semiconductor light emitting element according to the present invention may be further provided with a light reflection film provided on the second DBR layer and covering the multilayer region. Since the light reflected by the light reflection film is emitted from the glass substrate, the light emission output is improved.

The glass substrate may have a surface and a back surface. The surface of the glass substrate may be fixed to a film made of silicon oxide. The back surface of the glass substrate may have a lens portion that receives light emitted from the multilayer structure. The lens portion may be recessed than the highest portion of the rear surface of the glass substrate.

The manufacturing method of the semiconductor light emitting element which concerns on this invention is a process of preparing a semiconductor substrate, and providing the multilayer structure which produces | generates light on a semiconductor substrate, Comprising: The multilayer structure contains the several compound semiconductor layer laminated | stacked, and mutually A step in which the first and second main surfaces face each other and the second main surface is directed toward the semiconductor substrate, a step of forming the first electrode on the first main surface of the multilayer structure, and the first electrode Forming a film made of silicon oxide, preparing a glass substrate that is optically transparent to light generated by the multilayer structure, and having a surface and a back surface, and fusing the film made of silicon oxide to the surface of the glass substrate, Fixing the multilayer structure to the glass substrate, removing the semiconductor substrate, and forming a second electrode on the second main surface of the multilayer structure And it has a process.

In this method, a film made of silicon oxide is formed to cover the first electrode on the first main surface of the multilayer structure, and the semiconductor substrate is removed after the film made of silicon oxide is fused to the glass substrate. Thereby, the semiconductor light emitting element which has a structure in which the glass substrate was fixed to the 1st main surface of a multilayer structure through the film which consists of silicon oxide can be manufactured easily.

Since the glass substrate exists even after the semiconductor substrate is removed, even if the plurality of compound semiconductor layers included in the multilayer structure is made thin, the mechanical strength of the multilayer structure is maintained by the glass substrate. Moreover, since it is not necessary to form the part which maintained the board | substrate thickness like the prior art mentioned above, size reduction of an element is easy. In addition, before fixing the glass substrate to the multilayer structure, mechanical strength is maintained by the semiconductor substrate.

Since the glass substrate is fused to a film made of silicon oxide, the multilayer structure and the glass substrate can be bonded to each other without using an adhesive. Therefore, the light emitted from the multilayer structure can reach the glass substrate without being absorbed by the adhesive.

The method according to the present invention may further include a step of planarizing the film made of silicon oxide after forming the film made of silicon oxide and before fixing the multilayer structure to the glass substrate. Since the unevenness | corrugation by a 1st electrode is eliminated by the film | membrane which consists of silicon oxide, a glass substrate can be easily adhere | attached on the 1st main surface of a multilayer structure through the film | membrane which consists of silicon oxide.

The process of removing a semiconductor substrate may include the process of removing a semiconductor substrate by wet etching.

According to the method of the present invention, before the step of forming the multilayer structure, the etching stop layer for stopping wet etching is formed on the semiconductor substrate, and after the step of removing the semiconductor substrate, the etching stop layer is formed by wet etching. You may further include the process of removing. The process of forming a multilayer structure may include the process of forming a multilayer structure on an etch stop layer. The semiconductor substrate is removed by appropriately selecting and using an etchant which can etch the semiconductor substrate and cannot etch the etch stop layer, and an etchant that can etch the etch stop layer and cannot etch the compound semiconductor layer. After that, only the etch stop layer can be removed. Therefore, the semiconductor substrate can be removed reliably and easily by leaving the multilayer structure.

The multilayer structure includes a plurality of compound semiconductor layers, a first conductive type contact layer, a first distributed Bragg reflector (DBR) layer, a first conductive type first clad layer, an active layer, and a second conductive type. The second cladding layer and the second DBR layer of the second conductivity type may be included. The step of forming the multilayer structure may include a step of sequentially laminating a second DBR layer, the second clad layer, an active layer, a first clad layer, a first DBR layer, and a contact layer on a semiconductor substrate. The method according to the present invention encloses and insulates or semi-insulates a multi-layered region partially comprising a contact layer, a first DBR layer, a first cladding layer, an active layer, and a second cladding layer after the step of forming the multilayer structure. The process of forming the formed current confinement region in the multilayer structure may be further provided. In this case, a surface light emitting semiconductor light emitting element can be obtained.

The process of forming a 1st electrode may include the process of forming the wiring electrode electrically connected to the part contained in a multilayer area among contact layers after the process of forming a current constriction area | region. The step of forming the second electrode may include a step of forming a second pad electrode electrically connected to the second DBR layer. The method according to the present invention further includes a step of forming a first pad electrode on the second main surface of the multilayer structure after the step of removing the semiconductor substrate, and electrically connecting the first pad electrode and the wiring electrode. You may do it. Since the first pad electrode and the second pad electrode are arranged on the side opposite to the light exit surface, the semiconductor light emitting element can be easily installed.

The step of electrically connecting the first pad electrode and the wiring electrode may include a step of forming a through wiring penetrating through the multilayer structure, and electrically connecting the first pad electrode to the wiring electrode through the through wiring. In this case, the first pad electrode can be reliably electrically connected to the wiring electrode.

The method according to the present invention may further include a step of forming a light reflection film covering the multilayer region on the second DBR layer. In this case, since the light reflected by the light reflection film is also emitted from the glass substrate, the light emission output can be improved.

The back surface of the glass substrate may have a lens portion that receives light emitted from the multilayer structure. In this case, the lens unit can improve the directivity of the emitted light or obtain parallel light.

The lens portion may be recessed than the highest portion of the rear surface of the glass substrate. In this case, the glass substrate having a lens portion can be easily fused to a film made of silicon oxide. In addition, if the lens portion is processed before fusion, the lens processing method is less limited, and thus the degree of freedom in lens design such as lens shape increases.

The understanding of the present invention is further deepened by the following detailed description and accompanying drawings. In addition, the accompanying drawings are only examples, and are not intended to limit the scope of the present invention.

1 is a schematic plan view of a semiconductor light emitting element according to a first embodiment.

2 is a schematic cross-sectional view taken along the line II-II in FIG. 1.

3 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

4 is a schematic cross-sectional view showing a process for manufacturing the semiconductor light emitting element according to the first embodiment.

5 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting device according to the first embodiment.

6 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting device according to the first embodiment.

7 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

8 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

9 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

10 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

11 is a schematic cross-sectional view illustrating a process of manufacturing the semiconductor light emitting element according to the first embodiment.

12 is a schematic cross-sectional view of a semiconductor light emitting element according to the second embodiment.

13 is a schematic cross-sectional view illustrating a process for manufacturing the semiconductor light emitting element according to the second embodiment.

14 is a schematic cross-sectional view of a semiconductor light emitting element array according to the present embodiment.

15 is a schematic cross-sectional view of a semiconductor light emitting element array according to the present embodiment.

16 is a schematic plan view of a semiconductor light emitting element array according to the present embodiment.

17 is a schematic plan view of a semiconductor light emitting element array according to the present embodiment.

18 is a schematic diagram showing a configuration of an optical interconnection system according to the present embodiment.

<Code description>

1 ... glass substrate,

1a ... lens part,

3, contact layer,

4... First DBR layer,

5. first cladding layer,

6 ... active layer,

7. second cladding layer,

8... Second DBR layer,

10 film composed of silicon oxide,

11b ... emitting region,

11a ... current confinement region,

12 ... multi-layered area,

21... First electrode,

23 p-side electrode,

25 wiring electrodes,

27 ... through-through wiring,

29 p side pad electrode,

31... Second electrode,

33 n-side pad electrode,

41 ... bump electrodes,

51 ... semiconductor substrate,

53 ... etching stop layer,

61 .. first principal plane,

62 the second principal plane,

71... Surface of glass substrate,

72 ... back side of glass substrate,

72a ... lens part,

LE1, LE2 ... semiconductor light emitting element,

LE3 to LE6 semiconductor light emitting element array

LS ... multilayer structure,

TH ... through-holes.

EMBODIMENT OF THE INVENTION The semiconductor light emitting element which concerns on embodiment of this invention is demonstrated with reference to drawings. In addition, in description, the description which overlaps using the same code | symbol is abbreviate | omitted to the same element or the element which has the same function.

First embodiment

1 is a schematic plan view of a semiconductor light emitting element according to the first embodiment. 2 is a schematic cross-sectional view taken along the line II-II in FIG. 1.

The semiconductor light emitting element LE1 includes a multilayer structure LS and a glass substrate 1. This semiconductor light emitting element LE1 is a back-emitting vertical resonator type surface emitting laser (VCSEL: Vertical Cavity Surface Emitting Laser) that emits light from the glass substrate 1 side. The semiconductor light emitting element LE1 is, for example, a light emitting element for short-range optical communication having a wavelength band of 0.85 mu m.

The multilayer structure LS is composed of a p-type (first conductive type) contact layer 3 stacked in this order, a p-type first distributed Bragg reflector (DBR) layer 4, and a p-type first cladding layer ( 5), an active layer 6, an n-type (second conductivity type) second cladding layer 7, and an n-type second DBR layer 8 are included. Insulated or semi-insulated current confinement regions 11a are formed in the multilayer structure LS. The current confinement region 11a includes a contact region 3, a first DBR layer 4, a first cladding layer 5, an active layer 6, and a second cladding layer 7. 12) is arranged to surround. The current confinement region 11a extends from the contact layer 3 to the vicinity of the boundary between the second clad layer 7 and the second DBR layer 8.

The multilayer structure LS has a first main surface 61 and a second main surface 62 facing each other. The multilayer structure LS generates light by applying a voltage, and emits the light from the back surface (light emitting surface) 62. The insulating films 19 and 20 are formed on the 1st and 2nd main surfaces 61 and 62 of the multilayer structure LS, respectively. The insulating films 19 and 20 are made of, for example, SiN _X and have a thickness of about 0.2 μm.

In the multilayer structure LS, the vertical resonator is constituted by the first DBR layer 4 and the second DBR layer 8 sandwiching the active layer 6. Moreover, in the multilayer structure LS, the current supplied to the active layer 6 is constricted by the current confinement region 11a, and the region to emit light is limited. That is, in the multilayer structure LS, the first cladding layer 5 mainly sandwiched between the first DBR layer 4 and the second DBR layer 8 among the multilayer regions 12 located inside the current confinement region 11a. The active layer 6 and the second cladding layer 7 function as the light emitting region 11b.

The first electrode 21 is disposed on the first main surface 61 of the multilayer structure LS. The first electrode 21 includes a p-side electrode (anode) 23 and a wiring electrode 25. The p-side electrode 23 is electrically connected to a region located inside the current blocking region 11a of the contact layer 3 through the contact hole 19a formed in the insulating film 19. The p-side electrode 23 consists of a laminated body of Cr / Au, and the thickness is about 1.0 micrometer. The p-side electrode 23 is arranged so as not to block light from the light emitting region 11b. The wiring electrode 25 is disposed on the insulating film 19 so as to be electrically connected to the p-side electrode 23. The wiring electrode 25 consists of a laminated body of Ti / Pt / Au, and the thickness is about 1.5 micrometers.

In the multilayer structure LS, holes TH penetrating from the first main surface 61 to the second main surface 62 are formed. The insulating film 20 is formed also on the wall surface of the multilayer structure LS which defines the through-hole TH. Through-wires 27 are provided inside the insulating film 20 in the through-holes TH. One end portion 27a of the through wiring 27 passes through the contact hole 20a formed in the insulating film 20 and is electrically connected to the wiring electrode 25.

The p-side pad electrode 29 (first pad electrode) and the second electrode 31 are disposed on the second main surface 62 of the multilayer structure LS. The p-side pad electrode 29 is made of a stack of Ti / Pt / Au, and its thickness is about 2 μm. The p-side pad electrode 29 is formed to cover the through wiring 27, and is electrically connected to an end 27 b located on the opposite side of the end 27 a of the through wiring 27. The bump electrode 41 is disposed on the p-side pad electrode 29. Extraction of the electrode on the anode side is realized by the contact layer 3, the p-side electrode 23, the wiring electrode 25, the through wiring 27, the p-side pad electrode 29, and the bump electrode 41.

The second electrode 31 includes an n-side pad electrode 33 (second pad electrode). The n-side pad electrode 33 is electrically connected to the second DBR layer 8 through the contact hole 20b formed in the insulating film 20. Therefore, extraction of the electrode on the cathode side is realized by the n-side pad electrode 33 and the bump electrode 41. The n-side pad electrode 33 is made of a stack of Ti / Pt / Au, and its thickness is about 2 μm. The bump electrode 41 is disposed on the n-side pad electrode 33 in the same manner as the p-side pad electrode 29.

A portion of the n-side pad electrode 33 covers the multilayer region 12 located inside the current confinement region 11a and the light emitting region 11b included in the multilayer region 12, the portion of which is light. It functions as a reflecting film. In addition, a light reflection film may be provided separately from the n-side pad electrode 33.

On the first main surface 61 of the multilayer structure LS, a film 10 is formed to cover the first electrode 21 (p-side electrode 23 and wiring electrode 25). The film 10 is made of silicon oxide (SiO ₂ ) and is optically transparent to light generated in the light emitting region 11b. The surface 10a on the side opposite to the multilayer structure LS in the film 10 is planarized. The thickness of the film 10 is about 3-10 micrometers.

The glass substrate 1 contacts the surface 10a of the film 10, and is affixed. The glass substrate 1 has a thickness of about 0.3 mm and is optically transparent to the emitted light.

In the compound semiconductor layer, the contact layer 3 is made of, for example, GaAs having a carrier concentration of about 1 × 10 ¹⁹ / cm ³ . The thickness of the contact layer 3 is about 0.2 micrometer. The contact layer 3 also functions as a buffer layer.

The first DBR layer 4 is a Miller layer having a structure in which a plurality of compound semiconductor layers having different compositions are laminated alternately. In the present embodiment, the 1 DBR layer 4 is the AlAs layer of the non-doped, carrier concentration of 1 × 10 ¹⁸ / cm AlGaAs of the ^third degree (Al composition 0.9) layer and a carrier concentration of 1 × 10 ¹⁸ / cm ^Three AlGaAs (Al composition 0.2) layers are alternately laminated by 20 layers. The thickness of the AlAs layer is about 0.1 μm. The thickness of each AlGaAs (Al composition 0.9) layer is about 0.04 micrometer, and the thickness of each AlGaAs (Al composition 0.2) layer is about 0.02 micrometer.

In the compound semiconductor layer, the first cladding layer 5 is made of AlGaAs having a carrier concentration of about 1 × 10 ¹⁸ / cm ³ , for example. The thickness of the first cladding layer 5 is about 0.1 μm.

The active layer 6 is a multiple quantum well (MQW) active layer having a structure in which different compound semiconductor layers are alternately stacked. In the present embodiment, the active layer 6 is composed of three layers of AlGaAs layers and GaAs layers alternately stacked. The thickness of each AlGaAs layer is about 0.1 μm, and the thickness of each GaAs layer is about 0.05 μm.

In the compound semiconductor layer, the second cladding layer 7 is made of AlGaAs having a carrier concentration of about 1 × 10 ¹⁸ / cm ³ , for example. The thickness of the second cladding layer 7 is about 0.1 μm.

The second DBR layer 8 is a Miller layer having a structure in which a plurality of compound semiconductor layers having different compositions are alternately laminated in the same manner as the first DBR layer 4. In the present embodiment, the 2 DBR layer 8 is a carrier concentration of 1 × 10 ¹⁸ / cm AlGaAs of the ^third degree (Al composition 0.9) layer and a carrier concentration of 1 × 10 ¹⁸ / cm AlGaAs (Al composition of the ^third degree 0.2) layers are alternately laminated by 30 layers, and the non-doped GaAs layer is laminated | stacked on it. The thickness of each AlGaAs (Al composition 0.9) layer is about 0.04 micrometer, and the thickness of each AlGaAs (Al composition 0.2) layer is about 0.02 micrometer. The GaAs layer functions as a buffer layer and its thickness is about 0.01 μm.

When a sufficient voltage is applied between the n-side pad electrode 33 and the p-side pad electrode 29 through the two bump electrodes 41 and a current flows in the light emitting element LE1, light is generated in the light emitting region 11b. .

Hereinafter, a method of manufacturing the semiconductor light emitting device LE1 will be described with reference to FIGS. 3 to 11. 3-11 is a figure for demonstrating this manufacturing method, and has shown the longitudinal cross section of semiconductor light emitting element LE1. In this production method, the following steps (1) to (9) are executed in sequence.

Process (1)

First, the semiconductor substrate 51 is prepared. The semiconductor substrate 51 is made of, for example, n-type GaAs having a thickness of 300 to 500 µm and a carrier concentration of about 1 × 10 ¹⁸ / cm ³ . On one main surface (surface) 81 of the semiconductor substrate 51, an etch stop layer 53 and an n-type second layer are formed by an organometallic chemical vapor deposition (MOCVD) method or a molecular beam growth (MBE) method. DBR layer 8, n-type second cladding layer 7, active layer 6, p-type first cladding layer 5, p-type first DBR layer 4, and p-type contact layer (3) is sequentially grown and stacked (see Fig. 3).

The etching stop layer 53 consists of non-doped AlGaAs (Al composition 0.5), and the thickness is about 1.0 micrometer. The etch stop layer 53 is formed to be located between the semiconductor substrate 51 and the second DBR layer 8. It is preferable that the Al composition ratio of the etching stop layer 53 shall be 0.4 or more. It is because AlGaAs whose Al composition ratio is 0.4 or more is hard to be etched by the etching liquid used when etching GaAs mentioned later.

By this step (1), the multilayer structure LS and the etch stop layer 53 are formed on the surface 81 of the semiconductor substrate 51.

Process (2)

Next, a resist film 55 is formed on the contact layer 3 (multilayer structure LS). The resistor film 55 is patterned to have an opening in a two-dimensional position corresponding to the current confinement region 11a. The resist film 55 can be formed by a photolithographic method. Thereafter, using the patterned register film 55 as a mask, the pluton (H ⁺ ) is driven into the multilayer structure LS by an ion implantation apparatus. Floton is driven to the vicinity of the boundary between the second cladding layer 7 and the second DBR layer 8. The region in which the pluton is embedded is semi-insulated, resulting in the formation of the current confinement region 11a (see Fig. 4). Further, instead of the flow-tone, it may be used for the oxygen ions (O ^2-) or iron ions (Fe ^{+ 3).} Thereafter, the register film 55 is removed.

Process (3)

Next, an insulating film 19 made of SiN _X is formed on the surface of the contact layer 3 (multilayer structure LS) by the plasma chemical vapor deposition (PCVD) method. Next, a resist film (not shown) having an opening at a position corresponding to the p-side electrode 23 is formed on the insulating film 19. Using this register film as a mask, a portion of the insulating film 19 is removed using buffered hook acid (BHF) to form a contact hole 19a (see Fig. 5). Subsequently, the register film is removed.

Next, a resist film (not shown) having an opening at a two-dimensional position corresponding to the contact hole 19a is formed again on the insulating film 19. Then, on the contact layer 3 exposed by the formation of the contact hole 19a, the p-side electrode 23 made of a stack of Cr / Au is formed by vapor deposition and lift-off using the resist film as a mask. Form (see FIG. 5). Subsequently, the register film is removed.

Process (4)

Next, a resist film (not shown) having an opening at a two-dimensional position corresponding to the wiring electrode 25 is formed. Then, the resist film is used as a mask to form a wiring electrode 25 made of Ti / Pt / Au by a lift-off method (see FIG. 6). Subsequently, the register film is removed. Thereafter, sintering is performed in an H ₂ atmosphere.

Process (5)

Next, the film 10 is formed and planarized on the first main surface 61 of the multilayer structure LS so as to cover the first electrode 21 (the p-side electrode 23 and the wiring electrode 25) (Fig. 7). Here, the surface 10a located on the opposite side of the multilayer structure LS in the film 10 is planarized as the surface of the structure including the multilayer structure LS and the semiconductor substrate 51. The film 10 can be formed using a PCVD method or a coating method. In addition, "flatness" here does not necessarily mean that unevenness does not exist at all. In the step (6) described later, the glass substrate 1 and the semiconductor substrate 51 are overlapped with each other through the film 10 to press and heat both sides, so that the surface of the glass substrate 1 and the surface of the film 10 are pressed. If the glass substrate 1 and the film 10 are fused together in a state where the 10a is in contact with each other, a slight unevenness may be present.

Process (6)

Next, the glass substrate 1 is bonded to the semiconductor substrate 51 on which the multilayer structure LS, the etch stop layer 53 and the film 10 are formed (see FIG. 8). First, the glass substrate 1 is prepared, and one main surface (surface) 71 of the glass substrate 1 is cleaned. Next, the glass substrate 1 and the semiconductor substrate 51 are overlapped so that the cleaned surface 71 of the glass substrate 1 and the surface 10a of the film 10 contact each other. Subsequently, the overlapped glass substrate 1 and the semiconductor substrate 51 are pressed and heated, and the glass substrate 1 and the film 10 are fused together and bonded together.

Specifically, the pressure applied to the overlapped glass substrate 1 and the semiconductor substrate 51 is about 98 kPa, and the heating temperature is preferably 500 to 700 ° C. Since the uppermost film 10 on the semiconductor substrate 51 is made of silicon oxide, it is pressurized and heated under such conditions, so that the surface 10a of the film 10 is the surface 71 of the glass substrate 1. Fused to the multilayer structure LS and the semiconductor substrate 51 are fixed to the glass substrate 1.

In addition, when performing this bonding process, it is preferable that not only the surface 71 of the glass substrate 1 but the surface 10a of the film 10 is also clean. For this purpose, for example, a fusion operation may be performed immediately after taking out the semiconductor substrate 51 from the PCVD apparatus in which the film 10 is formed.

Moreover, it is preferable that the glass substrate to be used has a thermal expansion coefficient close to the thermal expansion coefficient of GaAs. Thereby, in the cooling process after heating, the stress which arises between the semiconductor substrate 51 and the glass substrate 1 by the difference of a thermal expansion coefficient can be reduced extremely, and the fall of the adhesive strength resulting from a stress, and The occurrence of crystal defects can be minimized.

Fair (7)

Next, the semiconductor substrate 51 is removed. After the multilayer structure LS and the semiconductor substrate 51 are fixed to the glass substrate 1, the main surface, ie, the back surface 82, located on the opposite side of the glass substrate 1 among the semiconductor substrates 51 is exposed. In this step, etching is performed from the back surface 82 side of the semiconductor substrate 51 to remove the semiconductor substrate 51 and the etching stop layer 53 (see FIG. 9).

Specifically, first, the semiconductor substrate 51 is removed using an etching solution having a slow etching rate with respect to the etching stop layer 53. Subsequently, the etch stop layer 53 can be etched, and the etch stop layer 53 is removed using an etchant having a slow etching rate with respect to the GaAs layer of the second DBR layer 8. Thereby, the glass substrate 1 which mounts multilayered structure LS can be obtained.

As the etching solution to be used, a mixed solution of aqueous ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) (NH ₄ OH water: H ₂ O ₂ water = 1: 5), and hydrochloric acid (HCl) are preferable. First, the bonded glass substrate 1 and the semiconductor substrate 51 are immersed in the mixed solution of NH ₄ OH water and H ₂ O ₂ water. As a result, the semiconductor substrate 51 is etched from the back surface side. When etching progresses and the semiconductor substrate 51 is removed, the etching stop layer 53 is exposed in the etching liquid. Since the etching stop layer 53 (Al _0.5 Ga _0.5 As) has high resistance to this etching solution, the etching rate becomes very slow. Therefore, the etching stops automatically when the etching stop layer 53 is exposed. In this way, first, the semiconductor substrate 51 is removed.

Subsequently, the glass substrate 1 with the etching stop layer 53 and the multilayer structure LS etc. left out is taken out of the mixed solution of NH ₄ OH and H ₂ O ₂ , washed, dried and then immersed in a hydrochloric acid (HCl) solution. In order to accelerate the etching rate, it is preferable to heat the HCl solution in advance at about 50 ° C. Since GaAs is hardly etched by HCl, only the etch stop layer 53 is etched this time, and the etching stops automatically when the GaAs layer of the second DBR layer 8 is exposed. In this way, the etching stop layer 53 is removed. Instead of etching, the semiconductor substrate 51 and the etching stop layer 53 may be removed by chemical mechanical polishing (CMP).

Process (8)

Next, a register film (not shown) is formed on the second DBR layer 8 (multilayer structure LS). This register film has an opening at a two-dimensional position where the through hole TH is to be formed. Using this register film as a mask, the multilayer structure LS and the insulating film 19 are etched (wet etching) until the wiring electrode 25 is exposed. As a result, the through hole TH is formed (see FIG. 10). As etching liquid to be used, hydrogen peroxide solution and hydrochloric acid (HCl) are preferable. Subsequently, the register film is removed.

Next, an insulating film 20 made of SiN _X is formed on the surface of the second DBR layer 8 (multilayer structure LS) by the PCVD method (see FIG. 10 in the same manner). As a result, the insulating film 20 is formed on the wall surface of the multilayer structure LS that defines the through hole TH.

Process (9)

Next, on the insulating film 20, a resist film (not shown) having openings is formed in two-dimensional positions corresponding to the through wiring 27 and the n-side pad electrode 33, respectively. Then, using this resist film as a mask, the insulating film 20 is removed by BHF, and contact holes 20a and 20b are formed in the insulating film 20 (see FIG. 11). Subsequently, the register film is removed.

Next, a resist film (not shown) having an opening is formed in two-dimensional positions corresponding to the p-side pad electrode 29 (through wiring 27) and the n-side pad electrode 33. Then, the p-side pad electrode 29, the through wiring 27, and the n-side pad electrode 33 made of Ti / Pt / Au are formed by the lift-off method using this register film as a mask (similarly. 11). At this time, the n-side pad electrode 33 is formed to cover the light emitting region 11b.

Here, the p-side pad electrode 29 and the through wiring 27 are integrally formed. Subsequently, the register film is removed. Thereafter, sintering is performed in an H ₂ atmosphere. In addition, although the through wiring 27 is integrally formed with the p-side pad electrode 29, you may form separately, without being limited to this.

By these steps (1) to (9), the semiconductor light emitting element LE1 having the structure shown in Figs. 1 and 2 is completed.

The bump electrode 41 can be obtained by inverting the p-side pad electrode 29 and the n-side pad electrode 33 by a plating method, a solder ball mounting method, or a printing method and performing reflow. The bump electrodes 41 are not limited to solder, but may be gold bumps, nickel bumps, or copper bumps, or may be conductive resin bumps containing metals such as conductive fillers.

In this embodiment, the contact layer 3, the first DBR layer 4, the first cladding layer 5, the active layer 6, the second cladding layer 7, and the second DBR layer 8 are made thin. , Multilayer structure LS (laminated contact layer 3, first DBR layer 4, first clad layer 5, active layer 6, second clad layer 7, and second DBR layer 8) The mechanical strength of) is maintained by the glass substrate 1. In addition, since a portion having the substrate thickness is maintained as in the conventional semiconductor light emitting device, the semiconductor light emitting device LE1 can be easily downsized.

Since the multilayer structure LS is fixed to the glass substrate 1 via the film 10, the glass substrate 1 can be adhered to the multilayer structure LS without using an adhesive else. Silicon oxide constituting the film 10 is optically transparent to light generated in the multilayer structure LS, similarly to the glass substrate 1. Therefore, light emitted from the multilayer structure LS can reach the glass substrate 1 without being absorbed by the adhesive agent. As a result, the light emission output can be prevented from decreasing.

The film 10 is formed on the first main surface 61 of the multilayer structure LS to cover the first electrode portion 21 (the p-side electrode 23 and the wiring electrode 25), and the multilayer structure LS The surface 10a located on the opposite side of is flattened. For this reason, the unevenness | corrugation by the 1st electrode 21 arrange | positioned on the 1st main surface 61 of the multilayer structure LS is eliminated by the film | membrane 10. FIG. As a result, the glass substrate 1 can be easily and reliably adhere | attached to the 1st main surface 61 of the multilayer structure LS through the film 10.

The first electrode 21 includes the wiring electrode 25, the second electrode 31 includes the n-side pad electrode 33, and the wiring electrode 25 passes through the multilayer structure LS. 27 is electrically connected to the p-side pad electrode 29 disposed on the second main surface 62 of the multilayer structure LS. As a result, the p-side pad electrode 29 and the n-side pad electrode 33 are arranged on the opposite side of the light exit surface, and the semiconductor light emitting element LE1 can be easily installed.

Since the n-side pad electrode 33 (light reflecting film) is formed to cover the light emitting region 11b, the light reflected by the n-side pad electrode 33 is also emitted from the glass substrate 1. Thereby, light emission output can be improved.

In the manufacturing method according to the present embodiment, the film 10 is formed on the first main surface 61 of the multilayer structure LS so as to cover the first electrode 21, and the glass substrate 1 is formed on the film 10. ) Is bonded, and then the semiconductor substrate 51 is removed. Thereby, the semiconductor light emitting element LE1 to which the glass substrate 1 was fixed to the multilayer structure LS via the film 10 can be manufactured easily.

Since the glass substrate 1 remains even after the semiconductor substrate 51 is removed, the mechanical strength of the multilayer structure LS is maintained by the glass substrate 1 also in the subsequent manufacturing process. In addition, before bonding the glass substrate 1, the mechanical strength of the multilayer structure LS is maintained by the semiconductor substrate 51.

The manufacturing method according to the present embodiment includes the multilayer structure LS (laminated contact layer 3, first DBR layer 4, first cladding layer 5, active layer 6, second cladding layer 7, and Before forming the second DBR layer 8, the step of forming the etching stop layer 53 so as to be located between the semiconductor substrate 51 and the multilayer structure LS, and the etching stop after removing the semiconductor substrate 51 The process of removing the layer 53 by wet etching is provided. Therefore, the etching liquid which can etch the semiconductor substrate 51, cannot etch the etching stop layer 53, and the etching liquid which can etch the etching stop layer 53, and cannot etch the multilayer structure LS. By appropriately selecting and using, the semiconductor substrate 51 can be removed and only the etching stop layer 53 can be removed after that. Therefore, the semiconductor substrate 51 can be removed reliably and easily, leaving the multilayer structure LS.

2nd embodiment

12 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting element according to the second embodiment. This semiconductor light emitting element LE2 differs from the semiconductor light emitting element LE1 according to the first embodiment in that the lens portion 72a is formed on the glass substrate 1.

The semiconductor light emitting element LE2 includes a multilayer structure LS and a glass substrate 1. This semiconductor light emitting element LE2 is a back emission type VCSEL that emits light from the glass substrate 1 side. The semiconductor light emitting element LE1 is a light emitting element for short range optical communication, for example, having a wavelength band of 0.85 mu m.

On the back surface 72 of the glass substrate 1, the lens part 72a which receives the light radiate | emitted from the multilayer structure LS is formed. The other part 72b of the back surface 72 is higher than the lens part 72a. That is, this lens portion 72a is recessed than the highest portion 72b of the back surface 72.

Next, the manufacturing method of semiconductor light emitting element LE2 is demonstrated, referring FIG. FIG. 13 is a diagram for explaining this manufacturing method and shows a longitudinal section of the semiconductor light emitting element.

In this production method, the following steps (1) to (9) are executed in sequence. Process (1)-(5) is the same as process (1)-(5) in 1st Embodiment, and abbreviate | omits description.

Process (6)

Next, the glass substrate 1 is bonded to the semiconductor substrate 51 on which the multilayer structure LS, the etch stop layer 53 and the film 10 are formed (see FIG. 13). The adhesion method is the same as that of the process (6) in 1st Embodiment. Specifically, the glass substrate 1 in which the lens part 72a was formed in the back surface 72 is prepared, and the surface 71 of the glass substrate 1 is cleaned. Next, the glass substrate 1 and the semiconductor substrate 51 overlap each other so that the cleaned surface 71 and the surface 10 a farther from the multilayer structure LS in the film 10 on the semiconductor substrate 51 contact each other. do. Subsequently, the glass substrate 1 and the semiconductor substrate 51 which were overlapped and pressed are pressed and heated, the glass substrate 1 and the film 10 are fused together, and they are bonded together. The detail of this bonding method is the same as that of the process (6) in 1st Embodiment.

Positioning of the light emitting region 11b on the semiconductor substrate 51 and the lens portion 72a on the glass substrate 1 is performed by applying a marker to the back surface 72 side of the glass substrate 1 to use a double-sided exposure machine. It can be performed easily based on a marker. In addition, you may use the external shape of the lens part 72a as a marker instead of providing a marker.

Process (7)-(9) is the same as process (7)-(9) in 1st Embodiment, and abbreviate | omits description here. By these steps (1) to (9), the semiconductor light emitting element LE2 having the structure shown in FIG. 12 is completed.

In this embodiment, as in the above-described first embodiment, the multilayer structure LS (laminated contact layer 3, first DBR layer 4, first cladding layer 5, active layer 6, and second cladding layer ( 7) and the mechanical strength of the second DBR layer 8 are maintained by the glass substrate 1, and the miniaturization of the semiconductor light emitting element LE2 is easy.

In addition, in this embodiment, the lens part 72a is provided in the glass substrate 1. Thereby, the directivity of the emitted light can be improved or parallel light can be formed.

The lens portion 72a is formed in a recessed shape than the highest portion 72b of the rear surface 72 of the glass substrate 1. For this reason, the glass substrate 1 in which the lens part 72a was formed can be easily adhere | attached to the multilayer structure LS. Moreover, since the lens part 72a can be processed before adhesion | attachment, it is hard to be restrict | limited by the processing method, and freedom of lens design, such as a lens shape, is high.

The lens portion 72a may be formed after the glass substrate 1 is attached to the semiconductor substrate 51 on which the multilayer structure LS, the etch stop layer 53 and the film 10 are mounted. However, in consideration of the degree of freedom in lens design, it is preferable to adhere the glass substrate 1 on which the lens portion 72a is formed in advance to the semiconductor substrate 51.

Next, the modification of this embodiment is demonstrated with reference to FIGS. 14-17. Such a modification is a semiconductor light emitting element array LE3 to LE6 in which a plurality of multilayer regions 12 including the light emitting regions 11b are arranged in parallel. Such light emitting element arrays LE3 to LE6 are so-called backside emission types.

In the light emitting element arrays LE3 to LE6, as illustrated in FIGS. 14 to 17, the plurality of multilayer regions 12 are arranged in one or two dimensions. In the light emitting element arrays LE3 to LE6, the n-side pad electrodes 33 are electrically connected to each other.

In the light emitting element arrays LE3 to LE6, the multilayer structure LS (the laminated contact layer 3, the first DBR layer 4, the first cladding layer 5, and the active layer 6) was the same as in the first and second embodiments described above. ), The second cladding layer 7, and the second DBR layer 8 are maintained by the glass substrate 1. In addition, since the pitch between the light emitting regions 11b can be narrowed, miniaturization of the light emitting element arrays LE3 to LE6 is easy.

Next, referring to FIG. 18, an optical interconnection system using the above-described semiconductor light emitting element (or semiconductor light emitting element array) will be described. 18 is a schematic diagram illustrating a configuration of an optical interconnection system.

The optical interconnection system 101 is a system for transmitting an optical signal between a plurality of modules (for example, a CPU, an integrated circuit chip, and a memory) M1 and M2, and includes a semiconductor light emitting device LE1, a driving circuit 103, and an optical waveguide substrate. 105, the semiconductor light receiving element 107, the amplifying circuit 109, and the like. A back incident light receiving element can be used for the semiconductor light receiving element 107. The module M1 is electrically connected to the drive circuit 103 via the bump electrode. The drive circuit 103 is electrically connected to the semiconductor light emitting element LE1 via the bump electrode 41. The semiconductor light receiving element 107 is electrically connected to the amplifying circuit 109 through the bump electrode. The amplifier circuit 109 is electrically connected to the module M2 through the bump electrode.

The electrical signal output from the module M1 is sent to the drive circuit 103 and converted into an optical signal by the semiconductor light emitting element LE1. The optical signal from the semiconductor light emitting element LE1 passes through the optical waveguide 105a on the optical waveguide substrate 105 and enters the semiconductor light receiving element 107. The optical signal is converted into an electrical signal by the semiconductor light receiving element 107 and sent to the amplifying circuit 109 for amplification. The amplified electrical signal is sent to module M2. In this way, the electrical signal output from the module M1 is transmitted to the module M2.

Instead of the semiconductor light emitting element LE1, the semiconductor light emitting element LE2 or the semiconductor light emitting element arrays LE3 to LE6 may be used. When using the semiconductor light emitting element arrays LE3 to LE6, the driving circuit 103, the optical waveguide substrate 105, the semiconductor light receiving element 107, and the amplifying circuit 109 are also arranged to form an array.

This invention is not limited to embodiment mentioned above. For example, the thickness of the contact layer 3, the first DBR layer 4, the first cladding layer 5, the active layer 6, the second cladding layer 7, and the second DBR layer 8 and the like. , Materials and the like are not limited to those described above. In addition, the structure of the multilayer structure LS is not limited to the above-mentioned embodiment, What is necessary is just to include the several compound semiconductor layer laminated | stacked.

As can be clearly seen from the above-described invention, the embodiment of the present invention may be modified in various ways. Such modifications are not intended to depart from the scope of the present invention, but as will be apparent to those skilled in the art, such modifications are intended to be included within the scope of the following claims.

This invention can provide the semiconductor light emitting element which has sufficient mechanical strength, and can be miniaturized, and its manufacturing method.

Claims (19)

A semiconductor light emitting device formed by stacking a plurality of compound semiconductor layers, A layer structure comprising the plurality of compound semiconductor layers, A first electrode portion disposed on one side of the layer structure; A second electrode portion disposed on the other surface side of the layer structure; A film made of silicon oxide formed on the one surface side of the layer structure so as to cover the first electrode portion, and having a surface opposite to the layer structure flattened; It is provided with a glass substrate which is optically transparent with respect to the emitted light, and bonded in contact with the surface on the side opposite to the layer structure in the film made of the silicon oxide, As the plurality of compound semiconductor layers, the first conductive type contact layer, the first DBR layer of the first conductivity type, the first cladding layer of the first conductivity type, the active layer, the second cladding layer of the second conductivity type, And a second DBR layer of a second conductivity type, An insulating or semi-insulated current confinement region is formed in the layer structure so as to surround a predetermined region including the contact layer, the first DBR layer, the first clad layer, the active layer, and the second clad layer. And The first electrode part includes a wiring electrode electrically connected to a contact layer part included in the predetermined region, The second electrode unit includes a second pad electrode electrically connected to the second DBR layer, And the wiring electrode is electrically connected to a first pad electrode disposed on the other surface side of the layer structure through a through wiring passing through the layer structure. The method according to claim 1, A bump electrode is disposed on the first pad electrode and the second pad electrode. The method according to claim 1, A plurality of the predetermined regions are arranged in parallel in an array shape. The method according to claim 1, In the layer structure, a light reflecting film is formed on the second DBR layer side corresponding to the predetermined region. The method according to claim 1, The glass substrate is provided with a lens portion through which the light emitted from the layer structure is transmitted. The method of claim 5, And the lens portion is formed in a recessed shape than the maximum surface of the glass substrate. As a manufacturing method of a semiconductor light emitting element formed by laminating a plurality of compound semiconductor layers, Preparing a semiconductor substrate and a glass substrate optically transparent to the emitted light, Forming a layer structure including the plurality of compound semiconductor layers laminated on one surface side of the semiconductor substrate; Forming a first electrode part on one surface side of the layer structure; Forming a second electrode portion on the other surface side of the layer structure; Forming and planarizing a film made of silicon oxide so as to cover said first electrode portion on said one surface side of said layer structure; Bonding the film made of silicon oxide and the glass substrate such that the film made of silicon oxide is in contact with a surface opposite to the layer structure and one surface of the glass substrate; And a step of removing the semiconductor substrate after the step of bonding the film made of silicon oxide and the glass substrate to each other. The method of claim 7, In the step of removing the semiconductor substrate, the semiconductor substrate is removed by wet etching. The method of claim 8, Forming an etching stationary layer which is performed before the step of forming the layer structure and stops the wet etching so as to be positioned between the semiconductor substrate and the layer structure; And a step of removing the etching stop layer by wet etching after the step of removing the semiconductor substrate. The method of claim 9, As said plurality of compound semiconductor layers, a first conductive type contact layer, a first conductive type first DBR layer, a first conductive type first cladding layer, an active layer, a second conductive type second cladding layer, and a first conductive type A second conductivity type second DBR layer, In the step of forming the layer structure, the second DBR layer, the second clad layer, the active layer, the first clad layer, the first DBR layer, and the contact layer are sequentially stacked from the semiconductor substrate side, After the step of forming the layer structure, the layer structure is insulated so as to surround a predetermined region including the contact layer, the first DBR layer, the first clad layer, the active layer, and the second clad layer. A method of manufacturing a semiconductor light emitting device, further comprising the step of forming a current or semi-insulated current confinement region. The method of claim 10, The step of forming the first electrode portion includes a step of forming a wiring electrode which is carried out after the step of forming the current constriction region and electrically connected to a contact layer portion included in the predetermined region, The step of forming the second electrode portion includes a step of forming a second pad electrode which is performed after the step of removing the semiconductor substrate and is electrically connected to the second DBR layer, And a step of forming a first pad electrode on the other surface side of the layer structure and electrically connecting the first pad electrode and the wiring electrode, after the step of removing the semiconductor substrate. The manufacturing method of the semiconductor light emitting element characterized by the above-mentioned. The method of claim 11, In the step of electrically connecting the first pad electrode and the wiring electrode, a through wiring penetrating through the layer structure is formed, and the first pad electrode and the wiring electrode are electrically connected through the through wiring. The manufacturing method of the semiconductor light emitting element made into. The method of claim 10, And a step of forming a light reflection film corresponding to the predetermined region on the second DBR layer side in the layer structure. The method of claim 7, And a lens portion through which the light emitted from the layer structure is transmitted is formed in the glass substrate. The method according to claim 14, The lens portion is formed in a recessed portion than the outermost surface of the glass substrate, characterized in that the manufacturing method of the semiconductor light emitting device. delete delete delete delete

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