KR101126051B1 - Multi-linearity mode lna having a deboost current path - Google Patents

Abstract

The modified differential overlap (MDS) low noise amplifier (LNA) includes a main current path and an erase current path. Third order distortion in the erase path is used to cancel the third order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of the other current paths without affecting one current path. In a second novel aspect, there is provided a deboost current path that is not delivered through an LNA load. The boost current causes negative feedback to increase without causing headroom problems. In a novel third aspect, the erase current path and / or the boost current path are programmatically disabled to reduce power consumption and improve noise figure in operating modes that do not require high linearity.

Description

MULTI-LINEARITY MODE LNA HAVING A DEBOOST CURRENT PATH}

The disclosed embodiments generally relate to wireless communication devices and, more particularly, to low noise amplifiers.

Generally, wireless receivers, such as code division multiple access (CDMA) cellular telephone receivers, include amplifiers called low noise amplifiers (LNAs). CDMA cellular telephone applications require the LNA to have a very high third order input intercept point (IIP ₃ ) as well as a low noise factor (NF), high gain and low current consumption. There are several linearization techniques used to achieve these performance characteristics.

One common technique involves using negative feedback. In a conventional source-degenerated LNA, the source degeneration inductor is used as a feedback circuit. In general, higher linearity may be achieved by increasing source degeneration inductance and / or LNA bias current. However, source-degeneration LNAs still suffer from poor linearity due to the second order non-linear feedback effect. In addition, LNAs with higher source degeneration inductance exhibit lower gain and higher noise factor, and increasing bias current results in higher power consumption. If the bias current is increased too much, you will face headroom problems.

The second technique is a derivative superposition (DS) technique. DS technology uses two or more parallel FETs of different gate widths and gate biases to achieve high linearity and improved IIP3 performance. However, the conventional DS method does not significantly increase IIP3 performance at high frequencies due to the second order nonlinear contribution to third order intermodulation distortion (IMD ₃ ).

Modified DS (MDS) technology solves the second order nonlinear contribution. In a modified DS technique, the magnitude and phase of the third order nonlinear contribution to IMD3 is tuned to cancel the second order nonlinear contribution to IMD3, thereby producing an output current with very low IMD3.

1 (Prior Art) is a circuit diagram of an LNA 100 using MDS technology. In the MDS circuit of FIG. 1, two FETs 104A and 104B are used. FET 104A is biased in its sub-critical region (weak inversion) and FET 104B is biased in its saturation region (strong inversion). It is known in the art that as the FET changes from weak inversion to strong inversion, the third order nonlinear contribution component (g ₃ ) of the FET to IMD3 changes from positive to negative. This means that when two FETs 104A and 104B are biased at a positive and negative peak of g ₃ having the same magnitude, the output currents by the two FETs 104A and 104B are summed and the result is almost zero. It means output current with IMD3. In addition, the MDS technique considers a second order nonlinear contribution component (g ₂ ) for IMD3. The tapping of the inductor 102, as shown in Fig. 1, ₃ g of the magnitude and phase is used to tune to erase a ₂ g. For a more detailed description of the operation of LNAs using Modified Derivative Superposition (MDS) technology, see US Patent Publication No. 2005/0176399, published August 11, 2005.

2 (Prior Art) is a circuit diagram of an LNA 120 utilizing a variation of the MDS technique. In the MDS circuit of FIG. 2, two FETs 122 and 124 and two inductors 126 and 128 are used. The same general MDS technique of phase cancellation as shown in FIG. 1 is used in LNA 120 of FIG. 2 to achieve high linearity. However, by connecting the gate of auxiliary transistor 124 to the source of main transistor 122, LNA 120 of FIG. 2 further improves NF. In addition, connecting the gate of the auxiliary transistor 124 to the source of the main transistor 122 allows tuning for input match and linearity to be performed independently. For further information on this variant of MDS technology, see May 2006, "Highly Linear Low Noise Amplifier" by Sivakumar Ganesan, Texas A & M Master of Science Thesis, pages 1-73.

If there are strong jammer tones, the LNA in the CDMA cellular telephone should have high linearity and low distortion. In general, such high linearity performance is achieved using MDS technology with the increased bias current of the LNA. However, the degree to which the bias current can be increased is limited. On the other hand, when no jammer tones are present, the LNA may have lower linearity and lower power consumption to extend the battery life of the CDMA cellular telephone.

The modified differential overlap (MDS) low noise amplifier (LNA) includes a main current path and an erase current path. In the main current path, main current I _MAIN flows through the load, the main field effect transistor (FET), and the first source degeneration inductor. In the erase current path, erase current I _CANCEL flows through the load, erase FET, and second source degeneration inductor. LNA current is the sum of I _MAIN and I _CANCEL . Third order distortion at I _CANCEL is used to cancel the third order distortion at I _MAIN , thus resulting in zero third order intermodulation distortion (IMD3) at the output current. In one novel aspect, the first source degeneration inductor in the main current path is a separate inductor from the second source degeneration inductor in the erase current path, whereby a different current path can be applied without affecting one current path. Make tuning easy. As a result, since the main current and the erase current are decoupled through the use of two separate source degeneration inductors, the LNA can be optimized with fewer iterations.

In a second novel aspect, a deboost current path is provided. In the boost current path, the boost current I _DEBOOST flows through the boost transistor and the first source degeneration inductor. The boost current does not flow through the LNA load. The boost current causes more negative feedback to be provided by the first source degeneration inductor without reducing the voltage headroom of the main FET. Thus, higher linearity performance of the LNA can be achieved. In one example, the boost current I _DEBOOST can be changed during the design of the LNA by changing the size of the boost transistor. Thus, the negative feedback associated with the main current path can also be adjusted by adjusting the boost current. Adjustable negative feedback factor provides extra tuning capability for optimum current cancellation. As a result, LNA can be optimized with fewer design iterations.

In a novel third aspect, the LNA is programmable to operate in two different modes of operation, namely, high linear mode and low linear mode. If there is a receive jammer or a transmit leak, the LNA operates in high linear mode. In the high linear mode, both the boost current path and the erase current path are enabled to achieve high linearity performance. On the other hand, when there is no reception jammer or no transmission leakage, the LNA operates in low linear mode. In the low linear mode, the boost current path is programmatically disabled to reduce power consumption. In one example, the erase current path is also disabled to improve the noise figure (NF) of the LNA.

It is to be appreciated that the foregoing is a summary and therefore includes, as necessary, simplifications, generalizations, and omissions of the details, and that the summaries are illustrative only and are not meant to be limiting in any way. As defined only by the claims, other aspects, inventive features, and advantages of the devices and / or processes described herein will become apparent in the non-limiting detailed description disclosed herein.

1 (Prior Art) is a circuit diagram of an LNA 100 using a modified differential overlap (MDS) technique.
2 (Prior Art) is a circuit diagram of an LNA 120 utilizing a variation of the MDS technique.
3 is a very simplified high level block diagram of a particular type of mobile communication device 200 in accordance with one novel aspect.
4 is a more detailed block diagram of the RF transceiver integrated circuit 204 of FIG. 3.
5 is a circuit diagram of the low noise amplifier (LNA) 222 of FIG. 4 with two separate source degeneration inductors.
FIG. 6 is a graph showing third-order intermodulation distortion (IMD3) modeled by two adjacent channel receive-jammers.
7 is a graph illustrating triple bit distortion modeled by two transmit-leaks and a receive-jammer in a CDMA system.
8 is a graph illustrating the third order nonlinear delivery effect.
FIG. 9 is a graph illustrating cancellation of third order nonlinear transfer coefficients in a differential superposition (DS) technique.
FIG. 10 is a simplified layout of two separate source degeneration inductors of FIG. 5.
FIG. 11 is a circuit diagram of a low noise amplifier (LNA) 400 having two separate source degeneration inductors 412 and 414 and also having a boost transistor 406.
FIG. 12 is a graph showing the linearity performance of the LNA 400 with respect to the bias current of the erase transistor 404 of FIG. 11 (when the LNA 400 is operating in its high linear mode).
FIG. 13 is a table showing LNA performance characteristics when the LNA is operating in the high linear mode and the low linear mode.

3 is a very simplified high level block diagram of a particular type of mobile communication device 200 in accordance with one novel aspect. In this example, the mobile communication device 200 is a cellular telephone using the CDMA2000 cellular telephone communications protocol. The cellular telephone includes an antenna 202 (among several other parts not shown) and two integrated circuits 204 and 206. Integrated circuit 206 is referred to as a "digital baseband integrated circuit" or "baseband processor integrated circuit". Integrated circuit 204 is an RF transceiver integrated circuit. The RF transceiver integrated circuit 204 is referred to as a "transceiver" because it includes a receiver as well as a transmitter.

4 is a more detailed block diagram of the RF transceiver integrated circuit 204 of FIG. 3. The receiver includes a local oscillator (LO) 214 as well as what is referred to as a "receive chain" 212. When the cellular telephone 200 is receiving, a high frequency RF signal 211 is received via the antenna 202. Information from signal 211 is communicated through duplexer 213, matching network 220, and receive chain 212. The RF signal 211 is amplified by a low noise amplifier (LNA) 222 and down-converted in frequency by the mixer 224. The resulting down-converted signal is filtered by baseband filter 226 and passed to digital baseband integrated circuit 206. The analog-to-digital converter 208 in the digital baseband integrated circuit 206 converts the signal into digital form, and the resulting digital information is processed by the digital circuit in the digital baseband integrated circuit 206.

If the cellular telephone 200 is transmitting, the information to be transmitted is converted to analog form by a digital-to-analog converter 210 in the digital baseband integrated circuit 206 and supplied to the "transmission chain" 216. Baseband filter 236 filters the noise due to the digital-to-analog conversion process. Thereafter, the mixer block 234 under the control of the local oscillator (LO) 218 up-converts the signal to a high frequency signal. The driver amplifier 232 and the external power amplifier 230 amplify the high frequency signal, and transmit the high frequency signal through the duplexer 213 to drive the antenna 202 such that the high frequency RF signal 231 is transmitted from the antenna 202. To pass.

5 is a detailed circuit diagram of the low noise amplifier (LNA) 222 of FIG. 4 in accordance with a novel aspect. The LNA 222 includes a main field effect transistor (FET) 302, an erase FET 304, a first source degeneration inductor 306, a second source degeneration inductor 308, a cascode transistor 310, And LNA rod 312. The LNA rod 312 is an LC tank circuit that includes an inductor 314 and a capacitor 316 coupled in parallel. Main FET 302 receives an RF signal from input node RFIN 330 via AC coupling capacitor C1. The erase FET 304 receives the RF signal from the input node RFIN 330 via an additional AC coupling capacitor C2. Source S1 of main FET 302 is coupled to ground node GND 332 via first source degeneration inductor 306. Source S2 of erase FET 304 is coupled to ground node GND 332 via second source degeneration inductor 308. The drain D1 of the main FET 302 is connected to the drain D2 of the erase FET 304. The drain D1 and the drain D2 are connected to the source S3 of the cascode transistor 310. Drain D3 of cascode transistor 310 is coupled to voltage supply node VDD 334 via load 312. In addition, drain D3 is coupled to output voltage node V _OUT 336. Main FET 302 is biased at bias voltage V _{G_MAIN} such that main FET 302 is biased in its saturation operating region (also known as strong _inversion ). Erase FET 304 is biased at bias voltage V _{G_CANCEL} such that erase FET 304 is biased to its (also known as weak _inversion ) sub-threshold operating region.

In the embodiment of FIG. 5, main FET 302, erase FET 304, and two separate source degeneration inductors 306 and 308 form modified differential overlap (MDS) element 318. Main FET 302 and erase FET 304 have interconnected drains and are driven by the same RF signal received from input node RFIN 330. For input gate-source voltage V _GS around the bias point, main FET 302 generates drain-source current I _MAIN and erase FET 304 generates drain-source current I _CANCEL . The total LNA current (expressed as output current I _OUT ) is the sum of I _MAIN and I _CANCEL , ie I _OUT = I _MAIN + I _CANCEL . Cascode transistor 310 is biased at bias voltage V _B and used as a current buffer to isolate MDS element 318 from load 312 and output node 336.

The linearity of the receiver of the transceiver integrated circuit 204 of FIG. 4 is governed by the performance of the LNA 222 of FIG. 5. The main FET 302 of the LNA 222 is a nonlinear device and produces various output frequency components, also known as distortion. In the equation, the main FET 302 biased in the saturation region is a small, which can be explained by the Taylor-series expansion of the following equation (1) in terms of the small signal gate-source voltage V _GS around the bias point. Produces a signal drain-source current I _MAIN ,

Where g ₁ represents the small signal transconductance of the FET 302 and g ₂ and g ₃ are the secondary and tertiary transconductance coefficients leading to the generation of distortions. Among the transconductance coefficients, g ₃ is particularly important because it controls the third order intermodulation distortion IMD3 and thus determines the third order input intercept point IIP ₃ . IIP ₃ is a figure of merit commonly used to characterize nonlinearity. The amplitude of IIP ₃ can be expressed according to the following equation (2).

Intermodulation distortion is a type of distortion that can be modeled by two strong jammer tones appearing at the input. In one example, the two jammer tones are two closely spaced frequencies with the same amplitude tones applied to the main FET 302, ie, V _GS = Acosω ₁ t + Acosω ₂ t, where ω ₁ and ω ₂ are Represent two closely spaced frequencies. By substituting the above-tone jammer in equation (1), the output current is IMAIN, including a new frequency component including a (2ω ₁ -ω ₂₎ and (2ω ₂ -ω ₁₎ frequency components. These two frequency components exhibit third order intermodulation distortion (IMD3). As will be explained in more detail in the following paragraphs, IMD3 is the most problematic intermodulation distortion because it is within the pass band of the transceiver 204 and corrupts the input signal.

FIG. 6 is a graph showing third-order intermodulation distortion (IMD3) modeled by two adjacent channel receive-jammers. In the example of FIG. 6, the desired RF signal band has a center frequency of 1 GHz with a bandwidth of 1 MHz. This means that any RF signal with a frequency between 0.999 GHz and 1.001 GHz is in the pass band of the transceiver 204. In addition to the desired RF signal, there are two received RF signals having a first frequency f _RX1 = 1.001 GHz and a second frequency f _RX2 = 1.002 GHz. These two received RF signals are also referred to as adjacent channel receive-jammers. The presence of receive-jammers results in two third-order distortion components, one IMD3 having a frequency component of (2f _RX2- f _RX1 ) equal to 1.003 GHz, and another IMD3 having exactly equal 1 GHz (2f _RX1 -f _RX2) ) Has a frequency component of As shown in FIG. 6, the 1 GHz IMD3 component is in the desired signal band. This in-band IMD3 component damages the input signal because it cannot be filtered.

In a CDMA2000 duplex system, such as the transceiver 204 of FIG. 4, the nonlinear nature of the LNA 222 also results in cross-modulation distortion caused by transmit-leaks. In the example of FIG. 4, both receiver chain 212 and transmitter chain 216 operate at the same time, and duplexer 213 is used to combine the receiver signal and the transmitter signal. Because of the combination of the receiver signal and the transmitter signal, a transmit-leak may be present at the receive input simultaneously with the receiver-jammer. The interaction of the two transmit-leak and receive-jammers produces horn-modulated distortion. In one example, one type of third order horn-modulation distortion, also known as triple-bit distortion, is modeled by two transmit-leak signals and one receive-jammer.

7 is a graph illustrating triple bit distortion modeled by two transmit-leak signals and one receive-jammer. In the example of FIG. 7, the desired RF signal band has a center frequency of 1 GHz with a bandwidth of 1 MHz. This means that any RF signal with a frequency between 0.999 GHz and 1.001 GHz is in the pass band of the transceiver 204. In addition to the desired RF signal, there are two transmit-leak signals with a first frequency f _TX1 = 900 MHz and a second frequency f _TX2 = 900.4 MHz. In addition, there is a receive-jammer with a frequency of 1.001 GHz. Transmit - to the leakage signal and receive - the presence of a jammer is equal to 1.006GHz results in a bit distortion components - (f _RX1 - (f _{TX2 TX1} -f)) having a frequency of 3 triple tea. As shown in Figure 7, the 1.006 GHz triple-bit distortion component is within the desired signal band. This triple-bit distortion component is problematic because it damages the input signal and cannot be filtered.

The above-described IMD3 and triple-bit distortions are all third-order distortions and are controlled by the third-order transconductance coefficient g ₃ . Therefore, it is particularly important to be able to reduce the value of g ₃ to almost zero, in order to remove third order distortions and improve linearity. From equation (1), the transconductance coefficients g ₁ , g ₂ and g ₃ can be determined according to equation (3) as follows.

FIG. 8 is a graph showing transconductance coefficients g ₁ , g ₂ and g ₃ related to the DC bias voltage V _{G_MAIN} of the main FET 302 of FIG. 5. In the example of FIG. 8, the tertiary transconductance g ₃ changes from positive to negative when the bias of main FET 302 is changed from weak inversion to strong inversion. When the bias voltage V _{G_MAIN} reaches a certain point (eg, V _{G_MAIN} = 0.64 volts), the tertiary transconductance g ₃ becomes zero. Thus, as g ₃ becomes zero at this particular bias point, IIP ₃ approaches infinity. However, this significant IIP ₃ improvement occurs only in a very small range of V _{G_MAIN} . This particular bias point is difficult to achieve and must change due to process, temperature and supply voltage variations.

FIG. 9 is a graph showing how tertiary nonlinear transconductance coefficients are erased from each other in a differential superposition (DS) technique. As shown in FIG. 5, two transistors, the main FET 302 and the erase FET 304 are connected in parallel. When the bias point to g when the case is present in the _three positive and negative peaks of the two output currents of the two transistors is added, and, g ₃ positive and negative peaks are the two transistors are scaled to be equal in size, the composite output current I _OUT Will have g ₃ being zero over a wide range of bias values. In the example of FIG. 9, g _3A and g _3B represent transconductance coefficients of two transistors biased in different regions. The resulting synthesis g ₃ (g ₃ = g _3A + g _3B ) becomes about zero, and the theoretical amplitude of IIP ₃ is significantly improved over a wide range of gate biases. However, the improvement in IIP ₃ only occurs for very low frequencies where the effect of circuit reactance is negligible. At high frequencies, source degeneration inductor 306 creates a strong feedback path for drain-source current I _MAIN . As a result, the secondary nonlinearity (controlled by g ₂ ) also contributes to IMD3. Thus, conventional DS methods do not provide an IIP ₃ improvement at high frequencies.

Modified differential superposition (MDS) technology solves the problem of secondary nonlinear contributions. As shown in FIG. 1 (prior art), the magnitude and phase of the third order nonlinear contribution g ₃ for IMD3 is determined by using the inductance 102 tapped for source degeneration. (g ₂ ) is tuned to erase. With proper selection of tap point, FET gate width, and biases, the overall IMD3 can have a value that is nearly zero over a wide range of biases. However, in the example of FIG. 1, the drain-source currents of FET 104A and FET 104B are coupled via tapped inductance 102. In turn, the change in tap point will affect the drain-source currents of both FET 104A and FET 104B. Thus, many design iterations are required to accurately tune tap points, FET gate widths, and biases to achieve optimized results. Due to the coupling of the two FET drain-source currents, it is often difficult and difficult to bring the entire IMD3 to near zero.

The novel LNA 222 of FIG. 5 overcomes these challenges by using two separate source degeneration inductors 306 and 308. As shown in FIG. 5, the output current I _OUT includes two current paths, a main current path 320 and an erase current path 322. In main current path 320, main current I _MAIN flows through main FET 302 and source degeneration inductor 306. In the erase current path 322, the erase current I _CANCEL flows through the erase FET 304 and the source degeneration inductor 308. By using the source degeneration inductor 306 in the main path 320 and the source degeneration inductor 308 in the erase path 322, the main current I _MAIN and the erase current I _CANCEL are more different than in the conventional circuit of FIG. 1. No longer coupled together. In the novel design process, the first step is to design the main path 320 to ensure the basic performance of the LNA 222. For example, the gate width and bias point of the main FET 302, and the inductance of the source degeneration inductor 306 are carefully selected to achieve low noise figure, high gain, low power consumption, and relatively high linearity. . In a second step, an erase path is realized and tuned to improve linearity. As described above, the main FET 302 is biased in its saturation region and has a negative third order contribution to IMD3. On the other hand, the erase FET 304 is biased in its sub-critical region and has a positive third order contribution to IMD3. More specifically, the MDS method also takes into account secondary nonlinear contributions to IMD3. By appropriately selecting the gate width and bias point of the erase FET 304 and the inductance of the source degeneration inductor 308, IMD3 of the current I _CANCEL is tuned to erase IMD3 of the current I _MAIN . Since the main path 320 and the erase path 322 are decoupled through the use of two separate inductors 306 and 308, the changes made to the erase path 322 are large for the operation of the main path 320. Does not affect Thus, the novel LNA 222 of FIG. 5 can be optimized with fewer iterations compared to the conventional LNA of FIG. 1 using a tapped inductor.

FIG. 10 is a simplified layout diagram illustrating the two source degeneration inductors 306 and 308 of FIG. 5. As shown in FIG. 10, the source degeneration inductor 306 is an integrated spiral inductor with one lead connected to the ground node 332 and another lead connected to the source S1 of the main FET 302. The source degeneration inductor 308 is also an integrated spiral inductor with one lead connected to the ground node 332 and another lead connected to the source S2 of the erase FET 304. In one example, L _DEG1 has an inductance of 1.8 _nanohenry , L _DEG2 has an inductance of 1.6 _nanohenry , and ground node 332 is a surface mount microbump of RF transceiver integrated circuit 204. The RF transceiver integrated circuit 204 is a flip-flop packaged integrated circuit.

Although the LNA 222 of FIG. 5 achieves high linearity by using the MDS technique, the much higher linearity requirement, especially in the presence of strong receive-jammer signals and / or transmit-leak signals, results in LNA in the CDMA transceiver. Is often imposed on. In general, higher linearity is achieved by increasing the LNA DC bias current so that increased negative feedback can be provided. In general, however, an increase in DC bias current results in more DC power consumption and headroom problems. Also, in general, higher linearity also results in degraded noise figure of the LNA. In practice, the probability of having strong receive-jammers or transmit leaks at any given time is less than 1 percent. If there are no strong receive-jammers or transmit leaks, the linearity requirement for the LNA is substantially relaxed. Due to the relaxed linearity requirements, LNAs can consume less DC power and have improved NF.

11 is a circuit diagram of a low noise amplifier (LNA) 400 having two linear modes of operation in accordance with a novel aspect. The LNA 400 includes a main field effect transistor (FET) 402, an erase FET 404, a boost transistor 406, a first cascode transistor 408, a second cascode transistor 410, and a first A source degeneration inductor 412, a second source degeneration inductor 414, a load 416, a multiplexer 422, and a bias circuit 424. The load 416 is an LC tank circuit that includes an inductor 418 and a capacitor 420. Main FET 402 receives an RF signal from input node RFIN 426 via AC coupling capacitor C1. The erase FET 404 receives the RF signal from the input node RFIN 426 via an additional AC coupling capacitor C2. Source S1 of main FET 302 is coupled to ground node GND 428 through source degeneration inductor 412. Source S2 of erase FET 404 is coupled to ground node GND 428 through source degeneration inductor 414. The drain D1 of the main FET 402 is connected to the drain D2 of the erase FET 404. Drain D1 and drain D2 are connected to source S3 of cascode transistor 408. Drain D3 of cascode transistor 408 is coupled to voltage supply node VDD 436 via load 416. Drain D3 is also coupled to output voltage node V _OUT 438. The gate of the boost transistor 406 is coupled to the gate of the main FET 402. The source S4 of the boost transistor 406 is connected to the source S1 of the main FET 402. The drain D4 of the defrost transistor 406 is connected to the source S5 of the cascode transistor 410. Drain D5 of cascode transistor 410 is connected to voltage supply node VDD 436. Main FET 402 is biased at bias voltage V _{G_MAIN} such that main FET 402 is biased to its saturation operating region (also known as strong _inversion ). The erase FET 404 is biased at bias voltage V _{G_CANCEL} such that the erase FET 404 is biased to its (also known slightly _inversion ) sub-threshold operating region. The cascode transistor 410 is biased at bias voltage V _{B_DEBOOST} . The gate of the cascode transistor 410 is coupled to the output lead of the multiplexer 422.

There are three current paths within the LNA 400. The first current path is the _main current path (where the current I _MAIN flows from the load 416 to the ground node GND 428 through the cascode transistor 408, the main FET 402, and the source degeneration inductor 412). 430). The second current path is the erase current path through which the current I _CANCEL flows from the load 416 to the ground node GND 428 via the cascode transistor 408, the erase FET 404, and the source degeneration inductor 414. 432). The third current path is a current in which current I _DEBOOST flows from supply node VDD 436 to ground node GND 428 via cascode transistor 410, _deboost transistor 406, and source degeneration inductor 412. Boost current path 434. _Deboost current I _DEBOOST does not flow through rod 416.

LNA 400 has two linear modes, namely high linear mode and low linear mode. The mode of operation is programmable based on the presence of jammer or leakage signals. If no jammer or leakage is present, LNA 400 operates in a low linear mode. The first mode value is supplied through the select input lead of the multiplexer 422 such that the input lead 0 of the multiplexer 422 is selected. As a result, V _{B_DEBOOST} is grounded, and the entire boost current path 434 is disabled. Without de-boost current I _DEBOOST , LNA 400 operates in the same manner as LNA 222 of FIG. 5. As mentioned above, LNA 400 utilizes MDS technology and meets relatively high linearity requirements. In the absence of jammers or leaks, it is often desirable to further reduce linearity requirements to improve NF performance. In one embodiment, the gate of the erase FET 404 is also connected to the bias circuit 424. If no jammer or leakage is present, the first mode value is also supplied to the bias circuit 424 such that the erase FET 404 is supplied with zero bias current. As a result, the bias voltage V _{G_CANCEL} drops to zero and the entire erase current path 432 is disabled. In this particular embodiment, LNA 400 is a source-degeneration low noise amplifier with very good NF but with a relatively low linearity.

On the other hand, when a jammer or leakage signal is present at the input node RFIN 426, the LNA 400 operates in a high linear mode. In order to increase the linearity of the LNA 400, the current flowing through the source degeneration inductor 412 is increased to provide more negative feedback. This increased negative feedback is achieved by increasing the DC bias current of the main FET 402. However, increasing the DC bias current of the main FET 402 also increases the DC current consumption. In addition, the DC bias current cannot be increased without limitation. A very large increase in DC bias current across the load 416 causes the output voltage V _OUT on the output node 438 to decrease very significantly so that there is no suitable voltage to keep the main FET 402 saturated. . This voltage headroom problem is _compounded in low voltage supply applications because the DC bias voltage V _{G_MAIN} on the main FET 402 cannot exceed the supply voltage. For example, the supply voltage of LNA 400 is typically 1.3 volts. As more current flows through the load 416, more voltage falls across the load 416. Increased voltage drop across the load 416 lowers the DC output voltage on the output node 438. As a result, the lower DC output voltage is the voltage headroom of the main FET 402 since the DC bias voltage V _{G_MAIN} cannot exceed V _OUT to ensure that the main FET 402 is biased in its saturation region. Decreases.

The novel despistor transistor 406 operates to improve voltage headroom, thus helping to increase the linearity of the LNA 400. When the second mode value is asserted, it operates in the LNA 400 high linear mode. The second mode value is supplied through the select input lead of the multiplexer 422 so that the input lead 1 of the multiplexer 422 is selected. Thus, the cascode transistor 410 is biased at the DC bias voltage, where V _{B_DEBOOST} = V _B. Deboost current path 434 is enabled. As shown in FIG. 11, the boost current I _DEBOOST flows through the source degeneration inductor 412 with the main current I _MAIN , thus increasing the negative feedback factor on the main FET 402. On the other hand, the boost current I _DEBOOST does not flow through the LNA load 416 and therefore does not lower the output voltage V _OUT on the output node 438. Thus, LNA 400 has a higher linearity by having more negative feedback without facing voltage headroom problems. When the LNA 400 operates in the high linear mode, a second mode value is also supplied to the bias circuit 424 such that the erase FET 404 is supplied with the DC bias current I _B. DC bias current I _B enables the erase current path 432. As described above, the third order distortion component of the erase current I _CANCEL cancels the third order distortion component of the main current I _MAIN , resulting in IMD3 being zero of the output current I _OUT . In one example, the boost current I _DEBOOST can be easily changed during the design process by adjusting the size of the cascode transistor 410 and the boost transistor 406. Thus, the negative feedback associated with the main current path is also adjustable. The adjustability of the negative feedback factor provides extra tuning capability for optimal current cancellation. As a result, LNA can be optimized with fewer design iterations.

12 is a graph showing the linearity performance IIP ₃ of the LNA 400 when the LNA 400 is operating in the high linear mode with respect to the bias current I _B of the erase FET 404. As shown in FIG. 12, IIP ₃ of LNA 400 gradually increases as the bias current I _B increases from 320 microamperes. IIP ₃ of LNA 400 reaches its optimal point when bias current I _B is at 608 microamperes and gradually decreases when bias current I _B further increases. It can be observed that IIP ₃ can be optimized by adjusting only the bias current I _B of the erase FET 404, without having to change any other parameters associated with the main current path 430 or the boost current path 434. . In the example of FIG. 12, the optimal IIP ₃ of LNA 400 is 22.1178 dBm.

FIG. 13 is a table showing LNA 400 characteristics in both the high linear mode and the low linear mode. In high linear mode, IIP ₃ is 8 dBm, noise figure is 5db, and total bias current is 20 milliamps. The total bias current of the LNA 400 includes the bias currents of the main FET 402, the boost transistor 406, and the erase FET 404. In one example, the bias current of main FET 402 is about 9.65 milliamps, the bias current of de-transistor transistor 406 is also 9.65 milliamps, and the bias current of erase FET 404 is 0.7 milliamps. In low linear mode, IIP ₃ is zero dBm, noise figure is 3 db and total bias current is 10 milliamps. Thus, in low linear mode, LNA 400 has a much better noise figure and a bias current that is approximately half as compared to LNA 400 in high linear mode.

Although specific general embodiments have been described above for purposes of explanation, the teachings of this patent specification have general applicability and are not limited to the specific embodiments described above. For example, the rod 416 of FIG. 11 may be a P-channel transistor rather than a tank circuit. P-channel transistors are often preferred because they are broadband loads with high impedance and small die area. Accordingly, various modifications, modifications and combinations of the various features of the specific embodiments described may be practiced without departing from the scope of the claims set out below.

Claims (21)

As a differential superposition (DS) low noise amplifier (LNA),
A first field effect transistor (FET) biased in a saturation region, the gate of the first FET coupled to an input node;
A second FET biased in a sub-critical region, wherein the gate of the second FET is coupled to the gate of the first FET and the drain of the second FET is coupled to the drain of the first FET Second FET;
A first source degeneration inductance coupling the source of the first FET to a ground node; And
And a second source degeneration inductance coupling a source of the second FET to the ground node, the second source degeneration inductance being at least one nanohenry. The method of claim 1,
And said first source degeneration inductance is a first spiral inductor and said second source degeneration inductance is a second spiral inductor. The method of claim 1,
The ground node comprises a surface-mounted microbump,
And the first source degeneration inductance is separate from the second source degeneration inductance. The method of claim 1,
The gate of the second FET is capacitively coupled to the gate of the first FET, and the gate of the first FET is capacitively coupled to the input node. The method of claim 1,
road; And
Further comprising a cascode transistor having a source and a drain,
The source of the cascode transistor is coupled to the drain of the first FET
And a drain of the cascode transistor is coupled to the load. The method of claim 1,
The input node receives an input signal,
The first FET generates a first third order distortion signal, the second FET generates a second third order distortion signal, and the second third order distortion signal outputs the first third order distortion signal. DS noise canceling amplifier. road;
A first source degeneration inductor;
A main transistor biased in a saturation region, the gate of the main transistor being coupled to an input node, the source of the main transistor being coupled to the first source degeneration inductor, wherein the main transistor is connected via the load; The main transistor for controlling a main current flowing through the main transistor and then through the first source degeneration inductor; And
A deboost transistor coupled to a saturation region, the gate of the depot transistor being coupled to the gate of the main transistor, the depot current flowing through the depot transistor without flowing through the load And then the boost transistor flowing through the first source degeneration inductor. The method of claim 7, wherein
Further comprising a boost cascode transistor,
A source of the deassert cascode transistor is coupled to a drain of the deassert transistor, and a drain of the deassert cascode transistor is coupled to a supply voltage node. The method of claim 8,
And the gate of the boost cascode transistor is coupled to a selectable one of a bias voltage node or a ground node. The method of claim 7, wherein
Further comprising an erase transistor biased in the sub-critical region,
The erase transistor has a drain coupled to the drain of the main transistor. The method of claim 10,
Further comprising a second source degeneration inductor having a first lead and a second lead,
The first lead is coupled to a source of the erase transistor, the second lead is coupled to a ground node, and the ground node is coupled to the first source degeneration inductor. The method of claim 7, wherein
Wherein said rod is a tank circuit. The method of claim 7, wherein
The load is a P-channel transistor. The method of claim 10,
A bias circuit for supplying a bias current to the erase transistor,
The bias current is programmable to have either a first current value or a second current value depending on a value of a mode control signal. The method of claim 8,
And means for disabling the boost cascode transistor such that the boost current does not flow through the depot transistor. (a) conducting a first current to the ground node via a load, then through a first transistor biased in the saturation region, and then through a first source degeneration inductor; And
(b) conducting a second current to the ground node through the load, then through a second transistor biased in a sub-critical region, and then through a second source degeneration inductor; ,
The load, the first transistor, the second transistor, the first source degeneration inductor, and the second source degeneration inductor together form part of a low noise amplifier, and the second source degeneration inductor comprises at least one nanometer. Henry's, low noise amplification method. 17. The method of claim 16,
(c) receiving a mode signal,
When the mode signal has a first value, the second transistor is enabled so that the second current flows. When the mode signal has a second value, the second transistor is disabled so that the second current does not flow. Letting, low noise amplification method. (a) receiving an input signal on a low noise amplifier (LNA), wherein the LNA comprises a load, a main transistor biased in the saturation region, and a source degeneration inductance, the main transistor through the load; Receiving the input signal through the main transistor and then controlling the main current flowing through the source degeneration inductance; And
(b) providing a de-boost transistor capable of conducting de-boost current flowing through the de-transistor transistor and then through the source degeneration inductance without flowing the load. . The method of claim 18,
(c) receiving a mode signal,
If the mode signal has a first value, the de-transistor transistor is enabled so that the de-spout current flows. If the mode signal has a second value, the de-transistor transistor is disabled so that the de-prompt current does not flow. Letting, low noise amplification method. A source degenerated low noise amplifier (LNA), wherein the LNA includes a load, a main transistor biased in the saturation region, and a source degeneration inductance, wherein the main transistor passes through the load and then the main transistor. And through the source degeneration inductance thereafter to control a first current flowing through the source degeneration inductance; And
Means for selectively increasing current flow through the source degeneration inductance without increasing the first current flowing through the rod. The method of claim 20,
The means for selectively increasing includes a boost transistor for controlling the boost current,
And the de-boost current flows through the de-transistor transistor and then through the source degeneration inductance without flowing through the load.

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