KR101067526B1 - Thin Film Transistor and the fabrication method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a thin film transistor having improved electrical characteristics and a manufacturing method thereof.

A thin film transistor according to the present invention includes a gate electrode formed on a substrate; A gate insulating film formed on the gate electrode; An active layer having a structure in which amorphous silicon, n-amorphous silicon, and amorphous silicon formed on the gate insulating film are stacked; An ohmic contact layer made of n + amorphous silicon formed on both sides of the active layer; And a source / drain electrode formed on the ohmic contact layer.

Accordingly, the present invention forms an active layer in a thin film transistor in which a structure in which amorphous silicon, n-amorphous silicon, and amorphous silicon is continuously changed and stacked is formed to improve mobility of electrons in a channel region, thereby increasing operating current and increasing threshold voltage. By reducing the power consumption, the phenomenon of deterioration due to electrical stress caused by long-term driving is improved, and thus, it has a stable characteristic, thereby improving reliability.

Active Layer, Channel, n-Amorphous Silicon

Description

Thin film transistor and its manufacturing method {Thin Film Transistor and the fabrication method}

1A to 1E are cross-sectional views showing a manufacturing process of a conventional thin film transistor.

2 is a cross-sectional view showing a thin film transistor according to the present invention.

3A to 3E are cross-sectional views showing a manufacturing process of a thin film transistor according to the present invention.

Figure 4 is an enlarged cross-sectional view of a thin film transistor according to the present invention.

5 is a graph showing the characteristics of the drain current according to the gate voltage of the thin film transistor according to the present invention.

Description of the Related Art [0002]

200: substrate 220: gate insulating film

222: gate electrode 240: active layer

240a, 240c: amorphous silicon 240b: n-amorphous silicon

250: n + amorphous silicon 251, 252: ohmic contact layer

262: source electrode 264: drain electrode

270 protective film 281 pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a thin film transistor having improved electrical characteristics and a manufacturing method thereof.

Recently, with the development of the electronics industry, display devices, which have been limitedly used for TV CRTs, have been widely used in personal computers, notebooks, wireless terminals, automobile dashboards, electronic displays, and the like, so that a large amount of image information can be transmitted with the development of information and communication technology. As a result, the importance of the next generation display device that can process and implement this is increasing.

Such next-generation display devices should be able to realize light and small, high brightness, large screen, low power consumption, and low cost. In response, recently, liquid crystal display devices (LCDs), plasma display panels (PDPs), and electro luminescent displays (ELDs) have been developed. And various flat panel display devices such as a vacuum fluorescent display (VFD) have been studied, and one of them has recently attracted attention.

The liquid crystal display device is superior in resolution to other flat panel display devices, and exhibits characteristics such that the response speed is faster than that of a CRT when a moving image is realized.

In addition, the liquid crystal display device has excellent characteristics such as high brightness, high contrast, low power consumption, and so is used in a wide range of fields such as a desktop computer monitor, a notebook computer monitor, a TV receiver, a vehicle-mounted TV receiver, and navigation.

In general, a liquid crystal display device is formed by arranging two substrates having electrodes formed on one side thereof so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

More specifically, the liquid crystal display may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the first and second substrates. And a liquid crystal layer injected between the two substrates.

The first substrate may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and each of the gate lines and the data lines. A plurality of pixel electrodes formed in a matrix form in the cross-defined pixel regions and a plurality of thin film transistors that are switched by signals of the gate lines and transfer the signals of the data lines to the pixel electrodes are formed.

The second substrate includes a black matrix layer for blocking light in portions other than the pixel region, a color filter layer for expressing R, G, and B color colors, and a common electrode for implementing an image.

As such, the gate electrode and the source / drain electrode constituting the gate line, the data line, and the thin film transistor formed on the first glass substrate of the liquid crystal panel are formed of metal to improve a signal transfer speed.

1A to 1E are cross-sectional views showing a manufacturing process of a conventional thin film transistor.

As shown in FIG. 1A, a metal is deposited on the entire upper surface of the glass substrate 100 and patterned by a photolithography process to form a gate electrode 122 on an upper portion of the glass substrate 100.

Subsequently, as illustrated in FIG. 1B, the gate insulating layer 120, amorphous silicon, and amorphous silicon containing impurities (n +) are sequentially deposited on the entire upper surface of the gate electrode 122.

In addition, the amorphous silicon and the amorphous silicon containing the impurity is patterned to form an active layer 140 on the gate insulating film on the gate electrode, and the amorphous containing impurities on the active layer 150 Silicon 150 is formed.

Subsequently, as shown in FIG. 1C, a metal material is deposited on the entire upper surface of the active layer 140, and the metal material is patterned to be spaced apart from each other at a central portion of the active layer 140 by the active layer 140. The source electrode 162 and the drain electrode 164 leading to the side surface of the ()) are formed.

In addition, the amorphous silicon 150 containing the impurities is etched between the source electrode 162 and the drain electrode 164 to etch the active layer 140 under the source electrode 162 and the drain electrode 164. A channel is formed by forming ohmic contact layers 151 and 152 in contact with the substrate.

Subsequently, as illustrated in FIG. 1D, a passivation layer 170 is deposited on the entire upper surface of the source electrode 162 and the drain electrode 164, and a drain contact hole is formed in the passivation layer 170 to form the drain electrode 164. Part of the

Finally, as illustrated in FIG. 1E, a transparent conductive material is deposited and patterned on the entire upper surface of the passivation layer 170 to form the pixel electrode 181 in contact with the exposed drain electrode 164.

The thin film transistor manufactured according to the manufacturing process sequence as described above is active with the gate insulating layer 120 when a threshold voltage or more is applied to the gate electrode 122 while a signal voltage is applied to the source electrode 162. Channels are formed at the interface of the layer 140 so that electrons flow from the source electrode 162 to the drain electrode 164 through the channel.

In this case, since the specific resistance of amorphous silicon is large in the active layer 140, impurities are included to reduce contact resistance with the metal layers, which are the source and drain electrodes 162 and 164, to be formed after the active layer 140. Ohmic contact layers 151 and 152 are formed using amorphous silicon.

In order to form a channel as described above, a threshold voltage of 2 to 3 V must be applied to the gate electrode 122. Since the resistivity of the active layer 140 is large, power consumption increases and loss of operating current is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor for improving the electrical characteristics of a channel by forming a low concentration of ion (n-) doped amorphous silicon layer between an active layer made of amorphous silicon in a liquid crystal display, and a method of manufacturing the same. have.

In order to achieve the above object, a thin film transistor according to the present invention includes a gate electrode formed on a substrate; A gate insulating film formed on the gate electrode; An active layer having a structure in which amorphous silicon, n-amorphous silicon, and amorphous silicon formed on the gate insulating film are stacked; An ohmic contact layer made of n + amorphous silicon formed on both sides of the active layer; And a source / drain electrode formed on the ohmic contact layer.

The amorphous silicon, n-amorphous silicon, amorphous silicon is characterized in that the continuous deposition.

In addition, to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises the steps of forming a gate electrode on a substrate; Forming a gate insulating film on the gate electrode; Continuously depositing and patterning amorphous silicon, n-amorphous silicon, amorphous silicon, and n + amorphous silicon on the gate insulating film to form an active layer made of amorphous silicon, n-amorphous silicon, and amorphous silicon; And depositing and patterning a metal material on the active layer and n + amorphous silicon to form source and drain electrodes and etching to form an ohmic contact layer.

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view showing a thin film transistor according to the present invention.

As shown in FIG. 2, in the thin film transistor according to the present invention, a gate electrode 222 is formed on a substrate 200, and a gate insulating layer 220 is formed on the entire surface of the gate electrode 222.

In addition, an active layer 240 sequentially formed of amorphous silicon 240a, n−amorphous silicon 240b, and amorphous silicon 240c is formed at the gate electrode 222 on the gate insulating layer 220. .

In addition, the ohmic contact layers 251 and 252 made of n + amorphous silicon 250 formed on both sides of the active layer 240 at predetermined intervals, and the ohmic contact layers 251 and 252 are in contact with each other. 240, a source electrode 262 and a drain electrode 264 spaced apart from each other by a predetermined distance are formed in the center.

In addition, a passivation layer 270 including a drain contact hole exposing the drain electrode 264 is formed on an entire top surface of the source and drain electrodes 262 and 264, and the drain electrode 264 is formed through the drain contact hole. ), A pixel electrode 281 is formed in electrical contact.

Hereinafter, the manufacturing method of the thin film transistor according to the present invention configured as described above will be described in detail.                     

3A to 3E are cross-sectional views showing a manufacturing process of a thin film transistor according to the present invention.

As shown in FIG. 3A, a metal is deposited on the entire upper surface of the substrate 200 and patterned by a photolithography process to form a gate electrode 222 on the upper portion of the substrate 200.

Subsequently, as shown in FIG. 3B, a gate insulating layer 220 is formed on the entire upper surface of the gate electrode 222.

In addition, an amorphous phase is formed on the gate insulating layer 220 by a method such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced CVD (PECVD). Silicon 240a, n-amorphous silicon 240b, amorphous silicon 240c, and n + amorphous silicon 250 are sequentially deposited.

Here, n-amorphous silicon 240b is doped with low concentration ions (n−) in amorphous silicon, and n + amorphous silicon 250 is doped with high concentration (n +) ions in amorphous silicon.

The amorphous silicon 240a, the n− amorphous silicon 240b, the amorphous silicon 240c, and the n + amorphous silicon 250 are patterned on the gate insulating layer 220 on the gate electrode 222. An active layer 240 in which amorphous silicon 240a, n-amorphous silicon 240b, and amorphous silicon 240c are sequentially stacked is formed, and n + amorphous silicon is formed on the active layer 240. 250 is formed.                     

Subsequently, as illustrated in FIG. 3C, a metal material is deposited on the entire upper surface of the active layer 240, and the metal material is patterned to be spaced apart from each other at a center of the active layer 240 by a predetermined distance. The source electrode 262 and the drain electrode 264 leading to the side surface of the ()) are formed.

The n + amorphous silicon 250 is etched between the source electrode 262 and the drain electrode 264 to be in contact with the active layer 240 under the source electrode 262 and the drain electrode 264. Channels are formed by forming ohmic contact layers 251 and 252.

Since the specific resistance of the amorphous silicon in the active layer 240 is large, amorphous silicon containing impurities to reduce contact resistance with the metal layers, which are the source and drain electrodes 262 and 264, to be formed after the active layer 240. The ohmic contact layers 251 and 252 were formed using the same.

Subsequently, as illustrated in FIG. 3D, a passivation layer 270 is deposited on the entire upper surface of the source electrode 262 and the drain electrode 264, and a drain contact hole is formed in the passivation layer 270 to form the drain electrode 264. Part of the

Finally, as illustrated in FIG. 3E, a transparent conductive material is deposited and patterned on the entire upper surface of the passivation layer 270 to form the pixel electrode 281 in contact with the exposed drain electrode 264.

The active layer 240 formed as described above has a structure in which an amorphous silicon layer 240a, an n− amorphous silicon layer 240b, and an amorphous silicon layer 240c are sequentially stacked, and the active layer 240 is formed thereafter. In order to reduce the contact resistance with the source and drain electrodes 262 and 264 to be formed, n + amorphous silicon is formed as the ohmic contact layers 251 and 252.

Here, the amorphous silicon 240a and 240c, the n− amorphous silicon 240b and the n + amorphous silicon 250 may be continuously deposited while changing the ion doping concentration in one chamber.

In addition, since the n− amorphous silicon layer 240b of the channel region of the active layer 240 has a higher doping concentration than amorphous silicon, the mobility of charge in the channel is improved.

The thin film transistor manufactured according to the manufacturing process sequence as described above is active with the gate insulating layer 220 when a threshold voltage or more is applied to the gate electrode 222 while a signal voltage is applied to the source electrode 262. A channel is formed at the interface of the layer 240, and another channel is formed in the n-amorphous silicon 240b so that electrons flow from the source electrode to the drain electrode 264 through the channels.

As shown in FIG. 4, the thin film transistor according to the present invention has a structure in which an active layer 240 is sequentially stacked with amorphous silicon 240a, n-amorphous silicon 240b, and an amorphous silicon layer 240c. The n-amorphous silicon 240b is formed in the channel region to improve the mobility of electrons so that a small amount of signal current always flows even without a gate voltage, so that the channel is easily formed even at a low voltage when the gate voltage is applied.

5 is a graph showing the characteristics of the drain current according to the gate voltage of the thin film transistor according to the present invention.                     

As shown in FIG. 5, the gate voltage was gradually applied at a constant value from −16 V to 20 V, and at this time, the amount of change of the drain current flowing through the channel of the active layer was measured.

The curve B of the thin film transistor according to the present invention decreases the threshold voltage by approximately 2 V from the curve of the thin film transistor A having the active layer made of only amorphous silicon.

In addition, it can be seen that the curve B of the thin film transistor according to the present invention increases the operating current than the thin film transistor A having the active layer made of amorphous silicon.

Accordingly, it can be seen that the curve B of the thin film transistor according to the present invention shifts to the left side than the curve of the thin film transistor A having the active layer made of amorphous silicon.

As described above, the thin film transistor according to the present invention has a structure in which an active layer is formed by sequentially stacking amorphous silicon, n-amorphous silicon, and amorphous silicon layers, and the n-amorphous silicon is formed in a channel region to improve electron mobility. A small amount of signal current always flows even without a gate voltage, so that a channel is easily formed even at a low voltage when the gate voltage is applied.

Thus, the operating current flowing in the channel is increased overall due to the current flowing into the n- amorphous silicon layer.

As described above, the present invention has been described in detail through specific embodiments, which are intended to specifically describe the present invention, and the thin film transistor and its manufacturing method according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art.

According to the present invention, an active layer is formed in a thin film transistor in a structure in which amorphous silicon, n-amorphous silicon, and amorphous silicon are continuously stacked and stacked, thereby improving the mobility of electrons in the channel region, thereby increasing the operating current and reducing the threshold voltage. It is effective to reduce power consumption.

In addition, the thin film transistor according to the present invention has an effect of improving the reliability because the phenomenon of deterioration (heating) due to the electrical stress received by long time driving is improved and has a stable characteristic.

Claims (5)

A gate electrode formed on the substrate; A gate insulating film formed on the gate electrode; An active layer having a structure in which amorphous silicon, n-amorphous silicon, and amorphous silicon formed on the gate insulating film are sequentially stacked; An ohmic contact layer made of n + amorphous silicon formed on both sides of the amorphous silicon on the top of the active layer; And a source / drain electrode formed on the ohmic contact layer. The method of claim 1, And the amorphous silicon, n-amorphous silicon, and amorphous silicon are continuously deposited. The method of claim 1, And a passivation layer formed on the source / drain electrodes. Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Sequentially depositing and patterning amorphous silicon, n-amorphous silicon, amorphous silicon, and n + amorphous silicon on the gate insulating film to form an active layer made of amorphous silicon, n-amorphous silicon, and amorphous silicon; And depositing and patterning a metal material on the active layer and n + amorphous silicon to form source and drain electrodes and etching to form an ohmic contact layer. The method of claim 4, wherein After forming and etching the source and drain electrodes to form an ohmic contact layer, And forming a passivation layer on the source and drain electrodes.

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