KR100202224B1 - Thin film transistors and manufacturing method thereof - Google Patents
Thin film transistors and manufacturing method thereof Download PDFInfo
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- KR100202224B1 KR100202224B1 KR1019960030563A KR19960030563A KR100202224B1 KR 100202224 B1 KR100202224 B1 KR 100202224B1 KR 1019960030563 A KR1019960030563 A KR 1019960030563A KR 19960030563 A KR19960030563 A KR 19960030563A KR 100202224 B1 KR100202224 B1 KR 100202224B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 90
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 18
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 229910019923 CrOx Inorganic materials 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 6
- 238000010030 laminating Methods 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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Abstract
액정표시장치의 박막트랜지스터는 기판과, 기판 위에 형성된 버퍼층과, 복수의 반도체층과, 반도체층 사이에 형성된 n+층 및 소스/드레인전극으로 구성되어 있다. 각 반도체층은 소스/드레인전극 사이의 채널층으로, n+층 에칭시 반도체층의 일부가 에칭되어도 별도의 반도체층에 형성된 채널에 의해 전류가 원활하게 흐르게 된다. 반도체층 위에는 게이트절연층이 형성되어 있으며, 그 위에 게이트전극이 형성되어 있다.The thin film transistor of the liquid crystal display device is composed of a substrate, a buffer layer formed on the substrate, a plurality of semiconductor layers, an n + layer and a source / drain electrode formed between the semiconductor layers. Each semiconductor layer is a channel layer between the source / drain electrodes, and even though a portion of the semiconductor layer is etched during n + layer etching, current flows smoothly through a channel formed in a separate semiconductor layer. A gate insulating layer is formed on the semiconductor layer, and a gate electrode is formed thereon.
Description
본 발명은 액정표시장치에 관한 것으로, 특히 반도체층을 복수의 층으로 형성하여 한 층의 반도체층이 손상되어도 다른 층의 반도체층에 형성된 채널층을 확보함으로써 전류의 흐름을 원활하게 함과 동시에 계면특성을 향상시키며 공정을 간단하게 한 액정표시장치의 박막트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, the semiconductor layer is formed of a plurality of layers, so that even if one layer of the semiconductor layer is damaged, the channel layer formed in the semiconductor layer of the other layer is ensured to smoothly flow current and at the same time. The present invention relates to a thin film transistor of a liquid crystal display device having improved characteristics and a simplified process, and a method of manufacturing the same.
텔레비전이나 퍼스널컴퓨터의 표시장치에 주로 사용되고 있는 CRT(Cathod Ray Tube)는 대면적의 화면을 만들 수 있다는 장점이 있지만, 이러한 대면적의 화면을 만들기 위해서는 전자총(electron gun)과 발광물질이 도포된 스크린과의 거리가 일정 이상을 유지해야만 하기 때문에 그 부피가 커지는 문제가 있었다. 따라서, CRT는 현재 활발하게 연구되고 있는 벽걸이용 텔레비전 등에 적용할 수 없을 뿐만 아니라, 근래에 주목받고 있는 휴대용 텔레비전이나 노트북 컴퓨터 등과 같이 저전력을 필요로 하며 소형화를 요구하는 전자제품에도 적용할 수가 없었다.CRT (Cathod Ray Tube), which is mainly used for display devices of televisions and personal computers, has the advantage of making a large area screen, but in order to make such a large area screen, an electron gun and a screen coated with a light emitting material Because the distance between the and must maintain a certain amount, there was a problem that the volume becomes large. Therefore, the CRT cannot be applied not only to wall-mounted televisions, which are currently being actively studied, but also to electronic products that require low power and require miniaturization, such as portable televisions and notebook computers, which are attracting attention in recent years.
이러한 표시장치의 요구에 부응하여 LCD(Liquid Crystal Display), PDP(Plasma Display Panel), ELD(Electroluminescent Display), VFD(Vacuum Fluorescent Display)와 같은 여러 가지의 평판 표시장치가 연구되고 있지만, 그 중에서도 LCD(액정표시장치)가 여러 가지의 단점에도 불구하고 화질이 우수하며 저전력을 사용한다는 점에서 근래에 가장 활발하게 연구되고 있다. 이러한 LCD로는 단순 매트릭스(Passive Matrix) 구동방식 LCD와 액티브 매트릭스(Active Matrix) 구동방식 LCD가 있는데, 이 중에서도 AMLCD가 각각의 화소를 독립적으로 구동시킴으로써, 인접화소의 데이터신호에 의한 영향을 최소화시켜서 콘트라스트비(contrast ratio)를 높이면서 주사선수를 증가 시킬 수 있기 때문에 근래의 LCD에 주로 사용되고 있다.In order to meet the demands of such display devices, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD) have been studied. In recent years, the liquid crystal display has been researched most actively in that it has excellent image quality and uses low power despite various disadvantages. Such LCDs include a passive matrix driving LCD and an active matrix driving LCD, among which AMLCD independently drives each pixel, thereby minimizing the influence of data signals of adjacent pixels. It is mainly used in modern LCDs because it can increase the number of injection players while increasing the contrast ratio.
도1은 일반적인 AMLCD의 평면도를 나타내는 도면으로서, 이 경우의 LCD는 능동소자로서 박막트랜지스터(TFT)가 적용된 TFT LCD이다. 일반적으로 LCD에서는 주사선(gate bus line)(15) 및 신호선(data bus line)(14)은 종횡으로 복수개 형성되어 매트릭스 형상을 이루고 있지만, 도면에서는 설명을 간단하게 하기 위해 한 화소만 나타내었다. 도면에 나타낸 바와 같이 주사선(15)과 신호선(14)에 의해 정의되는 화소 영역에는 화소전극(9)이 형성되어 있으며, 상기한 화소 영역내의 주사선(15)과 신호선(14)의 교차점에는 TFT가 형성되어 있다. TFT의 게이트전극(5)은 주사선(15)에 연결되고 소소/드레인전극(4)은 신호선(14)에 연결되어, 도면표시하지 않은 주사선 구동회로에 의해 주사선(15)에 전압이 인가되면 TFT가 턴 온(turn on)됨과 동시에 상기한 TFT를 통해 도면표시하지 않은 신호선 구동회로로부터 화상신호가 상기한 화소전극(7)에 전달된다.Fig. 1 shows a plan view of a typical AMLCD, in which the LCD is a TFT LCD to which a thin film transistor (TFT) is applied as an active element. In general, a plurality of gate bus lines 15 and data bus lines 14 are formed vertically and horizontally in an LCD to form a matrix, but in the drawings, only one pixel is shown for simplicity. As shown in the figure, a pixel electrode 9 is formed in the pixel region defined by the scan line 15 and the signal line 14, and a TFT is formed at the intersection of the scan line 15 and the signal line 14 in the pixel region. Formed. The gate electrode 5 of the TFT is connected to the scan line 15 and the source / drain electrode 4 is connected to the signal line 14. When the voltage is applied to the scan line 15 by a scan line driver circuit (not shown), the TFT is applied. Is turned on and an image signal is transmitted from the signal line driver circuit (not shown) to the pixel electrode 7 through the TFT.
도2는 종래 액정표시장치의 TFT 제조방법을 나타내는 도면으로, 상기한 방법에 의해 제조된 TFT는 코플래너(coplanar) TFT이다. 우선, 도2(a) 및 도2(b)에 나타낸 바와 같이 투명한 유리기판(1) 위에 비정질실리콘층(a-Si; 2)과 n+층(3)을 연속 적층한 후 에칭하여 활성층(2)과 오우믹컨택트층(3)을 형성한다. 이어서, 도2(c)에 나타낸 바와 같이 금속을 적충하고 에칭하여 소스/드레인전극(4)을 형성한 후, 도2(d)에 나타낸 바와 같이 상기한 소스/드레인전극(4)을 마스크(mask)로 하여 n+층(3)을 에칭한다.2 is a view showing a TFT manufacturing method of a conventional liquid crystal display device, wherein a TFT manufactured by the above method is a coplanar TFT. First, as shown in FIGS. 2 (a) and 2 (b), an amorphous silicon layer (a-Si) 2 and an n + layer 3 are sequentially stacked on the transparent glass substrate 1, and then etched to form an active layer ( 2) and the ohmic contact layer 3 are formed. Subsequently, as shown in FIG. 2 (c), metal is deposited and etched to form the source / drain electrodes 4, and then the source / drain electrodes 4 are masked as shown in FIG. n + layer 3 is etched as a mask.
그 후, 도2(e)와 같이 ITO(Indium Tin Oxide)를 적층하고 에칭하여 화소영역에 화소전극(7)을 형성하고, 이어서 도2(f)에 나타낸 바와 같이 게이트절연층(6)을 적층한 다음 금속을 적층하고 에칭하여 게이트전극(5)을 형성하여 TFT를 완성한다.Thereafter, indium tin oxide (ITO) is stacked and etched to form a pixel electrode 7 in the pixel region, as shown in FIG. 2 (e), and then the gate insulating layer 6 is formed as shown in FIG. After the lamination, the metal is laminated and etched to form the gate electrode 5 to complete the TFT.
그러나, 상기한 방법에 의해 제조된 TFT는 n+층 에칭시에 채널영역의 반도체층 일부분이 에칭되어 반도체층과 절연층 사이의 계면특성이 저하되고 소스/드레인전극 사이의 전류의 흐름이 원활하게 되지 않는 문제가 있었다. 더욱이, 제조과정에서도 n+층 및 반도체층 에칭용 마스크(mask), 소스/드레인전극 형성용 마스크, 게이트전극 형성용 마스크, 화소전극 에칭용 마스크 등 총 4개의 마스크가 필요하게 되어 공정이 복잡하게 되며, 제조비용이 상승하는 문제가 있었다.However, in the TFT manufactured by the above method, a portion of the semiconductor layer of the channel region is etched at the time of n + layer etching, so that the interface property between the semiconductor layer and the insulating layer is degraded and the current flows smoothly between the source / drain electrodes. There was no problem. In addition, the manufacturing process requires a total of four masks such as a mask for etching an n + layer and a semiconductor layer, a mask for forming a source / drain electrode, a mask for forming a gate electrode, and a mask for etching an electrode of a pixel electrode. And, there was a problem that the manufacturing cost increases.
본 발명은 상기한 문제를 감안하여 이루어진 것으로, 반도체층을 복수의 층으로 형성하여 반도체층의 계면특성이 향상되고 소스/드레인 사이의 전류의 흐름이 원활한 액정표시장치의 박막트랜지스터를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film transistor of a liquid crystal display device in which the semiconductor layer is formed of a plurality of layers to improve the interfacial characteristics of the semiconductor layer and smooth the flow of current between the source and the drain. It is done.
본 발명의 다른 목적은 사용되는 마스크의 수를 절감하여 공정이 간단한 액정표시장치의 박막트랜지스터 제조방법을 제공하는 것이다.Another object of the present invention is to provide a method for manufacturing a thin film transistor of a liquid crystal display device having a simple process by reducing the number of masks used.
상기한 목적을 달성하기 위해, 본 발명에 따른 액정표시장치의 박막트랜지스터는 기판 위에 차광층을 형성하는 단계와, 차광층 및 기판 위에 버퍼층, 제1반도체층, n+층, 금속층을 연속 적층하는 단계와, 금속층을 에칭하여 소스/드레인전극을 형성하는 단계와, 소스/드레인전극을 마스크로 하여 n+층을 에칭하는 단계와, 소스/드레인전극 및 제1반도체층 위에 적어도 한층 이상의 제2반도체층, 게이트절연층, 금속층을 적층하는 단계와, 금속층을 에칭하여 게이트전극을 형성하는 단계와, 게이트전극을 마스크로 하여 게이트절연층 및 제2반도체층을 에칭하는 동시에 게이트전극 및 소스/드레인전극을 마스크로 하여 제1반도체층을 에칭하는 단계와, 소스/드레인전극 및 버퍼층 위에 화소전극을 형성하는 단계로 구성된다.In order to achieve the above object, the thin film transistor of the liquid crystal display according to the present invention comprises the steps of forming a light shielding layer on a substrate, and a continuous stack of a buffer layer, a first semiconductor layer, n + layer, a metal layer on the light shielding layer and the substrate Etching the metal layer to form a source / drain electrode, etching the n + layer using the source / drain electrode as a mask, and at least one second semiconductor on the source / drain electrode and the first semiconductor layer Laminating a layer, a gate insulating layer, and a metal layer, etching the metal layer to form a gate electrode, etching the gate insulating layer and the second semiconductor layer using the gate electrode as a mask, and simultaneously the gate electrode and the source / drain electrode Etching the first semiconductor layer using the mask, and forming a pixel electrode on the source / drain electrode and the buffer layer.
n+층은 반도체층에 n형 이온을 도핑하거나 불순물 반도체을 직접 적층함으로써 형성된다. n형 이온의 도핑에 의해 n+층이 형성되는 경우에는 버퍼층 및 제1반도체층을 연속 적층한 후 n형 이온을 도핑하여, 직접 적층되는 경우에는 버퍼층, 제1반도체층 및 n+층이 연속 적층된다. 또한, 제2반도체층, 게이트절연층 및 금속층도 연속 적층되어 형성된다.The n + layer is formed by doping n-type ions into the semiconductor layer or directly depositing an impurity semiconductor. In the case where the n + layer is formed by the doping of the n-type ions, the buffer layer and the first semiconductor layer are successively stacked, and then the n-type ion is doped, and in the case of the direct stack, the buffer layer, the first semiconductor layer, and the n + layer are continuous. Are stacked. In addition, the second semiconductor layer, the gate insulating layer, and the metal layer are also formed by successive stacking.
제1반도체층 및 제2반도체층은 비정질실리콘층으로, 제1반도체층 위에는 n+층이 형성되어 있고, 그 위에 소스/드레인전극이 형성되어 있으며, 소스/드레인전극의 일부와 제1반도체층의 채널 영역 위에는 적어도 한층 이상의 제2반도체층이 형성되어 있다. 소스/드레인전극 사이의 전류의 흐름은 제1반도체층 또는 제2반도체층에 형성된 채널층을 통해 이루어지므로, 한층의 반도체층이 손상되어도 다른 반도체층의 채널층을 통해 전류가 원활하게 흐를 수 있다.The first semiconductor layer and the second semiconductor layer are amorphous silicon layers, an n + layer is formed on the first semiconductor layer, a source / drain electrode is formed thereon, a part of the source / drain electrode and the first semiconductor layer. At least one or more second semiconductor layers are formed on the channel region of. Since the current flows between the source / drain electrodes through the channel layer formed on the first semiconductor layer or the second semiconductor layer, current may flow smoothly through the channel layer of another semiconductor layer even if one semiconductor layer is damaged. .
제1도는 일반적인 액정표시장치의 평면도.1 is a plan view of a general liquid crystal display device.
제2도는 종래의 액정표시장치의 박막트랜지스터 제조방법.2 is a method of manufacturing a thin film transistor of a conventional liquid crystal display device.
제3도는 본 발명에 따른 액정표시장치의 박막트랜지스터 제조방법.3 is a thin film transistor manufacturing method of a liquid crystal display according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101 : 기판 102 : 제1반도체층101: substrate 102: first semiconductor layer
103 : n+층 104 : 소스/드레인전극103: n + layer 104: source / drain electrodes
106 : 게이트절연층 107 : 화소전극106: gate insulating layer 107: pixel electrode
109 : 버퍼층 122 : 제2반도체층109: buffer layer 122: second semiconductor layer
이하, 첨부한 도면을 참조하여 본 발명에 따른 액정표시장치의 박막트랜지스터 및 그 제조방법에 대하여 상세히 설명한다.Hereinafter, a thin film transistor and a manufacturing method thereof of a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 가장 큰 특징은, 코플래너 TFT에서 채널층인 반도체층을 복수의 층으로 형성하여 반도체층의 계면특성을 향상시킴과 동시에 전류가 흐르는 통로를 확실하게 확보함으로써 TFT의 특성을 향상시킨 것이다. 또한, 제조공정에서도 마스크의 수를 감소하여 제조공정을 간단하게 하여 제조비용을 절감한 것이다.The greatest feature of the present invention is to improve the characteristics of the TFT by forming a plurality of layers of the semiconductor layer as a channel layer in the coplanar TFT to improve the interfacial characteristics of the semiconductor layer and to secure a passage through which the current flows. . In addition, in the manufacturing process, the number of masks is reduced to simplify the manufacturing process, thereby reducing manufacturing costs.
도3은 본 발명의 일실시예에 따른 액정표시장치의 TFT 제조방법을 나타내는 도면으로, 우선 도3(a)에 나타낸 바와 같이 투명한 유리기판(101) 위에 Cr이나 CrOx 등의 금속을 스퍼터링(sputtering) 방법에 의해 적층하고 포토에칭(photoetching)하여 차광층(126)을 형성한다. 차광층(126)은 기판(101)의 아래에서 입사되어 코플래너 TFT에서 반도체층을 여기시키는 빛을 차단하기 위한 것이다. 이어서, 버퍼층(109), 제1반도체층(102), n+층(103) 및 제1금속층(104)을 형성한다. 버퍼층(109)은 플라즈마 CVD(Plasma Chemical Vapor Deposition) 방법에 의해 SiO2또는 SiNx를 적층하여 형성하며, 제1반도체층(102)은 비정질실리콘(a-Si)을 역시 플라즈마 CVC 방법에 의해 적층하여 형성한다. n+층(103)은 제1반도체층(102)에 n형 이온(P+)을 도핑하여 형성하거나 제1반도체층(102) 위에 n형의 불순물 비정질실리콘을 직접 플라즈마 CVD 방법에 의해 적층함으로써 형성한다. 또한, 제1금속층(104)은 스퍼터링(sputtering) 방법으로 Al, Cr, Mo 등을 적층하여 형성한다.3 is a view showing a TFT manufacturing method of a liquid crystal display according to an embodiment of the present invention. First, as shown in FIG. 3 (a), sputtering metal such as Cr or CrOx on a transparent glass substrate 101 is shown. Layer) and photoetching to form the light shielding layer 126. The light shielding layer 126 is for blocking light incident from under the substrate 101 to excite the semiconductor layer in the coplanar TFT. Subsequently, the buffer layer 109, the first semiconductor layer 102, the n + layer 103, and the first metal layer 104 are formed. The buffer layer 109 is formed by stacking SiO 2 or SiNx by a plasma chemical vapor deposition (CVD) method, and the first semiconductor layer 102 is formed by laminating amorphous silicon (a-Si) by a plasma CVC method. Form. The n + layer 103 is formed by doping n-type ions (P + ) to the first semiconductor layer 102 or by depositing n-type impurity amorphous silicon directly on the first semiconductor layer 102 by a plasma CVD method. Form. In addition, the first metal layer 104 is formed by stacking Al, Cr, Mo, and the like by a sputtering method.
n+층(103)을 불순물반도체를 직접 적층하여 형성하는 경우에는 버퍼층(109), 제1반도체층(102), n+층(103)을 플라즈마 CVD 방법으로, 제1금속층(104)을 스퍼터링 방법으로 연속 적층하고, 제1반도체층(102)에 n형 이온(P+)을 도핑하는 경우에는 버퍼층(109) 및 제1반도체층(102)을 연속 적층한 후, 상기한 제1반도체층(102)에 이온을 도핑하여 n+층(103)을 형성한다.When the n + layer 103 is formed by directly stacking impurity semiconductors, the buffer layer 109, the first semiconductor layer 102, and the n + layer 103 are sputtered on the first metal layer 104 by a plasma CVD method. In the case of continuous stacking and doping n-type ions (P + ) to the first semiconductor layer 102, the buffer layer 109 and the first semiconductor layer 102 are continuously stacked, and then the first semiconductor layer described above. Ion is doped with 102 to form n + layer 103.
이후, 도3(b)에 나타낸 바와 같이 금속층(104)을 포토에칭(photoetching)하여 소스/드레인전극(104)을 형성한 후, 도3(c)에 나타낸 바와 같이 소스/드레인전극(104)을 마스크로 하여 n+층(103)을 에칭한다.Thereafter, as illustrated in FIG. 3B, the metal layer 104 is photoetched to form the source / drain electrodes 104, and then the source / drain electrodes 104 are illustrated in FIG. 3C. The n + layer 103 is etched using as a mask.
이어서, 도3(d)에 나타낸 바와 같이 제2반도체층(122), 게이트절연층(106) 및 제2금속층(105)을 연속 적층하여 형성한다. 제2반도체층(122)도 제1반도체층(102)과 같이 플라즈마 CVD 방법에 의해 a-Si를 적층하여 형성하며, 게이트절연층(106)도 버퍼층(109)과 마찬가지로 SiO2나 SiNx를 플라즈마 CVD 방법에 의해 적층하여 형성한다. 또한, 제2금속층(105)도 제1금속층(104)과 마찬가지로 스퍼터링 방법에 의해 Cr, Mo, Al, 또는 Al합금을 적층함으로써 형성한다.Subsequently, as shown in FIG. 3D, the second semiconductor layer 122, the gate insulating layer 106, and the second metal layer 105 are successively stacked. Like the first semiconductor layer 102, the second semiconductor layer 122 is formed by laminating a-Si by the plasma CVD method, and the gate insulating layer 106 is similar to the buffer layer 109 to form SiO 2 or SiNx. It forms by laminating by the CVD method. The second metal layer 105 is also formed by laminating Cr, Mo, Al, or Al alloys by the sputtering method similarly to the first metal layer 104.
그리고, 도3(e)에 나타낸 바와 같이 금속층(105)을 에칭하여 게이트전극(105)을 형성한 후, 상기한 게이트전극(105)을 마스크로 하여 게이트절연층(106) 및 제2반도체층(122)을 에칭한다. 상기한 게이트절연층(106) 및 제2반도체층(122)의 에칭과 동시에, 제1반도체층(102)도 게이트전극(105) 및 소스/드레인전극(104)을 마스크로 하여 에칭된다.As shown in FIG. 3E, the gate electrode 105 is formed by etching the metal layer 105, and the gate insulating layer 106 and the second semiconductor layer are formed using the gate electrode 105 as a mask. Etch 122. At the same time as the etching of the gate insulating layer 106 and the second semiconductor layer 122, the first semiconductor layer 102 is also etched using the gate electrode 105 and the source / drain electrode 104 as a mask.
본 실시예에서는 제2반도체층(122)을 한 층으로 구성했지만, 적어도 한층 이상의 복수의 층으로 형성하는 것도 물론 가능하다.In the present embodiment, the second semiconductor layer 122 is composed of one layer, but of course, it is also possible to form a plurality of layers of at least one layer.
그 후, 도3(f)에 나타낸 바와 같이 상기한 소스/드레인전극(104) 위와 액정표시장치의 화소영역에 ITO 등을 적층하고 에칭하여 화소전극(107)을 형성하고 기판(101) 전체에 걸쳐서 보호막(도면표시하지 않음)을 형성함으로써 TFT가 완성된다. 이 TFT의 소스/드레인전극(104) 및 게이트전극(105)에 연결된 신호선 및 주사선이 보호막에 형성된 컨택트홀을 통해 외부 구동회로의 패드에 연결된다.Thereafter, as shown in FIG. 3 (f), ITO and the like are laminated and etched on the source / drain electrode 104 and the pixel region of the liquid crystal display device to form a pixel electrode 107, and the entire substrate 101 is formed. The TFT is completed by forming a protective film (not shown) over. Signal lines and scan lines connected to the source / drain electrodes 104 and the gate electrodes 105 of this TFT are connected to pads of an external driving circuit through contact holes formed in the protective film.
도3(f)는 상기한 방법에 의해 최종적으로 제조된 액정표시장치의 TFT로서, 이를 참조하여 본 실시예에 따른 TFT의 구조를 상세히 설명한다. 도면에 나타낸 바와 같이, 투명한 유리기판(101) 위에는 Cr이나 CrOx 등의 금속으로 이루어진 차광층(126)이 형성되어 있으며, 그 위에 SiO2나 SiNx 등으로 이루어진 버퍼층(109)이 형성되어 있다. 버퍼층(109) 위에는 일정한 폭의 제1반도체층(102)이 형성되어 있다. 제1반도체층(102)은 a-Si층으로, 전류가 흐르는 채널을 형성하고 있다. 이 제1반도체층(102) 위에는 n+층(103)이 형성되어 오우믹컨택트층을 이루고 있고, 그 위에 Cr, Mo, Al, 또는 Al합금 등으로 이루어진 소스/드레인전극(104)이 형성되어 있다. 상기한 소스/드레인전극(104)의 일부분 위와 그 사이의 제1반도체층(102) 위에는 역시 a-Si로 이루어진 제2반도체층(122)이 적층되어 상기한 제1반도체층(102)이 손상되는 경우에도 채널을 형성하여 전류의 흐름을 원활하게 한다. 이 때, 소스/드레인전극(104) 사이의 채널은 게이트전극(105)과 더 근접한 제2반도체층(122)에 형성되기 때문에, n+층(103) 에칭시 제1반도체층(102)의 일부분이 에칭되는 경우에도 상기한 제2반도체층(122)에 형성된 채널로 전류가 흐르게 되어 TFT의 특성이 향상된다. 이 때, 반도체층은 제1 및 제2반도체층으로 이루어진 2층 구조가 아니라 그 이상의 층으로 구성하는 것도 물론 가능하다.3 (f) is a TFT of the liquid crystal display device finally manufactured by the above-described method, and the structure of the TFT according to the present embodiment will be described in detail with reference to this. As shown in the figure, a light shielding layer 126 made of metal such as Cr or CrOx is formed on the transparent glass substrate 101, and a buffer layer 109 made of SiO 2 or SiNx is formed thereon. The first semiconductor layer 102 having a constant width is formed on the buffer layer 109. The first semiconductor layer 102 is an a-Si layer and forms a channel through which a current flows. An n + layer 103 is formed on the first semiconductor layer 102 to form an ohmic contact layer, and a source / drain electrode 104 made of Cr, Mo, Al, or Al alloy is formed thereon. have. A second semiconductor layer 122, also made of a-Si, is stacked on a portion of the source / drain electrode 104 and on the first semiconductor layer 102 therebetween, thereby damaging the first semiconductor layer 102. Even if the channel is formed to facilitate the flow of current. At this time, since the channel between the source / drain electrodes 104 is formed in the second semiconductor layer 122 which is closer to the gate electrode 105, the first semiconductor layer 102 of the first semiconductor layer 102 is etched when the n + layer 103 is etched. Even when a portion is etched, current flows through the channel formed in the second semiconductor layer 122, thereby improving the TFT characteristics. At this time, the semiconductor layer can of course be composed of more layers than the two-layer structure composed of the first and second semiconductor layers.
제2반도체층(122) 위에는 SiO2나 SiNx 등으로 이루어진 게이트절연층(106)이 형성되어 있으며, 그 위에 Cr, Mo, Al 또는 Al합금 등으로 이루어진 게이트전극(105)이 형성되어 있다.A gate insulating layer 106 made of SiO 2 , SiNx, or the like is formed on the second semiconductor layer 122, and a gate electrode 105 made of Cr, Mo, Al, or an Al alloy is formed thereon.
상기한 바와 같이, 본 발명에 따른 액정표시장치의 박막트랜지스터는 반도체층이 복수의 층으로 구성되어 있기 때문에, n+층 에칭시 반도체층의 일부가 에칭되어도 그 위에 다른 반도체층이 존재하기 때문에 반도체층과 절연층 사이의 계면특성이 저하되지 않을 뿐만 아니라 확실한 채널을 확보할 수 있게 된다.As described above, in the thin film transistor of the liquid crystal display according to the present invention, since the semiconductor layer is composed of a plurality of layers, even when a part of the semiconductor layer is etched during the n + layer etching, another semiconductor layer is present thereon. Not only does the interface property between the layer and the insulating layer deteriorate, but a certain channel can be secured.
더욱이, 제조 방법에서도 소스/드레인전극 형성용 마스크, 게이트전극 형성용 마스크, 화소전극 에칭용 마스크 등 총 3개의 마스크가 필요하게 되어 종래의 방법에 비해 공정이 간단하게 되며, 따라서, 제조비용이 크게 절감된다.Furthermore, in the manufacturing method, three masks are required, namely, a source / drain electrode forming mask, a gate electrode forming mask, and a pixel electrode etching mask, thereby simplifying the process compared to the conventional method, and thus, manufacturing cost is large. Savings.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019960030563A KR100202224B1 (en) | 1996-07-26 | 1996-07-26 | Thin film transistors and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960030563A KR100202224B1 (en) | 1996-07-26 | 1996-07-26 | Thin film transistors and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980012634A KR980012634A (en) | 1998-04-30 |
| KR100202224B1 true KR100202224B1 (en) | 1999-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960030563A KR100202224B1 (en) | 1996-07-26 | 1996-07-26 | Thin film transistors and manufacturing method thereof |
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| Country | Link |
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| KR (1) | KR100202224B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100705615B1 (en) * | 2000-12-30 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for fabricating tft lcd |
| KR101503310B1 (en) * | 2008-09-17 | 2015-03-17 | 엘지디스플레이 주식회사 | Method of fabricating thin film transistor |
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1996
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| Publication number | Publication date |
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| KR980012634A (en) | 1998-04-30 |
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