KR101034715B1 - Thin Film Transistor of Poly-type And Method of Fabricating The Same - Google Patents

Abstract

The present invention provides a poly-type TFT substrate and a method for manufacturing the same, which can simplify the manufacturing process while increasing the capacity of the storage capacitor without reducing the aperture ratio.

To this end, the poly-type TFT substrate of the present invention includes a pixel electrode formed in a pixel region defined by the intersection of a gate line and a data line in an image display unit, and a first thin film transistor connected between the gate line and the data line and the pixel electrode; A second thin film transistor formed on the driving circuit and having the same polarity as the first thin film transistor; A third thin film transistor formed in the driving circuit part and having a polarity opposite to that of the second thin film transistor; A storage line across the pixel electrode; And a storage lower electrode formed of a transparent conductive material covering the storage line and overlapping the pixel electrode with an insulating layer therebetween to form a storage capacitor.

Description

Thin Film Transistor of Poly-type And Method of Fabricating The Same             

1 is a view schematically showing a liquid crystal display panel using a conventional poly-silicon.

FIG. 2 is a plan view partially illustrating a thin film transistor substrate included in the liquid crystal display panel illustrated in FIG. 1.

3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′ and II-II ′.

4A to 4I are cross-sectional views for explaining a method of manufacturing the thin film transistor substrate illustrated in FIG. 3 step by step.

5 is a plan view partially showing a thin film transistor substrate using poly-silicon according to an embodiment of the present invention.

6 is a cross-sectional view of the thin film transistor substrate of FIG. 5 taken along lines III-III ', IV-IV', and V-V '.

7A and 7B are plan and cross-sectional views illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.                 

8A and 8B are plan and cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

9A and 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

10A and 10B are plan and cross-sectional views illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

11A and 11B are plan and cross-sectional views illustrating a fifth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

12A and 12B are a plan view and a sectional view for explaining a sixth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

13A and 13B are plan and cross-sectional views illustrating a seventh mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

14A and 14B are plan and cross-sectional views illustrating an eighth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

<Description of Main Parts of Drawing>

1, 101: substrate 2, 102: gate line

4, 104: data lines 6, 66, 106, 136, 166: gate electrodes

8, 38, 68, 108, 138, 168: source electrode

10, 40, 70, 110, 140, 170: drain electrode

12, 112: gate insulating film                 

14, 44, 50, 74, 114, 144, 174: active layer

16, 116: buffer film 18, 118: protective film

22, 122: pixel electrodes 26, 126: interlayer insulating film

30, 130, 90, 190: thin film transistor 60, 160: storage capacitor

150: storage lower electrode 92, 192: data driver

94, 194: gate driver 96, 196: image display unit

200: pad lower electrode 202: pad upper electrode

208: Link 210: Pad

212: pad portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate of a liquid crystal display panel using poly-silicon, and more particularly, to a poly type thin film transistor substrate and a method of manufacturing the same, which can simplify the manufacturing process without reducing the aperture ratio.

In general, a liquid crystal display (LCD) displays an image by allowing each of the liquid crystal cells arranged in a matrix form on a liquid crystal panel to adjust light transmittance according to a video signal.

Each liquid crystal cell uses a thin film transistor (TFT) as a switching element for independently supplying a video signal. Amorphous-Si or Poly-Si is used as the active layer of such a TFT. Here, in the case of using poly-silicon, as the charge mobility is about 100 times faster than that of amorphous-silicon, a driving circuit requiring a high response speed may be embedded in the liquid crystal panel.

1 schematically shows a liquid crystal panel using a conventional poly-TFT.

The liquid crystal panel illustrated in FIG. 1 includes an image display unit 96 including a liquid crystal cell matrix, a data driver 92 for driving the data line 4 of the image display unit 96, and a gate line of the image display unit 96. And a gate driver 94 for driving 2).

In the image display unit 96, liquid crystal cells LC are arranged in a matrix to display an image. Each of the liquid crystal cells LC includes a TFT 30 connected to a gate line 2 and a data line 4. The TFT 30 charges the liquid crystal cell LC with the video signal from the data line 4 in response to the scan signal of the gate line 2. In the liquid crystal cell LC, a liquid crystal having dielectric anisotropy reacts by a charged video signal to control grayscale.

The gate driver 94 drives the gate line 2 sequentially.

The data driver 92 supplies a video signal to the data line 4 every time the gate line 2 is driven.

The liquid crystal panel includes a TFT substrate on which the data driver 92 and the gate driver 94 are formed together with the TFT 30 of the liquid crystal cell LC, and a color filter substrate on which the common electrode and the color filter are formed, with the liquid crystal interposed therebetween. It is formed by bonding.

FIG. 2 is a plan view partially illustrating a structure of a TFT substrate included in the liquid crystal panel illustrated in FIG. 1, and FIG. 3 is a cross-sectional view of the TFT substrate illustrated in FIG. 1 along lines II ′ and II-II ′. It is sectional drawing.

The image display portion 96 of the TFT substrate shown in FIGS. 2 and 3 includes a TFT 30 connected to the gate line 2 and a data line 4, a pixel electrode 22 connected to the TFT 30, and A storage capacitor 60 is provided. The TFT 30 is formed of an N type or a P type, but only a case where the TFT 30 is formed of an N type will be described below.

The gate driver 94 and data driver 92 include a P-type TFT 90 and a driving N-type TFT 80 connected in a CMOS structure.

The N-type TFT 30 of the image display unit 96 charges the pixel electrode 22 with the video signal. To this end, the N-type TFT 30 penetrates through the gate electrode 6 connected to the gate line 2, the source electrode 8 connected to the data line 4, the pixel electrode 22 and the protective film 18. A drain electrode 10 connected through the pixel contact hole 20 is provided. The gate electrode 6 is formed to overlap the channel region 14C of the first active layer 14 formed on the buffer film 16 with the gate insulating film 12 interposed therebetween. The source electrode 8 and the drain electrode 10 are formed to be insulated with the gate electrode 6 and the interlayer insulating film 26 therebetween. The source electrode 8 and the drain electrode 10 are formed of n + impurity implanted through each of the source contact hole 24S and the drain contact hole 24D passing through the interlayer insulating film 26 and the gate insulating film 12. 1 is connected to each of the source region 14S and the drain region 14D of the active layer 14. In addition, the first active layer 14 has an LDD region in which n- impurity is injected between the channel region 14C and the source and drain regions 14S and 14D to reduce the off current. (Not shown) may be further provided.

The storage capacitor 60 keeps the video signal charged in the pixel electrode 22 stable. To this end, the storage capacitor 60 includes a storage line 52 crossing the pixel electrode 22 and a second active layer extending from the active layer 14 of the N-type TFT 30 to serve as a lower storage electrode. 50 is formed to overlap with the gate insulating film 12 therebetween.

The P-type TFT 90 included in the gate driver 94 and the data driver 92 is formed on the lower substrate 1 with the buffer film 16 interposed therebetween, so as to implant the p-type impurity into the active layer 74, The third active layer through the gate electrode 66, the source contact hole 84S, and the drain contact hole 84D overlapping the channel region 74C of the third active layer 74 with the gate insulating layer 12 therebetween. A source electrode 68 and a drain electrode 70 connected to each of the source region 74S and the drain region 74D of 74 are provided.

The second N-type TFT 80 included in the gate driver 94 and the data driver 92 has a fourth active layer interposed between the fourth active layer 44 and the gate insulating layer 12 into which n impurities are injected. The source region 44S and the drain region of the fourth active layer 44 through the gate electrode 36, the source contact hole 54S and the drain contact hole 54D overlapping the channel region 44C of the layer 44. A source electrode 38 and a drain electrode 40 connected to each of 44D are provided.

Such a poly-type TFT substrate is formed by a nine mask process as shown in Figs. 4A to 4I. Here, since the second N-type TFT 80 included in the gate driver 94 and the data driver 92 is formed at the same time as the N-type TFT 30 of the image display unit 96, it will be omitted.

Referring to FIG. 4A, a buffer layer 16 is formed on the lower substrate 1, and first to third active layers 14, 50, and 74 are formed on the lower substrate 1 by a first mask process.

The buffer layer 16 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 1.

The first to third active layers 14, 50, and 74 are amorphous silicon-silicon deposited on the buffer layer 16, and then crystallized with a laser to become poly-silicon, followed by a photolithography process using a first mask. It is formed by patterning with an etching process.

Referring to FIG. 4B, n impurity is implanted into the second active layer 50 only by the second mask process to serve as a lower storage electrode.

Specifically, after forming a photoresist pattern exposing only the second active layer 50 by a photolithography process using a second mask, implanting n impurity such as PH _{3 into} only the exposed second active layer 50, and then The resist pattern is removed.

Referring to FIG. 4C, the gate insulating layer 12 is formed on the buffer layer 16 on which the active layers 14, 50, and 74 are formed, and the gate electrodes 6 and 66 are formed thereon in a third mask process. The gate pattern and the storage line 52 are formed.

The gate insulating layer 12 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 16 on which the active layers 14, 50, and 74 are formed.

The gate pattern including the gate electrodes 6 and 66 and the gate line 2 and the storage line 52 form a gate metal layer on the gate insulating layer 12, and then photolithography and etching using a third mask. It is formed by patterning in the process. As the gate metal, an aluminum-based metal containing aluminum (Al), aluminum / nedium (Al / Nd), or the like is mainly used.

In addition, n− impurities are implanted into the first and third active layers 14 and 74 using the gate electrodes 6 and 66 as masks to form LDD regions not overlapped with the gate electrodes 6 and 66.

Referring to FIG. 4D, the source region 14S and the drain region 14D of the first active layer 14 are formed by implanting n + impurities into the first active layer 14 by a fourth mask process.

Specifically, a photoresist pattern exposing only the source region 14S and the drain region 14D of the first active layer 14 is formed by a photolithography process using a fourth mask. After the n + impurity is implanted into the exposed source region 14S and the drain region 14D, the photoresist pattern is removed. The source and drain regions 14S and 14D of the first active layer 14 face each other with the channel region 14C overlapping the gate electrode 6 interposed therebetween.

Referring to FIG. 4E, the source region 74S and the drain region 74D of the third active layer 74 are formed by implanting p + impurities into the third active layer 74 by a fifth mask process.

Specifically, a photoresist pattern exposing only the source region 74S and the drain region 74D of the third active layer 74 is formed by a photolithography process using a fifth mask. After the p + impurity is implanted into the exposed source region 74S and the drain region 74D of the third active layer 74, the photoresist pattern is removed. The source and drain regions 74S and 74D of the third active layer 74 face each other with the channel region 74C overlapping the gate electrode 66 interposed therebetween.

Referring to FIG. 4F, an interlayer insulating layer 26 is formed on the gate insulating layer 12 on which the gate pattern and the storage line 52 are formed, and the source and drain contact holes 24S, 24D, 84S, 84D) are formed.

The interlayer insulating layer 26 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 12 on which the gate pattern and the storage line 52 are formed.

Subsequently, the source and drain regions 14S and 14D of the first active layer 14 and the third active layer penetrate the interlayer insulating layer 26 and the gate insulating layer 12 by a photolithography process and an etching process using a sixth mask. Source and drain contact holes 24S, 24D, 84S, and 84D are formed to expose the source and drain regions 74S and 74D of the layer 74, respectively.

Referring to FIG. 4G, a source / drain pattern including a data line 94 is formed on the interlayer insulating layer 26 along with the source and drain electrodes 8, 10, 68, and 70 on the interlayer insulating layer 26 by a seventh mask process. The TFT 30 and the P-type TFT 90 are completed.

The source / drain pattern includes a data line 4 together with the source and drain electrodes 8 and 10 of the N-type TFT 30 and the source and drain electrodes 68 and 70 of the P-type TFT 90. The source / drain pattern is formed by forming a source / drain metal layer on the interlayer insulating layer 26 and then patterning the photo / lithography process and etching process using a seventh mask. At this time, the source and drain electrodes 8 and 10 of the N-type TFT 30 are respectively source and drain regions 14S and 14D of the first active layer 14 through the source and drain contact holes 24S and 24D. ) Is connected to each. The source and drain electrodes 68 and 70 of the P-type TFT 90 respectively have a source region 74S and a drain region 74D of the third active layer 74 through the source and drain contact holes 84S and 84D, respectively. Connected with.

Referring to FIG. 4H, the passivation layer 18 is formed on the interlayer insulating layer 26 on which the source / drain patterns are formed, and the pixel contact hole 20 penetrating the passivation layer 18 is formed by an eighth mask process.

The passivation layer 18 is formed by depositing an inorganic insulating material or an organic insulating material on the interlayer insulating film 26 on which the source / drain patterns are formed.

Subsequently, a pixel contact hole 20 is formed through the protective film 18 to expose the drain electrode 10 of the N-type TFT 30 of the image display part 96 by a photolithography process and an etching process using an eighth mask. do.

Referring to FIG. 4I, a pixel electrode 22 is formed on the passivation layer 18 by a ninth mask process.

The pixel electrode 22 is formed by depositing a transparent conductive material on the passivation layer 18, and then patterning the photoresist and etching processes using a ninth mask. The pixel electrode 22 is connected to the drain electrode 10 of the N-type TFT 30 of the image display unit 96 through the pixel contact hole 20.

As described above, the second active layer 50 doped with impurities to the lower storage electrode of the conventional poly-type TFT substrate is suitable for line inversion driving requiring fast response speed by alternating current driving of the common voltage Vcom. However, since the impurity doping of the second active layer 50 must be performed through a separate mask process, the manufacturing process becomes complicated. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like.

In order to solve this problem, instead of forming the storage capacitor 60 by overlapping the second active layer 50 and the storage line 52 as described above, a method of forming the storage line and the source / drain metal layer by overlapping with each other has been considered. . Such a TFT substrate is reduced in one mask process for doping the second active layer 50, but has a limitation in increasing the capacity of the storage capacitor as the aperture ratio decreases due to the source / drain metal layer serving as the storage electrode. In addition, a method of increasing the aperture ratio by overlapping the pixel electrode 22 and the data line 4 by using an organic insulating material as the passivation layer 18 has been proposed, but due to the organic insulating material having a relatively high unit cost, There is a disadvantage that rises.

Accordingly, it is an object of the present invention to provide a poly-type TFT substrate and a method of manufacturing the same, which can simplify the manufacturing process while increasing the capacity of the storage capacitor without reducing the aperture ratio.                         

Another object of the present invention is to provide a poly-type TFT substrate capable of increasing the aperture ratio without using an expensive organic insulating material and a manufacturing method thereof.

In order to achieve the above object, a poly-type TFT substrate according to the present invention includes a substrate on which an image display portion, a gate driver, a data driver, a pad portion are to be formed; A pixel electrode formed in the pixel region defined by the intersection of the gate line and the data line in the image display section, and a first thin film transistor connected between the gate line and the data line and the pixel electrode; A second thin film transistor formed on the gate driver and the data driver and having the same polarity as the first thin film transistor; A third thin film transistor formed in the gate driver and the data driver and having a polarity opposite to that of the second thin film transistor; A storage line across the pixel electrode; And a storage lower electrode formed of a transparent conductive material covering the storage line of the pixel region, and overlapping the pixel electrode with an insulating layer therebetween to form a storage capacitor.

The first thin film transistor may include a first active layer including a source region and a drain region doped with impurities, a first gate electrode partially overlapping the first active layer with a gate insulating layer interposed therebetween, and connected to the gate line; A source electrode of the first active layer and a source electrode connected to the data line, the gate insulating layer, the interlayer insulating layer, and the protective layer through the gate insulating layer, a first source contact hole penetrating through the interlayer insulating layer and the protective layer stacked thereon; And a drain electrode connected to the drain region of the first active layer through a first drain contact hole therethrough and connected to the pixel electrode through a pixel contact hole penetrating through the passivation layer.

The storage lower electrode overlaps the pixel electrode with the interlayer insulating layer interposed therebetween.

Further, the TFT substrate of the present invention further includes a pad connected to the gate driver or the data driver via a link; The pad may include a pad lower electrode connected to the link; And a pad upper electrode formed on the pad lower electrode and exposed through a first contact hole penetrating the interlayer insulating layer and the passivation layer.

The pad lower electrode is formed on the gate insulating layer, the link is formed on the passivation layer, and the link is connected to the pad lower electrode through the second contact hole penetrating through the interlayer insulating layer and the passivation layer.

The method for manufacturing a poly-type TFT substrate according to the present invention includes the steps of: preparing a substrate on which an image display unit, a gate driver, a data driver, and a pad unit are to be formed; Forming a poly type first active layer on the image display portion of the substrate; Forming a gate insulating film covering the active layer, and forming a first gate electrode, a gate line, and a storage line on the gate insulating film; Forming a storage lower electrode of a transparent conductive material covering the storage line; Forming an interlayer insulating layer covering the storage lower electrode, and forming a pixel electrode on the interlayer insulating layer to overlap the storage lower electrode; Forming a passivation layer covering the pixel electrode, forming a first source and drain contact hole exposing the source and drain regions of the first active layer, and a pixel contact hole exposing the pixel electrode; Forming a first source electrode connected to the source region of the first active layer, a first drain electrode connected to the drain region and the pixel electrode, and a data line connected to the first source electrode.

In addition, the manufacturing method of the present invention comprises the steps of forming the second and third active layers in the gate driver and the data driver of the substrate; Forming second and third gate electrodes on the gate insulating film; Forming second source and drain contact holes, third source and drain contact holes through the gate insulating film, the interlayer insulating film, and the protective film to expose source and drain regions of the second and third active layers, respectively; Forming a second source and drain electrode connected to each of the source and drain regions of the second active layer, and a third source and drain electrode connected to each of the source and drain regions of the third active layer on the passivation layer. It includes.

Doping the source and drain regions of the first and second active layers with impurities of the same polarity; Doping the source region and the drain region of the third active layer with impurities of different polarities.

Forming a pad lower electrode on the gate insulating film of the pad part; Forming a pad upper electrode on the pad lower electrode with the transparent conductive material; Exposing each of the pad upper electrode and the pad lower electrode through first and second contact holes penetrating the interlayer insulating layer and the passivation layer; And forming a link connected to the pad lower electrode on the passivation layer.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.                     

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 14B.

5 is a plan view partially illustrating a poly-type TFT substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a line along the III-III ', IV-IV', and V-V 'lines of the TFT substrate shown in FIG. It is sectional drawing cut out.

5 and 6 show an image display unit 196 including a liquid crystal cell matrix, a data driver 192 for driving a data line 104 of the image display unit 196, and an image display unit 196. A gate driver 194 for driving the gate line 102 of the () and a pad unit 212 to which the FPC (Flexible Printed Circuit) is attached.

The image display unit 196 includes a TFT 130 connected with the gate line 102 and the data line 104, a pixel electrode 122 connected with the TFT 130, and a storage capacitor 160. The TFT 130 is formed of an N type or a P type, but only a case where the TFT 130 is formed of an N type will be described below.

The gate driver 194 and the data driver 192 include a P-type TFT 190 and a driving N-type TFT 180 connected in a CMOS structure.

The N-type TFT 130 of the image display unit 196 charges the video signal to the pixel electrode 122. To this end, the N-type TFT 130 of the image display unit 196 includes a first gate electrode 106 connected to the gate line 102, a first source electrode 108 connected to the data line 104, and a pixel electrode. A first drain electrode 110 connected through the pixel contact hole 120 penetrating through the 122 and the passivation layer 118 is provided. The first gate electrode 106 is formed to overlap the channel region 114C of the first active layer 114 formed on the buffer layer 116 and the gate insulating layer 112 therebetween. The first source electrode 108 and the first drain electrode 110 are formed to be insulated from each other with the first gate electrode 106 and the interlayer insulating layer 126 therebetween. The first source electrode 108 and the first drain electrode 110 are respectively formed of the first source contact hole 124S and the first drain contact hole 124D that pass through the interlayer insulating layer 126 and the gate insulating layer 112. The n + impurity is connected to each of the source region 114S and the drain region 114D through which the n + impurity is implanted. In addition, the first active layer 114 has a lightly doped drain (LDD) region in which n- impurity is injected between the channel region 114C and the source and drain regions 114S and 114D to reduce the off current. (Not shown) may be further provided.

The storage capacitor 160 keeps the video signal charged in the pixel electrode 122 stable. To this end, the storage capacitor 160 overlaps the storage lower electrode 121 connected to the storage line 150 crossing the pixel electrode 122, and the pixel electrode 122 overlaps the interlayer insulating layer 126 therebetween. Is formed. Here, the overlapping area of the storage lower electrode 121 and the pixel electrode 122 is enlarged to increase the storage capacitor capacity. In this case, since the lower storage electrode 121 is formed of a transparent conductive material like the pixel electrode 122, the opening ratio decrease due to the increase of the capacity of the storage capacitor 160 can be prevented. In addition, the storage line 150 is formed of a gate metal layer together with the gate line 102 to increase conductivity.

The N-type TFT 180 included in the gate driver 194 and the data driver 192 has a second active layer 144 with the second active layer 144 implanted with n impurities and the gate insulating layer 112 interposed therebetween. Source region 144S of second active layer 144 through second gate electrode 136, second source contact hole 154S and second drain contact hole 154D overlapping channel region 144C of FIG. And a second source electrode 138 and a second drain electrode 140 connected to each of the drain regions 144D.

In addition, the P-type TFT 190 included in the gate driver 194 and the data driver 192 is formed on the lower substrate 101 with the buffer layer 116 interposed therebetween, and the third active layer implanted with p impurities. 174, the third gate electrode 166, the third source contact hole 184S and the third drain contact overlapping the channel region 174C of the third active layer 174 with the gate insulating layer 112 interposed therebetween. The third source electrode 168 and the third drain electrode 170 are connected to the source region 174S and the drain region 174D of the third active layer 174 through the hole 184D.

The pad 210 formed on the pad part 212 may be formed on the pad lower electrode 200 formed on the gate insulating layer 112 and on the pad lower electrode 200 to pass through the passivation layer 118 and the interlayer insulating layer 126. And a pad upper electrode 202 to be exposed through the first contact hole 204 and to be in contact with the output pad of the FPC. The pad lower electrode 200 is formed of a gate metal, and the pad upper electrode 202 is formed of a transparent conductive material. Here, the pad lower electrode 200 is connected to the link 208 formed of the source / drain metal through the second contact hole 206 penetrating through the passivation layer 118 and the interlayer insulating layer 126. The link 208 is connected with the data driver 192 or the gate driver 194.

The poly-type TFT substrate of the present invention having such a configuration is formed by an eight mask process as shown in Figs. 7A to 14B. Here, since the N-type TFT 180 included in the gate driver 194 and the data driver 192 is formed at the same time as the N-type TFT 130 of the image display unit 196, its cross-sectional structure will be omitted.

7A and 7B, a buffer layer 116 is formed on the lower substrate 101, and first to third active layers 114, 144, and 174 are formed on the lower substrate 101 by a first mask process.

The buffer layer 116 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101.

The first to third active layers 114, 144, and 174 are deposited on the buffer layer 116 and then crystallized by laser to become poly-silicon, followed by a photolithography process using a first mask. It is formed by patterning in an etching process.

8A and 8B, the gate insulating layer 112 is formed on the buffer layer 116 on which the first to third active layers 114, 144, and 174 are formed in the second mask process, and the second insulating layer is formed thereon. The gate pattern including the first to third gate electrodes 106, 136, and 166 and the gate line 102, the storage line 150, and the pad lower electrode 200 are formed by a mask process.

The gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 116 on which the first to third active layers 114, 144, and 174 are formed.

The gate pattern including the first to third gate electrodes 106, 136, and 166 and the gate line 102, and the storage line 150 and the pad lower electrode 200 form a gate metal layer on the gate insulating layer 112. After forming, it is formed by patterning in a photolithography process and an etching process using a third mask. As the gate metal, an aluminum-based metal containing aluminum (Al), aluminum / nedium (Al / Nd), or the like is mainly used.

In addition, n- impurity is implanted into the first to third active layers 114, 144, and 174 using the first to third gate electrodes 106, 136, and 166 as a mask to form the first to third gate electrodes ( 106, 136, and 166 to form non-overlapping LDD regions, respectively.

9A and 9B, a lower storage electrode 121 and a pad upper electrode 202 are formed to cover the storage line 150 in each pixel area by a third mask process.

The storage lower electrode 121 and the pad upper electrode 202 are formed by depositing a transparent conductive material and then patterning the photolithography and etching processes using a third mask.

10A and 10B, source regions 114S of the first and second active layers 114 and 144 may be implanted by implanting n + impurities into the first and second active layers 114 and 144 using a fourth mask process. 144S and drain regions 114D and 144D are formed.

Specifically, a photoresist pattern exposing only the source regions 114S and 144S and the drain regions 114D and 144D of the first and second active layers 114 and 144 is formed by a photolithography process using a fourth mask. After the n + impurity is implanted into the exposed source regions 114S and 144S and the drain regions 114D and 144D of the first and second active layers 114 and 144, the photoresist pattern is removed. The source and drain regions 114S, 114D, 144S, and 144D of the first and second active layers 114 and 144 overlap the channel regions 114C and 144C respectively overlapping the first and second gate electrodes 106 and 136. Faced with).

11A and 11B, a p + impurity is implanted into the third active layer 174 by a fifth mask process to form a source region 174S and a drain region 174D of the third active layer 174.

Specifically, a photoresist pattern exposing only the source region 174S and the drain region 174D of the third active layer 174 is formed by a photolithography process using a fifth mask. After the p + impurity is implanted into the exposed source region 174S and the drain region 174D of the third active layer 174, the photoresist pattern is removed. The source and drain regions 174S and 174D of the third active layer 174 face each other with the channel region 174C overlapping with the third gate electrode 166.

12A and 12B, an interlayer insulating layer 126 is formed on a gate insulating layer 112 on which a gate pattern and a storage lower electrode 121 are formed, and a pixel electrode 122 is formed thereon by a sixth mask process. do.

The interlayer insulating layer 126 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 on which the gate pattern and the storage lower electrode 121 are formed.

The pixel electrode 122 is formed independently of each pixel area by depositing a transparent conductive material and then patterning the same by a photolithography process and an etching process using a sixth mask.

13A and 13B, the passivation layer 118 is formed on the interlayer insulating layer 126 on which the pixel electrode 122 is formed, and the first to third source and drain contact holes 124S, 124D, 154S, 154D, 184S, and 184D, and pixel contact holes 120 and first and second contact holes 204 and 206 of the pad portion 212 are formed.

The passivation layer 118 is formed by depositing an inorganic insulating material or an organic insulating material on the interlayer insulating film 126 on which the pixel electrode 122 is formed.

Subsequently, the first to third source and drain contact holes 124S, 124D, 154S, 154D, 184S, and 184D and the first and second pad portions 212 may be formed by a photolithography process and an etching process using a seventh mask. 2 contact holes 204 and 206 are formed. Here, the first to third source and drain contact holes 124S, 124D, 154S, 154D, 184S, and 184D pass through the passivation layer 118, the interlayer insulating layer 126, and the gate insulating layer 112 to form the first to third sources. The source regions 114S, 144S, and 174S and the drain regions 114D, 144D, and 174D of the active layers 114, 144, and 174 are exposed. The pixel contact hole 120 penetrates the passivation layer 118 to expose the pixel electrode 122. The first and second contact holes 204 and 206 of the pad part 121 pass through the passivation layer 118 and the interlayer insulating layer 126 to expose the pad upper electrode 202 and the pad lower electrode 200, respectively. .

14A and 14B, the data line 104 and the first to third source and drain electrodes 108, 110, 138, 140, 168, and 170 may be formed on the passivation layer 118 by a seventh mask process. The N-type TFTs 130 and 180 and the P-type TFT 190 are completed by forming the source / drain pattern including the link 208.

First and second source electrodes 108 and 110 of the N-type TFTs 130 and 180, first and second drain electrodes 138 and 140, and third source and drain electrodes of the P-type TFT 190 ( The source / drain pattern including the 168 and 170, the data line 104, and the link 208 may be formed by forming a source / drain metal layer on the passivation layer 118, and then performing a photolithography and etching process using an eighth mask. It is formed by patterning. The first source and drain electrodes 108 and 110 are connected to each of the source region 114S and the drain region 114D of the first active layer 114 through the first source and drain contact holes 124S and 124D, respectively. . In addition, the first drain electrode 110 is connected to the pixel electrode 122 through the pixel contact hole 120. The second source and drain electrodes 138 and 140 are connected to each of the source regions 144S and 144D of the second active layer 144 through the second source and drain contact holes 154S and 154D, respectively. The third source and drain electrodes 168 and 170 are connected to each of the source region 174S and the drain region 174D of the third active layer 174 through the third source and drain contact holes 184S and 184D, respectively. . The pad upper electrode 202 is exposed through the first contact hole 204 to be in contact with the output pad of the FPC, and the link 208 is connected to the pad lower electrode 200 through the second contact hole 206. do.

As described above, the poly-type TFT substrate and the method of manufacturing the same according to the present invention form a storage capacitor by overlapping a storage lower electrode made of a transparent conductive material and a pixel electrode so that the capacity of the storage capacitor can be increased without decreasing the aperture ratio. do. Accordingly, the aperture ratio can be sufficiently secured without using an expensive organic insulating material, thereby reducing the manufacturing cost.

In addition, the poly-type TFT substrate and the method of manufacturing the same according to the present invention can reduce the one mask process for the doping of the active layer, which is the lower storage electrode as in the prior art, by using a transparent conductive material as the lower storage electrode. . As a result, the manufacturing process can be simplified.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A substrate on which an image display portion, a gate driver, a data driver, and a pad portion are formed; A pixel electrode formed in the pixel region defined by the intersection of the gate line and the data line in the image display unit; A first thin film transistor connected between the gate line and the data line and a pixel electrode; A second thin film transistor formed in the gate driver and the data driver and having the same polarity as the first thin film transistor; A third thin film transistor formed in the gate driver and the data driver and having a polarity opposite to that of the second thin film transistor; A storage line across the pixel electrode; And a lower storage electrode formed of a transparent conductive material covering the storage line of the pixel region, wherein the lower storage electrode overlaps the pixel electrode and the insulating layer therebetween to form a storage capacitor. The method of claim 1, The first thin film transistor is A first active layer including a source region and a drain region doped with impurities, A first gate electrode partially overlapping the first active layer with a gate insulating layer interposed therebetween and connected to the gate line; A source electrode connected to the source region and the data line of the first active layer through a first source contact hole penetrating through the gate insulating layer, the interlayer insulating layer and the protective layer stacked thereon; A drain electrode connected to the drain region of the first active layer through a first drain contact hole penetrating the gate insulating film, an interlayer insulating film, and a protective film, and connected to the pixel electrode through a pixel contact hole penetrating the protective film; A poly-type thin film transistor substrate, characterized in that. The method of claim 2, And the storage lower electrode overlaps the pixel electrode with the interlayer insulating layer interposed therebetween. The method of claim 2, Further comprising a pad connected via a link with said gate driver or said data driver; The pad A pad lower electrode connected to the link; And a pad upper electrode formed on the pad lower electrode and exposed through the first contact hole penetrating the interlayer insulating layer and the passivation layer. The method of claim 4, wherein The pad lower electrode is formed on the gate insulating layer, and the link is formed on the passivation layer. And the link is connected to the pad lower electrode through a second contact hole penetrating through the interlayer insulating layer and the passivation layer. Providing a substrate on which an image display unit, a gate driver, a data driver, and a pad unit are to be formed; Forming a poly type first active layer on the image display portion of the substrate; Forming a gate insulating film covering the active layer, and forming a first gate electrode, a gate line, and a storage line on the gate insulating film; Forming a lower storage electrode of a transparent conductive material covering the storage line of the pixel region; Forming an interlayer insulating layer covering the storage lower electrode, and forming a pixel electrode on the interlayer insulating layer to overlap the storage lower electrode; Forming a passivation layer covering the pixel electrode, forming a first source and drain contact hole exposing the source and drain regions of the first active layer, and a pixel contact hole exposing the pixel electrode; And forming a first source electrode connected to the source region of the first active layer, a first drain electrode connected to the drain region and the pixel electrode, and a data line connected to the first source electrode. A method of manufacturing a poly-type thin film transistor substrate. The method of claim 6, Forming second and third active layers on the gate driver and the data driver of the substrate; Forming second and third gate electrodes on the gate insulating film; Forming second source and drain contact holes, third source and drain contact holes through the gate insulating film, the interlayer insulating film, and the protective film to expose source and drain regions of the second and third active layers, respectively; Forming a second source and drain electrode connected to each of the source and drain regions of the second active layer, and a third source and drain electrode connected to each of the source and drain regions of the third active layer on the passivation layer. Method for producing a poly-type thin film transistor substrate comprising a. The method of claim 7, wherein Doping the source and drain regions of the first and second active layers with impurities of the same polarity; And doping the source region and the drain region of the third active layer with impurities of different polarities. The method of claim 7, wherein Forming a pad lower electrode on the gate insulating film of the pad part; Forming a pad upper electrode on the pad lower electrode with the transparent conductive material; Exposing each of the pad upper electrode and the pad lower electrode through first and second contact holes penetrating the interlayer insulating layer and the passivation layer; And forming a link connected to the pad lower electrode on the passivation layer.

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