KR20070080470A - Thin film transistor substrate and method for producing the same and liquid crystal display having the thin film transistor substrate - Google Patents

Abstract

A thin film transistor substrate, a method for manufacturing the same, and an LCD(Liquid Crystal Display) comprising the same are provided to reduce the variance in coupling capacitance between a gate line and a pixel electrode, by forming a shielding line on a gate line and connecting the gate line to the shielding line through a contact hole. A plurality of gate line groups are formed in one direction on a substrate. A plurality of data lines cross the gate line groups. A plurality of pixel groups(I,II) are formed at the crossing portions of the gate line groups and the data lines. A plurality of shielding lines(390) are formed on the gate line groups to reduce the variance in coupling capacitance between the pixel group and the gate line group. Each of the gate line groups is composed of a plurality of gate lines, and each of the pixel groups is composed of a plurality of unit pixels. The shielding lines are electrically connected to the gate line groups through contact holes(400).

Description

A thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display including the same {THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR PRODUCING THE SAME AND LIQUID CRYSTAL Display

1 is a schematic plan view of a liquid crystal display according to the related art.

2 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

3 is a schematic cross-sectional view taken along line AA ′ of the thin film transistor substrate illustrated in FIG. 2.

4 is a schematic layout diagram of the thin film transistor substrate illustrated in FIG. 2.

5A to 5E are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

6 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

7 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

380; The pixel electrode 390; Shielding line

400; Contact

A thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display device including the same, and more particularly, a thin film transistor substrate having a structure for reducing variation in coupling capacitance between a gate line and a pixel electrode between unit pixels, and a method of manufacturing the same. And a liquid crystal display including the same.

The liquid crystal display device has advantages of small size, light weight, and large screen compared with the conventional CRT (Cathode Ray Tube), and its development is being actively conducted. The monitor, large display device, It is also used in a display device of a mobile communication terminal, and its use range is rapidly expanding. Such a liquid crystal display device has a light transmittance adjusted according to an image signal applied to a plurality of control switches arranged in a matrix form. The desired image is displayed on the panel.

Recently, an amorphous silicon thin film transistor liquid crystal display device includes a gate driving IC and a source driving IC in a tape carrier package (TCP) or a chip on glass (COG) method. On the other hand, in the case of the gate driving IC, research is being conducted in order to integrate on a substrate in consideration of cost, simplification of the module process, and mechanism design, and to reduce the number as much as possible for the source driving IC.

FIG. 1 shows a schematic plan view of a liquid crystal display according to the prior art, wherein the liquid crystal display of FIG. 1 reduces the source driver IC to half, instead of doubling the gate line, thereby integrating the gate driver IC to the substrate. It is an integrated structure. That is, in the liquid crystal display device, instead of using the same data line between the left and right unit pixels, gate lines are formed on the upper and lower portions of the unit pixels, respectively, to drive the respective unit pixels.

However, even in adjacent unit pixels using the same data line, the gate line driving them is formed at the top or the bottom. As a result, even if the same data voltage is applied between adjacent unit pixels, each unit pixel causes variation in coupling capacitance between the gate line and the pixel electrode of the unit pixel, resulting in a voltage difference, resulting in display defects. Will occur.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-described problems, and a technical problem to be solved by the present invention is to fabricate a thin film transistor substrate having a structure for reducing variation in coupling capacitance between a gate line and a pixel electrode between unit pixels. A method and a liquid crystal display including the same are provided.

According to an aspect of the present invention for achieving the object of the present invention, a plurality of gate line groups formed in one direction on the substrate, a plurality of data lines formed to be insulated and crossed with the plurality of gate line groups, A plurality of pixel groups formed at intersections of a plurality of gate line groups and a plurality of data lines, and a plurality of pixel groups formed on the plurality of gate line groups to reduce variation in coupling capacitance between the plurality of pixel groups and the gate line group. A plurality of shielding lines, each gate line group is composed of a plurality of gate lines, each pixel group is composed of a plurality of unit pixels, the plurality of shielding lines are the plurality of gate lines through a contact hole A thin film transistor substrate is provided that is electrically connected with a group.

Each gate line group includes a first gate line and a second gate line formed to be spaced apart from the first gate line by a predetermined distance, and each pixel group includes a first unit pixel and a second unit pixel.

The first unit pixel and the second unit pixel are connected to different gate lines and to the same data line.

Each pixel group includes a pixel electrode, a thin film transistor, and a storage capacitor electrode, and each shielding line is formed of the same material as the pixel electrode.

Each shielding line is formed in parallel with the gate line.

Each shielding line is formed separately for each unit pixel.

Gate voltages applied to the plurality of gate line groups are applied to the plurality of shielding lines.

The pixel electrode is formed with at least one incision pattern for forming multiple domains.

According to another aspect of the present invention, a plurality of gate line groups formed in one direction on a substrate, a plurality of data lines formed to be insulated from and intersected with the plurality of gate line groups, and the plurality of gate line groups and a plurality of gate lines And a plurality of shielding lines formed on the plurality of gate line groups so as to reduce a variation in coupling capacitance between the plurality of pixel groups and the plurality of pixel groups and the gate line group formed in an intersection region of the data lines of the plurality of pixel groups. Each gate line group includes a plurality of gate lines, each pixel group includes a plurality of unit pixels, and the plurality of shielding lines are electrically connected to the plurality of gate line groups through a contact hole. Board; The liquid crystal display device which faces the thin film transistor substrate and includes a color filter substrate having a common electrode and a liquid crystal layer injected between the thin film transistor substrate and the color filter substrate is provided.

Each gate line group includes a first gate line and a second gate line formed to be spaced apart from the first gate line by a predetermined interval, and each pixel group includes a first unit pixel and a second unit pixel. The first unit pixel and the second unit pixel are connected to different gate lines and to the same data line.

The first unit pixel and the second unit pixel are disposed on opposite sides of the data line.

The first unit pixel and the second unit pixel are disposed on the same side with respect to the data line.

The liquid crystal display performs dot inversion.

According to another aspect of the invention, forming a plurality of gate line groups formed in one direction on a substrate; Forming a plurality of data lines insulated from and intersecting the plurality of gate line groups; Forming a plurality of pixel groups formed at intersections of the plurality of gate line groups and the plurality of data lines, and reducing variation in coupling capacitance between the plurality of pixel groups and the gate line group, And forming a plurality of shielding lines formed on the line group, wherein forming the plurality of shielding lines comprises electrically connecting the plurality of gate line groups and the plurality of shielding lines through a contact hole. Provided is a method of manufacturing a thin film transistor substrate, comprising:

Meanwhile, in the detailed description of the present invention, when a part such as a layer, a film, an area, or a plate is expressed on or above another part, each part is different from each part as well as when the part is directly on or directly above the other part. It also includes cases where there is another part between.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 3 is a schematic cross-sectional view taken along line AA ′ of the thin film transistor substrate of FIG. 2.

2 and 3, the thin film transistor substrate includes a plurality of gate line groups formed in one direction on the substrate, a plurality of data lines formed to be insulated from and cross the plurality of gate line groups, and the plurality of gate lines. A plurality of pixel groups formed in an intersection region of a gate line group and a plurality of data lines, and a plurality of pixel groups formed on the plurality of gate line groups so as to reduce a variation in coupling capacitance between the plurality of pixel groups and the gate line group. A shielding line 390 of which each gate line group includes a plurality of gate lines, each pixel group includes a plurality of unit pixels, and the plurality of shielding lines pass through a contact hole 400. It is electrically connected to the plurality of gate line groups.

The thin film transistor substrate transmits a gate signal on the transparent insulating substrate 301, and includes a plurality of gate line groups formed in a horizontal direction on the substrate, wherein each gate line group includes a first gate line GL _{1 (n). And} GL _{1 (n + 1)} and second gate lines GL _{2 (n) and} GL _{2 (n + 1)} formed spaced apart from the first gate line by a predetermined interval. A plurality of pixel groups are formed in an intersection area of the plurality of gate line groups and the plurality of data lines. Hereinafter, a first pixel group I and a second pixel group II adjacent to the first pixel group among the plurality of pixel groups will be described as an example.

The first pixel group I includes a first unit pixel and a second unit pixel. Each of the first unit pixel and the second unit pixel includes first and second thin film transistors TFT ₁ and TFT ₂ , a first pixel electrode 381 and a second pixel electrode 382, and a storage capacitor electrode line. Storage capacitor electrodes (not shown) extending from (not shown). The first and second thin film transistors TFT ₁ and TFT ₂ each include a gate electrode connected to a gate line, a source electrode connected to a data line, a drain electrode connected to a pixel electrode, and the gate electrode. And a gate insulating layer and an active layer sequentially formed between the source electrode and the drain electrode, and an ohmic contact layer formed on at least a portion of the active layer, wherein the ohmic contact layer may be formed on the active layer except for the channel portion. The thin film transistor causes the pixel signal supplied to the data line DL _n to be charged in the first pixel electrode 381 in response to the signal supplied to the first gate line GL _{1 (n)} . The second thin film transistor is configured to charge the pixel signal supplied to the data line DL _n to the second pixel electrode 382 in response to the signal supplied to the second gate line GL _{2 (n)} . All.

The second pixel group II also includes a first unit pixel and a second unit pixel, and each of the first unit pixel and the second unit pixel includes first and second thin film transistors TFT ₃ and TFT ₄ . And a storage capacitor electrode (not shown) extending from the first pixel electrode 383, the second pixel electrode 384, and a storage capacitor electrode line (not shown).

In the present embodiment, an example in which a first unit pixel and a second unit pixel of a pixel group connected to the same data line are disposed with the data line interposed therebetween is not limited thereto. Both the first unit pixel and the second unit pixel of the connected pixel group may be disposed on the left side or the right side of the data line. In addition, in the present exemplary embodiment, the liquid crystal display performs dot inversion, but the present invention is limited thereto.

The plurality of shielding lines 390 are formed on the gate lines, and are formed in parallel with the gate lines. In this case, the shielding line 390 is formed on the gate line to have a length corresponding to the pixel electrode of each unit pixel, and the shielding lines are separated from each other. In addition, each shielding line is electrically connected to the gate line through a contact hole, so that a voltage applied to the gate line can be applied to the shielding line. That is, shielding lines 391a and 391b are formed on the upper and lower portions of the first pixel electrode 381 of the first pixel group, respectively, and shielding lines 392a and 162 are respectively formed on the upper and lower portions of the second pixel electrode 382. 392b) is formed. In addition, contact holes 401a, 401b, 402a and 402b are formed in the shielding lines 391a and 391b of the first pixel electrode and the shielding lines 392a and 392b of the second pixel electrode, respectively. The remaining pixel groups are also formed in the same shape as the first pixel group.

3 illustrates a schematic cross-sectional view of a thin film transistor substrate along a line A-A ', and the thin film transistor substrate of the liquid crystal display device includes a transparent insulating substrate 301 and a first gate line GL formed on the transparent insulating substrate. _{1 (n + 1)} ) and a second gate line GL _{2 (n)} , a gate insulating film formed on the first and second gate lines, and a second gate line GL _{2 (n)} formed on the second gate line GL _{2 (n)} . A shielding line 393a formed on a shielding line 392b and the first gate line GL _{1 (n + 1)} , and the second gate line GL _{2 (n} ) and the shielding line 392b ) Is connected through a contact hole 402b, and the first gate line GL _{1 (n + 1} ) and the shielding line 393a are connected through a contact hole 403a. In addition, the shielding line 392b and the second pixel electrode 382 of the first pixel group are spaced apart from each other by a predetermined interval, and the shielding line 393a is also disposed in the first pixel of the second pixel group. The electrodes 383 are disposed to be spaced apart from each other by a predetermined interval. As described above, the pixel electrode is electrically connected through the gate line and the contact hole, so that a predetermined voltage can be applied, thereby stably controlling the pixel electrode. As a result, the variation of the coupling capacitance between the pixel electrode and the gate line is controlled. It can be minimized.

4 is a schematic layout diagram of the thin film transistor substrate illustrated in FIG. 2, and FIGS. 5A to 5E are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

First, referring to FIG. 5A, a first conductive film is formed on a transparent insulating substrate 301, and then a first electrode including a gate electrode 310 having a predetermined line width is formed through an etching process using a first photoresist mask pattern (not shown). A second gate line GL _{2 (n)} including one gate line (not shown) and a second gate electrode (not shown) are formed.

First, a first conductive film is formed on the transparent insulating substrate 301 through a deposition method using a CVD method, a PVD method, a sputtering method, or the like. It is preferable to use at least one of Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), and Cr / Al (Nd) as the first conductive film. The first conductive film may be formed of a multilayer film. Subsequently, after the photoresist is applied, a photolithography process using the first mask is performed to form a first photoresist mask pattern. An etching process using the first photoresist mask pattern as an etching mask is performed to form the gate electrode 310 and the second gate line GL _{2 (n)} as shown in FIG. 5A. Thereafter, a predetermined strip process is performed to remove the first photoresist mask pattern.

Referring to FIG. 5B, a gate insulating film 350, an active layer 361, and an ohmic contact layer 363 are sequentially formed on the entire surface of the substrate illustrated in FIG. 5A, and then a second photoresist mask pattern (not shown) is formed. The etching process is used to form the active region of the thin film transistor. The gate insulating film 350 is formed on the substrate by a deposition method using a PECVD method, a sputtering method, or the like. In this case, it is preferable to use an inorganic insulating material including silicon oxide or silicon nitride as the gate insulating film 350. The active layer 361 and the ohmic contact layer 363 are sequentially formed on the gate insulating layer 350 through the above-described deposition method. An amorphous silicon layer is used as the active layer 361, and an amorphous silicon layer doped with a high concentration of silicide or N-type impurities is used as the ohmic contact layer 363. Thereafter, a photoresist film is coated on the ohmic contact layer, and then a second photoresist mask pattern is formed through a photolithography process using a second mask. An etching process using the second photoresist mask pattern as an etch mask and the gate insulating film 350 as an etch stop layer is performed to remove the ohmic contact layer 363 and the active layer 361 to form an upper portion of the gate electrode 310. To form an active region. Thereafter, a predetermined strip process is performed to remove the remaining second photoresist mask pattern.

Referring to FIG. 5C, a second conductive layer is formed on the entire surface of the substrate on which the active region of the thin film transistor is formed, and then an etching process using the third photoresist mask pattern (not shown) is performed to form the source electrode 365 and the drain electrode ( 367). A second conductive film is formed on the entire surface of the substrate by a deposition method using a CVD method, a PVD method, a sputtering method, or the like. At this time, it is preferable to use at least one metal single layer or multiple layers of Mo, Al, Cr, Ti as the second conductive film. Of course, the same material as that of the first conductive film may be used for the second conductive film. After the photosensitive film is coated on the second conductive film, a lithography process using a mask is performed to form a third photoresist mask pattern. The second conductive film is etched by performing an etching process using the third photoresist mask pattern as an etch mask, and then the third photoresist mask pattern is removed, followed by etching using the etched second conductive film as an etch mask. The ohmic contact layer 363 of the exposed region between the depositions is removed to form a channel formed of the active layer 361 between the source electrode 365 and the drain electrode 367.

Referring to FIG. 5D, the passivation layer 370 is formed on the entire surface of the substrate, and a portion of the passivation layer 370 is removed through an etching process using a fourth photoresist mask pattern to contact the gate drain line and the gate line between the drain drain electrode and the pixel electrode. A contact hole 400 is formed for the electrical connection between the following shielding lines.

Referring to FIG. 5E, a third conductive layer is formed on the passivation layer 370, and then the third conductive layer is patterned using a fifth photoresist mask pattern (not shown) to form the pixel electrode 388 and the shielding line 390. ). At this time, it is preferable to use the transparent conductive film containing ITO and IZO for a 3rd conductive film.

6 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a second exemplary embodiment of the present invention. The second embodiment of the present invention illustrated in FIG. 6 differs from the first embodiment in that the shielding line is integrally formed on the gate line instead of the unit pixel, and the remaining components are almost similar. Hereinafter, the different configurations will be described in detail.

Referring to FIG. 6, the thin film transistor substrate transmits a gate signal on the transparent insulating substrate 301, and includes a plurality of gate line groups formed in a horizontal direction on the substrate, wherein each gate line group includes a first gate. Lines GL _{1 (n) and} GL _{1 (n + 1)} and second gate lines GL _{2 (n) and} GL _{2 (n + 1)} spaced apart from the first gate line by a predetermined interval. . A plurality of pixel groups are formed in an intersection area of the plurality of gate line groups and the plurality of data lines. The plurality of shielding lines 391 to 394 are formed on each gate line, and are formed in parallel with the gate line. In this case, the shielding lines formed on the respective gate lines are integrally formed and extend in the same direction as the gate lines. In addition, each shielding line is electrically connected to the gate line through contact holes 401 to 404, and at least one contact hole is formed on one shielding line.

7 is a schematic plan view of a thin film transistor substrate of a liquid crystal display according to a third exemplary embodiment of the present invention. The first embodiment of the present invention illustrated in FIG. 7 differs from the first embodiment in that at least one incision pattern for forming a multi-domain is formed in the pixel electrode of the unit pixel, and the remaining components are almost similar. Hereinafter, the different configurations will be described in detail.

Referring to FIG. 7, the thin film transistor substrate transmits a gate signal on the transparent insulating substrate 301, and includes a plurality of gate line groups formed in a horizontal direction on the substrate, wherein each gate line group includes a first gate. Lines GL _{1 (n) and} GL _{1 (n + 1)} and second gate lines GL _{2 (n) and} GL _{2 (n + 1)} spaced apart from the first gate line by a predetermined interval. . A plurality of pixel groups are formed in an intersection area of the plurality of gate line groups and the plurality of data lines. The first pixel group I includes a first unit pixel and a second unit pixel, and each of the first unit pixel and the second unit pixel includes a first thin film transistor and a second thin film transistor TFT ₁ and TFT ₂ . And a storage capacitor electrode (not shown) extending from the first pixel electrode 381 and the second pixel electrode 382 and the storage capacitor electrode line (not shown). In this case, the first pixel electrode 381 includes cutting patterns 321a, 321b, and 321c for forming a multi-domain, and similarly, the remaining pixel electrodes include a cutting pattern 320 for forming a multi-domain. In the present embodiment, the incision pattern is used as the multi-domain regulation means, but is not limited thereto, and protrusions may be formed.

What has been described above is only an exemplary embodiment of a thin film transistor substrate, a method of manufacturing the same, and a liquid crystal display device including the same, and the present invention is not limited to the above-described embodiment, which is claimed in the following claims. As will be apparent to those skilled in the art to which the present invention pertains without departing from the spirit of the present invention, the technical spirit of the present invention may be modified to the extent that various modifications can be made.

As described above, according to the present invention, a shielding line is formed on the gate line, and the gate line and the shielding line are connected through a contact to control the shielding line, thereby reducing the variation in coupling capacitance between the gate line and the pixel electrode. You will get a reducing effect.

Claims (14)

A plurality of gate line groups formed in one direction on the substrate; A plurality of data lines insulated from and intersecting the plurality of gate line groups; A plurality of pixel groups formed at intersections of the plurality of gate line groups and the plurality of data lines; And a plurality of shielding lines formed on the plurality of gate line groups in order to reduce variation in coupling capacitance between the plurality of pixel groups and the gate line group. Each gate line group includes a plurality of gate lines, each pixel group includes a plurality of unit pixels, and the plurality of shielding lines are electrically connected to the plurality of gate line groups through a contact hole. A thin film transistor substrate. The method of claim 1, Each gate line group includes a first gate line and a second gate line formed to be spaced apart from the first gate line by a predetermined distance. Each pixel group includes a first unit pixel and a second unit pixel. The method of claim 2, The thin film transistor substrate of claim 1, wherein the first unit pixel and the second unit pixel are connected to different gate lines and to the same data line. The method of claim 3, Wherein each pixel group includes a pixel electrode, a thin film transistor, and a storage capacitor electrode, wherein each shielding line is formed of the same material as the pixel electrode. The method of claim 4, wherein And each shielding line is formed to be parallel to the gate line. The method of claim 5, The shielding line may be formed separately from each of the unit pixels. The method of claim 1, And the gate voltages applied to the plurality of gate line groups are applied to the plurality of shielding lines. The method of claim 4, wherein The pixel electrode is a thin film transistor substrate, characterized in that at least one incision pattern for forming a multi-domain is formed. A plurality of gate line groups formed in one direction on the substrate, a plurality of data lines insulated from and intersecting the plurality of gate line groups, and a plurality of gate line groups formed in an intersection region of the plurality of gate line groups and the plurality of data lines And a plurality of shielding lines formed on the plurality of gate line groups in order to reduce a variation in coupling capacitance between the pixel group and the plurality of pixel groups and the gate line group, wherein each gate line group includes a plurality of gates. A thin film transistor substrate, each pixel group including a plurality of unit pixels, and the plurality of shielding lines electrically connected to the plurality of gate line groups through a contact hole; A color filter substrate facing the thin film transistor substrate and having a common electrode formed thereon; And a liquid crystal layer injected between the thin film transistor substrate and the color filter substrate. The method of claim 9, Each gate line group includes a first gate line and a second gate line formed to be spaced apart from the first gate line by a predetermined interval, and each pixel group includes a first unit pixel and a second unit pixel. The first unit pixel and the second unit pixel are connected to different gate lines and to the same data line, respectively. The method of claim 10, And the first unit pixel and the second unit pixel are disposed on opposite sides of the data line. The method of claim 10, And the first unit pixel and the second unit pixel are disposed on the same side with respect to the data line. The method of claim 10, And the liquid crystal display performs dot inversion. Forming a plurality of gate line groups formed in one direction on the substrate; Forming a plurality of data lines insulated from and intersecting the plurality of gate line groups; Forming a plurality of pixel groups formed at intersections of the plurality of gate line groups and the plurality of data lines; and Forming a plurality of shielding lines formed on the plurality of gate line groups to reduce a variation in coupling capacitance between the plurality of pixel groups and the gate line group, The forming of the plurality of shielding lines may include electrically connecting the plurality of gate line groups and the plurality of shielding lines through contact holes.

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