KR100982481B1 - 프론트 메모리 저장 시스템 및 방법 - Google Patents
프론트 메모리 저장 시스템 및 방법 Download PDFInfo
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- KR100982481B1 KR100982481B1 KR1020087007413A KR20087007413A KR100982481B1 KR 100982481 B1 KR100982481 B1 KR 100982481B1 KR 1020087007413 A KR1020087007413 A KR 1020087007413A KR 20087007413 A KR20087007413 A KR 20087007413A KR 100982481 B1 KR100982481 B1 KR 100982481B1
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000005055 memory storage Effects 0.000 title claims abstract description 35
- 230000015654 memory Effects 0.000 claims abstract description 184
- 230000007246 mechanism Effects 0.000 claims abstract description 6
- 238000013459 approach Methods 0.000 description 4
- 238000007726 management method Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 230000003542 behavioural effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (13)
- 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법으로서,a. 상기 메모리 어레이의 제1그룹의 메모리 셀을, 상기 제1그룹의 메모리 셀의 각각이 제1비트수를 저장하도록, 지정하는 단계;b. 상기 메모리 어레이의 제2그룹의 메모리 셀을, 상기 제2그룹의 메모리 셀의 각각이 제2비트수를 저장하도록 지정하는 단계;c. 상기 제1그룹의 메모리 셀에 데이터를 기록하는 단계;d. 상기 제1그룹의 메모리 셀로부터 상기 제2그룹의 메모리 셀로 데이터를 복사하는 단계;e. 자체 내의 상기 제1그룹의 메모리 셀 만의 균일하게 분포된 마모를 위해, 상기 제1그룹의 메모리 셀에 제1마모 레벨링 기술을 적용하는 단계를 포함하고,상기 제2비트수는 상기 제1비트수 보다 크고, 상기 제1그룹의 메모리 셀과 상기 제2그룹의 메모리 셀은 중첩되지 않은 것을 특징으로 하는 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법.
- 제 1 항에 있어서, 상기 제1비트수는 1이고, 상기 제2비트수는 2인 것을 특징으로 하는 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법.
- 제 1 항에 있어서, 상기 제1비트수는 1이고 상기 제2비트수는 4인 것을 특징으로 하는 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법.
- 제 1 항에 있어서, 상기 제1그룹의 메모리 셀 개수와 상기 제2그룹의 메모리 셀 개수 간의 비율은 상기 제1비트수 및 상기 제2비트수 간의 비율이 곱해진 상기 제1그룹의 메모리 셀의 내구성 및 상기 제2그룹의 메모리 셀의 내구성 간의 비율과 동일하도록 설정되는 것을 특징으로 하는 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법.
- 제 1 항에 있어서,f. 그 자체 내의 상기 제2그룹의 메모리 셀의 균일하게 분포된 마모를 위해 상기 제2그룹의 메모리 셀에 제2마모 레벨링 기술을 적용하는 단계를 더 포함하는 것을 특징으로 하는 컨트롤러 및 메모리 어레이를 갖춘 플래시 메모리 저장 시스템에 데이터를 저장하는 방법.
- 플래시 메모리 저장 시스템으로서,a. 복수의 메모리 셀을 포함하는 메모리 어레이;b. 제1그룹의 메모리 셀을 셀당 제1비트수를 저장하도록 지정하고, 제2그룹의 메모리 셀을 셀당 제2비트수를 저장하도록 지정함으로써 상기 플래시 메모리 어레이를 컨트롤하고, 상기 셀당 제2비트수는 상기 셀당 제1비트수보다 크고, 상기 제1그룹의 메모리 셀과 상기 제2그룹의 메모리 셀은 중첩되지 않는 컨트롤러;를 포함하고, 상기 컨트롤러는:데이터를 상기 제1그룹의 메모리 셀에 기록하고;상기 제1그룹의 메모리 셀로부터 상기 제2그룹의 메모리 셀로 데이터를 복사하고;그 자체 내의 상기 제1그룹의 메모리 셀 만의 균일하게 분포된 마모를 위해 상기 제1그룹의 메모리 셀에 제1마모 레벨링 기술을 적용하도록;더 설정되는 것을 특징으로 하는 플래시 메모리 저장 시스템.
- 제 6 항에 있어서, 상기 컨트롤러는 상기 제1그룹의 메모리 셀에 데이터를 저장한 다음, 상기 제2그룹의 메모리 셀에 상기 데이터를 복사하도록 더 동작하는 것을 특징으로 하는 플래시 메모리 저장 시스템.
- 제 6 항에 있어서, 상기 제1비트수는 1이고, 상기 제2비트수는 2인 것을 특징으로 하는 플래시 메모리 저장 시스템.
- 제 6 항에 있어서, 상기 제1비트수는 1이고, 상기 제2비트수는 4인 것을 특징으로 하는 플래시 메모리 저장 시스템.
- 제 6 항에 있어서, 상기 제1그룹의 메모리 셀 개수와 상기 제2그룹의 메모리 셀 개수 간의 비율은 상기 제1비트수와 상기 제2비트수 간의 비율이 곱해진 상기 제1그룹의 메모리 셀의 내구성 및 상기 제2그룹의 메모리 셀의 내구성 간의 비율과 동일하도록 설정되는 것을 특징으로 하는 플래시 메모리 저장 시스템.
- 제 6 항에 있어서, 그 자체 내에 상기 제2그룹의 메모리 셀의 균일하게 분포된 마모를 위해 상기 제2그룹의 메모리 셀 내에 제2마모 레벨링 기술을 적용하기 위한 메카니즘을 더 포함하는 것을 특징으로 하는 플래시 메모리 저장 시스템.
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Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US71539105P | 2005-09-09 | 2005-09-09 | |
US60/715,391 | 2005-09-09 | ||
US11/318,906 | 2005-12-28 | ||
US11/318,906 US7752382B2 (en) | 2005-09-09 | 2005-12-28 | Flash memory storage system and method |
PCT/IL2006/001049 WO2007029259A2 (en) | 2005-09-09 | 2006-09-07 | Front memory storage system and method |
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KR20080038441A KR20080038441A (ko) | 2008-05-06 |
KR100982481B1 true KR100982481B1 (ko) | 2010-09-16 |
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US (2) | US7752382B2 (ko) |
EP (1) | EP1922623B1 (ko) |
JP (1) | JP4759057B2 (ko) |
KR (1) | KR100982481B1 (ko) |
CN (1) | CN101356507B (ko) |
WO (1) | WO2007029259A2 (ko) |
Cited By (1)
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KR20140000751A (ko) * | 2012-06-25 | 2014-01-06 | 에스케이하이닉스 주식회사 | 데이터 저장 장치의 동작 방법 |
KR101989018B1 (ko) * | 2012-06-25 | 2019-06-13 | 에스케이하이닉스 주식회사 | 데이터 저장 장치의 동작 방법 |
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US20070061502A1 (en) | 2007-03-15 |
WO2007029259A2 (en) | 2007-03-15 |
EP1922623B1 (en) | 2013-07-10 |
KR20080038441A (ko) | 2008-05-06 |
EP1922623A4 (en) | 2009-04-29 |
EP1922623A2 (en) | 2008-05-21 |
CN101356507B (zh) | 2012-04-18 |
JP4759057B2 (ja) | 2011-08-31 |
US20100274955A1 (en) | 2010-10-28 |
JP2009510549A (ja) | 2009-03-12 |
US8069302B2 (en) | 2011-11-29 |
WO2007029259A3 (en) | 2007-11-15 |
US7752382B2 (en) | 2010-07-06 |
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