CN101356507B - 存储器存储系统和方法 - Google Patents

存储器存储系统和方法 Download PDF

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CN101356507B
CN101356507B CN2006800327676A CN200680032767A CN101356507B CN 101356507 B CN101356507 B CN 101356507B CN 2006800327676 A CN2006800327676 A CN 2006800327676A CN 200680032767 A CN200680032767 A CN 200680032767A CN 101356507 B CN101356507 B CN 101356507B
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M·拉瑟
M·穆里恩
A·埃亚尔
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
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Abstract

一种闪存存储系统(10)，包含存储器阵列(12)和控制该闪存阵列(12)的控制器(16)，其中该存储器阵列(12)包括多个存储器单元(14)。该控制器(16)专用第一组存储器单元用于每个单元存储第一位数，并且专用分开的第二组存储器单元(14)用于每个单元存储第二位数。提供了一种机构来把磨损平衡技术独立地应用于两组存储器单元来平均对存储器单元(14)的磨损。

Description

存储器存储系统和方法
技术领域
本发明总的来说涉及一种闪存存储系统。更具体地，本发明涉及一种包含能够每存储器单元存储多个位的缓冲存储机构的闪存存储系统。 
背景技术
一种作为多层单元(MLC)闪存实现的闪存系统用于在每个存储器单元上存储多于一个数据位。对多层单元(MLC)闪存的数据的写入速度典型地低于对在每个单元只存储一个数据位的单层单元(SLC)闪存的数据写入速度。因此，基于MLC闪存的存储系统可能不能够以一个较高的写入速度来记录传输给它的输入数据流。 
在数据产生速度高到不能直接存储的典型情况下，提供一种缓冲存储机构并将其设计成足够快速地处理输入的数据流。把利用第二(并且较快的)存储器的缓冲存储器设置在输入数据源和主(并且较慢的)存储器之间。输入数据流首先被写入到较快的缓冲存储器中，并且在稍后阶段从这个较快的缓冲存储器复制到主存储器中。由于复制操作典型地在后台执行，所以不必满足由输入数据流速度而强制实行的严格的性能条件，因此主存储器的较低的写入性能不再是障碍。 
然而，用于缓冲存储的第二存储器的实现具有其自身的缺点。该实现需要为缓冲存储器及其控制提供额外的器件，而且也使得存储器系统的设计和管理变得复杂。 
现有技术包括Lee等人的美国专利NO.5,930,167，其披露了在闪存存储系统中用于缓冲存储写操作的一种存储方法和系统，其具有在MLC闪存中的缓冲存储的优点，同时具有更少的缺点。MLC闪存介质配置成作为其自身的缓冲存储器操作。这样是可能的，因为存储多个位的存储器单元可以更进一步实现为类似于SLC存储器单元操作并且只存储单个位，从技术的角度来看是一个更容易的目标。因而，MLC存储器单元可以被实现为具有SLC闪存特征的更快 的写性能。Lee的专利通过引用而结合于此，就像完全在这里阐述一样，用于所有目的。 
在现有技术中已知的技术，诸如Lee等人的技术，提供了一种嵌入到MLC闪存存储系统中的“内置”的较快速的缓冲存储器。当接收到要存储的数据位时，它们首先被写入到运行于SLC模式下的存储器单元中。该第一写操作可以相对快地完成。在该操作之后，在后台中并且当时间允许时，数据位从SLC单元中复制到设置为运行于MLC模式下的存储器单元中。这样，由于系统被设计成使用了MLC闪存存储系统的较高存储密度，它更能处理较快的输入数据流，而不是在没有缓冲存储机构的情况下不能被处理。 
共有两种可能的方法用于配置闪存系统，同时利用了这样一个SLC缓冲存储方案： 
A.专用的缓冲存储器，存储器单元中的特定部分一直被分配成运行在SLC模式下，同时其它单元被分配成仅运行在MLC模式下。换句话说，运行在SLC模式下的存储器单元(SLC单元)与运行在MLC模式下的存储器单元(MLC单元)同时共存于存储系统中，每个特定的存储器单元被分配成运行在SLC模式下或者在MLC模式下，且不能交替地分配成在一个时间点运行在SLC模式下和在另一个时间点运行在MLC模式下。 
B.混合缓冲存储器，至少一些存储器单元在系统的运行期间更改模式。即，一个特定的存储器单元可以在一个时间点被分配成运行在SLC模式下并用来缓冲存储数据，而在第二时间点，相同的存储器单元被分配成运行在MLC模式下，并用于主存储器中的高密度数据存储。 
在闪存系统中，专用缓冲存储方法比混合缓冲存储方法管理起来更加简单。存储器单元的每个部分被预分配成运行在SLC模式下或在MLC模式下。因此，不需要实时模式切换。此外，没有必要提供信息管理模块用于存储和检测任一存储部分的当前运行模式。 
但是，尽管该优点很清楚，但Lee的专利披露了一种应用更加复杂的混合缓冲存储方法的存储系统，位于第2栏第49行： 
“没有必要专用闪速EEPROM存储器的某些部分只作为写缓冲存储器运行...因此，本发明的闪速EEPROM存储器的以高密度存储数据的部分也能够作为写缓冲存储器而运行...，用于长期、高密度存储的存储器扇区的识别通过 诸如文件分配表来保留，以便能够将低密度的输入数据引向那些没有被使用的扇区。” 
Lee的专利中进一步给出了使用更复杂的混和缓冲存储的方法的解释，位于第2栏第51行： 
“使用存储器中的专用部分作为写缓冲器可能引起该部分中的单元比存储器的其它部分中的单元被使用的更加多一些，与均匀地耗损存储器的通用需求相反。” 
换句话说，由于每块输入数据要写两次，一次在SLC模式(当被缓冲存储时)和一次在MLC模式(当被复制到主存储器时)，并且由于分配给缓冲存储器的存储器单元部分通常要比分配给主存储器的存储器单元部分小得多，那么，在平均时间上，仅分配给缓冲存储器的存储器单元要比仅分配给主存储器的存储器单元写入和随后的擦写更频繁。 
众所周知闪存单元在使用期间要磨损，即，经历的写/擦写周期越多，它们遭受的磨损也就越多。因此，根据Lee的说法，按照专用缓冲存储方法分配给缓冲存储器的存储器单元将比其它存储器单元磨损得更快，并且可能已经达到其使用寿命(即它们正常使用工作的能力的尽头)，同时没有用作缓冲存储器的单元仍运行良好。 
因此，Lee的专利应用混合缓冲存储方法，以便均匀地分配对所有存储器单元的磨损，因为没有一个单元在缓冲存储器中被总是大量的使用。 
事实上，Lee的专利可以更进一步加强其反对利用专用方法的论点，位于第3栏第2行： 
“...由于低密度编程的情况比高密度编程的情况能引发的磨损更多一些。” 
因此，不但缓冲存储器的存储器单元写入得更频繁并且趋向于磨损得更加快，而且根据Lee的专利，即使在相同数目的写/擦写周期下，配置成运行在SLC模式下的存储器单元也比配置成运行在MLC模式下的存储器单元要磨损得更加早一些。 
Lee的专利更进一步提到了一个应用专用缓冲存储方法的案例，位于第9栏第44行： 
“可选地，在存储系统的使用并不预期为大到足以需要这样的磨损平衡的应用中，某些数据块或者扇区可专用于初始双态数据的写操作。” 
换句话说，如果存储系统不频繁写入以致于即使没有使用磨损平衡技术，也不预期有存储器单元磨损掉，那么此处就适合应用专用缓冲存储方法。 
用于实现磨损平衡以便平均分配对所有存储器块的磨损的技术在本领域是公知的。它们包括Lofgren等人的美国专利NO.6,230,233，Wells的美国专利NO.5,341,339，Jou等人的美国专利NO.5,568,423，Assar等人的美国专利NO.5,388,083，Harari的美国专利第5,712,819、6,570,790和5,963,480号等，以及Chang等人的美国专利NO.6,831,865。所有这些专利通过引用结合于此，就像完全在这里阐述一样，用于所有的目的。 
所有上述现有技术的方法是基于闪存单元中的每个块经历的写/擦写周期的计数，且在写操作需要新的数据块时使用这些计数来决定分配哪个块。事实上，Lee也使用了此方法，进一步保存了每个数据块的独立的SLC计数值和MLC计数值。 
总结如下，根据Lee的专利，这样一个自缓冲存储的MLC/SLC的闪存系统的设计者只可以在如下两者之间选择： 
A.使用混合缓冲存储方法，使用磨损平衡技术，并得到可以经受频繁的写入的一种存储系统。这是主要的也是推荐的方法。 
B.使用专用缓冲存储方法，而不使用磨损平衡技术，并得到只在数据写入不频繁的情况下可以使用的一种存储系统，。 
然而，该方法的主要缺点在于，混合缓冲存储方法实现和处理起来更加复杂，因为需要实时模式切换管理。 
因此，期望提供一种使用专用缓冲存储方法的存储系统，同时克服了对存储器单元频繁写入而引发的磨损问题。 
发明内容
因此，本发明的主要目的是克服使用专用缓冲存储方法的现有技术的缺点，同时克服对存储器单元的频繁写入而引起的磨损问题。 
提出的闪存存储系统包括具有两组存储器单元的闪存存储器阵列。提供控制器以通过在SLC模式下运行第一组存储器单元和在MLC模式下运行第二组存储器单元来控制该闪存存储器阵列。在MLC模式下运行的存储器单元(MLC单元)比SLC单元含有更多的位，使得两组存储器单元的位不接合。 
根据本发明的优选实施例，提供了一种闪存存储系统和在具有控制器和存储器阵列的闪存存储系统中存储数据的方法，该方法包括以下步骤： 
专用存储器阵列的第一组存储器单元，以使第一组存储器单元中的每一个存储第一位数； 
专用存储器阵列的第二组存储器单元，以使第二组存储器单元中的每一个存储第二位数， 
其中，所述第二位数大于所述第一位数， 
以使得第一组存储器单元和第二组存储器单元不接合； 
把数据写入第一组存储器单元； 
把数据从第一组存储器单元复制到第二组存储器单元；以及 
在所述第一组存储器单元中应用第一磨损平衡技术来在所述第一组存储器单元自身中均匀分配其磨损。 
根据本发明的另一方法，第一位数是一且第二位数是二。 
根据本发明的另一方法，第一位数是一且第二位数是四。 
根据本发明的另一方法，第二组的单元数与第一组的单元数之间的比率被设置为近似等于第一组存储器单元的耐久性与第二组存储器单元的耐久性之间的比率乘以第一位数与第二位数之间的比率。 
根据本发明的另一方法进一步包括如下步骤： 
在第二组存储器单元中应用第二磨损平衡技术来在第二组存储器单元自身中均匀分配其磨损。 
根据本发明的另一个实施例，提供了一种闪存存储系统，包括： 
包含多个存储器单元的存储器阵列；以及 
控制器，用于通过专用第一组存储器单元来每单元存储第一位数和专用第二组存储器单元来每单元存储第二位数控制闪存存储器阵列，其中，第二位数大于所述第一位数，以使得第一组存储器单元和第二组存储器单元不接合；以及 
一种机构，用于在第一组存储器单元中应用第一磨损平衡技术来在第一组存储器单元自身中均匀分配其磨损。 
通过下述的附图和描述使本发明的另外的特征和优点变得更加显而易见。 
附图说明
为了参照本发明的实施例更好地理解本发明，参考附图，其中贯穿全文相同的数字指示相应的部分或元件，并且其中： 
唯一的附图示出了根据本发明优选实施例的包括提出的闪存存储系统的部件的框图。 
具体实施方式
本发明披露了一种创新的闪存存储系统，其使用了专用缓冲存储方法，同时克服了由于频繁写入存储器单元而引起的磨损问题。 
提出的闪存存储系统包括具有两组存储器单元的闪存存储器阵列。提供控制器以通过在SLC模式下运行第一组存储器单元和在MLC模式下运行第二组存储器单元来控制该闪存存储器阵列。在MLC模式下运行的存储器单元(MLC单元)具有比SLC单元更大的位数，以使得两组存储器单元的位不接合(也就是说，两组存储器单元不重叠，不共有任一元素，等等)。通俗地讲，如果不会有对象是两组的实例的情况下，那么两组是不接合的。 
根据专用缓冲存储方法，存储器单元的特定部分总是被分配成在SLC模式下运行，同时其它存储器单元被分配成仅在MLC模式下运行。换句话说，每个特定的存储器单元被分配成在SLC模式下运行或者在MLC模式下运行，且不能交替地分配成在一个时间点在SLC模式下运行且在另一个时间点在MLC模式下运行。 
存储器单元的特定部分专用于总是在特定模式下运行不再需要执行实时模式切换技术。同时也没有必要提供为识别存储器单元的当前操作模式所需的信息管理。因此，设计的总体复杂性被简化了。 
存储器单元被设置运行在SLC模式下(即，SLC单元)比被设置运行在MLC模式下时(即，MLC单元)积聚了更少的磨损。这是由于MLC单元的更长的运行时间引起对这些存储器单元更大的压力且增加了磨损的事实。 
此外，MLC闪存存储系统中的SLC单元的磨损特性与典型的SLC闪存存储系统中的SLC单元的相类似。例如，与MLC闪存存储系统只有10,000个编程/擦写周期相比典型的SLC闪存存储系统具有100,000个的编程/擦写周期的耐久性。 
在Lee的专利中关于在SLC模式下(而不是MLC模式)运行时存在较高磨损的假设实际上是不正确的。或许这些假设未被验证，或许在Lee的专利中披露的闪存设备与本领域当前公知的闪存设备相比呈现不同的运行特性。 
不管什么原因，提出的闪存存储系统在SLC模式下的运行比在MLC模式下的运行引起较小的磨损的事实在使本发明可用方面是关键因素。 
因此，如果SLC单元用作MLC单元的缓冲存储器，那么在应用专用缓冲存储方法时即使分配给缓冲存储器的存储器单元经历更多的写入/擦写周期，SLC单元(由于它们运行在SLC模式下)的较好的磨损特性补偿该更频繁的写入。 
参照图1，示出了根据本发明的闪存存储系统10的优选实施例的组件的框图。闪存存储系统10包括存储器阵列12，该存储器阵列12包含多个存储器单元14，这些存储器单元或运行在SLC模式下或运行在MLC模式下，分别表示为C11到C1m和C21到C2n。还提供了用于控制存储器阵列12并且把数据写入到存储器单元14的控制器16。 
存储器单元14在每单元存储一位时具有200,000个编程/擦写周期的SLC耐久性并且在每单元存储两位时具有10,000个编程/擦写周期的MLC耐久性。 
控制器16控制存储器阵列12，以使得存储器单元的9％C11到C1m只是运行在SLC模式下(分配为SLC单元)，并且存储器单元的剩余的91％C21到C2n只是运行在MLC模式下(分配为MLC单元)。 
初看起来，可以得出平均起来一个SLC单元几乎10倍于一个MLC单元的循环频率。但是必须考虑到如下定义-在SLC单元中存储给定的数据量需要的存储器单元数为MLC单元中存储相同的数据量需要的存储器单元数的两倍。 
因此，正确的结论是平均起来C11到C1m中的每一个SLC单元几乎20倍于C21到C2n中的每一个MLC单元的循环频率。 
然而，由于每个SLC单元(具有200,000个编程/擦写周期的耐久性)的耐久性几乎是每个MLC单元(具有10,000个编程/擦写周期的耐久性)的耐久性的20倍。平均起来，SLC单元和MLC单元，相应的C11到C1m和C21到C2n，都在同一时间磨损掉并达到它们寿命的尽头(即，它们正常使用工作的能力的尽头)。结果是，所有存储器单元14的磨损在系统中均匀分配。 
使SLC单元和MLC单元均匀磨损掉达到了最佳的效果。因此，闪存存储 系统对于最佳的时间可用，与以下情况相反，在一些存储器单元被完全磨损掉而不能再对系统存储使用时，其它存储器单元仍旧是“新的”且可以使用。 
为了使上述有效，闪存存储系统10使用磨损平衡技术来均匀分配缓冲存储器单元自身内的磨损。磨损平衡技术均匀分配一组单元自身内的磨损意味着，该技术试图促使该组中的所有单元具有类似的磨损，而不考虑该组之外的任意单元的磨损。因此此处的磨损平衡技术试图促使缓冲存储器的所有单元具有类似的磨损，而不考虑其它单元的磨损。这需要SLC写/擦写的计数值(即，通过对由可作为一组进行擦写的每个存储器单元块执行的在SLC模式下的写/擦写周期的数目进行计数)和使用现有技术已知的磨损平衡技术来实现。 
类似地，磨损平衡技术也可以用来均匀分配非缓冲存储器单元自身的磨损。即，磨损平衡技术试图促使所有非缓冲存储器单元具有类似的磨损，而不考虑其它单元的磨损。这需要MLC写/擦写的计数值(即，通过对由每个存储器单元块执行的在MLC模式下的写/擦写周期的数目进行计数)和再次使用现有技术已知的磨损平衡技术来实现。与Lee的专利相反，此处不必为每个块提供两个计数值，因为根据专用缓冲存储方法，每个块或者使用在SLC模式下或者使用在MLC模式下但是从来不同时在两个模式下，所以每个块只需要一个计数。 
根据本发明的一个优选实施例，存储器阵列的每个MLC单元存储两位。然而，提出的闪存存储系统并不限制于此情况。存储器阵列中分配的MLC单元可以在每个单元中存储3位，或者4位，或者其他大于1的任意位数。类似地，SLC单元中的每个单元也不必然存储一位。每个“SLC”单元(“SLC”带引号是因为该单元不再是单层单元)可以在每个单元中存储任意位数，只要每个MLC单元中存储的位数大于每个“SLC”单元中存储的位数。只要保持该关系，对“SLC”单元的写操作花费的时间就少于对MLC单元花费的时间。因此，就获得了对输入流高速度的支持。 
优选地，MLC单元的数目与“SLC”单元的数目之间的比率被设置为近似等于“SLC”单元的耐久性与MLC单元的耐久性之间的比率乘以“SLC”单元的位数与MLC单元的位数之间的比率。 
应当理解的是，尽管在此披露的闪存存储系统优先使用NAND型闪存，但也可以使用其它类型的闪存。此外，在本发明的范围内的其它实现也是可能的，由此涉及使用了专用缓冲存储的方法同时克服了磨损问题和提供了类似的功能的任何系统。 
在此已经关于一个特定的实施例本发明，应当理解的是该描述并不作为一 个限制，这是因为根据本发明的启示本领域技术人员可以做更进一步的修改，本发明覆盖在附带的权利要求范围内的这些修改。 

Claims (11)

1.一种用于在闪存存储系统中存储数据的方法，该闪存存储系统具有控制器和存储器阵列，该方法包括以下步骤：
a.将存储器阵列的第一组存储器单元专用，使得所述第一组存储器单元中的每一个以第一位数进行存储；
b.将存储器阵列的第二组存储器单元专用，使得所述第二组存储器单元中的每一个以第二位数进行存储，其中，所述第二位数大于所述第一位数，以及所述第一组存储器单元和所述第二组存储器单元不接合；
c.把数据写入所述第一组存储器单元；
d.把数据从所述第一组存储器单元复制到所述第二组存储器单元；以及
e.与所述第二组存储器单元的所述存储器单元分离地、在所述第一组存储器单元的所述存储器单元中应用磨损平衡，以独立于所述第二组存储器单元的磨损在所述第一组存储器单元自身中均匀分配磨损；以及
其中，所述第一和第二组存储器单元的所述存储器单元的相应数量被选择为使得所述第二组存储器单元的所述存储器单元的所述相应数量与所述第一组存储器单元的所述存储器单元的所述相应数量之间的比率近似等于所述第一组存储器单元的耐久性与所述第二组存储器单元的耐久性之间的比率乘以所述第一位数与所述第二位数之间的比率。
2.根据权利要求1所述的方法，其中，所述第一位数是一位且所述第二位数是二位。
3.根据权利要求1所述的方法，其中，所述第一位数是一位且所述第二位数是四位。
4.根据权利要求1所述的方法，进一步包括如下步骤：
f.与所述第一组存储器单元的所述存储器单元分离地、在所述第二组存储器单元的所述存储器单元中应用磨损平衡，以独立于所述第一组存储器单元的所述磨损在所述第二组存储器单元自身中均匀分配磨损。
5.一种闪存存储系统，包括：
a.包含多个存储器单元的存储器阵列；
b.控制器，用于通过从所述多个存储器单元中将第一组存储器单元专用于每单元以第一位数进行存储和通过从所述多个存储器单元中将第二组存储器单元专用于每单元以第二位数进行存储来控制所述存储器阵列，其中，所述第二位数大于所述第一位数，以及所述第一组存储器单元和所述第二组存储器单元不接合；以及
c.一种机构，用于与所述第二组存储器单元的所述存储器单元分离地、在所述第一组存储器单元的所述存储器单元中应用磨损平衡，以独立于所述第二组存储器单元的磨损在所述第一组存储器单元自身中均匀分配磨损，
其中，所述控制器选择所述第一和第二组存储器单元的所述存储器单元的相应数量，使得所述第二组存储器单元的所述存储器单元的所述相应数量与所述第一组存储器单元的所述存储器单元的所述相应数量之间的比率近似等于所述第一组存储器单元的耐久性与所述第二组存储器单元的耐久性之间的比率乘以所述第一位数与所述第二位数之间的比率。
6.根据权利要求5所述的闪存存储系统，其中，所述控制器进一步可操作以将数据存储在所述第一组存储器单元中并且随后将所述数据复制到所述第二组存储器单元中。
7.根据权利要求5所述的闪存存储系统，其中，所述第一位数是一位且所述第二位数是二位。
8.根据权利要求5所述的闪存存储系统，其中，所述第一位数是一位且所述第二位数是四位。
9.根据权利要求5所述的闪存存储系统，其中所述控制器还用于与所述第一组存储器单元的所述存储器单元分离地、在所述第二组存储器单元的所述存储器单元中应用磨损平衡，以独立于所述第一组存储器单元的所述磨损在所述第二组存储器单元自身中均匀分配磨损。
10.根据权利要求5所述的闪存存储系统，其中，用于应用所述磨损平衡的所述机构被包括在所述控制器中。
11.根据权利要求9所述的闪存存储系统，其中，用于应用所述磨损平衡的所述机构被包括在所述控制器中。
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EP1922623A2 (en) 2008-05-21
WO2007029259A2 (en) 2007-03-15
CN101356507A (zh) 2009-01-28
US20070061502A1 (en) 2007-03-15
JP2009510549A (ja) 2009-03-12
JP4759057B2 (ja) 2011-08-31
EP1922623B1 (en) 2013-07-10
EP1922623A4 (en) 2009-04-29
KR20080038441A (ko) 2008-05-06
US20100274955A1 (en) 2010-10-28
US8069302B2 (en) 2011-11-29

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