KR100950569B1 - 정확한 메모리 읽기 동작을 위한 회로 - Google Patents
정확한 메모리 읽기 동작을 위한 회로 Download PDFInfo
- Publication number
- KR100950569B1 KR100950569B1 KR1020057009918A KR20057009918A KR100950569B1 KR 100950569 B1 KR100950569 B1 KR 100950569B1 KR 1020057009918 A KR1020057009918 A KR 1020057009918A KR 20057009918 A KR20057009918 A KR 20057009918A KR 100950569 B1 KR100950569 B1 KR 100950569B1
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- South Korea
- Prior art keywords
- cell
- memory cell
- bit
- memory
- current
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Abstract
Description
Claims (10)
- 읽기 동작 동안 타겟 셀(305)에서의 전류를 감지하는 메모리 회로 장치로서,접지(365)에 연결되는 제 1 비트 라인(316)을 갖는 상기 타겟 셀(305)과, 상기 타겟 셀(305)은 감지 회로(360)에 연결되는 제 2 비트 라인(321)을 가지며;상기 타겟 셀(305)에 인접하는 제 1 이웃 셀(355)과, 상기 제 1 이웃 셀(355)은 상기 제 2 비트 라인(321)을 상기 타겟 셀(305)과 공유하며, 상기 제 1 이웃 셀(355)은 상기 읽기 동작 동안 상기 감지 회로(360)에 연결되는 제 3 비트 라인(341)을 가지며;상기 제 1 이웃 셀(355)에 인접하는 제 2 이웃 셀(370)과, 상기 제 2 이웃 셀(370)은 상기 제 3 비트 라인(341)을 상기 제 1 이웃 셀(355)과 공유하며, 상기 제 2 이웃 셀(370)은 상기 읽기 동작 동안 프리차지 회로(380)에 연결되는 제 4 비트 라인(351)을 가지며; 그리고상기 제 2 이웃 셀(370)에 인접하는 제 3 이웃 셀(372)을 포함하여 구성되며, 여기서 상기 제 3 이웃 셀(372)은 상기 제 4 비트 라인(351)을 상기 제 2 이웃 셀(370)과 공유하며, 상기 제 3 이웃 셀(372)은 상기 읽기 동작 동안 상기 프리차지 회로(380)에 연결되는 제 5 비트 라인(375)을 가지는 것을 특징으로 하는 메모리 회로 장치.
- 삭제
- 제1항에 있어서,상기 타겟 셀(305), 상기 제 1 이웃 셀(355), 및 상기 제 2 이웃 셀(370) 각각은 공통 워드 라인(325)에 연결되는 각각의 게이트 단자를 포함하는 것을 특징으로 하는 메모리 회로 장치.
- 제1항 또는 제3항에 있어서,상기 타겟 셀(305)은 제 1 비트(382) 및 제 2 비트(384)를 저장하는 것을 특징으로 하는 메모리 회로 장치.
- 삭제
- 삭제
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- 삭제
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/313,444 US6731542B1 (en) | 2002-12-05 | 2002-12-05 | Circuit for accurate memory read operations |
US10/313,444 | 2002-12-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050084090A KR20050084090A (ko) | 2005-08-26 |
KR100950569B1 true KR100950569B1 (ko) | 2010-04-01 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020057009918A KR100950569B1 (ko) | 2002-12-05 | 2003-07-24 | 정확한 메모리 읽기 동작을 위한 회로 |
Country Status (9)
Country | Link |
---|---|
US (1) | US6731542B1 (ko) |
EP (1) | EP1573746B1 (ko) |
JP (1) | JP2006509324A (ko) |
KR (1) | KR100950569B1 (ko) |
CN (1) | CN1714409A (ko) |
AU (1) | AU2003256718A1 (ko) |
DE (1) | DE60325509D1 (ko) |
TW (1) | TWI328815B (ko) |
WO (1) | WO2004053885A1 (ko) |
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US5027321A (en) * | 1989-11-21 | 1991-06-25 | Intel Corporation | Apparatus and method for improved reading/programming of virtual ground EPROM arrays |
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EP1573746B1 (en) | 2008-12-24 |
EP1573746A1 (en) | 2005-09-14 |
CN1714409A (zh) | 2005-12-28 |
WO2004053885A1 (en) | 2004-06-24 |
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JP2006509324A (ja) | 2006-03-16 |
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