KR100930496B1 - Array substrate and method for manufacturing same - Google Patents

Abstract

An array substrate and a method of manufacturing the same are disclosed to improve line repair success rates. A repair line is formed on a substrate on which a plurality of unit pixels are formed, and the repair line intersects with a signal line providing a driving signal to the plurality of unit pixels with a first insulating film interposed therebetween. If a defect occurs in the signal line, the repair line is electrically connected to the signal line and performs the role of the signal line instead. On the first insulating film on which the signal line is formed, a second insulating film having an opening for exposing a section where the signal line and the repair line cross each other is formed. Therefore, the line repair success rate of the array substrate can be improved.

Description

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

1 is a plan view illustrating an array substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the array substrate illustrated in FIG. 1.

3 is a plan view illustrating a repaired state of a specific data line.

4 is a cross-sectional view of the array substrate illustrated in FIG. 3 taken along a cutting line A-A`.

5A through 5D are cross-sectional views illustrating a manufacturing process of the array substrate illustrated in FIG. 2.

<Explanation of symbols for the main parts of the drawings>

100: array substrate 110: substrate

120: unit pixel 121: TFT

122: pixel electrode 130: organic insulating film

133: opening DL: data line

GL: Gate Line RL: Repair Line

The present invention relates to an array substrate and a method for manufacturing the same, and more particularly, to an array substrate and a method for manufacturing the same that can improve the line repair success rate.

Recently, an information processing device requires a display device that serves as an interface so that a user may visually check the information processed by the information processing device. A liquid crystal display is a typical display device, which applies a voltage to a specific molecular array of a liquid crystal to convert it into another molecular array, and converts a change in optical properties into a visual change. to be.

In order to be driven by this principle, the liquid crystal display includes a thin film transistor (TFT) substrate, a color filter substrate facing the TFT substrate, and a liquid crystal layer interposed between the TFT substrate and the color filter substrate. Is done. The TFT substrate is a substrate in which a unit pixel consisting of a gate line transferring a scan signal, a data line transferring an image signal, a TFT connected to the gate line and the data line, and a pixel electrode connected to the TFT is formed in a matrix form. The TFT is driven by a scan signal applied through the gate line to apply an image signal provided through the data line to the pixel electrode.

Since each of the gate lines and the data lines is formed for each pixel, each of the wirings is formed with a very fine size of micrometer or less. Therefore, in the manufacturing process of the TFT substrate, there is a possibility that a defect occurs due to disconnection of the wiring or a short circuit between the wirings.                         

In order to repair such a defect, a technique of forming a repair line for installing an additional wiring configuration, that is, an auxiliary wiring considering a repairing case, is generally used. Normally, the repair line is electrically separated from the respective wirings by the boundary of the insulating film. For example, when a data line of a specific site is disconnected, a section in which the repair line and the disconnected data line cross each other is welded with a laser. Thus, through the repair line, a signal arrives at the disconnected data line which is arranged opposite to the disconnection site. Therefore, even if the data line is disconnected, the unit pixels connected to the data line operate normally.

Such a structure is described in detail in US Pat. No. 6,317,176 and US Pat. No. 6,014,191, filed by the Applicant.

However, on the data line, a protective film formed of an organic insulating layer is interposed between the pixel electrode and the data line to form pixel electrodes for each unit pixel. In general, the protective film is formed to a thickness of about 2㎛ to 3㎛. After the welding of the data line and the repair line by the protective film, the rate at which the data line and the repair line are normally connected is reduced, thereby increasing the defective rate.

In addition, a contact resistance is generated at a portion where the data line and the repair line contact each other. The contact resistance is determined according to the contact area, and the load applied to the lines is determined by the contact area between the data line and the repair line. In order to reduce the load on the respective lines, a structure capable of increasing the contact area between the data line and the repair line is needed.

Accordingly, it is a first object of the present invention to provide an array substrate for improving the line repair success rate.

It is also a second object of the present invention to provide a method of manufacturing the above array substrate.

According to another aspect of the present invention, an array substrate includes: a repair line formed on a substrate on which a plurality of unit pixels are formed; A first insulating film formed on the substrate on which the repair line is formed; A signal line formed on the first insulating layer to intersect the repair line and applying a driving signal to the plurality of unit pixels; And a second insulating film formed on the first insulating film on which the signal line is formed and having an opening exposing the signal line in a section where the signal line and the repair line cross each other.

In addition, the method of manufacturing an array substrate according to the present invention for achieving the second object of the present invention, forming a repair line on a substrate on which a plurality of unit pixels are formed; Forming a first insulating film on the substrate on which the repair line is formed; Forming a signal line intersecting the repair line and providing a driving signal to the plurality of unit pixels on the first insulating layer; And forming a second insulating film on the first insulating film on which the signal line is formed, the second insulating film having an opening exposing the signal line in a section where the signal line and the repair line cross each other.                     

According to such an array substrate and a method of manufacturing the same, a signal line intersecting the repair line with a repair line and a first insulating layer therebetween is provided on the substrate. On the first insulating film on which the signal line is formed, a second insulating film having an opening for exposing a section where the signal line and the repair line cross each other is formed. Therefore, the line repair success rate of the array substrate can be improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

In general, a poly-si liquid crystal display device includes an array substrate, a color filter substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate. Hereinafter, the present invention will be described in detail with reference to an array substrate used in the poly-si liquid crystal display.

1 is a plan view illustrating an array substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the array substrate illustrated in FIG. 1.

1 and 2, an array substrate 100 according to an exemplary embodiment of the present invention may include a display area D in which a plurality of unit pixels 120 are formed, and a peripheral area formed around the display area D. (S) consists of. The display area D is an area in which the plurality of unit pixels 120 are formed in a matrix form on the substrate 110, and the peripheral area S is a driving signal for driving the plurality of unit pixels 120. Is an area where pads are formed to receive externally.

A gate line GL extending in a first direction and a data line DL extending in a second direction orthogonal to the first direction are formed in the display area D, and the TFT 121 is connected to the gate line GL. The gate line GL and the data line DL are connected to each other in a region partitioned by GL and the data line DL. That is, the gate electrode 121c of the TFT 121 is connected to the gate line GL, and the source electrode 121e is connected to the data line DL. In addition, the drain electrode 121f of the TFT 121 is connected to the pixel electrode 122.

In detail, the poly-si layer 121a, the gate insulating layer 121b formed thereon, and the gate electrode 121c formed on the gate insulating layer 121b are provided on the substrate 110. Thereafter, the poly-si layer 121a is doped with boron (B) or phosphorus (P) to form an n or p channel. In addition, an interlayer insulating layer 121d having first and second contact holes for exposing a portion of the poly-si layer 121a is formed on the gate insulating layer 121b on which the gate electrode 121c is formed. The source electrode 121e electrically connected to the poly-si layer 121a through the first contact hole and the poly-si layer 121a through the second contact hole are disposed on the interlayer insulating layer 121d. The connected drain electrode 121f is formed.

Subsequently, a passivation layer 130 is formed on the substrate 110 on which the source and drain electrodes 121e and 121f are formed, and the third contact hole 131 is formed to expose a portion of the drain electrode 121f. The passivation layer 130 is formed of an organic insulating layer such as a photosensitive acrylic resin. The pixel electrode 122, which is a transparent electrode electrically connected to the drain electrode 121f through the third contact hole 131, is formed on the passivation layer 130. The pixel electrode 122 is formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

The peripheral area S may include a gate peripheral area in which a gate pad extending from one end of the gate line GL is formed, and a data peripheral area in which a data pad extending from one end of the data line DL is formed.

The repair line RL for repairing the data line DL intersects one end of the data line DL in the data peripheral area. The repair line RL extends through the display area D and intersects at the other end of the data line DL facing the one end. Although a repair line RL for repairing the data line DL is shown in the drawing, the array substrate 100 may further include a repair line for repairing the gate line GL.

In detail, the repair line RL is formed on the gate insulating layer 121b by the same process as the gate electrode 121c. The interlayer insulating layer 121d is formed on the substrate 110 on which the repair line RL is formed, and the data formed by the same process as the source and drain electrodes 121e and 121f on the interlayer insulating layer 121d. Line DL is provided. The passivation layer 130 is formed on the substrate 110 on which the data line DL is formed.

A fourth contact hole 133 is formed in the passivation layer 130 to expose the data line DL at a portion where the data line DL and the repayment line RL cross each other. Since the repair line RL crosses each of the data lines DL, the fourth contact hole 133 is formed in the passivation layer 130 corresponding to the crossing section. The fourth contact hole 133 may be formed to be larger than the cross section.

3 is a plan view illustrating a repaired state of a specific data line, and FIG. 4 is a cross-sectional view of the array substrate illustrated in FIG. 3 taken along a cutting line A-A '.

3 and 4, a repair line RL extending in a specific direction is disposed on the substrate 110, and the repair line RL has a specific defect generated between the interlayer insulating layers 121d therebetween. Orthogonal to the data line DL. The passivation layer 130 is disposed on the substrate 110 on which the specific data line DL is formed, and the passivation layer 130 is disposed at a portion where the specific data line DL and the repair line RL cross each other. A fourth contact hole 133 is formed to expose a specific data line.

When a defect occurs in the specific data line DL, the specific data line DL is electrically connected to the repair line RL. For example, when the specific data line DL is disconnected, a signal cannot be applied to a plurality of unit pixels (not shown) connected to the specific data line DL after the disconnected point. In this case, the plurality of unit pixels connected to the specific data line DL may be normally driven by electrically connecting the specific data line DL to the repair line RL.

In general, in order to electrically connect the specific data line DL and the repair line RL, laser light is irradiated to the first and second points p1 and p2 so that the specific data line DL and the repair line RL are electrically connected. A method of welding the repair line RL is used. Specifically, when the laser light is irradiated at the first and second points, the interlayer insulating layer 121d is destroyed by the laser light. The specific data line DL penetrates through the broken interlayer insulating layer 121d and is electrically connected to the repair line RL.

As shown in FIG. 4, the passivation layer 130 is removed by the fourth contact hole 133 at the first and second points p1 and p2 to which the laser light is irradiated. Therefore, the success rate of the repair process for electrically connecting the specific data line DL and the repair line RL at the first and second points p1 and p2 during the laser light irradiation may be increased.

In addition, since the upper surface and the sidewalls of the specific data line DL are exposed to the outside through the opening 133, the area where the repair line RL and the specific data line DL contact each other when laser light is irradiated. Is increased. When the contact area is improved, the contact resistance between the specific data line DL and the repair line RL is reduced. As the contact area between the specific data line DL and the repair line RL increases, the load on the specific data lines DL may be reduced. Therefore, it is possible to prevent the delay of the video signal applied through the repair line RL.

5A through 5D are cross-sectional views illustrating a manufacturing process of the array substrate illustrated in FIG. 2.

Referring to FIG. 5A, the a-si layer is deposited on the display region D of the substrate 110 at about 540 ° C. by using Low Plasma Chemical Vapor Deposition (LPCVD). Thereafter, the a-si layer is heat-treated at about 600 ° C. for a long time to crystallize to form a poly-si layer 121a. In order to increase crystallinity, silicon ion implantation may be performed before crystallization. Thereafter, the poly-si layer 121a is patterned through a dry etching process.

Next, an oxide layer is formed on the ploy-si layer 121a by reacting the poly-si layer 121a with oxygen. The oxide film is used as the gate insulating film 121b. Thereafter, a gate electrode layer (not shown) is formed on the gate insulating layer 121b, and then the gate electrode layer is patterned. Accordingly, a gate electrode 121c is formed in the display area D, and a repair line RL is formed in the peripheral area S. FIG.

Referring to FIG. 5B, after the gate electrode 123 and the repair line RL are formed, an ion implantation process for doping the poly-si layer 121a is performed. In other words, it is doped with boron (B) to make a p-type TFT, and doped with phosphorus (P) to make an n-type TFT. One of boron (B) and phosphorus (P) is injected into the poly-si layer 121a to determine an n channel or a p channel.

Thereafter, an interlayer insulating layer 126 on which the gate electrode 123 and the repair line RL are formed is deposited. First and second contact holes are formed in the interlayer insulating layer 126, respectively.

Next, a source electrode 121e is formed on the interlayer insulating layer 121d to be connected to the poly-si layer 121a through the first contact hole to correspond to the display area D, and the second contact hole is formed. A drain electrode 121f is formed to be connected to the poly-si layer 121a through. Thus, the poly-si TFT 121 is completed in the display area D. FIG.

The data line DL is formed on the interlayer insulating layer 121d through the same process as the source and drain electrodes 121e and 121f corresponding to the peripheral region S.

Referring to FIG. 5C, a photosensitive organic insulating layer 135 is formed over the entire surface of the display area D and the peripheral area S on which the poly-si TFT 120 is formed.

As shown in FIG. 5D, a mask 137 having first and second openings 137a and 137b is disposed on the photosensitive organic insulating layer 135. In detail, the first opening 137a is formed in a region where a third contact hole 131 is formed to expose the drain electrode 121f of the poly-si TFT 121. In addition, the second opening 137b is formed in a region where the fourth contact hole 133 is formed to expose the data line DL at a portion where the repair line RL and the data line DL intersect each other. do.

When the photosensitive organic insulating layer 135 is exposed while the mask 137 is disposed, the photosensitive organic insulating layer 135 is full-exposed at portions exposed by the first and second openings 137a and 137b. do. Subsequently, when the array substrate 100 is reacted with a developer, the mask 137 is removed to form a passivation layer 130 on which the third and fourth contact holes 131 and 133 are formed. .

Next, as illustrated in FIG. 2, a pixel electrode 122 is formed on the passivation layer 130 to be electrically connected to the drain electrode 122f through the third contact hole 131. The pixel electrode 122 is made of any one of ITO and IZO, which are transparent conductive materials. Thus, the array substrate 100 used in the poly-si liquid crystal display device is completed.

In the above, the array substrate 100 used in the poly-si liquid crystal display is described as an embodiment of the present invention. However, the present invention is not limited to the poly-si liquid crystal display device, and is a structure that can be sufficiently applied to the array substrate used for the a-si liquid crystal display device.

According to such an array substrate and a method of manufacturing the same, a signal line intersecting the repair line with a repair line and a first insulating layer therebetween is provided on the substrate. On the first insulating film on which the signal line is formed, a second insulating film having an opening for exposing a section where the signal line and the repair line cross each other is formed.

Therefore, the second insulating film formed at the portion where the signal line and the repair line cross each other is opened, thereby facilitating welding of the signal line and the repair line, and improving the success rate of line repair of the array substrate.

In addition, the contact resistance between the signal line and the repair line may be reduced by increasing the area where the repair line and the signal line contact each other. Furthermore, the load on the repair line may be reduced to prevent a delay of an image signal applied through the repair line.

Although described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (7)

A repair line formed on a substrate on which a plurality of unit pixels are formed; A first insulating film formed on the substrate on which the repair line is formed; A signal line formed on the first insulating layer to intersect the repair line and applying a driving signal to the plurality of unit pixels; And And a second insulating film formed on the first insulating film on which the signal line is formed and having an opening for exposing an upper portion of the signal line in a section where the signal line and the repair line cross each other. The array substrate of claim 1, wherein the opening is wider than an area where the repair line and the signal line cross each other. The array substrate of claim 1, wherein the repair line and the signal line are connected by laser welding a point where an end portion of the repair line and the signal line intersects in a region where the repair line and the signal line intersect. The display device of claim 1, wherein the unit pixel comprises a TFT and a pixel electrode connected to a drain electrode of the TFT. And said signal line comprises a gate line connected to a gate electrode of said TFT, and a data line orthogonal to said gate line and connected to a source electrode of said TFT. The array substrate of claim 4, wherein the TFT is a poly-crystallize-silicon TFT. Forming a repair line on a substrate on which a plurality of unit pixels are formed; Forming a first insulating film on the substrate on which the repair line is formed; Forming a signal line intersecting the repair line and providing a driving signal to the plurality of unit pixels on the first insulating layer; And And forming a second insulating film on the first insulating film on which the signal line is formed, the second insulating film having an opening exposing an upper portion of the signal line in a section where the signal line and the repair line cross each other. The method of claim 6, wherein the forming of the second insulating film, Forming an entire photosensitive organic insulating film on the first insulating film on which the signal line is formed; Disposing a mask having a pattern corresponding to the crossing section on the photosensitive organic insulating layer; And Exposing and developing the photosensitive organic insulating film to form the second insulating film having the opening.

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