CN101621038B - Manufacturing method of active element array base plate - Google Patents
Manufacturing method of active element array base plate Download PDFInfo
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- CN101621038B CN101621038B CN2008101279280A CN200810127928A CN101621038B CN 101621038 B CN101621038 B CN 101621038B CN 2008101279280 A CN2008101279280 A CN 2008101279280A CN 200810127928 A CN200810127928 A CN 200810127928A CN 101621038 B CN101621038 B CN 101621038B
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Abstract
The invention discloses a manufacturing method of an active element array base plate. Firstly, a plurality of grid electrodes and a plurality of scanning lines are formed in the displaying zone of the substrate, and at least one short circuit bar is formed in the peripheral circuit zone of the substrate; then, an insulation layer and a semiconductor material layer are formed on the substrate in order, and a patterned photoresist layer is formed on the semiconductor material layer; parts of semiconductor material layer and insulation layer are removed to form a plurality of contact holes; parts of patterned photoresist layer are removed; parts of semiconductor material layer are removed to define a plurality of path layers; parts of patterned photoresist layer are removed; then, a plurality of data lines are formed, a source electrode and a drain electrode are formed on each path layer, and the data lines extend from the displaying zone to the peripheral circuit zone and is connected with the short circuit bar via the contact holes.
Description
Technical field
The invention relates to a kind of active elements array substrates with and manufacture method, and particularly relevant for a kind of active elements array substrates that is applied to video display with and manufacture method.
Background technology
The technology of display has developed the out-of-plane display at present, LCD (Liquid CrystalDisplay for example, LCD), organic light emitting diode display (Organic Light Emitting Diode, OLED) and plasma display (Plasma Display Panel, PDP) etc.Yet no matter be any flat display apparatus, it all must detect in manufacture process so that determine can normal operation.
With Thin Film Transistor-LCD (Thin Film Transistor LCD, TFT LCD) is example, it comprises a thin-film transistor array base-plate (TFT array substrate), and thin-film transistor array base-plate must be to its pixel and signal line after manufacturing is finished, just scan line and data wire detect, can normal operation to determine Thin Film Transistor-LCD.
Figure 1A is the schematic top plan view of known a kind of thin-film transistor array base-plate, and Figure 1B is the generalized section of Figure 1A I-I ' along the line.Please consult Figure 1A earlier, the detection method of thin-film transistor array base-plate 100 is short bar (shorting bar) detection method, and thin-film transistor array base-plate 100 comprises a substrate 110, a plurality of dot structure 120, many barss circuit 130, a short bar 140 and a plurality of contact structures 150a and 150b.
Please consult Figure 1A and Figure 1B simultaneously, in non-display area 114, also comprise an indium tin oxide layer (IndiumTin Oxide layer, ITO layer) 160, wherein these contact structures 150a is between indium tin oxide layer 160 and short bar 140, and these contact structures 150b is between indium tin oxide layer 160 and these data wires 134.Therefore, be to electrically connect between data wire 134 and the short bar 140 through the setting of indium tin oxide layer 160 and two contact structures 150a, 150b.
Because short bar 140 sees through these contact structures 150a, 150b and indium tin oxide layer 160 electrically connects these data wires 134 indirectly.Whether so, when desiring to detect step, can see through short bar 140 test signal is imported to detect these data wires 134, detecting these dot structures 120 simultaneously can normal operation.Similarly, the part at scan line 132 ends also is to see through short bar (not illustrating) to come input test signal.
Generally speaking, data wire 134 is generally metal with the material of short bar 140, but in order to the resistance coefficient of indium tin oxide layer 160 that data wire 134 and short bar 140 the are electrically connected resistance coefficient much larger than metal.Therefore, there is higher resistance between short bar 140 and these data wires 134.Secondly, must see through two contact structures 150a, 150b between each data wire 134 and the short bar 140 and electrically connect, therefore can occupy the limited area of substrate 110.
Summary of the invention
The invention provides a kind of manufacture method of active elements array substrates, with the short bar of reduction active elements array substrates and the resistance between many barss circuit.
The invention provides a kind of manufacture method of active elements array substrates, can occupy the problem of many areas with contact structures in the solution non-display area.
The present invention proposes a kind of manufacture method of active elements array substrates.At first, provide a substrate, it has a viewing area and a perimeter circuit district.Then, the multi-strip scanning line that in the viewing area, forms a plurality of grids and be connected with these grids, and form at least one first short bar simultaneously in the perimeter circuit district.Afterwards, form an insulating barrier, it covers these grids, these scan lines and first short bar.Then, form the semiconductor material layer on insulating barrier.Next, on semiconductor material layer, form a patterning photoresist layer, wherein the patterning photoresist layer has a plurality of first openings that are positioned at first short bar top, with the exposure semiconductor material layer, and be positioned at the thickness of the thickness of the patterning photoresist layer above these grids greater than the patterning photoresist layer that is positioned at other part., remove, to form a plurality of first contact holes by these first semiconductor material layer that opening exposes and insulating barrier thereupon.Afterwards, keep the patterning photoresist layer that is positioned at the grid top, and remove other patterning photoresist layer partly.Then, remove and be not patterned the semiconductor material layer that photoresist layer covers, to define a plurality of channel layers.Then, remove the patterning photoresist layer of grid top.Next, on the insulating barrier of viewing area, form many data wires, an and formation one source pole and a drain electrode on each channel layer, and these data wires extend perimeter circuit district and meeting cross-over connection first short bar, and wherein these data wires can directly see through these first contact holes and connect first short bar.
In an embodiment of the present invention, also be included in formation one protective layer (passivation layer) on the insulating barrier.Then, form a plurality of pixel electrodes on protective layer, wherein these pixel electrodes electrically connect these drain electrodes.
In an embodiment of the present invention, the above-mentioned method that removes other patterning photoresist layer partly comprises the patterning photoresist layer is carried out plasma ashing (ashing) processing procedure.
In an embodiment of the present invention, the method for these first contact holes of above-mentioned formation comprises semiconductor material layer and insulating barrier is carried out etch process.
In an embodiment of the present invention, these scan lines extend to the perimeter circuit district, and the patterning photoresist layer has more a plurality of second openings that are positioned at perimeter circuit district and these scan lines top, it exposes semiconductor material layer, and the manufacture method of above-mentioned active elements array substrates also comprises after forming the patterning photoresist layer, remove by these second semiconductor material layer that opening exposes and insulating barrier, to form a plurality of second contact holes.Then, after the patterning photoresist layer above removing grid, form at least one second short bar in the perimeter circuit district, wherein second short bar and these data wires form simultaneously, and second short bar can directly see through these second contact holes and connect these scan lines.
In an embodiment of the present invention, the method for these first contact holes of above-mentioned formation and these second contact holes comprises semiconductor material layer and insulating barrier is carried out etch process.
In an embodiment of the present invention, the method for above-mentioned formation semiconductor material layer comprises, at first, forms a channel material layer on insulating barrier.Then, form an ohmic contact material layer on the channel material layer.
In an embodiment of the present invention, the above-mentioned method that is not patterned the semiconductor material layer that photoresist layer covers that removes comprises, at first, removes and is not patterned this ohmic contact material layer that photoresist layer covers.Then, remove and be not patterned the channel material layer that photoresist layer covers.
In an embodiment of the present invention, the manufacture method of above-mentioned active elements array substrates comprised before forming protective layer and carries out a backward channel etch process.
In an embodiment of the present invention, the manufacture method of above-mentioned active elements array substrates also comprises, forms a flatness layer (planarization layer) on protective layer.Then, on flatness layer, form these pixel electrodes.
The present invention proposes a kind of manufacture method of active elements array substrates in addition.At first, provide a substrate, it has a viewing area and a perimeter circuit district.Then, the multi-strip scanning line that in the viewing area, forms a plurality of grids and be connected with these grids, wherein these scan lines extend the perimeter circuit district.Afterwards, form an insulating barrier, it covers these grids and these scan lines.Then, form the semiconductor material layer on insulating barrier.Next, on semiconductor material layer, form a patterning photoresist layer, wherein the patterning photoresist layer has a plurality of openings that are positioned at perimeter circuit district and these scan lines top, it exposes semiconductor material layer, and is positioned at the thickness of the thickness of the patterning photoresist layer above these grids greater than the patterning photoresist layer that is positioned at other part., remove, to form a plurality of contact holes by semiconductor material layer that these openings expose and insulating barrier thereupon.Then, keep the patterning photoresist layer that is positioned at the grid top, and remove other patterning photoresist layer partly.Afterwards, remove and be not patterned the semiconductor material layer that photoresist layer covers, to define a plurality of channel layers.Then, remove the patterning photoresist layer of grid top.Then, form many data wires, a plurality of source electrode, a plurality of drain electrode and at least one short bars on the insulating barrier of viewing area, wherein short bar can cross-over connection extend to these scan lines in perimeter circuit district, and directly connects these scan lines through these contact holes.Afterwards, on insulating barrier, form a protective layer.Then, form a plurality of pixel electrodes on protective layer, wherein these pixel electrodes electrically connect these drain electrodes.
In an embodiment of the present invention, the above-mentioned method that removes other patterning photoresist layer partly comprises the patterning photoresist layer is carried out the plasma ashing processing procedure.
In an embodiment of the present invention, the method for above-mentioned these contact holes of formation comprises semiconductor material layer and insulating barrier is carried out etch process.
In an embodiment of the present invention, the method for above-mentioned formation semiconductor material layer comprises, forms a channel material layer on insulating barrier.Then, form an ohmic contact material layer on the channel material layer.
In an embodiment of the present invention, the above-mentioned method that is not patterned the semiconductor material layer that photoresist layer covers that removes comprises, removes and is not patterned the ohmic contact material layer that photoresist layer covers.Then, remove and be not patterned the channel material layer that photoresist layer covers.
In an embodiment of the present invention, the manufacture method of above-mentioned active elements array substrates also comprised before forming protective layer and carries out a backward channel etch process.
In an embodiment of the present invention, the manufacture method of above-mentioned active elements array substrates also comprises, forms a flatness layer on protective layer.Then, on flatness layer, form these pixel electrodes.
Short bar of the present invention is directly connected in these scan lines or these data wires by these contact structures, so the present invention can reduce the resistance between short bar and these scan lines effectively, or reduces the resistance between short bar and these data wires.So, the accuracy of detection active elements array substrates is improved.
In addition, the present invention can also reduce the quantity that short bar electrically connects the required contact structures of these scan lines and these data wires, so the area in the perimeter circuit district of active elements array substrates is dwindled.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A is the schematic top plan view of known a kind of thin-film transistor array base-plate.
Figure 1B is the generalized section of Figure 1A I-I ' along the line.
Fig. 2 A is the schematic top plan view of the active elements array substrates of one embodiment of the invention.
Fig. 2 B is the generalized section of Fig. 2 A J-J ' along the line.
Fig. 3 A to Fig. 3 K is the generalized section of the manufacture method of the active elements array substrates among Fig. 2 B.
Embodiment
Fig. 2 A is the schematic top plan view of the active elements array substrates of one embodiment of the invention, and Fig. 2 B is the generalized section of Fig. 2 A J-J ' along the line.Please consult Fig. 2 A and Fig. 2 B simultaneously, active elements array substrates 200 comprises a substrate 210, a plurality of dot structure 220, multi-strip scanning line 230a, many data wire 230b, at least one first short bar 240a and a plurality of first contact structures 250a.
These scan lines 230a and these data wires 230b extend to perimeter circuit district 214, and these data wires 230b that wherein extends to perimeter circuit district 214 can the cross-over connection first short bar 240a.In addition, in the present embodiment, the bearing of trend of the first short bar 240a is identical with the bearing of trend of these scan lines 230a, and the first short bar 240a can also be parallel in fact with these scan lines 230a, shown in Fig. 2 A.
These first contact structures 250a and contacts the first short bar 240a and these data wires 230b between the first short bar 240a and these data wires 230b.Therefore, the first short bar 240a is seen through these first contact structures 250a and is electrically connected these data wires 230b.
In addition, the material of these first contact structures 250a is identical with the material of these data wires 230b, and one of them first contact structures 250a and connected data wire 230b can also be integrally formed.In the present embodiment, the material of scan line 230a and data wire 230b is a metal, and the material of these first contact structures 250a can also be metal.
What deserves to be mentioned is that though Fig. 2 A and Fig. 2 B only illustrate one first short bar 240a, in the embodiment that other does not illustrate, at different product demands, active elements array substrates 200 can comprise two or more the first short bar 240a.Therefore, emphasize that the quantity of the first short bar 240a shown in Fig. 2 A is for illustrating, and non-limiting the present invention at this.
Each dot structure 220 can comprise an active element 222 and a pixel electrode 224, and in same dot structure 220, active element 222 electrically connects pixel electrode 224.Active element 222 for example is a thin-film transistor, and can comprise a channel layer C, a grid G, a drain D and one source pole S, shown in Fig. 2 B.In addition, active element 222 also can comprise an ohmic contact layer O, and it is positioned on the channel layer C.
In the present embodiment, active elements array substrates 200 also comprises at least one second short bar 240b and a plurality of second contact structures 250b, and wherein the second short bar 240b and these second contact structures 250b all are disposed in the perimeter circuit district 214.Second short bar 240b meeting cross-over connection extends to these scan lines 230a in perimeter circuit district 214, and these second contact structures 250b is between the second short bar 240b and these scan lines 230a.
These second contact structures 250b can contact the second short bar 240b and these scan lines 230a.Therefore, by these second contact structures 250b, the second short bar 240b is directly electrically connected these scan lines 230a.In addition, in the present embodiment, the bearing of trend of the second short bar 240b is identical with the bearing of trend of these data wires 230b, and the second short bar 240b more can be parallel in fact with these data wires 230b.
In addition, the material of these second contact structures 250b is identical with the material of the second short bar 240b, and the second short bar 240b and these second contact structures 250b can also be integrally formed.In the present embodiment, the material of the second short bar 240b can be a metal, and the material of these second contact structures 250b can also be a metal.
Though Fig. 2 A and Fig. 2 B only illustrate one second short bar 240b.But in the embodiment that other does not illustrate, active elements array substrates 200 can comprise two or more the second short bar 240b.Therefore, the quantity of the second short bar 240b shown in Fig. 2 A and Fig. 2 B is only for illustrating, and non-limiting the present invention.
In addition, mandatory declaration is that at the design and the demand of different product, the active elements array substrates 200 of present embodiment can not comprise the first short bar 240a or the second short bar 240b.Specifically, active elements array substrates 200 can comprise the one or more the first short bar 240a, and does not comprise any second short bar 240b, or, active elements array substrates 200 can comprise the one or more the second short bar 240b, and does not comprise any first short bar 240a.Therefore, the active elements array substrates 200 shown in Fig. 2 A and Fig. 2 B only illustrates, and non-limiting the present invention.
Below only introduce the structure of the active elements array substrates 200 of present embodiment.Next, will cooperate Fig. 3 A to Fig. 3 K, the manufacture method of active elements array substrates 200 will be described in detail.
Fig. 3 A to Fig. 3 K is the generalized section of the manufacture method of the active elements array substrates among Fig. 2 B.See also Fig. 3 A, at first, provide a substrate 210, wherein substrate 210 has viewing area 212 and perimeter circuit district 214.
Then, these scan lines 230a (Fig. 3 A to Fig. 3 K only illustrates a grid G and a scan line 230a) that in viewing area 212, forms a plurality of grid G and is connected, and while formation at least one the first short bar 240a in perimeter circuit district 214 with these grid G.
See also Fig. 3 B, afterwards, form an insulating barrier 260, it covers these grid G, these scan lines 230a and the first short bar 240a.Insulating barrier 260 can be made by silicon dioxide, silicon nitride or other insulating material.
Please consult Fig. 3 C and Fig. 3 D simultaneously, then, form semiconductor material layer 270 on insulating barrier 260, wherein the material of semiconductor material layer 270 can be amorphous silicon (amorphous-silicon, a-Si), polysilicon (polysilicon) or other suitable semi-conducting material.
In addition, in the present embodiment, semiconductor material layer 270 can comprise a channel material layer C ' and an ohmic contact material layer O ', and the method for formation semiconductor material layer 270 can may further comprise the steps.At first, form channel material layer C ' (shown in Fig. 3 C) on insulating barrier 260.Then, form ohmic contact material layer O ' and go up (shown in Fig. 3 D) in channel material layer C ', wherein the material of ohmic contact material layer O ' can be the semi-conducting material that the N type mixes.
See also Fig. 3 E, next, form a patterning photoresist layer 280 on semiconductor material layer 270, the thickness of patterning photoresist layer 280 that wherein is positioned at these grid G tops is greater than the thickness that is positioned at other patterning photoresist layer 280 partly.That is to say that the thickness of patterning photoresist layer 280 is not identical.
In addition, patterning photoresist layer 280 has a plurality of first openings 282 that are positioned at first short bar 240a top
(Fig. 3 E and Fig. 3 F only illustrate one).These first openings 282 can expose semiconductor material layer 270, and for example these first openings 282 can expose ohmic contact material layer O '.
The method of formation patterning photoresist layer 280 has a variety of, and proposes wherein a kind of formation method of patterning photoresist layer 280 at this.Patterning photoresist layer 280 can be by being that exposure and the developing manufacture process that mask was carried out forms with a photomask 300, and photomask 300 has at least one transparent area 302, at least one part transparent area 304 and at least one light tight district 306, and wherein the light transmittance of part transparent area 304 is between the light transmittance of light tight district 306 and transparent area 302.Therefore, photomask 300 can be the photomask of half mode (half-tone) photomask or other and photomask 300 structural similarities.
The material of patterning photoresist layer 280 can be eurymeric photoresist (positive photoresist) or negative photoresist (negative photoresist), and the patterning photoresist layer 280 shown in Fig. 3 E is to be example with the eurymeric photoresist.Therefore, patterning photoresist layer 280 can form these first openings 282 in the part of corresponding transparent area 302, and the part of patterning photoresist layer 280 in the light tight district 306 of correspondence has thicker thickness.
In addition, in the present embodiment, patterning photoresist layer 280 has more a plurality of second openings 284 (Fig. 3 E and Fig. 3 F only illustrate) that are positioned at perimeter circuit district 214 and these scan lines 230a top.These second openings 284 can expose semiconductor material layer 270, and for example these second openings 284 can expose ohmic contact material layer O '.
Please consult Fig. 3 E and Fig. 3 F simultaneously, then, remove the semiconductor material layer 270 and insulating barrier 260 that are exposed by these first openings 282, to form a plurality of first contact hole 252a.The method that forms these first contact holes 252a can be that semiconductor material layer 270 and insulating barrier 260 are carried out etch process.
When forming these first contact holes 252a, can also be removed simultaneously by semiconductor material layer that these second openings 284 expose 270 and insulating barrier 260, forming a plurality of second contact hole 252b, can be identical and form the method for these second contact holes 252b with the first contact hole 252a.That is to say that these second contact holes 252b can be that etching semiconductor material layer 270 forms with insulating barrier 260.
Please consult Fig. 3 F and Fig. 3 G simultaneously, afterwards, remove other patterning photoresist layer 280 partly, be positioned at the patterning photoresist layer 280 of grid G top with reservation.So, partly semiconductor material layer 270 can come out.In the present embodiment, remove other partly the method for patterning photoresist layer 280 can be that patterning photoresist layer 280 is carried out the plasma ashing processing procedure.
Please consult Fig. 3 G and Fig. 3 H simultaneously, then, remove and be not patterned the semiconductor material layer 270 that photoresist layer 280 is covered, to define a plurality of channel layer C (Fig. 3 H only illustrates) and ohmic contact layer O.In the present embodiment, removing the method that is patterned the semiconductor material layer 270 that photoresist layer 280 exposed comprises, at first, remove and be not patterned the ohmic contact material layer O ' that photoresist layer 280 is covered, to define ohmic contact layer O and to expose channel material layer C '.Then, remove and be not patterned the channel material layer C ' that photoresist layer 280 is covered, to define channel layer C.
Please consult Fig. 3 H and Fig. 3 I simultaneously, afterwards, remove the patterning photoresist layer 280 of grid G top.Then, on the insulating barrier 260 of viewing area 212, form many data wire 230b, a plurality of source S and a plurality of drain D (Fig. 3 I to Fig. 3 K only illustrates a source S, a drain D and a data wire 230b).So, these active elements 222 have been made and have been finished.In addition, these data wires 230b extends to perimeter circuit district 214, and can the cross-over connection first short bar 240a.
See also Fig. 3 I, these data wires 230b can directly see through these first contact hole 252a and connect the first short bar 240a.Specifically, these data wires 230b can extend in these first contact holes 252a, and these first contact structures 250a can be formed at respectively in these first contact holes 252a, wherein the material of these first contact structures 250a is identical with these data wires 230b, and these first contact structures 250a and these data wires 230b can form simultaneously.
In addition, when forming these data wires 230b, these source S with these drain D, the whiles at least one the second, short bar 240b also can be formed in the perimeter circuit district 214.That is to say that the second short bar 240b and these data wires 230b form simultaneously.The second short bar 240b can directly see through these second contact hole 252b and connect these scan lines 230a, and these second contact structures 250b can be formed at respectively in these second contact holes 252b.The second short bar 240b is identical with the material of these second contact structures 250b, and the second short bar 240b and these second contact structures 250b can form simultaneously.
See also Fig. 3 J, after these data wires 230b, these source S and drain D and second short bar 240b formation, can carry out a backward channel etch process.Specifically, utilize the mode of plasma etching to remove a part of ohmic contact layer O between source S and drain D.So, source S can directly not be electrically connected at drain D, and is normal with the running of guaranteeing these active elements 222.Then form a protective layer 292 on insulating barrier 260, wherein protective layer 292 can be silicon nitride, silicon dioxide or other appropriate insulation material, and protective layer 292 covers these data wires 230b, these source S and the drain D and the second short bar 240b.
Please participate in Fig. 3 K, then, in one embodiment, can more form a flatness layer 294 on protective layer 292, wherein flatness layer 294 can be by polymer (polymer) or other macromolecular material is formed.
Next, form a plurality of pixel electrodes 224 (Fig. 3 K only illustrates) on protective layer 292, wherein these pixel electrodes 224 electrically connect these drain D.Specifically, flatness layer 294 has the contact hole 294a of a plurality of these drain D of exposure, and these pixel electrodes 224 can extend in these contact holes 294a, and connects these drain D.After these pixel electrodes 224 formed, active elements array substrates 200 had been made and has been finished basically.
It should be noted that, because the active elements array substrates 200 of present embodiment can only comprise at least one the first short bar 240a, and do not comprise any second short bar 240b, or, active elements array substrates 200 can only comprise at least one the second short bar 240b, and do not comprise any first short bar 240a, so the manufacture method of the active elements array substrates 200 shown in Fig. 3 A to Fig. 3 K can not comprise the related procedure of making the first short bar 240a or the second short bar 240b.
Moreover, be familiar with technical field person of the present invention and can from Fig. 3 A to Fig. 3 K and above-mentioned explanation, learn how to make the active elements array substrates 200 that does not comprise the first short bar 240a or the second short bar 240b.Therefore, in this manufacture method of emphasizing the active elements array substrates 200 shown in Fig. 3 A to Fig. 3 K only for illustrating, and non-limiting the present invention.
In sum, by these first contact structures, first short bar is directly connected these data wires, and by these second contact structures, second short bar is directly connected these scan lines.Compared to known technology, there is low-down resistance between first short bar and these data wires, and has low-down resistance too between second short bar and these scan lines.So, the present invention can improve the accuracy that detects active elements array substrates, and avoids testing result to be affected too greatly because of resistance.
In addition, because first short bar is directly to connect these data wires through these first contact structures, and second short bar is directly to connect these scan lines through these second contact structures, therefore, compared to known technology, active elements array substrates of the present invention has less contact structures.Hence one can see that, and the present invention can reduce the quantity that short bar (i.e. first short bar and second short bar) electrically connects the required contact structures of these scan lines and these data wires, and the area of viewing area is increased further.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (18)
1. the manufacture method of an active elements array substrates comprises:
One substrate is provided, and this substrate has a viewing area and a perimeter circuit district;
The multi-strip scanning line that in this viewing area, forms a plurality of grids and be connected with those grids, and form at least one first short bar simultaneously in the perimeter circuit district;
Form an insulating barrier, it covers those grids, those scan lines and this first short bar;
Form the semiconductor material layer on this insulating barrier;
On this semiconductor material layer, form a patterning photoresist layer, wherein this patterning photoresist layer has a plurality of first openings that are positioned at this first short bar top, exposing this semiconductor material layer, and the thickness of this patterning photoresist layer that is positioned at those grids tops is greater than the thickness that is positioned at other this patterning photoresist layer partly;
Remove by those first openings and expose this semiconductor material layer and this insulating barrier, to form a plurality of first contact holes;
Keep this patterning photoresist layer that is positioned at this grid top, and remove other this patterning photoresist layer partly;
Remove this semiconductor material layer that is not covered, to define a plurality of channel layers by this patterning photoresist layer;
Remove this patterning photoresist layer of those grid tops;
On this insulating barrier of this viewing area, form many data wires, an and formation one source pole and a drain electrode on each channel layer, and those data wires extend this perimeter circuit district and this first short bar of meeting cross-over connection, and wherein those data wires can directly see through those first contact holes and connect this first short bar.
2. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, also comprises:
On this insulating barrier, form a protective layer; And
Form a plurality of pixel electrodes on this protective layer, wherein those pixel electrodes electrically connect those drain electrodes.
3. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, the method that removes other this patterning photoresist layer partly comprises carries out the plasma ashing processing procedure to this patterning photoresist layer.
4. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, the method that forms those first contact holes comprises carries out etch process to this semiconductor material layer and this insulating barrier.
5. the manufacture method of active elements array substrates as claimed in claim 1, it is characterized in that, those scan lines extend to this perimeter circuit district, and this patterning photoresist layer also has a plurality of second openings that are positioned at this perimeter circuit district and those scan lines top, it exposes this semiconductor material layer, and after forming this patterning photoresist layer, also comprise:
Remove by those second openings and expose this semiconductor material layer and this insulating barrier, to form a plurality of second contact holes; And
After this patterning photoresist layer above removing this grid, form at least one second short bar in this perimeter circuit district, wherein this second short bar and those data wires form simultaneously, and this second short bar can directly see through those second contact holes and connect those scan lines.
6. the manufacture method of active elements array substrates as claimed in claim 5 is characterized in that, the method that forms those first contact holes and those second contact holes comprises carries out etch process to this semiconductor material layer and this insulating barrier.
7. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, the method that forms this semiconductor material layer comprises:
Form a channel material layer on this insulating barrier; And
Form an ohmic contact material layer on this channel material layer.
8. the manufacture method of active elements array substrates as claimed in claim 7 is characterized in that, the method that removes not this semiconductor material layer that is covered by this patterning photoresist layer comprises:
Remove this ohmic contact material layer that is not covered by this patterning photoresist layer; And
Remove this channel material layer that is not covered by this patterning photoresist layer.
9. the manufacture method of active elements array substrates as claimed in claim 2 is characterized in that, before forming this protective layer, also comprises and carries out a backward channel etch process.
10. the manufacture method of active elements array substrates as claimed in claim 2 is characterized in that, also comprises:
On this protective layer, form a flatness layer; And
On this flatness layer, form those pixel electrodes.
11. the manufacture method of an active elements array substrates comprises:
One substrate is provided, and this substrate has a viewing area and a perimeter circuit district;
The multi-strip scanning line that in this viewing area, forms a plurality of grids and be connected with those grids, wherein those scan lines extend this perimeter circuit district;
Form an insulating barrier, it covers those grids and those scan lines;
Form the semiconductor material layer on this insulating barrier;
On this semiconductor material layer, form a patterning photoresist layer, wherein this patterning photoresist layer has a plurality of openings that are positioned at this perimeter circuit district and those scan lines top, it exposes this semiconductor material layer, and is positioned at the thickness of the thickness of this patterning photoresist layer above those grids greater than this patterning photoresist layer that is positioned at other part;
Remove by those openings and expose this semiconductor material layer and this insulating barrier, to form a plurality of contact holes;
Keep this patterning photoresist layer that is positioned at this grid top, and remove other this patterning photoresist layer partly;
Remove this semiconductor material layer that is not covered, to define a plurality of channel layers by this patterning photoresist layer;
Remove this patterning photoresist layer of those grid tops;
On this insulating barrier of this viewing area, form many data wires and at least one short bar, an and formation one source pole and a drain electrode on each channel layer, wherein this short bar can cross-over connection extend to those scan lines in this perimeter circuit district, and directly connects those scan lines through those contact holes.
12. the manufacture method of active elements array substrates as claimed in claim 11 is characterized in that, also comprises:
On this insulating barrier, form a protective layer; And
Form a plurality of pixel electrodes on this protective layer, wherein those pixel electrodes electrically connect those drain electrodes.
13. the manufacture method of active elements array substrates as claimed in claim 11 is characterized in that, the method that removes other this patterning photoresist layer partly comprises carries out the plasma ashing processing procedure to this patterning photoresist layer.
14. the manufacture method of active elements array substrates as claimed in claim 11 is characterized in that, the method that forms those contact holes comprises carries out etch process to this semiconductor material layer and this insulating barrier.
15. the manufacture method of active elements array substrates as claimed in claim 11 is characterized in that, the method that forms this semiconductor material layer comprises:
Form a channel material layer on this insulating barrier; And
Form an ohmic contact material layer on this channel material layer.
16. the manufacture method of active elements array substrates as claimed in claim 15 is characterized in that, the method that removes not this semiconductor material layer that is covered by this patterning photoresist layer comprises:
Remove this ohmic contact material layer that is not covered by this patterning photoresist layer; And
Remove this channel material layer that is not covered by this patterning photoresist layer.
17. the manufacture method of active elements array substrates as claimed in claim 12 is characterized in that, before forming this protective layer, also comprises and carries out a backward channel etch process.
18. the manufacture method of active elements array substrates as claimed in claim 12 is characterized in that, also comprises:
On this protective layer, form a flatness layer; And
On this flatness layer, form those pixel electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101279280A CN101621038B (en) | 2008-07-01 | 2008-07-01 | Manufacturing method of active element array base plate |
Applications Claiming Priority (1)
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| CN103163668B (en) * | 2011-12-15 | 2015-09-23 | 武汉天马微电子有限公司 | The pick-up unit of liquid crystal indicator |
| CN102981340B (en) * | 2012-12-11 | 2015-11-25 | 京东方科技集团股份有限公司 | A kind of array base palte of liquid crystal display and manufacture method |
| CN103545378B (en) | 2013-11-05 | 2016-09-07 | 京东方科技集团股份有限公司 | Oxide thin film transistor and preparation method thereof, array base palte, display device |
| TWI696868B (en) * | 2019-05-21 | 2020-06-21 | 友達光電股份有限公司 | Display panel and display panel menufacturing method |
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| CN1453615A (en) * | 2002-04-16 | 2003-11-05 | Lg.菲利浦Lcd株式会社 | Array base plate for liquid crystal display device and producing method thereof |
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