TWI696868B - Display panel and display panel menufacturing method - Google Patents

Display panel and display panel menufacturing method Download PDF

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TWI696868B
TWI696868B TW108117474A TW108117474A TWI696868B TW I696868 B TWI696868 B TW I696868B TW 108117474 A TW108117474 A TW 108117474A TW 108117474 A TW108117474 A TW 108117474A TW I696868 B TWI696868 B TW I696868B
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conductive
substrate
display panel
pillars
conductive material
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TW202043867A (en
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劉展睿
梁育馨
王脩華
黃巧俐
鄭君丞
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友達光電股份有限公司
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Priority to CN202010013538.1A priority patent/CN111081140B/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

A display panel includes a substrate, a plurality of active device, a conduction structure, and a plurality of first conductive patterns. The substrate has a plurality of through holes passing through the substrate. The active devices are arranged in an array on an upper surface of the substrate. The conduction structure includes a wiring layer disposed on a lower surface of the substrate and a plurality of first conduction pillars. The first conduction pillars are embedded in the through holes and penetrate the substrate respectively. The first conduction pillars are coupled between the wiring layer and the active devices respectively. The first conductive patterns disposed on the upper surface of the substrate cover sidewalls of the first conduction pillars respectively.

Description

顯示面板及顯示面板製作方法 Display panel and display panel manufacturing method

本發明是有關於一種電子裝置及電子裝置製作方法,且特別是有關於一種顯示面板及顯示面板製作方法。 The invention relates to an electronic device and a manufacturing method of the electronic device, and in particular to a display panel and a manufacturing method of the display panel.

一般而言,顯示面板可具有顯示區及位於顯示區周圍的非顯示區。非顯示區可包括佈線區域以設置走線以及驅動電路區以設置用來驅動顯示面板中的主動元件的驅動電路,例如源級驅動電路或閘極驅動電路,因此,顯示面板的非顯示區無法顯示影像,而影響顯示面板的外觀設計。 In general, the display panel may have a display area and a non-display area located around the display area. The non-display area may include a wiring area to set traces and a drive circuit area to set a drive circuit for driving active elements in the display panel, such as a source drive circuit or a gate drive circuit. Therefore, the non-display area of the display panel cannot Display images and affect the design of the display panel.

具體而言,當非顯示區的面積縮小時,顯示區佔據顯示面板更大的面積,而對應地設置更多的畫素,因此可提高顯示面板的解析度。當非顯示區的面積縮小時,顯示區的邊界更接近顯示面板的外緣,因此可實現窄邊框設計。對於拼接而成的大型顯示面板,非顯示區形成無法顯示影像的拼接縫隙,造成整體影像的不連續性,而影響顯示品質。因此現有的顯示面板仍有待改進。 Specifically, when the area of the non-display area is reduced, the display area occupies a larger area of the display panel, and correspondingly more pixels are provided, so the resolution of the display panel can be improved. When the area of the non-display area is reduced, the boundary of the display area is closer to the outer edge of the display panel, so a narrow bezel design can be realized. For large display panels spliced together, the non-display area forms a splicing gap where images cannot be displayed, causing discontinuity in the overall image and affecting display quality. Therefore, the existing display panel still needs to be improved.

本發明的一實施例中,提供一種顯示面板,其架構有助於縮小顯示面板的尺寸,或者可縮減基板上的佈線區域面積。 In one embodiment of the present invention, a display panel is provided, the structure of which is helpful for reducing the size of the display panel or reducing the area of the wiring area on the substrate.

本發明的一實施例提出一種顯示面板,包括一基板、多個主動元件、一導通結構以及多個第一導電圖案。該基板具有貫穿該基板的多個貫孔。該些主動元件呈陣列排列且設置於該基板的一上表面上。該導通結構包括設置於該基板的一下表面上的一線路層以及多個第一導通柱。該些第一導通柱分別與該些貫孔嵌合而貫穿該基板,該些第一導通柱分別耦接該線路層與該些主動元件之間。該些第一導電圖案設置於該基板的該上表面上,該些第一導電圖案分別包覆該些第一導通柱的側壁。 An embodiment of the invention provides a display panel including a substrate, a plurality of active elements, a conductive structure, and a plurality of first conductive patterns. The substrate has a plurality of through holes penetrating the substrate. The active devices are arranged in an array and arranged on an upper surface of the substrate. The conducting structure includes a circuit layer disposed on a lower surface of the substrate and a plurality of first conducting pillars. The first conductive pillars are respectively fitted into the through holes to penetrate the substrate, and the first conductive pillars are respectively coupled between the circuit layer and the active devices. The first conductive patterns are disposed on the upper surface of the substrate, and the first conductive patterns respectively cover the sidewalls of the first conductive pillars.

本發明的一實施例提出一種顯示面板製作方法,包括形成多個主動元件於一基板的一上表面上、形成多個第一導電圖案於該基板的該上表面上、形成貫穿該基板的多個貫孔以及形成一導通結構。該些主動元件呈陣列排列。該導通結構包括一線路層以及多個第一導通柱。該線路層設置於該基板的一下表面上。該些第一導通柱分別與該些貫孔嵌合而貫穿該基板。該些第一導通柱分別耦接該線路層與該些主動元件之間。該些第一導電圖案分別包覆該些第一導通柱的側壁。 An embodiment of the present invention provides a method for manufacturing a display panel, including forming a plurality of active elements on an upper surface of a substrate, forming a plurality of first conductive patterns on the upper surface of the substrate, and forming a plurality of A through hole and a conducting structure are formed. The active elements are arranged in an array. The conducting structure includes a circuit layer and a plurality of first conducting pillars. The circuit layer is disposed on the lower surface of the substrate. The first conducting posts are respectively fitted into the through holes and penetrate the substrate. The first conductive pillars are respectively coupled between the circuit layer and the active devices. The first conductive patterns respectively cover the sidewalls of the first conductive pillars.

在本發明的實施例的顯示面板具有貫穿基板的貫孔,因此位於基板的上表面的元件可藉由嵌入貫孔的導通結構,而耦接至位於基板的下表面的元件,如此一來,可達成尺寸微型化,或 者可縮減基板上的佈線區域面積,而可實現窄邊框設計或是無縫拼接設計。此外,本發明的顯示面板以導電材料結構的導電圖案或基板的表面處理覆膜作為晶種層,其包覆導通結構,而利於導通結構的形成。 The display panel according to the embodiment of the present invention has a through hole penetrating through the substrate. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the lower surface of the substrate by the conductive structure embedded in the through hole. Can be miniaturized, or It can reduce the area of the wiring area on the substrate, and can achieve a narrow border design or a seamless splicing design. In addition, the display panel of the present invention uses the conductive pattern of the conductive material structure or the surface treatment coating of the substrate as the seed layer, which covers the conductive structure, which is beneficial to the formation of the conductive structure.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

10、30、40、50、60:顯示面板 10, 30, 40, 50, 60: display panel

100、199、600、699、500、599a、599b:基板 100, 199, 600, 699, 500, 599a, 599b: substrate

100B、600B:下表面 100B, 600B: lower surface

100T、600T:上表面 100T, 600T: upper surface

100Va、100Vb、500V1a~500V22a、500V1b~500V18b、600V:貫孔 100Va, 100Vb, 500V1a~500V22a, 500V1b~500V18b, 600V: through hole

102:表面處理覆膜 102: Surface treatment coating

110a、110b、610a、610b:緩衝層 110a, 110b, 610a, 610b: buffer layer

120a、120b、620a、620b:閘絕緣層 120a, 120b, 620a, 620b: gate insulating layer

130、630:層間介電層 130, 630: interlayer dielectric layer

140:平坦層 140: flat layer

181C、182C、183C、184C、185C、186C、681C~686C:連接圖案 181C, 182C, 183C, 184C, 185C, 186C, 681C~686C: connection pattern

181H1、181H2、182H、183H1、183H2、184H、181H1’、183H1’:開口 181H1, 181H2, 182H, 183H1, 183H2, 184H, 181H1’, 183H1’: opening

181P1、181P2、182P、183P1、183P2、184P、185P、186P、181P1’、183P1’、681P~684P:導電圖案 181P1, 181P2, 182P, 183P1, 183P2, 184P, 185P, 186P, 181P1’, 183P1’, 681P~684P: conductive patterns

181S、182S、183S、184S、185S、186S、181S’、183S’、681S、682S、683S、684S、685S、686S:導電材料結構 181S, 182S, 183S, 184S, 185S, 186S, 181S’, 183S’, 681S, 682S, 683S, 684S, 685S, 686S: conductive material structure

190:導通結構 190: conduction structure

190L、650:線路層 190L, 650: line layer

190L1、190L2a~190L5a、190L2b~190L5b、590L1a~590L22a、590L1b~590L18b:訊號線 190L1, 190L2a~190L5a, 190L2b~190L5b, 590L1a~590L22a, 590L1b~590L18b: signal line

190P1a、190P2a、190P1b、190P2b、690P1a、690P1b:導通柱 190P1a, 190P2a, 190P1b, 190P2b, 690P1a, 690P1b: conductive column

190Pa、190Pb、690Pa、690Pb、690Pc:導通部 190Pa, 190Pb, 690Pa, 690Pb, 690Pc: conduction part

190Sa、190Sb、690Sa、690Sb、690Sc:連接區塊 190Sa, 190Sb, 690Sa, 690Sb, 690Sc: connection block

640:絕緣層 640: Insulation

BDa、BDb:接合區 BDa, BDb: junction zone

CH1、CH2:通道區 CH1, CH2: channel area

D1、D2:汲極 D1, D2: Drain

DP1a、DP1b、DP2a、DP2b:汲極區 DP1a, DP1b, DP2a, DP2b: Drain region

G1、G2:閘極 G1, G2: Gate

H1~H3、H4~H6、H1’:接觸洞 H1~H3, H4~H6, H1’: contact hole

IC:驅動電路 IC: drive circuit

L1、L2:發光單元 L1, L2: light emitting unit

LL:特徵長度 LL: characteristic length

PE1、PE2:畫素電極 PE1, PE2: pixel electrode

PE1a、PE1b、PE2c:電極圖案 PE1a, PE1b, PE2c: electrode pattern

S1、S2:源極 S1, S2: source

SE1、SE2:半導體層 SE1, SE2: semiconductor layer

SP1a、SP1b、SP2a、SP2b:源極區 SP1a, SP1b, SP2a, SP2b: source region

T1、T2:主動元件 T1, T2: active components

XX:交線 XX: intersection line

X、Y、Z:方向 X, Y, Z: direction

圖1A及圖1B分別是本發明一實施方式的顯示面板局部的剖面示意圖。 1A and 1B are schematic partial cross-sectional views of a display panel according to an embodiment of the invention.

圖2A至圖2D是圖1A所示的顯示面板之局部區域的製造流程的剖面示意圖。 2A to 2D are schematic cross-sectional views of a manufacturing process of a partial area of the display panel shown in FIG. 1A.

圖3A及圖3B分別是本發明一實施方式的顯示面板局部的剖面示意圖。 3A and 3B are respectively partial cross-sectional schematic diagrams of a display panel according to an embodiment of the invention.

圖4A及圖4B分別是本發明一實施方式的顯示面板局部的剖面示意圖。 4A and 4B are schematic partial cross-sectional views of a display panel according to an embodiment of the invention.

圖5是本發明一實施方式的顯示面板的平面示意圖。 5 is a schematic plan view of a display panel according to an embodiment of the invention.

圖6分別是本發明一實施方式的顯示面板局部的剖面示意圖。 6 is a schematic partial cross-sectional view of a display panel according to an embodiment of the present invention.

實施方式中所提到的方向用語,例如:「上」、「下」、「前」、 「後」、「左」、「右」等,僅是參考附圖的方向。因此,使用的方向用語是用來說明,而並非用來限制本發明。在附圖中,各圖式繪示的是特定示範實施例中所使用的方法、結構及/或材料的通常性特徵。然而,這些圖式不應被解釋為界定或限制由這些示範實施例所涵蓋的範圍或性質。舉例來說,為了清楚起見,各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。 Direction words mentioned in the embodiment, for example: "up", "down", "front", "Rear", "Left", "Right", etc., are only the directions referring to the drawings. Therefore, the directional terms used are for illustration, not for limiting the invention. In the drawings, each drawing depicts general features of methods, structures, and/or materials used in certain exemplary embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these exemplary embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of the various film layers, regions, and/or structures may be reduced or enlarged.

在實施方式中,相同或相似的元件將採用相同或相似的標號,且將省略其贅述。此外,不同示範實施例中的特徵在沒有衝突的情況下可相互組合,且依本說明書或申請專利範圍所作之簡單的等效變化與修飾,皆仍屬本專利涵蓋之範圍內。另外,本說明書或申請專利範圍中提及的「第一」、「第二」等用語僅用以命名分立(discrete)的元件或區別不同實施例或範圍,而並非用來限制元件數量上的上限或下限,也並非用以限定元件的製造順序或設置順序。 In the embodiments, the same or similar elements will use the same or similar reference numbers, and the redundant description thereof will be omitted. In addition, the features in the different exemplary embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or the scope of the patent application are still covered by this patent. In addition, the terms "first" and "second" mentioned in this specification or the scope of patent application are only used to name discrete elements or distinguish different embodiments or ranges, not to limit the number of elements. The upper limit or the lower limit is not intended to limit the manufacturing order or setting order of the components.

圖1A及圖1B分別是本發明一實施方式的顯示面板10局部的剖面示意圖,其中,圖1A及圖1B的剖面相交於交線XX。請參照圖1A及圖1B,顯示面板10可包括基板100、199、緩衝層(buffer)110a、110b、閘絕緣層(gate insulator,GI)120a、120b、一層間介電層(inter-layer dielectric,ILD)130、一平坦層(planarization layer,PL)140、導電材料結構181S、182S、183S、184S、185S、186S、一導通結構190、一驅動電路IC、一主動元件T1、一發光單元L1以及一畫素電極PE1。但本發明元件的數量 不以此為限,而可視不同設計考量而適當調整,也就是說顯示面板10可包括一個或多個基板、緩衝層、閘絕緣層、層間介電層、平坦層、導電材料結構、導通結構、驅動電路、主動元件、發光單元以及畫素電極。 FIGS. 1A and 1B are schematic partial cross-sectional views of a display panel 10 according to an embodiment of the present invention, wherein the cross-sections of FIGS. 1A and 1B intersect at an intersection line XX. 1A and 1B, the display panel 10 may include substrates 100, 199, buffer layers 110a, 110b, gate insulators (GI) 120a, 120b, and an inter-layer dielectric layer (inter-layer dielectric , ILD) 130, a planarization layer (PL) 140, conductive material structures 181S, 182S, 183S, 184S, 185S, 186S, a conductive structure 190, a driving circuit IC, an active element T1, a light-emitting unit L1 And a pixel electrode PE1. But the number of elements of the invention It is not limited to this, but can be appropriately adjusted according to different design considerations, that is to say, the display panel 10 may include one or more substrates, buffer layers, gate insulating layers, interlayer dielectric layers, flat layers, conductive material structures, conductive structures , Drive circuit, active element, light-emitting unit and pixel electrode.

基板100適於承載其他元件,其可具有彼此相對的一上表面100T以及一下表面100B,並且上表面100T及下表面100B的法線方向可平行於方向Z。基板100可具有貫穿基板100的多個貫孔(如貫孔100Va、100Vb)。基板100包括一表面處理覆膜102。表面處理覆膜102包覆基板100的貫孔100Va、100Vb以及基板100的下表面100B。在本實施例中,基板100可以是可撓性基板,但本發明不限於此,在其他的實施例中,基板100也可以是剛性基板。貫孔100Va、100Vb的特徵長度LL介於5微米(micrometer,μm)與50微米之間。 The substrate 100 is suitable for carrying other components. It may have an upper surface 100T and a lower surface 100B opposite to each other, and the normal directions of the upper surface 100T and the lower surface 100B may be parallel to the direction Z. The substrate 100 may have a plurality of through holes (eg, through holes 100Va, 100Vb) penetrating the substrate 100. The substrate 100 includes a surface treatment film 102. The surface treatment film 102 covers the through holes 100Va, 100Vb of the substrate 100 and the lower surface 100B of the substrate 100. In this embodiment, the substrate 100 may be a flexible substrate, but the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a rigid substrate. The characteristic length LL of the through holes 100Va and 100Vb is between 5 microns (micrometer, μm) and 50 microns.

緩衝層110a、110b配置在基板100上且可為無機材料所構成的無機薄膜,且構成緩衝層110a、110b的材料通常可為絕緣材料。閘絕緣層120a、120b配置在緩衝層110a、110b上,且閘絕緣層120a、120b的材料例如是氧化矽、氮化矽或其他絕緣材料。層間介電層130配置在閘絕緣層120a、120b上,且層間介電層130的材料可包括無機材料、有機材料或其組合。平坦層140配置在層間介電層130上,且平坦層140的材料可包括各種適用的有機材料。 The buffer layers 110a and 110b are disposed on the substrate 100 and may be an inorganic thin film composed of an inorganic material, and the material constituting the buffer layers 110a and 110b may generally be an insulating material. The gate insulating layers 120a, 120b are disposed on the buffer layers 110a, 110b, and the material of the gate insulating layers 120a, 120b is, for example, silicon oxide, silicon nitride, or other insulating materials. The interlayer dielectric layer 130 is disposed on the gate insulating layers 120a and 120b, and the material of the interlayer dielectric layer 130 may include inorganic materials, organic materials, or a combination thereof. The flat layer 140 is disposed on the interlayer dielectric layer 130, and the material of the flat layer 140 may include various suitable organic materials.

主動元件(如主動元件T1)設置於基板100的上表面100T 上且呈陣列排列。在本實施例中,主動元件T1可例如是頂部閘極型的薄膜電晶體(top gate TFT)。然而,本發明並不限於此,在其他實施例中,也可設計為底部閘極型的薄膜電晶體(bottom gate TFT)或其他適當型式的薄膜電晶體。主動元件T1可包括半導體層SE1、源極S1、汲極D1及閘極G1。半導體層SE1配置在緩衝層110a、110b上,且半導體層SE1的材料例如是多晶矽(例如低溫多晶矽(low temperature crystalline silicon,LTPS))、非晶矽(amorphous silicon)、金屬氧化物半導體(例如銦鎵鋅氧化物(Indium Gallium Zinc Oxide,IGZO))或是其他半導體材料。半導體層SE1可包括源極區SP1a、SP1b、汲極區DP1a、DP1b及通道區CH1。部分的源極S1及汲極D1配置在層間介電層130上,而其他部分的源極S1及汲極D1貫穿閘絕緣層120a、120b及層間介電層130且分別與源極區SP1a、SP1b及汲極區DP1a、DP1b的半導體層SE1接觸。 Active components (such as active component T1) are disposed on the upper surface 100T of the substrate 100 Arranged in an array. In this embodiment, the active device T1 may be, for example, a top gate TFT. However, the present invention is not limited to this. In other embodiments, it can also be designed as a bottom gate TFT or other appropriate type of TFT. The active device T1 may include a semiconductor layer SE1, a source S1, a drain D1, and a gate G1. The semiconductor layer SE1 is disposed on the buffer layers 110a and 110b, and the material of the semiconductor layer SE1 is, for example, polycrystalline silicon (such as low temperature crystalline silicon (LTPS)), amorphous silicon (amorphous silicon), and metal oxide semiconductor (such as indium Indium Gallium Zinc Oxide (IGZO) or other semiconductor materials. The semiconductor layer SE1 may include source regions SP1a, SP1b, drain regions DP1a, DP1b, and channel region CH1. Part of the source S1 and the drain D1 are disposed on the interlayer dielectric layer 130, while the other parts of the source S1 and the drain D1 penetrate through the gate insulating layers 120a, 120b and the interlayer dielectric layer 130 and are respectively connected to the source region SP1a, SP1b is in contact with the semiconductor layer SE1 of the drain regions DP1a and DP1b.

基於導電性的考量,導電材料結構181S~185S的材質一般是金屬材料或合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物等的其他導電材料。導電材料結構181S~185S設置於基板100的上表面100T上。導電材料結構181S(也可稱作第一導電材料結構)可包括一導電圖案181P1(也可稱作第一導電圖案)、一導電圖案181P2(也可稱作第二導電圖案)以及一連接圖案181C。導電材料結構182S(也可稱作第二導電材料結構)可包括一導電圖案182P(也可稱作第三導電圖案)以及一連接圖 案182C。類似地,導電材料結構183S包括導電圖案183P1、183P2以及一連接圖案183C。導電材料結構184S、185S、186S可分別包括導電圖案184P、185P、186P以及連接圖案184C、185C、186C。 Based on the consideration of conductivity, the materials of the conductive material structures 181S~185S are generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, and nitrogen oxides of metal materials. The conductive material structures 181S-185S are disposed on the upper surface 100T of the substrate 100. The conductive material structure 181S (also referred to as a first conductive material structure) may include a conductive pattern 181P1 (also referred to as a first conductive pattern), a conductive pattern 181P2 (also referred to as a second conductive pattern), and a connection pattern 181C. The conductive material structure 182S (also referred to as a second conductive material structure) may include a conductive pattern 182P (also referred to as a third conductive pattern) and a connection diagram Case 182C. Similarly, the conductive material structure 183S includes conductive patterns 183P1, 183P2 and a connection pattern 183C. The conductive material structures 184S, 185S, and 186S may include conductive patterns 184P, 185P, and 186P, and connection patterns 184C, 185C, and 186C, respectively.

在本實施例中,導電材料結構181S電性連接至導電材料結構182S,導電材料結構183S電性連接至導電材料結構184S、185S。導電圖案181P1~186P大致沿著方向Z延伸。導電材料結構181S的導電圖案181P1的底表面接觸導電材料結構182S的頂表面,導電材料結構181S的導電圖案181P2的底表面接觸主動元件T1的源極S1,導電材料結構181S的連接圖案181C電性連接於導電圖案181P1與導電圖案181P2之間。導電材料結構182S的導電圖案182P的底表面接觸基板100的上表面100T,導電材料結構182S的連接圖案182C電性連接至導電圖案182P。類似地,導電材料結構183S的導電圖案183P1的底表面接觸導電材料結構184S的頂表面,導電材料結構183S的導電圖案183P2的底表面接觸導電材料結構185S的頂表面,導電材料結構183S的連接圖案183C電性連接於導電圖案183P1與導電圖案183P2之間。導電材料結構184S的導電圖案184P的底表面接觸基板100的上表面100T,導電材料結構184S的連接圖案184C電性連接至導電圖案184P。導電材料結構185S的導電圖案185P的底表面接觸主動元件T1的閘極G1,導電材料結構185S的連接圖案185C電性連接至導電圖案185P。導電材料結構186S的導電圖案186P的底表面接觸主動元件T1的汲極D1,導電材料結構186S的連接圖案186C電性連 接至導電圖案186P。 In this embodiment, the conductive material structure 181S is electrically connected to the conductive material structure 182S, and the conductive material structure 183S is electrically connected to the conductive material structures 184S, 185S. The conductive patterns 181P1 to 186P extend substantially along the direction Z. The bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the conductive material structure 182S, the bottom surface of the conductive pattern 181P2 of the conductive material structure 181S contacts the source S1 of the active element T1, and the connection pattern 181C of the conductive material structure 181S is electrically It is connected between the conductive pattern 181P1 and the conductive pattern 181P2. The bottom surface of the conductive pattern 182P of the conductive material structure 182S contacts the upper surface 100T of the substrate 100, and the connection pattern 182C of the conductive material structure 182S is electrically connected to the conductive pattern 182P. Similarly, the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the top surface of the conductive material structure 184S, the bottom surface of the conductive pattern 183P2 of the conductive material structure 183S contacts the top surface of the conductive material structure 185S, and the connection pattern of the conductive material structure 183S 183C is electrically connected between the conductive pattern 183P1 and the conductive pattern 183P2. The bottom surface of the conductive pattern 184P of the conductive material structure 184S contacts the upper surface 100T of the substrate 100, and the connection pattern 184C of the conductive material structure 184S is electrically connected to the conductive pattern 184P. The bottom surface of the conductive pattern 185P of the conductive material structure 185S contacts the gate G1 of the active element T1, and the connection pattern 185C of the conductive material structure 185S is electrically connected to the conductive pattern 185P. The bottom surface of the conductive pattern 186P of the conductive material structure 186S contacts the drain D1 of the active element T1, and the connection pattern 186C of the conductive material structure 186S is electrically connected Connect to conductive pattern 186P.

連接圖案181C、182C、183C、184C、185C、186C是用來連接導電圖案,其沿方向Z於基板100上的投影形狀可視不同設計考量而適應性調整。導電圖案181P1、181P2、182P、183P1、183P2、184P分別具有開口181H1、181H2、182H、183H1、183H2、184H,而大致為管狀的中空結構。導電圖案181P1~184P沿方向Z於基板100上的投影形狀亦可視不同設計考量而適應性調整。在一些實施例中,投影形狀的內輪廓與外輪廓共形(conformal),舉例來說,投影形狀的內輪廓與外輪廓均為矩形。在一些實施例中,投影形狀的內輪廓與外輪廓可為同心圓,但不限於此。在本實施例中,導電圖案181P1、182P的投影形狀的內輪廓為開口181H1~182H投影後的輪廓,其可與貫孔100Va重疊且對齊,在此情況下,導電圖案181P1、182P的投影形狀的內輪廓與貫孔100Va的形狀、面積、尺寸且/或位置均相同,但本發明不限於此。也就是說,開口181H1~182H連通至貫孔100Va。類似地,導電圖案183P1、184P的投影形狀的內輪廓可為開口183H1~184H投影後的輪廓,其與貫孔100Vb重疊且對齊。也就是說,開口183H1~184H連通至貫孔100Vb。導電圖案181P1、182P的投影形狀的外輪廓可重疊且對齊,導電圖案183P1、184P的投影形狀的外輪廓可重疊且對齊。另一方面,在本實施例中,導電圖案185P、186P可為實心柱,但本發明不限於此。 The connection patterns 181C, 182C, 183C, 184C, 185C, and 186C are used to connect the conductive patterns, and their projection shapes on the substrate 100 in the direction Z can be adjusted adaptively according to different design considerations. The conductive patterns 181P1, 181P2, 182P, 183P1, 183P2, and 184P have openings 181H1, 181H2, 182H, 183H1, 183H2, and 184H, respectively, and are generally tubular hollow structures. The projected shapes of the conductive patterns 181P1 to 184P on the substrate 100 in the direction Z can also be adaptively adjusted according to different design considerations. In some embodiments, the inner and outer contours of the projected shape are conformal. For example, the inner and outer contours of the projected shape are both rectangular. In some embodiments, the inner and outer contours of the projected shape may be concentric circles, but it is not limited thereto. In this embodiment, the inner contour of the projected shapes of the conductive patterns 181P1 and 182P is the contour of the projections of the openings 181H1 to 182H, which can overlap and be aligned with the through holes 100Va. In this case, the projected shapes of the conductive patterns 181P1 and 182P The inner contour of is the same as the shape, area, size and/or position of the through hole 100Va, but the invention is not limited thereto. That is, the openings 181H1 to 182H communicate with the through hole 100Va. Similarly, the inner contours of the projected shapes of the conductive patterns 183P1 and 184P may be the contours of the projections of the openings 183H1 to 184H, which overlap and align with the through holes 100Vb. That is, the openings 183H1 to 184H communicate with the through hole 100Vb. The outer contours of the projected shapes of the conductive patterns 181P1 and 182P may overlap and align, and the outer contours of the projected shapes of the conductive patterns 183P1 and 184P may overlap and align. On the other hand, in this embodiment, the conductive patterns 185P, 186P may be solid pillars, but the invention is not limited thereto.

基於導電性的考量,導通結構190的材質一般是金屬材 料或合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物等的其他導電材料。導通結構190可包括一線路層190L、導通部190Pa、190Pb。 Based on the consideration of conductivity, the material of the conducting structure 190 is generally a metal material Materials or alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials and other conductive materials. The conducting structure 190 may include a circuit layer 190L, conducting portions 190Pa, and 190Pb.

導通部190Pa可包括導通柱190P1a(也可稱作第一導通柱)、導通柱190P2a(也可稱作第二導通柱)以及一連接區塊190Sa。類似地,導通部190Pb可包括導通柱190P1b(也可稱作第一導通柱)、導通柱190P2b(也可稱作第二導通柱)以及一連接區塊190Sb。導通部190Pa的導通柱190P1a及導通部190Pb的導通柱190P1b分別電性連接至線路層190L。導通部190Pa的導通柱190P2a及導通部190Pb的導通柱190P2b分別耦接至主動元件T1,其中,導通柱190P2a電性連接至主動元件T1的源極S1,導通柱190P2b耦接至主動元件T1的閘極G1。連接區塊190Sa、連接區塊190Sb設置於基板100的上表面100T上。連接區塊190Sa電性連接於導通柱190P1a、190P2a之間,連接區塊190Sb電性連接於導通柱190P1b、190P2b之間。 The conducting portion 190Pa may include a conducting post 190P1a (also may be referred to as a first conducting post), a conducting post 190P2a (also may be referred to as a second conducting post), and a connection block 190Sa. Similarly, the conductive portion 190Pb may include a conductive pillar 190P1b (also referred to as a first conductive pillar), a conductive pillar 190P2b (also referred to as a second conductive pillar), and a connection block 190Sb. The conductive pillar 190P1a of the conductive portion 190Pa and the conductive pillar 190P1b of the conductive portion 190Pb are electrically connected to the circuit layer 190L, respectively. The conducting post 190P2a of the conducting part 190Pa and the conducting post 190P2b of the conducting part 190Pb are respectively coupled to the active device T1, wherein the conducting post 190P2a is electrically connected to the source S1 of the active device T1, and the conducting post 190P2b is coupled to the active device T1 Gate G1. The connection block 190Sa and the connection block 190Sb are disposed on the upper surface 100T of the substrate 100. The connection block 190Sa is electrically connected between the conductive pillars 190P1a and 190P2a, and the connection block 190Sb is electrically connected between the conductive pillars 190P1b and 190P2b.

線路層190L設置於基板100的下表面100B上,其可包括訊號線190L1、190L2a~190L5a、190L2b~190L5b。線路層190L耦接於多個導通柱(如導通柱190P1a、190P1b)與驅動電路IC之間。但本發明元件的數量不以此為限,而可視不同設計考量而適當調整,也就是說導通結構190可包括多個導通部,線路層190L可包括多個訊號線。 The circuit layer 190L is disposed on the lower surface 100B of the substrate 100 and may include signal lines 190L1, 190L2a~190L5a, 190L2b~190L5b. The circuit layer 190L is coupled between the plurality of conductive pillars (such as the conductive pillars 190P1a and 190P1b) and the driving circuit IC. However, the number of components of the present invention is not limited to this, but can be adjusted appropriately according to different design considerations, that is to say, the conductive structure 190 can include multiple conductive portions, and the circuit layer 190L can include multiple signal lines.

由上述可知,位於基板100上表面100T上的主動元件 T1的源極S1可藉由導通部190Pa耦接至位於基板100下表面100B上的線路層190L,並藉由線路層190L耦接至位於基板100下表面100B上的驅動電路IC。位於基板100上表面100T上的主動元件T1的閘極G1可藉由導通部190Pb耦接至位於基板100下表面100B上的線路層190L,並藉由線路層190L耦接至位於基板100下表面100B上的驅動電路IC。如此一來,可充分利用基板100上表面100T以及下表面100B的空間進行佈線,而可縮小顯示面板10的尺寸,進而達成尺寸微型化。並且,將線路層190L中的訊號線(例如訊號線190L1、190L2a~190L5a、190L2b~190L5b)設置於基板100下表面100B上,可縮減基板100上表面100T上的佈線區域面積(即不發光區域)。在此情況下,顯示面板10可實現窄邊框設計或是無縫拼接設計。 As can be seen from the above, the active device on the upper surface 100T of the substrate 100 The source S1 of T1 may be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through the conductive portion 190Pa, and coupled to the driving circuit IC on the lower surface 100B of the substrate 100 through the circuit layer 190L. The gate G1 of the active device T1 located on the upper surface 100T of the substrate 100 can be coupled to the circuit layer 190L located on the lower surface 100B of the substrate 100 through the conducting portion 190Pb, and coupled to the lower surface of the substrate 100 through the circuit layer 190L Driver IC on 100B. In this way, the space on the upper surface 100T and the lower surface 100B of the substrate 100 can be fully utilized for wiring, and the size of the display panel 10 can be reduced, thereby achieving miniaturization. Moreover, the signal lines in the circuit layer 190L (for example, the signal lines 190L1, 190L2a to 190L5a, 190L2b to 190L5b) are provided on the lower surface 100B of the substrate 100, which can reduce the area of the wiring area on the upper surface 100T of the substrate 100 (that is, the non-light emitting area) ). In this case, the display panel 10 can realize a narrow frame design or a seamless splicing design.

導電材料結構181S~185S的材質可不同於導通結構190的材質,但本發明不限於此,導電材料結構181S~185S的材質可相同於導通結構190的材質,惟可分別於不同的時間點形成。在本實施例中,導通柱190P1a與貫孔100Va嵌合而貫穿基板100,且導電材料結構181S的導電圖案181P1以及導電材料結構182S的導電圖案182P分別包覆導通部190Pa的導通柱190P1a的側壁,而利於導通柱190P1a的形成。類似地,導通柱190P1b與貫孔100Va嵌合而貫穿基板100,且導電材料結構183S的導電圖案183P1以及導電材料結構184S的導電圖案184P分別包覆導通部190Pb的導通柱190P1b的側壁,而利於導通柱190P1b的形成。導電圖案 181P2包覆導通部190Pa的導通柱190P2a的側壁而利於導通柱190P2a的形成,導電圖案183P2包覆導通部190Pb的導通柱190P2b的側壁而利於導通柱190P2b的形成。 The materials of the conductive material structures 181S~185S can be different from the materials of the conductive structure 190, but the invention is not limited thereto. The materials of the conductive material structures 181S~185S can be the same as the materials of the conductive structure 190, but they can be formed at different points in time . In this embodiment, the conductive pillar 190P1a is fitted with the through hole 100Va to penetrate the substrate 100, and the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively cover the sidewalls of the conductive pillar 190P1a of the conductive portion 190Pa , And is conducive to the formation of conductive pillars 190P1a. Similarly, the conductive post 190P1b is fitted with the through hole 100Va to penetrate the substrate 100, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive pattern 184P of the conductive material structure 184S respectively cover the sidewalls of the conductive post 190P1b of the conductive portion 190Pb, which is beneficial to The formation of the conductive post 190P1b. Conductive pattern 181P2 covers the side wall of the conductive pillar 190P2a of the conductive portion 190Pa to facilitate the formation of the conductive pillar 190P2a, and the conductive pattern 183P2 covers the side wall of the conductive pillar 190P2b of the conductive portion 190Pb to facilitate the formation of the conductive pillar 190P2b.

導通部190Pa的導通柱190P1a、190P2a、連接區塊190Sa及導通部190Pb的導通柱190P1b、190P2b、連接區塊190Sb沿方向Z於基板100上的投影形狀可視不同設計考量而適應性調整。在本實施例中,導通部190Pa的導通柱190P1a、190P2a及導通部190Pb的導通柱190P1b、190P2b均為實心柱,但本發明不限於此。基於鍍膜特性,在一些實施例中,導通部190Pa沿方向Z於基板100上的投影(也可稱作第一投影)的外輪廓與導電材料結構181S沿方向Z於基板100上的投影(也可稱作第二投影)的外輪廓重疊,更具體地為重疊且對齊,在此情況下,第一投影與第二投影的形狀、面積、尺寸且/或位置均相同,但本發明不限於此。在本實施例中,導電材料結構181S沿方向Z於基板100上投影的外輪廓即為導電材料結構181S的連接圖案181C沿方向Z於基板100上投影的外輪廓,導通部190Pa沿方向Z於基板100上投影的外輪廓即為導通部190Pa的連接區塊190Sa沿方向Z於基板100上投影的外輪廓。如圖1A所示,導通部190Pa的連接區塊190Sa沿方向Z於基板100上的投影的外輪廓與導電材料結構181S的連接圖案181C沿方向Z於基板100上的投影的外輪廓重疊且對齊。類似地,導通部190Pb沿方向Z於基板100上的投影的外輪廓與導電材料結構183S沿方向Z於基板100上的投影的外輪廓重疊且 對齊。 The projection shapes of the conductive pillars 190P1a and 190P2a of the conductive portion 190Pa, the connection block 190Sa and the conductive pillars 190P1b, 190P2b of the conductive portion 190Pb, and the connection block 190Sb along the direction Z on the substrate 100 can be adaptively adjusted according to different design considerations. In this embodiment, the conductive pillars 190P1a and 190P2a of the conductive portion 190Pa and the conductive pillars 190P1b and 190P2b of the conductive portion 190Pb are solid pillars, but the invention is not limited thereto. Based on the coating characteristics, in some embodiments, the outer contour of the projection of the conducting portion 190Pa on the substrate 100 in the direction Z (also referred to as the first projection) and the projection of the conductive material structure 181S on the substrate 100 in the direction Z (also (It can be called the second projection) The outer contours overlap, more specifically overlap and align. In this case, the shape, area, size and/or position of the first projection and the second projection are the same, but the invention is not limited to this. In this embodiment, the outer contour of the conductive material structure 181S projected on the substrate 100 in the direction Z is the outer contour of the connection pattern 181C of the conductive material structure 181S projected on the substrate 100 in the direction Z, and the conducting portion 190Pa is along the direction Z The outer contour projected on the substrate 100 is the outer contour projected on the substrate 100 along the direction Z by the connection block 190Sa of the conducting portion 190Pa. As shown in FIG. 1A, the outer contour of the projection of the connection block 190Sa of the conducting portion 190Pa on the substrate 100 in the direction Z overlaps and aligns with the outer contour of the projection of the connection pattern 181C of the conductive material structure 181S on the substrate 100 in the direction Z . Similarly, the outer contour of the projection of the conducting portion 190Pb on the substrate 100 in the direction Z overlaps with the outer contour of the projection of the conductive material structure 183S on the substrate 100 in the direction Z and Align.

基板199適於承載其他元件,其可為薄膜覆晶(Chip on Film,COF)基板,但本發明不限於此。驅動電路IC可用以提供驅動訊號至主動元件(如主動元件T1),其位於基板100的下表面100B上,且設置於基板199上。主動元件T1可電性連接畫素電極PE1,以傳輸畫素電壓至畫素電極PE1。基於導電性的考量,畫素電極PE1的材質可包括金屬材料或合金,或者畫素電極PE1的材質可包括透明金屬氧化物導電材料,例如包括(但不限於)銦錫氧化物。畫素電極PE1可包括電極圖案PE1a、PE1b。畫素電極PE1的電極圖案PE1b設置於導電材料結構186S的連接圖案186C與平坦層140之間。導電材料結構186S的連接圖案186C可電性連接至發光單元L1,畫素電極PE1的電極圖案PE1a包覆導電材料結構186S的導電圖案186P的側壁。發光單元L1可為發光二極體(Light-emitting diode,LED),但本發明不限於此。 The substrate 199 is suitable for carrying other elements, which may be a chip on film (COF) substrate, but the invention is not limited thereto. The driving circuit IC can be used to provide a driving signal to an active device (such as the active device T1), which is located on the lower surface 100B of the substrate 100 and is disposed on the substrate 199. The active element T1 can be electrically connected to the pixel electrode PE1 to transmit the pixel voltage to the pixel electrode PE1. Based on conductivity considerations, the material of the pixel electrode PE1 may include a metal material or alloy, or the material of the pixel electrode PE1 may include a transparent metal oxide conductive material, such as, but not limited to, indium tin oxide. The pixel electrode PE1 may include electrode patterns PE1a and PE1b. The electrode pattern PE1b of the pixel electrode PE1 is disposed between the connection pattern 186C of the conductive material structure 186S and the flat layer 140. The connection pattern 186C of the conductive material structure 186S may be electrically connected to the light-emitting unit L1, and the electrode pattern PE1a of the pixel electrode PE1 covers the sidewall of the conductive pattern 186P of the conductive material structure 186S. The light-emitting unit L1 may be a light-emitting diode (LED), but the invention is not limited thereto.

為了詳細說明本實施例之顯示面板10的技術內容,以下更搭配圖2A至圖2D來說明顯示面板10的製造方法。圖2A至圖2D是圖1A所示的顯示面板10之局部區域的製造流程的剖面示意圖。 In order to explain the technical content of the display panel 10 of this embodiment in detail, the manufacturing method of the display panel 10 will be described below with reference to FIGS. 2A to 2D. 2A to 2D are schematic cross-sectional views of a manufacturing process of a partial area of the display panel 10 shown in FIG. 1A.

請參照圖2A,首先提供基板100。在一些實施例中,基板100可設置於一承載基板(未繪示)上。接著於基板100上全面性地形成緩衝層110a、110b。接著於緩衝層110a、110b上形成半導體層SE1,其中,半導體層SE1的形成方法可包括於緩衝層 110b上全面性地形成一層材料層(未繪示)後,進行一道或多道圖案化步驟。圖案化步驟可包括於材料層上形成一光阻材料層(未繪示)後,利用一個或多個光罩(未繪示)對光阻材料層進行曝光顯影製程而圖案化光阻材料層,並以圖案化的光阻材料層(未繪示)作為遮罩來對材料層進行蝕刻製程而完成材料層的圖案化,此後再移除圖案化的光阻材料層。 Referring to FIG. 2A, the substrate 100 is first provided. In some embodiments, the substrate 100 may be disposed on a carrier substrate (not shown). Next, the buffer layers 110 a and 110 b are formed on the substrate 100 in a comprehensive manner. Next, a semiconductor layer SE1 is formed on the buffer layers 110a and 110b, wherein the method for forming the semiconductor layer SE1 may be included in the buffer layer After a material layer (not shown) is formed comprehensively on 110b, one or more patterning steps are performed. The patterning step may include forming a photoresist material layer (not shown) on the material layer, and then using one or more photomasks (not shown) to expose and develop the photoresist material layer to pattern the photoresist material layer And using the patterned photoresist layer (not shown) as a mask to etch the material layer to complete the patterning of the material layer, and then remove the patterned photoresist layer.

接著於半導體層SE1、緩衝層110a、110b上全面性地形成閘絕緣層120a、120b。接著於閘絕緣層120a、120b上形成閘極G1。閘極G1的形成方法可包括物理氣相沉積(Physical vapor deposition,PVD)法或化學氣相沉積法,並且,於閘絕緣層120b上全面性地形成一層材料層(未繪示)後,進行一道或多道圖案化步驟。接著以閘極G1為遮罩,對半導體層SE1進行離子摻雜製程,以形成源極區SP1a、SP1b、汲極區DP1a、DP1b及通道區CH1。 Next, gate insulating layers 120a and 120b are formed on the semiconductor layer SE1, the buffer layers 110a and 110b in a comprehensive manner. Next, a gate G1 is formed on the gate insulating layers 120a and 120b. The formation method of the gate electrode G1 may include a physical vapor deposition (PVD) method or a chemical vapor deposition method, and a layer of material (not shown) is formed on the gate insulating layer 120b in a comprehensive manner, One or more patterning steps. Then, using the gate G1 as a mask, an ion doping process is performed on the semiconductor layer SE1 to form the source regions SP1a, SP1b, the drain regions DP1a, DP1b, and the channel region CH1.

接著於閘極G1上全面性地形成層間介電層130。接著圖案化緩衝層110a、110b、閘絕緣層120a、120b、層間介電層130,例如進行一道或多道圖案化步驟,以於緩衝層110a、110b、閘絕緣層120a、120b、層間介電層130形成接觸洞H1~H3。接觸洞H1~H3分別暴露出至少部分的基板100及半導體層SE1。 Then, an interlayer dielectric layer 130 is formed on the gate G1 in a comprehensive manner. Then patterning the buffer layers 110a, 110b, the gate insulating layers 120a, 120b, and the interlayer dielectric layer 130, for example, performing one or more patterning steps for the buffer layers 110a, 110b, the gate insulating layers 120a, 120b, the interlayer dielectric The layer 130 forms contact holes H1~H3. The contact holes H1 to H3 respectively expose at least part of the substrate 100 and the semiconductor layer SE1.

接著於層間介電層130上形成導電材料結構182S、源極S1及汲極D1。如此一來,可於一基板100的上表面100T上形成主動元件(如主動元件T1)。其中,形成導電材料結構182S、源極S1及汲極D1的材料填入接觸洞H1~H3,而使導電材料結構 182S、源極S1及汲極D1分別接觸基板100及半導體層SE1。在一些實施例中,導電材料結構182S、源極S1及汲極D1可於同一道程序中一併形成,並且,導電材料結構182S、源極S1及汲極D1的形成方法包括於層間介電層130上全面性地形成一層材料層(未繪示)後,進行一道或多道圖案化步驟。在另一些實施例中,導電材料結構182S、源極S1及汲極D1也可於不同道程序中分別形成。在一些實施例中,圖1B中的導電材料結構184S、185S也可與導電材料結構182S、源極S1及汲極D1於同一道程序中一併形成。 Next, a conductive material structure 182S, a source S1 and a drain D1 are formed on the interlayer dielectric layer 130. In this way, active devices (such as active device T1) can be formed on the upper surface 100T of a substrate 100. Among them, the materials forming the conductive material structure 182S, the source electrode S1 and the drain electrode D1 are filled into the contact holes H1~H3 to make the conductive material structure 182S, source S1 and drain D1 contact substrate 100 and semiconductor layer SE1, respectively. In some embodiments, the conductive material structure 182S, the source S1 and the drain D1 can be formed together in the same process, and the method of forming the conductive material structure 182S, the source S1 and the drain D1 includes interlayer dielectric After a material layer (not shown) is completely formed on the layer 130, one or more patterning steps are performed. In other embodiments, the conductive material structure 182S, the source S1 and the drain D1 can also be formed separately in different processes. In some embodiments, the conductive material structures 184S and 185S in FIG. 1B can also be formed together with the conductive material structure 182S, the source electrode S1 and the drain electrode D1 in the same process.

請參照圖2B,於層間介電層130、導電材料結構182S、源極S1及汲極D1上全面性地形成平坦層140。接著圖案化平坦層140,例如進行一道或多道圖案化步驟,以於平坦層140形成接觸洞H4~H6。接觸洞H4~H6分別暴露出至少部分的導電材料結構182S、源極S1及汲極D1。在一些實施例中,接觸洞H4沿方向Z於基板100上的投影可與接觸洞H1沿方向Z於基板100上的投影重疊且對齊,在此情況下,接觸洞H4與接觸洞H1的形狀、面積、尺寸且/或位置均相同,但本發明不限於此。 2B, a flat layer 140 is formed on the interlayer dielectric layer 130, the conductive material structure 182S, the source electrode S1, and the drain electrode D1. Next, the flat layer 140 is patterned, for example, one or more patterning steps are performed to form contact holes H4~H6 in the flat layer 140. The contact holes H4 to H6 respectively expose at least part of the conductive material structure 182S, the source electrode S1 and the drain electrode D1. In some embodiments, the projection of the contact hole H4 on the substrate 100 in the direction Z may overlap and align with the projection of the contact hole H1 on the substrate 100 in the direction Z. In this case, the shapes of the contact hole H4 and the contact hole H1 , Area, size and/or location are the same, but the invention is not limited thereto.

接著於平坦層140上形成導電材料結構181S及畫素電極PE1。其中,形成導電材料結構181S及畫素電極PE1的材料填入接觸洞H4~H6,而使導電材料結構181S及畫素電極PE1分別接觸導電材料結構182S、源極S1及汲極D1。在一些實施例中,導電材料結構181S及畫素電極PE1可於同一道程序中一併形成,也 就是說,於形成導電材料結構181S的導電圖案181P1時,一併形成畫素電極PE1於基板100的上表面100T上。其中,導電材料結構181S及畫素電極PE1的形成方法可包括物理氣相沉積法或化學氣相沉積法,並且,於平坦層140上全面性地形成一層材料層(未繪示)後,進行一道或多道圖案化步驟。在另一些實施例中,導電材料結構181S及畫素電極PE1也可於不同道程序中分別形成。在一些實施例中,圖1B中的導電材料結構183S也可與導電材料結構181S及畫素電極PE1於同一道程序中一併形成。 Next, a conductive material structure 181S and a pixel electrode PE1 are formed on the flat layer 140. The materials forming the conductive material structure 181S and the pixel electrode PE1 are filled into the contact holes H4 to H6, so that the conductive material structure 181S and the pixel electrode PE1 contact the conductive material structure 182S, the source electrode S1, and the drain electrode D1, respectively. In some embodiments, the conductive material structure 181S and the pixel electrode PE1 may be formed together in the same procedure, also That is, when the conductive pattern 181P1 of the conductive material structure 181S is formed, the pixel electrode PE1 is also formed on the upper surface 100T of the substrate 100. The method for forming the conductive material structure 181S and the pixel electrode PE1 may include physical vapor deposition or chemical vapor deposition, and after forming a material layer (not shown) on the flat layer 140 in a comprehensive manner, One or more patterning steps. In other embodiments, the conductive material structure 181S and the pixel electrode PE1 can also be formed separately in different procedures. In some embodiments, the conductive material structure 183S in FIG. 1B can also be formed together with the conductive material structure 181S and the pixel electrode PE1 in the same process.

請參照圖2C,於基板100上形成貫穿基板100的貫孔100Va。在一些實施例中,圖1B中的貫孔100Vb也可與貫孔100Va於同一道程序中一併形成。貫孔100Va的形成方法可包括雷射或蝕刻(如乾式蝕刻)。貫孔100Va沿方向Z於基板100上的投影面積小於接觸洞H1、H4沿方向Z於基板100上的投影面積。在一些實施例中,接著還會將承載基板自基板100移除,即進行離型程序。於基板100上形成貫穿基板100的貫孔100Va之後,形成表面處理覆膜102。在一些實施例中,可利用表面金屬化程序而形成表面處理覆膜102。在一些實施例中,可藉由物理性處理(如電漿處理)或化學性處理(如強鹼處理)來進行基板100的表面開環(ring opening),即打開基板100的雜環或打開較弱的鍵結,接著,對基板100的表面進行金屬離子交換,接著,再還原金屬至基板100的表面,而形成表面處理覆膜102。表面處理覆膜102包覆基板100的貫孔100Va、100Vb以及基板100的下表面100B, 其可作為晶種層(seed layer),而利於導通結構190的形成,或可加強基板100與導通柱190P1a、190P1b的結合情形。 Referring to FIG. 2C, a through hole 100Va penetrating the substrate 100 is formed on the substrate 100. In some embodiments, the through hole 100Vb in FIG. 1B may be formed together with the through hole 100Va in the same procedure. The formation method of the through hole 100Va may include laser or etching (such as dry etching). The projected area of the through hole 100Va on the substrate 100 in the direction Z is smaller than the projected area of the contact holes H1 and H4 on the substrate 100 in the direction Z. In some embodiments, the carrier substrate is then removed from the substrate 100, that is, a release process is performed. After the through-hole 100Va penetrating the substrate 100 is formed in the substrate 100, the surface treatment film 102 is formed. In some embodiments, the surface treatment coating 102 can be formed using a surface metallization process. In some embodiments, the ring opening of the surface of the substrate 100 may be performed by physical treatment (such as plasma treatment) or chemical treatment (such as strong alkali treatment), that is, opening the heterocycle or opening of the substrate 100 For the weaker bond, metal ion exchange is performed on the surface of the substrate 100, and then the metal is reduced to the surface of the substrate 100 to form the surface treatment film 102. The surface treatment film 102 covers the through holes 100Va, 100Vb of the substrate 100 and the lower surface 100B of the substrate 100, It can be used as a seed layer to facilitate the formation of the conductive structure 190, or can strengthen the combination of the substrate 100 and the conductive pillars 190P1a, 190P1b.

請參照圖2D,形成導通結構190及導電材料結構186S。導通結構190及導電材料結構186S的形成方法可包括物理氣相沉積法或化學氣相沉積法,並且,於形成一層材料層(未繪示)後,進行一道或多道圖案化步驟。如此一來,導通結構190的線路層190L可圖案化為圖1B所示的訊號線190L1、190L2a~190L5a、190L2b~190L5b,並且,導通結構190的導通部190Pa可圖案化出連接區塊190Sa。在一些實施例中,導通結構190及導電材料結構186S可於同一道程序中一併形成。在另一些實施例中,導通結構190及導電材料結構186S也可於不同道程序中分別形成。其中,形成導電材料結構186S的材料填入接觸洞H6,而使導電材料結構186S的導電圖案186P接觸汲極D1。 Referring to FIG. 2D, a conductive structure 190 and a conductive material structure 186S are formed. The forming method of the conductive structure 190 and the conductive material structure 186S may include a physical vapor deposition method or a chemical vapor deposition method, and after forming a material layer (not shown), one or more patterning steps are performed. In this way, the circuit layer 190L of the conductive structure 190 can be patterned into the signal lines 190L1, 190L2a~190L5a, 190L2b~190L5b shown in FIG. 1B, and the conductive portion 190Pa of the conductive structure 190 can pattern the connection block 190Sa. In some embodiments, the conductive structure 190 and the conductive material structure 186S may be formed together in the same process. In other embodiments, the conductive structure 190 and the conductive material structure 186S can also be formed separately in different procedures. The material forming the conductive material structure 186S fills the contact hole H6, and the conductive pattern 186P of the conductive material structure 186S contacts the drain D1.

此外,導通結構190的線路層190L及導通部(如導通部190Pa及圖1B所示的導通部190Pb)可一體成形,也就是說,線路層190L及導通部在同一個程序中形成。形成導通結構190的材料填入貫孔100Va、導電圖案181P1的開口181H1以及導電圖案182P的開口182H,而使導通結構190的導通部190Pa的導通柱190P1a與貫孔100Va、開口181H1、182H嵌合而貫穿基板100及基板100的上表面100T上的膜層。形成導通結構190的材料填入導電圖案181P2的開口181H2,而使導通結構190的導通部190Pa的導通柱190P2a接觸源極S1。導電材料結構181S、182S可作為 晶種層(seed layer),其利於導通柱190P1a、190P2a的形成,或者可提升導通柱190P1a、190P2a的形成均勻度,或者可加強導通柱190P1a、190P2a與緩衝層110a、110b、閘絕緣層120a、120b、層間介電層130及/或平坦層140的結合情形。位於基板100上表面100T上的主動元件T1的源極S1可藉由導通部190Pa耦接至位於基板100下表面100B上的線路層190L。 In addition, the circuit layer 190L and the conductive part (such as the conductive part 190Pa and the conductive part 190Pb shown in FIG. 1B) of the conductive structure 190 can be integrally formed, that is, the circuit layer 190L and the conductive part are formed in the same process. The material forming the conductive structure 190 fills the through hole 100Va, the opening 181H1 of the conductive pattern 181P1, and the opening 182H of the conductive pattern 182P, so that the conductive post 190P1a of the conductive portion 190Pa of the conductive structure 190 is fitted with the through hole 100Va, the openings 181H1, 182H On the other hand, it penetrates the substrate 100 and the film layer on the upper surface 100T of the substrate 100. The material forming the conductive structure 190 fills the opening 181H2 of the conductive pattern 181P2 so that the conductive pillar 190P2a of the conductive portion 190Pa of the conductive structure 190 contacts the source electrode S1. Conductive material structure 181S, 182S can be used as A seed layer, which facilitates the formation of the conductive pillars 190P1a, 190P2a, or can improve the uniformity of the formation of the conductive pillars 190P1a, 190P2a, or can strengthen the conductive pillars 190P1a, 190P2a and the buffer layers 110a, 110b, and the gate insulating layer 120a , 120b, the combination of the interlayer dielectric layer 130 and/or the flat layer 140. The source S1 of the active device T1 on the upper surface 100T of the substrate 100 can be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through the conductive portion 190Pa.

請一併參照圖1A及圖2D,於形成導通結構190之後,於導電材料結構186S上形成發光單元L1。並且,將驅動電路IC及基板199設置於基板100的下表面100B上,並接合至導通結構190的線路層190L。於此,可完成顯示面板10的製作。 Please refer to FIG. 1A and FIG. 2D together. After the conductive structure 190 is formed, the light emitting unit L1 is formed on the conductive material structure 186S. Furthermore, the driving circuit IC and the substrate 199 are provided on the lower surface 100B of the substrate 100 and bonded to the circuit layer 190L of the conductive structure 190. Here, the manufacturing of the display panel 10 can be completed.

在圖1A及圖1B中,導電材料結構181S的導電圖案181P1以及導電材料結構182S的導電圖案182P分別包覆導通部190Pa的導通柱190P1a的側壁,且導電材料結構183S的導電圖案183P1以及導電材料結構184S的導電圖案184P分別包覆導通部190Pb的導通柱190P1b的側壁。然而,本發明不以此為限,導電材料結構可依據不同設計考量而選擇性設置。舉例來說,請參照圖3A及圖3B,圖3A及圖3B分別是本發明一實施方式的顯示面板30局部的剖面示意圖。本實施例的顯示面板30與圖1A及圖1B所述實施例的顯示面板10兩者結構相似,不同之處在於,顯示面板30不包括導電材料結構182S、184S。在此情況下,導電材料結構181S的導電圖案181P1的底表面接觸層間介電層130的頂表面,導電材料結構183S的導電圖案183P1的底表面接觸層間介電層130的 頂表面。導電材料結構181S的導電圖案181P1及表面處理覆膜102包覆導通部190Pa的導通柱190P1a的部分側壁,且導通柱190P1a的部分側壁未接觸導電材料。導電材料結構183S的導電圖案183P1以及表面處理覆膜102包覆導通部190Pb的導通柱190P1b的部分側壁,且導通柱190P1b的部分側壁未接觸導電材料。在一些實施例中,緩衝層110a、110b、閘絕緣層120a、120b、層間介電層130中形成的接觸洞H1’以及導電圖案181P1的開口181H1連通至貫孔100Va,且接觸洞H1’、開口181H1以及貫孔100Va沿方向Z於基板100上的投影重疊且對齊,在此情況下,接觸洞H1’、開口181H1以及貫孔100Va的形狀、面積、尺寸且/或位置均相同,但本發明不限於此。 In FIGS. 1A and 1B, the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively cover the sidewalls of the conductive pillars 190P1a of the conductive portion 190Pa, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive material The conductive patterns 184P of the structure 184S respectively cover the sidewalls of the conductive pillars 190P1b of the conductive portion 190Pb. However, the invention is not limited to this, and the conductive material structure can be selectively set according to different design considerations. For example, please refer to FIGS. 3A and 3B. FIGS. 3A and 3B are schematic partial cross-sectional views of a display panel 30 according to an embodiment of the present invention. The display panel 30 of this embodiment is similar in structure to the display panel 10 of the embodiment described in FIGS. 1A and 1B, except that the display panel 30 does not include conductive material structures 182S and 184S. In this case, the bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the interlayer dielectric layer 130, and the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the interlayer dielectric layer 130. Top surface. The conductive pattern 181P1 of the conductive material structure 181S and the surface treatment film 102 cover part of the sidewalls of the conductive pillar 190P1a of the conductive portion 190Pa, and the partial sidewalls of the conductive pillar 190P1a do not contact the conductive material. The conductive pattern 183P1 of the conductive material structure 183S and the surface treatment film 102 cover part of the side walls of the conductive pillar 190P1b of the conductive portion 190Pb, and part of the side walls of the conductive pillar 190P1b do not contact the conductive material. In some embodiments, the buffer holes 110a, 110b, the gate insulating layers 120a, 120b, the contact hole H1' formed in the interlayer dielectric layer 130, and the opening 181H1 of the conductive pattern 181P1 communicate with the through hole 100Va, and the contact hole H1', The projections of the opening 181H1 and the through hole 100Va on the substrate 100 in the direction Z are overlapped and aligned. In this case, the shape, area, size, and/or position of the contact hole H1′, the opening 181H1, and the through hole 100Va are the same, but the original The invention is not limited to this.

此外,請參照圖4A及圖4B,圖4A及圖4B分別是本發明一實施方式的顯示面板40局部的剖面示意圖。本實施例的顯示面板40與圖3A及圖3B所述實施例的顯示面板30兩者結構相似,不同之處在於,顯示面板40除了不包括導電材料結構182S、184S,顯示面板40中的導電材料結構181S’的導電圖案181P1’的底表面接觸基板100的上表面100T,且導電材料結構183S’的導電圖案183P1’的底表面接觸基板100的上表面100T。導電材料結構181S’的導電圖案181P1’及表面處理覆膜102完全包覆導通部190Pa的導通柱190P1a的側壁,且導電材料結構183S’的導電圖案183P1’以及表面處理覆膜102完全包覆導通部190Pb的導通柱190P1b的側壁。此外,導電圖案181P1’的開口181H1’連通至貫孔 100Va,導電圖案183P1’的開口183H1’連通至貫孔100Vb。 In addition, please refer to FIGS. 4A and 4B, which are partial cross-sectional schematic views of the display panel 40 according to an embodiment of the present invention. The display panel 40 of this embodiment is similar in structure to the display panel 30 of the embodiment described in FIGS. 3A and 3B, except that the display panel 40 does not include conductive material structures 182S and 184S. The bottom surface of the conductive pattern 181P1' of the material structure 181S' contacts the upper surface 100T of the substrate 100, and the bottom surface of the conductive pattern 183P1' of the conductive material structure 183S' contacts the upper surface 100T of the substrate 100. The conductive pattern 181P1' of the conductive material structure 181S' and the surface treatment film 102 completely cover the sidewall of the conductive post 190P1a of the conductive portion 190Pa, and the conductive pattern 183P1' of the conductive material structure 183S' and the surface treatment film 102 completely cover the conduction The side wall of the conductive post 190P1b of the portion 190Pb. In addition, the opening 181H1' of the conductive pattern 181P1' communicates with the through hole 100Va, the opening 183H1' of the conductive pattern 183P1' communicates with the through hole 100Vb.

基板100中的貫孔(如貫孔100Va、100Vb)可依據不同設計考量而設置於基板100中。舉例來說,請參照圖5,圖5是本發明一實施方式的顯示面板50的平面示意圖。如圖5所示,顯示面板50可包括基板500、599a、599b以及導通結構的訊號線590L1a~590L22a、590L1b~590L18b。其中,圖5的顯示面板50可應用於圖1A至圖4B的顯示面板10~40中,而作為圖1A至圖4B的顯示面板10~40的實施例。因此,基板500可對應基板100,基板599a、599b可分別對應基板199,訊號線590L1a~590L22a、590L1b~590L18b可分別對應訊號線190L1~190L5b。並且,為便於說明,圖5的顯示面板50主要繪示出基板500的下表面的一側,圖5中省略繪示基板500的上表面上的元件。 The through holes in the substrate 100 (such as the through holes 100Va and 100Vb) can be provided in the substrate 100 according to different design considerations. For example, please refer to FIG. 5, which is a schematic plan view of a display panel 50 according to an embodiment of the present invention. As shown in FIG. 5, the display panel 50 may include substrates 500, 599a, 599b and signal lines 590L1a~590L22a, 590L1b~590L18b of the conductive structure. The display panel 50 of FIG. 5 can be applied to the display panels 10-40 of FIGS. 1A-4B as an embodiment of the display panels 10-40 of FIGS. 1A-4B. Therefore, the substrate 500 can correspond to the substrate 100, the substrates 599a and 599b can respectively correspond to the substrate 199, and the signal lines 590L1a to 590L22a and 590L1b to 590L18b can respectively correspond to the signal lines 190L1 to 190L5b. In addition, for ease of description, the display panel 50 of FIG. 5 mainly illustrates one side of the lower surface of the substrate 500, and the elements on the upper surface of the substrate 500 are omitted in FIG.

如圖5所示,基板500可具有貫穿基板500的貫孔500V1a~500V22a、500V1b~500V18b。在圖5中,貫孔500V1a~500V22a、500V1b~500V18b分別沿著一矩形路徑排列,但本發明不以此為限,貫孔的排列方式可依據不同設計考量而調整,例如沿著其他形狀的路徑排列,或者呈陣列排列,或者不規則排列。此外,基板500可具有顯示區與非顯示區。在一些實施例中,貫孔500V1a~500V22a、500V1b~500V18b可均分布於顯示區。在另一些實施例中,貫孔500V1a~500V22a、500V1b~500V18b可均分布於非顯示區,並且,貫孔500V1a~500V22a、500V1b~500V18b對應的兩個矩形路徑各自圍繞基板500的兩個顯 示區。在另一些實施例中,一部分的貫孔500V1a~500V22a、500V1b~500V18b可分布於非顯示區,另一部分的貫孔500V1a~500V22a、500V1b~500V18b可分布於非顯示區。 As shown in FIG. 5, the substrate 500 may have through holes 500V1a to 500V22a and 500V1b to 500V18b penetrating the substrate 500. In FIG. 5, the through holes 500V1a to 500V22a and 500V1b to 500V18b are arranged along a rectangular path, but the invention is not limited to this. The arrangement of the through holes can be adjusted according to different design considerations, for example, along other shapes The paths are arranged either in an array or irregularly. In addition, the substrate 500 may have a display area and a non-display area. In some embodiments, the through holes 500V1a to 500V22a and 500V1b to 500V18b may be distributed in the display area. In other embodiments, the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area, and the two rectangular paths corresponding to the through holes 500V1a to 500V22a, 500V1b to 500V18b each surround the two displays of the substrate 500. 示区。 Show area. In other embodiments, a part of the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area, and another part of the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area.

如圖5所示,顯示面板50的導通結構的每個訊號線590L1a~590L22a、590L1b~590L18b的一端分別連接至貫孔500V1a~500V22a、500V1b~500V18b,每個訊號線590L1a~590L22a、590L1b~590L18b的另一端分別連接至接合區BDa、BDb。在一些實施例中,基板100藉由接合區BDa、BDb與基板599a、599b相接合,在一些實施例中,基板100的線路藉由接合區BDa、BDb分別耦接至基板599a、599b上的驅動電路。 As shown in FIG. 5, one end of each signal line 590L1a to 590L22a, 590L1b to 590L18b of the conducting structure of the display panel 50 is respectively connected to the through holes 500V1a to 500V22a, 500V1b to 500V18b, and each signal line 590L1a to 590L22a, 590L1b to 590L18b The other ends are connected to the junction areas BDa and BDb, respectively. In some embodiments, the substrate 100 is bonded to the substrates 599a and 599b through the bonding areas BDa and BDb. In some embodiments, the circuit of the substrate 100 is coupled to the substrates 599a and 599b through the bonding areas BDa and BDb respectively Drive circuit.

此外,請參照圖6,圖6分別是本發明一實施方式的顯示面板60局部的剖面示意圖。本實施例的顯示面板60與圖1A及圖1B所述實施例的顯示面板10兩者結構相似,不同之處在於,除了緩衝層110a、110b、閘絕緣層120a、120b、層間介電層130、平坦層140、驅動電路IC、主動元件T1、發光單元L1以及畫素電極PE1,顯示面板60另包括基板600、699、緩衝層610a、610b、閘絕緣層620a、620b、一層間介電層630、一絕緣層640、一線路層650、導電材料結構681S、682S、683S、684S、685S、686S、導通部690Pa、690Pb、690Pc、一主動元件T2、一發光單元L2以及一畫素電極PE2。 In addition, please refer to FIG. 6, which is a schematic partial cross-sectional view of a display panel 60 according to an embodiment of the present invention. The display panel 60 of this embodiment has a similar structure to the display panel 10 of the embodiment described in FIGS. 1A and 1B except for the buffer layers 110a and 110b, the gate insulating layers 120a and 120b, and the interlayer dielectric layer 130. , Flat layer 140, driving circuit IC, active element T1, light emitting unit L1 and pixel electrode PE1, the display panel 60 further includes substrates 600, 699, buffer layers 610a, 610b, gate insulating layers 620a, 620b, an interlayer dielectric layer 630, an insulating layer 640, a circuit layer 650, a conductive material structure 681S, 682S, 683S, 684S, 685S, 686S, a conducting part 690Pa, 690Pb, 690Pc, an active element T2, a light emitting unit L2 and a pixel electrode PE2 .

主動元件T2可包括半導體層SE2、源極S2、汲極D2及閘極G2。半導體層SE2可包括源極區SP2a、SP2b、汲極區DP2a、 DP2b及通道區CH2。導電材料結構681S、682S、684S~686S設置於基板600的上表面600T上,導電材料結構683S設置於基板600的下表面600B上。導電材料結構681S~684S的導電圖案681P~684P分別連接至導電材料結構681S~684S的連接圖案681C~684C;類似地,導電材料結構685S、686S的導電圖案(圖未示)分別連接至導電材料結構685S、686S的連接圖案685C、686C。導通部690Pa、690Pb的連接區塊690Sa、690Sb分別連接至導通部690Pa、690Pb的導通柱690P1a、690P1b,導通部690Pc的連接區塊690Sc分別連接至導通部690Pc的導通柱(圖未示)。 The active device T2 may include a semiconductor layer SE2, a source S2, a drain D2, and a gate G2. The semiconductor layer SE2 may include source regions SP2a, SP2b, drain regions DP2a, DP2b and channel area CH2. The conductive material structures 681S, 682S, 684S-686S are disposed on the upper surface 600T of the substrate 600, and the conductive material structures 683S are disposed on the lower surface 600B of the substrate 600. The conductive patterns 681P~684P of the conductive material structures 681S~684S are respectively connected to the connection patterns 681C~684C of the conductive material structures 681S~684S; similarly, the conductive patterns (not shown) of the conductive material structures 685S and 686S are respectively connected to the conductive materials The connection patterns 685C and 686C of the structure 685S and 686S. The connection blocks 690Sa and 690Sb of the conduction parts 690Pa and 690Pb are respectively connected to the conduction columns 690P1a and 690P1b of the conduction parts 690Pa and 690Pb, and the connection blocks 690Sc of the conduction part 690Pc are respectively connected to the conduction columns of the conduction part 690Pc (not shown).

導通部690Pa的導通柱690P1a與貫孔600V嵌合而貫穿基板600,且導電材料結構681S的導電圖案681P1、導電材料結構682S的導電圖案682P以及導電材料結構683S的導電圖案683P分別包覆導通部690Pa的導通柱690P1a的側壁,而利於導通柱690P1a的形成。導電材料結構684S的導電圖案684P包覆導通部690Pb的導通柱690P1b的側壁而利於導通柱690P1b的形成,導電材料結構685S的導電圖案(圖未示)包覆導通部690Pc的導通柱(圖未示)的側壁而利於導通柱的形成。 The conductive post 690P1a of the conductive portion 690Pa is fitted into the through hole 600V to penetrate the substrate 600, and the conductive pattern 681P1 of the conductive material structure 681S, the conductive pattern 682P of the conductive material structure 682S, and the conductive pattern 683P of the conductive material structure 683S respectively cover the conductive portion The side wall of the conductive post 690P1a of 690Pa facilitates the formation of the conductive post 690P1a. The conductive pattern 684P of the conductive material structure 684S covers the sidewalls of the conductive pillar 690P1b of the conductive portion 690Pb to facilitate the formation of the conductive pillar 690P1b. The conductive pattern of the conductive material structure 685S (not shown) covers the conductive pillar of the conductive portion 690Pc (not shown) The side wall shown) is conducive to the formation of conductive pillars.

位於基板600上表面600T上的發光單元L2可藉由導通部690Pa耦接至位於基板600下表面600B上的主動元件T2的源極S2。如此一來,可充分利用基板600上表面600T以及下表面600B的空間進行佈線,而可縮小顯示面板60的尺寸,進而達成尺寸微型化。 The light-emitting unit L2 on the upper surface 600T of the substrate 600 can be coupled to the source S2 of the active device T2 on the lower surface 600B of the substrate 600 through the conducting portion 690Pa. In this way, the space on the upper surface 600T and the lower surface 600B of the substrate 600 can be fully utilized for wiring, and the size of the display panel 60 can be reduced to achieve miniaturization.

綜上所述,本發明的顯示面板具有貫穿基板的貫孔,因此位於基板的上表面的元件可藉由嵌入貫孔的導通結構或導通部,而耦接至位於基板的下表面的元件,如此一來,可達成尺寸微型化,或者可縮減基板上的佈線區域面積(即不發光區域),而可實現窄邊框設計或是無縫拼接設計。此外,本發明的顯示面板以導電材料結構的導電圖案或基板的表面處理覆膜作為晶種層,其包覆導通結構或導通部,而利於導通結構或導通部的形成。 In summary, the display panel of the present invention has a through hole penetrating through the substrate. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the lower surface of the substrate through the conductive structure or the conductive portion embedded in the through hole. In this way, the miniaturization of the size can be achieved, or the area of the wiring area (ie, the non-light emitting area) on the substrate can be reduced, and a narrow frame design or a seamless splicing design can be realized. In addition, the display panel of the present invention uses the conductive pattern of the conductive material structure or the surface treatment coating of the substrate as the seed layer, which covers the conductive structure or the conductive part, which is beneficial to the formation of the conductive structure or the conductive part.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10:顯示面板 10: Display panel

100、199:基板 100, 199: substrate

100B:下表面 100B: Lower surface

100T:上表面 100T: upper surface

100Va:貫孔 100Va: through hole

102:表面處理覆膜 102: Surface treatment coating

110a、110b:緩衝層 110a, 110b: buffer layer

120a、120b:閘絕緣層 120a, 120b: gate insulating layer

130:層間介電層 130: Interlayer dielectric layer

140:平坦層 140: flat layer

181C、182C、186C:連接圖案 181C, 182C, 186C: connection pattern

181H1、181H2、182H:開口 181H1, 181H2, 182H: opening

181P1、181P2、182P、186P:導電圖案 181P1, 181P2, 182P, 186P: conductive pattern

181S、182S、186S:導電材料結構 181S, 182S, 186S: conductive material structure

190:導通結構 190: conduction structure

190L:線路層 190L: line layer

190L1:訊號線 190L1: Signal cable

190P1a、190P2a:導通柱 190P1a, 190P2a: conduction column

190Pa:導通部 190Pa: conduction part

190Sa:連接區塊 190Sa: connection block

CH1:通道區 CH1: Channel area

D1:汲極 D1: Drain

DP1a、DP1b:汲極區 DP1a, DP1b: Drain area

G1:閘極 G1: Gate

IC:驅動電路 IC: drive circuit

L1:發光單元 L1: light emitting unit

LL:特徵長度 LL: characteristic length

PE1:畫素電極 PE1: pixel electrode

PE1a、PE1b:電極圖案 PE1a, PE1b: electrode pattern

S1:源極 S1: source

SE1:半導體層 SE1: Semiconductor layer

SP1a、SP1b:源極區 SP1a, SP1b: source region

T1:主動元件 T1: Active component

XX:交線 XX: intersection line

X、Y、Z:方向 X, Y, Z: direction

Claims (9)

一種顯示面板,包括:一基板,具有貫穿該基板的多個貫孔;多個主動元件,呈陣列排列且設置於該基板的一上表面上;一導通結構,包括:一線路層,設置於該基板的一下表面上;多個第一導通柱,該些第一導通柱分別與該些貫孔嵌合而貫穿該基板,該些第一導通柱分別耦接該線路層與該些主動元件之間;以及多個導通部,各該導通部包括該些第一導通柱中的一第一導通柱、一第二導通柱以及一連接區塊,各該第一導通柱電性連接至該線路層,該些第二導通柱分別電性連接至該些主動元件,並且該些連接區塊分別電性連接於該些第一導通柱與該些第二導通柱之間;以及多個第一導電圖案,設置於該基板的該上表面上,該些第一導電圖案分別包覆該些第一導通柱的側壁。 A display panel includes: a substrate having a plurality of through holes penetrating the substrate; a plurality of active elements arranged in an array and arranged on an upper surface of the substrate; a conducting structure including: a circuit layer, which is arranged on On the lower surface of the substrate; a plurality of first conductive pillars, the first conductive pillars are respectively fitted with the through holes to penetrate the substrate, the first conductive pillars are respectively coupled to the circuit layer and the active devices Between; and a plurality of conducting parts, each of the conducting parts includes a first conducting post, a second conducting post and a connecting block among the first conducting posts, each of the first conducting posts is electrically connected to the In the circuit layer, the second conductive pillars are electrically connected to the active devices, respectively, and the connecting blocks are electrically connected between the first conductive pillars and the second conductive pillars; A conductive pattern is disposed on the upper surface of the substrate, and the first conductive patterns respectively cover the sidewalls of the first conductive pillars. 如申請專利範圍第1項所述的顯示面板,另包括一驅動電路,位於該基板的該下表面上,該線路層電性連接於該些第一導通柱與該驅動電路之間。 The display panel as described in item 1 of the patent application scope further includes a driving circuit located on the lower surface of the substrate, and the circuit layer is electrically connected between the first conducting posts and the driving circuit. 如申請專利範圍第1項所述的顯示面板,另包括多個第一導電材料結構,設置於該基板的該上表面上,各該第一導電材料結構包括該些第一導電圖案中的一第一導電圖案、一第二導電 圖案以及一連接圖案,該些第二導電圖案分別包覆該些第二導通柱,並且該些連接圖案分別電性連接於該些第一導電圖案與該些第二導電圖案之間。 The display panel as described in item 1 of the patent application scope further includes a plurality of first conductive material structures disposed on the upper surface of the substrate, and each of the first conductive material structures includes one of the first conductive patterns First conductive pattern, a second conductive A pattern and a connection pattern, the second conductive patterns respectively cover the second conductive posts, and the connection patterns are electrically connected between the first conductive patterns and the second conductive patterns, respectively. 如申請專利範圍第3項所述的顯示面板,其中各該導通部於該基板上之一第一投影的外輪廓與各該第一導電材料結構於該基板上之一第二投影的外輪廓重疊。 The display panel according to item 3 of the patent application scope, wherein the outer contour of each first projection of the conducting portion on the substrate and the outer contour of a second projection of each first conductive material structure on the substrate overlapping. 如申請專利範圍第1項所述的顯示面板,另包括多個第二導電材料結構,各該第二導電材料結構包括一第三導電圖案,該些第三導電圖案分別包覆該些第一導通柱。 The display panel as described in Item 1 of the patent application scope further includes a plurality of second conductive material structures, each of the second conductive material structures includes a third conductive pattern, and the third conductive patterns respectively cover the first Conducting column. 如申請專利範圍第5項所述的顯示面板,其中各該第一導電圖案的一底表面接觸該該基板的該上表面或該第二導電材料結構的一頂表面。 The display panel according to item 5 of the patent application scope, wherein a bottom surface of each of the first conductive patterns contacts the top surface of the substrate or a top surface of the second conductive material structure. 一種顯示面板製作方法,包括:形成多個主動元件於一基板的一上表面上,該些主動元件呈陣列排列;形成多個第一導電圖案於該基板的該上表面上;以及形成貫穿該基板的多個貫孔;以及形成一導通結構,該導通結構包括一線路層、多個第一導通柱以及多個導通部,該線路層設置於該基板的一下表面上,該些第一導通柱分別與該些貫孔嵌合而貫穿該基板,該些第一導通柱分別耦接該線路層與該些主動元件之間,其中各導通部包括該些第一導通柱中的一第一導通柱、一第 二導通柱以及一連接區塊,各該第一導通柱電性連接至該線路層,該些第二導通柱分別電性連接至該些主動元件,並且該些連接區塊分別電性連接於該些第一導通柱與該些第二導通柱之間,其中該些第一導電圖案分別包覆該些第一導通柱的側壁。 A display panel manufacturing method includes: forming a plurality of active elements on an upper surface of a substrate, the active elements are arranged in an array; forming a plurality of first conductive patterns on the upper surface of the substrate; and forming a through A plurality of through holes of the substrate; and forming a conductive structure, the conductive structure includes a circuit layer, a plurality of first conductive pillars and a plurality of conductive parts, the circuit layer is disposed on the lower surface of the substrate, the first conductive The pillars are respectively fitted with the through holes to penetrate the substrate, and the first conductive pillars are respectively coupled between the circuit layer and the active devices, wherein each conductive portion includes a first of the first conductive pillars Conducting column, first Two conductive pillars and a connection block, each of the first conductive pillars is electrically connected to the circuit layer, the second conductive pillars are electrically connected to the active devices, respectively, and the connection blocks are electrically connected to the Between the first conductive pillars and the second conductive pillars, wherein the first conductive patterns respectively cover the sidewalls of the first conductive pillars. 如申請專利範圍第7項所述的顯示面板製作方法,其中於形成該些第一導電圖案時,一併形成多個畫素電極於該基板的該上表面上,該些畫素電極分別電性連接該些主動元件。 The method for manufacturing a display panel as described in item 7 of the patent application scope, wherein when forming the first conductive patterns, a plurality of pixel electrodes are formed on the upper surface of the substrate, and the pixel electrodes are electrically To connect these active components. 如申請專利範圍第7項所述的顯示面板製作方法,其中於形成貫穿該基板的該些貫孔之後,形成一表面處理覆膜,該表面處理覆膜包覆該基板的該些貫孔以及該基板的該下表面。 The method for manufacturing a display panel according to item 7 of the patent application scope, wherein after forming the through holes penetrating the substrate, a surface treatment film is formed, the surface treatment film covering the through holes of the substrate and The lower surface of the substrate.
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