TWI696868B - Display panel and display panel menufacturing method - Google Patents

Abstract

A display panel includes a substrate, a plurality of active device, a conduction structure, and a plurality of first conductive patterns. The substrate has a plurality of through holes passing through the substrate. The active devices are arranged in an array on an upper surface of the substrate. The conduction structure includes a wiring layer disposed on a lower surface of the substrate and a plurality of first conduction pillars. The first conduction pillars are embedded in the through holes and penetrate the substrate respectively. The first conduction pillars are coupled between the wiring layer and the active devices respectively. The first conductive patterns disposed on the upper surface of the substrate cover sidewalls of the first conduction pillars respectively.

Description

Display panel and display panel manufacturing method

The invention relates to an electronic device and a manufacturing method of the electronic device, and in particular to a display panel and a manufacturing method of the display panel.

In general, the display panel may have a display area and a non-display area located around the display area. The non-display area may include a wiring area to set traces and a drive circuit area to set a drive circuit for driving active elements in the display panel, such as a source drive circuit or a gate drive circuit. Therefore, the non-display area of the display panel cannot Display images and affect the design of the display panel.

Specifically, when the area of the non-display area is reduced, the display area occupies a larger area of the display panel, and correspondingly more pixels are provided, so the resolution of the display panel can be improved. When the area of the non-display area is reduced, the boundary of the display area is closer to the outer edge of the display panel, so a narrow bezel design can be realized. For large display panels spliced together, the non-display area forms a splicing gap where images cannot be displayed, causing discontinuity in the overall image and affecting display quality. Therefore, the existing display panel still needs to be improved.

In one embodiment of the present invention, a display panel is provided, the structure of which is helpful for reducing the size of the display panel or reducing the area of the wiring area on the substrate.

An embodiment of the invention provides a display panel including a substrate, a plurality of active elements, a conductive structure, and a plurality of first conductive patterns. The substrate has a plurality of through holes penetrating the substrate. The active devices are arranged in an array and arranged on an upper surface of the substrate. The conducting structure includes a circuit layer disposed on a lower surface of the substrate and a plurality of first conducting pillars. The first conductive pillars are respectively fitted into the through holes to penetrate the substrate, and the first conductive pillars are respectively coupled between the circuit layer and the active devices. The first conductive patterns are disposed on the upper surface of the substrate, and the first conductive patterns respectively cover the sidewalls of the first conductive pillars.

An embodiment of the present invention provides a method for manufacturing a display panel, including forming a plurality of active elements on an upper surface of a substrate, forming a plurality of first conductive patterns on the upper surface of the substrate, and forming a plurality of A through hole and a conducting structure are formed. The active elements are arranged in an array. The conducting structure includes a circuit layer and a plurality of first conducting pillars. The circuit layer is disposed on the lower surface of the substrate. The first conducting posts are respectively fitted into the through holes and penetrate the substrate. The first conductive pillars are respectively coupled between the circuit layer and the active devices. The first conductive patterns respectively cover the sidewalls of the first conductive pillars.

The display panel according to the embodiment of the present invention has a through hole penetrating through the substrate. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the lower surface of the substrate by the conductive structure embedded in the through hole. Can be miniaturized, or It can reduce the area of the wiring area on the substrate, and can achieve a narrow border design or a seamless splicing design. In addition, the display panel of the present invention uses the conductive pattern of the conductive material structure or the surface treatment coating of the substrate as the seed layer, which covers the conductive structure, which is beneficial to the formation of the conductive structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

10, 30, 40, 50, 60: display panel

100, 199, 600, 699, 500, 599a, 599b: substrate

100B, 600B: lower surface

100T, 600T: upper surface

100Va, 100Vb, 500V1a~500V22a, 500V1b~500V18b, 600V: through hole

102: Surface treatment coating

110a, 110b, 610a, 610b: buffer layer

120a, 120b, 620a, 620b: gate insulating layer

130, 630: interlayer dielectric layer

140: flat layer

181C, 182C, 183C, 184C, 185C, 186C, 681C~686C: connection pattern

181H1, 181H2, 182H, 183H1, 183H2, 184H, 181H1’, 183H1’: opening

181P1, 181P2, 182P, 183P1, 183P2, 184P, 185P, 186P, 181P1’, 183P1’, 681P~684P: conductive patterns

181S, 182S, 183S, 184S, 185S, 186S, 181S’, 183S’, 681S, 682S, 683S, 684S, 685S, 686S: conductive material structure

190: conduction structure

190L, 650: line layer

190L1, 190L2a~190L5a, 190L2b~190L5b, 590L1a~590L22a, 590L1b~590L18b: signal line

190P1a, 190P2a, 190P1b, 190P2b, 690P1a, 690P1b: conductive column

190Pa, 190Pb, 690Pa, 690Pb, 690Pc: conduction part

190Sa, 190Sb, 690Sa, 690Sb, 690Sc: connection block

640: Insulation

BDa, BDb: junction zone

CH1, CH2: channel area

D1, D2: Drain

DP1a, DP1b, DP2a, DP2b: Drain region

G1, G2: Gate

H1~H3, H4~H6, H1’: contact hole

IC: drive circuit

L1, L2: light emitting unit

LL: characteristic length

PE1, PE2: pixel electrode

PE1a, PE1b, PE2c: electrode pattern

S1, S2: source

SE1, SE2: semiconductor layer

SP1a, SP1b, SP2a, SP2b: source region

T1, T2: active components

XX: intersection line

X, Y, Z: direction

1A and 1B are schematic partial cross-sectional views of a display panel according to an embodiment of the invention.

2A to 2D are schematic cross-sectional views of a manufacturing process of a partial area of the display panel shown in FIG. 1A.

3A and 3B are respectively partial cross-sectional schematic diagrams of a display panel according to an embodiment of the invention.

4A and 4B are schematic partial cross-sectional views of a display panel according to an embodiment of the invention.

5 is a schematic plan view of a display panel according to an embodiment of the invention.

6 is a schematic partial cross-sectional view of a display panel according to an embodiment of the present invention.

Direction words mentioned in the embodiment, for example: "up", "down", "front", "Rear", "Left", "Right", etc., are only the directions referring to the drawings. Therefore, the directional terms used are for illustration, not for limiting the invention. In the drawings, each drawing depicts general features of methods, structures, and/or materials used in certain exemplary embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these exemplary embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of the various film layers, regions, and/or structures may be reduced or enlarged.

In the embodiments, the same or similar elements will use the same or similar reference numbers, and the redundant description thereof will be omitted. In addition, the features in the different exemplary embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or the scope of the patent application are still covered by this patent. In addition, the terms "first" and "second" mentioned in this specification or the scope of patent application are only used to name discrete elements or distinguish different embodiments or ranges, not to limit the number of elements. The upper limit or the lower limit is not intended to limit the manufacturing order or setting order of the components.

FIGS. 1A and 1B are schematic partial cross-sectional views of a display panel 10 according to an embodiment of the present invention, wherein the cross-sections of FIGS. 1A and 1B intersect at an intersection line XX. 1A and 1B, the display panel 10 may include substrates 100, 199, buffer layers 110a, 110b, gate insulators (GI) 120a, 120b, and an inter-layer dielectric layer (inter-layer dielectric , ILD) 130, a planarization layer (PL) 140, conductive material structures 181S, 182S, 183S, 184S, 185S, 186S, a conductive structure 190, a driving circuit IC, an active element T1, a light-emitting unit L1 And a pixel electrode PE1. But the number of elements of the invention It is not limited to this, but can be appropriately adjusted according to different design considerations, that is to say, the display panel 10 may include one or more substrates, buffer layers, gate insulating layers, interlayer dielectric layers, flat layers, conductive material structures, conductive structures , Drive circuit, active element, light-emitting unit and pixel electrode.

The substrate 100 is suitable for carrying other components. It may have an upper surface 100T and a lower surface 100B opposite to each other, and the normal directions of the upper surface 100T and the lower surface 100B may be parallel to the direction Z. The substrate 100 may have a plurality of through holes (eg, through holes 100Va, 100Vb) penetrating the substrate 100. The substrate 100 includes a surface treatment film 102. The surface treatment film 102 covers the through holes 100Va, 100Vb of the substrate 100 and the lower surface 100B of the substrate 100. In this embodiment, the substrate 100 may be a flexible substrate, but the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a rigid substrate. The characteristic length LL of the through holes 100Va and 100Vb is between 5 microns (micrometer, μm) and 50 microns.

The buffer layers 110a and 110b are disposed on the substrate 100 and may be an inorganic thin film composed of an inorganic material, and the material constituting the buffer layers 110a and 110b may generally be an insulating material. The gate insulating layers 120a, 120b are disposed on the buffer layers 110a, 110b, and the material of the gate insulating layers 120a, 120b is, for example, silicon oxide, silicon nitride, or other insulating materials. The interlayer dielectric layer 130 is disposed on the gate insulating layers 120a and 120b, and the material of the interlayer dielectric layer 130 may include inorganic materials, organic materials, or a combination thereof. The flat layer 140 is disposed on the interlayer dielectric layer 130, and the material of the flat layer 140 may include various suitable organic materials.

Active components (such as active component T1) are disposed on the upper surface 100T of the substrate 100 Arranged in an array. In this embodiment, the active device T1 may be, for example, a top gate TFT. However, the present invention is not limited to this. In other embodiments, it can also be designed as a bottom gate TFT or other appropriate type of TFT. The active device T1 may include a semiconductor layer SE1, a source S1, a drain D1, and a gate G1. The semiconductor layer SE1 is disposed on the buffer layers 110a and 110b, and the material of the semiconductor layer SE1 is, for example, polycrystalline silicon (such as low temperature crystalline silicon (LTPS)), amorphous silicon (amorphous silicon), and metal oxide semiconductor (such as indium Indium Gallium Zinc Oxide (IGZO) or other semiconductor materials. The semiconductor layer SE1 may include source regions SP1a, SP1b, drain regions DP1a, DP1b, and channel region CH1. Part of the source S1 and the drain D1 are disposed on the interlayer dielectric layer 130, while the other parts of the source S1 and the drain D1 penetrate through the gate insulating layers 120a, 120b and the interlayer dielectric layer 130 and are respectively connected to the source region SP1a, SP1b is in contact with the semiconductor layer SE1 of the drain regions DP1a and DP1b.

Based on the consideration of conductivity, the materials of the conductive material structures 181S~185S are generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, and nitrogen oxides of metal materials. The conductive material structures 181S-185S are disposed on the upper surface 100T of the substrate 100. The conductive material structure 181S (also referred to as a first conductive material structure) may include a conductive pattern 181P1 (also referred to as a first conductive pattern), a conductive pattern 181P2 (also referred to as a second conductive pattern), and a connection pattern 181C. The conductive material structure 182S (also referred to as a second conductive material structure) may include a conductive pattern 182P (also referred to as a third conductive pattern) and a connection diagram Case 182C. Similarly, the conductive material structure 183S includes conductive patterns 183P1, 183P2 and a connection pattern 183C. The conductive material structures 184S, 185S, and 186S may include conductive patterns 184P, 185P, and 186P, and connection patterns 184C, 185C, and 186C, respectively.

In this embodiment, the conductive material structure 181S is electrically connected to the conductive material structure 182S, and the conductive material structure 183S is electrically connected to the conductive material structures 184S, 185S. The conductive patterns 181P1 to 186P extend substantially along the direction Z. The bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the conductive material structure 182S, the bottom surface of the conductive pattern 181P2 of the conductive material structure 181S contacts the source S1 of the active element T1, and the connection pattern 181C of the conductive material structure 181S is electrically It is connected between the conductive pattern 181P1 and the conductive pattern 181P2. The bottom surface of the conductive pattern 182P of the conductive material structure 182S contacts the upper surface 100T of the substrate 100, and the connection pattern 182C of the conductive material structure 182S is electrically connected to the conductive pattern 182P. Similarly, the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the top surface of the conductive material structure 184S, the bottom surface of the conductive pattern 183P2 of the conductive material structure 183S contacts the top surface of the conductive material structure 185S, and the connection pattern of the conductive material structure 183S 183C is electrically connected between the conductive pattern 183P1 and the conductive pattern 183P2. The bottom surface of the conductive pattern 184P of the conductive material structure 184S contacts the upper surface 100T of the substrate 100, and the connection pattern 184C of the conductive material structure 184S is electrically connected to the conductive pattern 184P. The bottom surface of the conductive pattern 185P of the conductive material structure 185S contacts the gate G1 of the active element T1, and the connection pattern 185C of the conductive material structure 185S is electrically connected to the conductive pattern 185P. The bottom surface of the conductive pattern 186P of the conductive material structure 186S contacts the drain D1 of the active element T1, and the connection pattern 186C of the conductive material structure 186S is electrically connected Connect to conductive pattern 186P.

The connection patterns 181C, 182C, 183C, 184C, 185C, and 186C are used to connect the conductive patterns, and their projection shapes on the substrate 100 in the direction Z can be adjusted adaptively according to different design considerations. The conductive patterns 181P1, 181P2, 182P, 183P1, 183P2, and 184P have openings 181H1, 181H2, 182H, 183H1, 183H2, and 184H, respectively, and are generally tubular hollow structures. The projected shapes of the conductive patterns 181P1 to 184P on the substrate 100 in the direction Z can also be adaptively adjusted according to different design considerations. In some embodiments, the inner and outer contours of the projected shape are conformal. For example, the inner and outer contours of the projected shape are both rectangular. In some embodiments, the inner and outer contours of the projected shape may be concentric circles, but it is not limited thereto. In this embodiment, the inner contour of the projected shapes of the conductive patterns 181P1 and 182P is the contour of the projections of the openings 181H1 to 182H, which can overlap and be aligned with the through holes 100Va. In this case, the projected shapes of the conductive patterns 181P1 and 182P The inner contour of is the same as the shape, area, size and/or position of the through hole 100Va, but the invention is not limited thereto. That is, the openings 181H1 to 182H communicate with the through hole 100Va. Similarly, the inner contours of the projected shapes of the conductive patterns 183P1 and 184P may be the contours of the projections of the openings 183H1 to 184H, which overlap and align with the through holes 100Vb. That is, the openings 183H1 to 184H communicate with the through hole 100Vb. The outer contours of the projected shapes of the conductive patterns 181P1 and 182P may overlap and align, and the outer contours of the projected shapes of the conductive patterns 183P1 and 184P may overlap and align. On the other hand, in this embodiment, the conductive patterns 185P, 186P may be solid pillars, but the invention is not limited thereto.

Based on the consideration of conductivity, the material of the conducting structure 190 is generally a metal material Materials or alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials and other conductive materials. The conducting structure 190 may include a circuit layer 190L, conducting portions 190Pa, and 190Pb.

The conducting portion 190Pa may include a conducting post 190P1a (also may be referred to as a first conducting post), a conducting post 190P2a (also may be referred to as a second conducting post), and a connection block 190Sa. Similarly, the conductive portion 190Pb may include a conductive pillar 190P1b (also referred to as a first conductive pillar), a conductive pillar 190P2b (also referred to as a second conductive pillar), and a connection block 190Sb. The conductive pillar 190P1a of the conductive portion 190Pa and the conductive pillar 190P1b of the conductive portion 190Pb are electrically connected to the circuit layer 190L, respectively. The conducting post 190P2a of the conducting part 190Pa and the conducting post 190P2b of the conducting part 190Pb are respectively coupled to the active device T1, wherein the conducting post 190P2a is electrically connected to the source S1 of the active device T1, and the conducting post 190P2b is coupled to the active device T1 Gate G1. The connection block 190Sa and the connection block 190Sb are disposed on the upper surface 100T of the substrate 100. The connection block 190Sa is electrically connected between the conductive pillars 190P1a and 190P2a, and the connection block 190Sb is electrically connected between the conductive pillars 190P1b and 190P2b.

The circuit layer 190L is disposed on the lower surface 100B of the substrate 100 and may include signal lines 190L1, 190L2a~190L5a, 190L2b~190L5b. The circuit layer 190L is coupled between the plurality of conductive pillars (such as the conductive pillars 190P1a and 190P1b) and the driving circuit IC. However, the number of components of the present invention is not limited to this, but can be adjusted appropriately according to different design considerations, that is to say, the conductive structure 190 can include multiple conductive portions, and the circuit layer 190L can include multiple signal lines.

As can be seen from the above, the active device on the upper surface 100T of the substrate 100 The source S1 of T1 may be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through the conductive portion 190Pa, and coupled to the driving circuit IC on the lower surface 100B of the substrate 100 through the circuit layer 190L. The gate G1 of the active device T1 located on the upper surface 100T of the substrate 100 can be coupled to the circuit layer 190L located on the lower surface 100B of the substrate 100 through the conducting portion 190Pb, and coupled to the lower surface of the substrate 100 through the circuit layer 190L Driver IC on 100B. In this way, the space on the upper surface 100T and the lower surface 100B of the substrate 100 can be fully utilized for wiring, and the size of the display panel 10 can be reduced, thereby achieving miniaturization. Moreover, the signal lines in the circuit layer 190L (for example, the signal lines 190L1, 190L2a to 190L5a, 190L2b to 190L5b) are provided on the lower surface 100B of the substrate 100, which can reduce the area of the wiring area on the upper surface 100T of the substrate 100 (that is, the non-light emitting area) ). In this case, the display panel 10 can realize a narrow frame design or a seamless splicing design.

The materials of the conductive material structures 181S~185S can be different from the materials of the conductive structure 190, but the invention is not limited thereto. The materials of the conductive material structures 181S~185S can be the same as the materials of the conductive structure 190, but they can be formed at different points in time . In this embodiment, the conductive pillar 190P1a is fitted with the through hole 100Va to penetrate the substrate 100, and the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively cover the sidewalls of the conductive pillar 190P1a of the conductive portion 190Pa , And is conducive to the formation of conductive pillars 190P1a. Similarly, the conductive post 190P1b is fitted with the through hole 100Va to penetrate the substrate 100, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive pattern 184P of the conductive material structure 184S respectively cover the sidewalls of the conductive post 190P1b of the conductive portion 190Pb, which is beneficial to The formation of the conductive post 190P1b. Conductive pattern 181P2 covers the side wall of the conductive pillar 190P2a of the conductive portion 190Pa to facilitate the formation of the conductive pillar 190P2a, and the conductive pattern 183P2 covers the side wall of the conductive pillar 190P2b of the conductive portion 190Pb to facilitate the formation of the conductive pillar 190P2b.

The projection shapes of the conductive pillars 190P1a and 190P2a of the conductive portion 190Pa, the connection block 190Sa and the conductive pillars 190P1b, 190P2b of the conductive portion 190Pb, and the connection block 190Sb along the direction Z on the substrate 100 can be adaptively adjusted according to different design considerations. In this embodiment, the conductive pillars 190P1a and 190P2a of the conductive portion 190Pa and the conductive pillars 190P1b and 190P2b of the conductive portion 190Pb are solid pillars, but the invention is not limited thereto. Based on the coating characteristics, in some embodiments, the outer contour of the projection of the conducting portion 190Pa on the substrate 100 in the direction Z (also referred to as the first projection) and the projection of the conductive material structure 181S on the substrate 100 in the direction Z (also (It can be called the second projection) The outer contours overlap, more specifically overlap and align. In this case, the shape, area, size and/or position of the first projection and the second projection are the same, but the invention is not limited to this. In this embodiment, the outer contour of the conductive material structure 181S projected on the substrate 100 in the direction Z is the outer contour of the connection pattern 181C of the conductive material structure 181S projected on the substrate 100 in the direction Z, and the conducting portion 190Pa is along the direction Z The outer contour projected on the substrate 100 is the outer contour projected on the substrate 100 along the direction Z by the connection block 190Sa of the conducting portion 190Pa. As shown in FIG. 1A, the outer contour of the projection of the connection block 190Sa of the conducting portion 190Pa on the substrate 100 in the direction Z overlaps and aligns with the outer contour of the projection of the connection pattern 181C of the conductive material structure 181S on the substrate 100 in the direction Z . Similarly, the outer contour of the projection of the conducting portion 190Pb on the substrate 100 in the direction Z overlaps with the outer contour of the projection of the conductive material structure 183S on the substrate 100 in the direction Z and Align.

The substrate 199 is suitable for carrying other elements, which may be a chip on film (COF) substrate, but the invention is not limited thereto. The driving circuit IC can be used to provide a driving signal to an active device (such as the active device T1), which is located on the lower surface 100B of the substrate 100 and is disposed on the substrate 199. The active element T1 can be electrically connected to the pixel electrode PE1 to transmit the pixel voltage to the pixel electrode PE1. Based on conductivity considerations, the material of the pixel electrode PE1 may include a metal material or alloy, or the material of the pixel electrode PE1 may include a transparent metal oxide conductive material, such as, but not limited to, indium tin oxide. The pixel electrode PE1 may include electrode patterns PE1a and PE1b. The electrode pattern PE1b of the pixel electrode PE1 is disposed between the connection pattern 186C of the conductive material structure 186S and the flat layer 140. The connection pattern 186C of the conductive material structure 186S may be electrically connected to the light-emitting unit L1, and the electrode pattern PE1a of the pixel electrode PE1 covers the sidewall of the conductive pattern 186P of the conductive material structure 186S. The light-emitting unit L1 may be a light-emitting diode (LED), but the invention is not limited thereto.

In order to explain the technical content of the display panel 10 of this embodiment in detail, the manufacturing method of the display panel 10 will be described below with reference to FIGS. 2A to 2D. 2A to 2D are schematic cross-sectional views of a manufacturing process of a partial area of the display panel 10 shown in FIG. 1A.

Referring to FIG. 2A, the substrate 100 is first provided. In some embodiments, the substrate 100 may be disposed on a carrier substrate (not shown). Next, the buffer layers 110 a and 110 b are formed on the substrate 100 in a comprehensive manner. Next, a semiconductor layer SE1 is formed on the buffer layers 110a and 110b, wherein the method for forming the semiconductor layer SE1 may be included in the buffer layer After a material layer (not shown) is formed comprehensively on 110b, one or more patterning steps are performed. The patterning step may include forming a photoresist material layer (not shown) on the material layer, and then using one or more photomasks (not shown) to expose and develop the photoresist material layer to pattern the photoresist material layer And using the patterned photoresist layer (not shown) as a mask to etch the material layer to complete the patterning of the material layer, and then remove the patterned photoresist layer.

Next, gate insulating layers 120a and 120b are formed on the semiconductor layer SE1, the buffer layers 110a and 110b in a comprehensive manner. Next, a gate G1 is formed on the gate insulating layers 120a and 120b. The formation method of the gate electrode G1 may include a physical vapor deposition (PVD) method or a chemical vapor deposition method, and a layer of material (not shown) is formed on the gate insulating layer 120b in a comprehensive manner, One or more patterning steps. Then, using the gate G1 as a mask, an ion doping process is performed on the semiconductor layer SE1 to form the source regions SP1a, SP1b, the drain regions DP1a, DP1b, and the channel region CH1.

Then, an interlayer dielectric layer 130 is formed on the gate G1 in a comprehensive manner. Then patterning the buffer layers 110a, 110b, the gate insulating layers 120a, 120b, and the interlayer dielectric layer 130, for example, performing one or more patterning steps for the buffer layers 110a, 110b, the gate insulating layers 120a, 120b, the interlayer dielectric The layer 130 forms contact holes H1~H3. The contact holes H1 to H3 respectively expose at least part of the substrate 100 and the semiconductor layer SE1.

Next, a conductive material structure 182S, a source S1 and a drain D1 are formed on the interlayer dielectric layer 130. In this way, active devices (such as active device T1) can be formed on the upper surface 100T of a substrate 100. Among them, the materials forming the conductive material structure 182S, the source electrode S1 and the drain electrode D1 are filled into the contact holes H1~H3 to make the conductive material structure 182S, source S1 and drain D1 contact substrate 100 and semiconductor layer SE1, respectively. In some embodiments, the conductive material structure 182S, the source S1 and the drain D1 can be formed together in the same process, and the method of forming the conductive material structure 182S, the source S1 and the drain D1 includes interlayer dielectric After a material layer (not shown) is completely formed on the layer 130, one or more patterning steps are performed. In other embodiments, the conductive material structure 182S, the source S1 and the drain D1 can also be formed separately in different processes. In some embodiments, the conductive material structures 184S and 185S in FIG. 1B can also be formed together with the conductive material structure 182S, the source electrode S1 and the drain electrode D1 in the same process.

2B, a flat layer 140 is formed on the interlayer dielectric layer 130, the conductive material structure 182S, the source electrode S1, and the drain electrode D1. Next, the flat layer 140 is patterned, for example, one or more patterning steps are performed to form contact holes H4~H6 in the flat layer 140. The contact holes H4 to H6 respectively expose at least part of the conductive material structure 182S, the source electrode S1 and the drain electrode D1. In some embodiments, the projection of the contact hole H4 on the substrate 100 in the direction Z may overlap and align with the projection of the contact hole H1 on the substrate 100 in the direction Z. In this case, the shapes of the contact hole H4 and the contact hole H1 , Area, size and/or location are the same, but the invention is not limited thereto.

Next, a conductive material structure 181S and a pixel electrode PE1 are formed on the flat layer 140. The materials forming the conductive material structure 181S and the pixel electrode PE1 are filled into the contact holes H4 to H6, so that the conductive material structure 181S and the pixel electrode PE1 contact the conductive material structure 182S, the source electrode S1, and the drain electrode D1, respectively. In some embodiments, the conductive material structure 181S and the pixel electrode PE1 may be formed together in the same procedure, also That is, when the conductive pattern 181P1 of the conductive material structure 181S is formed, the pixel electrode PE1 is also formed on the upper surface 100T of the substrate 100. The method for forming the conductive material structure 181S and the pixel electrode PE1 may include physical vapor deposition or chemical vapor deposition, and after forming a material layer (not shown) on the flat layer 140 in a comprehensive manner, One or more patterning steps. In other embodiments, the conductive material structure 181S and the pixel electrode PE1 can also be formed separately in different procedures. In some embodiments, the conductive material structure 183S in FIG. 1B can also be formed together with the conductive material structure 181S and the pixel electrode PE1 in the same process.

Referring to FIG. 2C, a through hole 100Va penetrating the substrate 100 is formed on the substrate 100. In some embodiments, the through hole 100Vb in FIG. 1B may be formed together with the through hole 100Va in the same procedure. The formation method of the through hole 100Va may include laser or etching (such as dry etching). The projected area of the through hole 100Va on the substrate 100 in the direction Z is smaller than the projected area of the contact holes H1 and H4 on the substrate 100 in the direction Z. In some embodiments, the carrier substrate is then removed from the substrate 100, that is, a release process is performed. After the through-hole 100Va penetrating the substrate 100 is formed in the substrate 100, the surface treatment film 102 is formed. In some embodiments, the surface treatment coating 102 can be formed using a surface metallization process. In some embodiments, the ring opening of the surface of the substrate 100 may be performed by physical treatment (such as plasma treatment) or chemical treatment (such as strong alkali treatment), that is, opening the heterocycle or opening of the substrate 100 For the weaker bond, metal ion exchange is performed on the surface of the substrate 100, and then the metal is reduced to the surface of the substrate 100 to form the surface treatment film 102. The surface treatment film 102 covers the through holes 100Va, 100Vb of the substrate 100 and the lower surface 100B of the substrate 100, It can be used as a seed layer to facilitate the formation of the conductive structure 190, or can strengthen the combination of the substrate 100 and the conductive pillars 190P1a, 190P1b.

Referring to FIG. 2D, a conductive structure 190 and a conductive material structure 186S are formed. The forming method of the conductive structure 190 and the conductive material structure 186S may include a physical vapor deposition method or a chemical vapor deposition method, and after forming a material layer (not shown), one or more patterning steps are performed. In this way, the circuit layer 190L of the conductive structure 190 can be patterned into the signal lines 190L1, 190L2a~190L5a, 190L2b~190L5b shown in FIG. 1B, and the conductive portion 190Pa of the conductive structure 190 can pattern the connection block 190Sa. In some embodiments, the conductive structure 190 and the conductive material structure 186S may be formed together in the same process. In other embodiments, the conductive structure 190 and the conductive material structure 186S can also be formed separately in different procedures. The material forming the conductive material structure 186S fills the contact hole H6, and the conductive pattern 186P of the conductive material structure 186S contacts the drain D1.

In addition, the circuit layer 190L and the conductive part (such as the conductive part 190Pa and the conductive part 190Pb shown in FIG. 1B) of the conductive structure 190 can be integrally formed, that is, the circuit layer 190L and the conductive part are formed in the same process. The material forming the conductive structure 190 fills the through hole 100Va, the opening 181H1 of the conductive pattern 181P1, and the opening 182H of the conductive pattern 182P, so that the conductive post 190P1a of the conductive portion 190Pa of the conductive structure 190 is fitted with the through hole 100Va, the openings 181H1, 182H On the other hand, it penetrates the substrate 100 and the film layer on the upper surface 100T of the substrate 100. The material forming the conductive structure 190 fills the opening 181H2 of the conductive pattern 181P2 so that the conductive pillar 190P2a of the conductive portion 190Pa of the conductive structure 190 contacts the source electrode S1. Conductive material structure 181S, 182S can be used as A seed layer, which facilitates the formation of the conductive pillars 190P1a, 190P2a, or can improve the uniformity of the formation of the conductive pillars 190P1a, 190P2a, or can strengthen the conductive pillars 190P1a, 190P2a and the buffer layers 110a, 110b, and the gate insulating layer 120a , 120b, the combination of the interlayer dielectric layer 130 and/or the flat layer 140. The source S1 of the active device T1 on the upper surface 100T of the substrate 100 can be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through the conductive portion 190Pa.

Please refer to FIG. 1A and FIG. 2D together. After the conductive structure 190 is formed, the light emitting unit L1 is formed on the conductive material structure 186S. Furthermore, the driving circuit IC and the substrate 199 are provided on the lower surface 100B of the substrate 100 and bonded to the circuit layer 190L of the conductive structure 190. Here, the manufacturing of the display panel 10 can be completed.

In FIGS. 1A and 1B, the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively cover the sidewalls of the conductive pillars 190P1a of the conductive portion 190Pa, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive material The conductive patterns 184P of the structure 184S respectively cover the sidewalls of the conductive pillars 190P1b of the conductive portion 190Pb. However, the invention is not limited to this, and the conductive material structure can be selectively set according to different design considerations. For example, please refer to FIGS. 3A and 3B. FIGS. 3A and 3B are schematic partial cross-sectional views of a display panel 30 according to an embodiment of the present invention. The display panel 30 of this embodiment is similar in structure to the display panel 10 of the embodiment described in FIGS. 1A and 1B, except that the display panel 30 does not include conductive material structures 182S and 184S. In this case, the bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the interlayer dielectric layer 130, and the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the interlayer dielectric layer 130. Top surface. The conductive pattern 181P1 of the conductive material structure 181S and the surface treatment film 102 cover part of the sidewalls of the conductive pillar 190P1a of the conductive portion 190Pa, and the partial sidewalls of the conductive pillar 190P1a do not contact the conductive material. The conductive pattern 183P1 of the conductive material structure 183S and the surface treatment film 102 cover part of the side walls of the conductive pillar 190P1b of the conductive portion 190Pb, and part of the side walls of the conductive pillar 190P1b do not contact the conductive material. In some embodiments, the buffer holes 110a, 110b, the gate insulating layers 120a, 120b, the contact hole H1' formed in the interlayer dielectric layer 130, and the opening 181H1 of the conductive pattern 181P1 communicate with the through hole 100Va, and the contact hole H1', The projections of the opening 181H1 and the through hole 100Va on the substrate 100 in the direction Z are overlapped and aligned. In this case, the shape, area, size, and/or position of the contact hole H1′, the opening 181H1, and the through hole 100Va are the same, but the original The invention is not limited to this.

In addition, please refer to FIGS. 4A and 4B, which are partial cross-sectional schematic views of the display panel 40 according to an embodiment of the present invention. The display panel 40 of this embodiment is similar in structure to the display panel 30 of the embodiment described in FIGS. 3A and 3B, except that the display panel 40 does not include conductive material structures 182S and 184S. The bottom surface of the conductive pattern 181P1' of the material structure 181S' contacts the upper surface 100T of the substrate 100, and the bottom surface of the conductive pattern 183P1' of the conductive material structure 183S' contacts the upper surface 100T of the substrate 100. The conductive pattern 181P1' of the conductive material structure 181S' and the surface treatment film 102 completely cover the sidewall of the conductive post 190P1a of the conductive portion 190Pa, and the conductive pattern 183P1' of the conductive material structure 183S' and the surface treatment film 102 completely cover the conduction The side wall of the conductive post 190P1b of the portion 190Pb. In addition, the opening 181H1' of the conductive pattern 181P1' communicates with the through hole 100Va, the opening 183H1' of the conductive pattern 183P1' communicates with the through hole 100Vb.

The through holes in the substrate 100 (such as the through holes 100Va and 100Vb) can be provided in the substrate 100 according to different design considerations. For example, please refer to FIG. 5, which is a schematic plan view of a display panel 50 according to an embodiment of the present invention. As shown in FIG. 5, the display panel 50 may include substrates 500, 599a, 599b and signal lines 590L1a~590L22a, 590L1b~590L18b of the conductive structure. The display panel 50 of FIG. 5 can be applied to the display panels 10-40 of FIGS. 1A-4B as an embodiment of the display panels 10-40 of FIGS. 1A-4B. Therefore, the substrate 500 can correspond to the substrate 100, the substrates 599a and 599b can respectively correspond to the substrate 199, and the signal lines 590L1a to 590L22a and 590L1b to 590L18b can respectively correspond to the signal lines 190L1 to 190L5b. In addition, for ease of description, the display panel 50 of FIG. 5 mainly illustrates one side of the lower surface of the substrate 500, and the elements on the upper surface of the substrate 500 are omitted in FIG.

As shown in FIG. 5, the substrate 500 may have through holes 500V1a to 500V22a and 500V1b to 500V18b penetrating the substrate 500. In FIG. 5, the through holes 500V1a to 500V22a and 500V1b to 500V18b are arranged along a rectangular path, but the invention is not limited to this. The arrangement of the through holes can be adjusted according to different design considerations, for example, along other shapes The paths are arranged either in an array or irregularly. In addition, the substrate 500 may have a display area and a non-display area. In some embodiments, the through holes 500V1a to 500V22a and 500V1b to 500V18b may be distributed in the display area. In other embodiments, the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area, and the two rectangular paths corresponding to the through holes 500V1a to 500V22a, 500V1b to 500V18b each surround the two displays of the substrate 500. 示区。 Show area. In other embodiments, a part of the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area, and another part of the through holes 500V1a to 500V22a, 500V1b to 500V18b may be distributed in the non-display area.

As shown in FIG. 5, one end of each signal line 590L1a to 590L22a, 590L1b to 590L18b of the conducting structure of the display panel 50 is respectively connected to the through holes 500V1a to 500V22a, 500V1b to 500V18b, and each signal line 590L1a to 590L22a, 590L1b to 590L18b The other ends are connected to the junction areas BDa and BDb, respectively. In some embodiments, the substrate 100 is bonded to the substrates 599a and 599b through the bonding areas BDa and BDb. In some embodiments, the circuit of the substrate 100 is coupled to the substrates 599a and 599b through the bonding areas BDa and BDb respectively Drive circuit.

In addition, please refer to FIG. 6, which is a schematic partial cross-sectional view of a display panel 60 according to an embodiment of the present invention. The display panel 60 of this embodiment has a similar structure to the display panel 10 of the embodiment described in FIGS. 1A and 1B except for the buffer layers 110a and 110b, the gate insulating layers 120a and 120b, and the interlayer dielectric layer 130. , Flat layer 140, driving circuit IC, active element T1, light emitting unit L1 and pixel electrode PE1, the display panel 60 further includes substrates 600, 699, buffer layers 610a, 610b, gate insulating layers 620a, 620b, an interlayer dielectric layer 630, an insulating layer 640, a circuit layer 650, a conductive material structure 681S, 682S, 683S, 684S, 685S, 686S, a conducting part 690Pa, 690Pb, 690Pc, an active element T2, a light emitting unit L2 and a pixel electrode PE2 .

The active device T2 may include a semiconductor layer SE2, a source S2, a drain D2, and a gate G2. The semiconductor layer SE2 may include source regions SP2a, SP2b, drain regions DP2a, DP2b and channel area CH2. The conductive material structures 681S, 682S, 684S-686S are disposed on the upper surface 600T of the substrate 600, and the conductive material structures 683S are disposed on the lower surface 600B of the substrate 600. The conductive patterns 681P~684P of the conductive material structures 681S~684S are respectively connected to the connection patterns 681C~684C of the conductive material structures 681S~684S; similarly, the conductive patterns (not shown) of the conductive material structures 685S and 686S are respectively connected to the conductive materials The connection patterns 685C and 686C of the structure 685S and 686S. The connection blocks 690Sa and 690Sb of the conduction parts 690Pa and 690Pb are respectively connected to the conduction columns 690P1a and 690P1b of the conduction parts 690Pa and 690Pb, and the connection blocks 690Sc of the conduction part 690Pc are respectively connected to the conduction columns of the conduction part 690Pc (not shown).

The conductive post 690P1a of the conductive portion 690Pa is fitted into the through hole 600V to penetrate the substrate 600, and the conductive pattern 681P1 of the conductive material structure 681S, the conductive pattern 682P of the conductive material structure 682S, and the conductive pattern 683P of the conductive material structure 683S respectively cover the conductive portion The side wall of the conductive post 690P1a of 690Pa facilitates the formation of the conductive post 690P1a. The conductive pattern 684P of the conductive material structure 684S covers the sidewalls of the conductive pillar 690P1b of the conductive portion 690Pb to facilitate the formation of the conductive pillar 690P1b. The conductive pattern of the conductive material structure 685S (not shown) covers the conductive pillar of the conductive portion 690Pc (not shown) The side wall shown) is conducive to the formation of conductive pillars.

The light-emitting unit L2 on the upper surface 600T of the substrate 600 can be coupled to the source S2 of the active device T2 on the lower surface 600B of the substrate 600 through the conducting portion 690Pa. In this way, the space on the upper surface 600T and the lower surface 600B of the substrate 600 can be fully utilized for wiring, and the size of the display panel 60 can be reduced to achieve miniaturization.

In summary, the display panel of the present invention has a through hole penetrating through the substrate. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the lower surface of the substrate through the conductive structure or the conductive portion embedded in the through hole. In this way, the miniaturization of the size can be achieved, or the area of the wiring area (ie, the non-light emitting area) on the substrate can be reduced, and a narrow frame design or a seamless splicing design can be realized. In addition, the display panel of the present invention uses the conductive pattern of the conductive material structure or the surface treatment coating of the substrate as the seed layer, which covers the conductive structure or the conductive part, which is beneficial to the formation of the conductive structure or the conductive part.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10: Display panel

100, 199: substrate

100B: Lower surface

100T: upper surface

100Va: through hole

102: Surface treatment coating

110a, 110b: buffer layer

120a, 120b: gate insulating layer

130: Interlayer dielectric layer

140: flat layer

181C, 182C, 186C: connection pattern

181H1, 181H2, 182H: opening

181P1, 181P2, 182P, 186P: conductive pattern

181S, 182S, 186S: conductive material structure

190: conduction structure

190L: line layer

190L1: Signal cable

190P1a, 190P2a: conduction column

190Pa: conduction part

190Sa: connection block

CH1: Channel area

D1: Drain

DP1a, DP1b: Drain area

G1: Gate

IC: drive circuit

L1: light emitting unit

LL: characteristic length

PE1: pixel electrode

PE1a, PE1b: electrode pattern

S1: source

SE1: Semiconductor layer

SP1a, SP1b: source region

T1: Active component

XX: intersection line

X, Y, Z: direction

Claims (9)

A display panel includes: a substrate having a plurality of through holes penetrating the substrate; a plurality of active elements arranged in an array and arranged on an upper surface of the substrate; a conducting structure including: a circuit layer, which is arranged on On the lower surface of the substrate; a plurality of first conductive pillars, the first conductive pillars are respectively fitted with the through holes to penetrate the substrate, the first conductive pillars are respectively coupled to the circuit layer and the active devices Between; and a plurality of conducting parts, each of the conducting parts includes a first conducting post, a second conducting post and a connecting block among the first conducting posts, each of the first conducting posts is electrically connected to the In the circuit layer, the second conductive pillars are electrically connected to the active devices, respectively, and the connecting blocks are electrically connected between the first conductive pillars and the second conductive pillars; A conductive pattern is disposed on the upper surface of the substrate, and the first conductive patterns respectively cover the sidewalls of the first conductive pillars. The display panel as described in item 1 of the patent application scope further includes a driving circuit located on the lower surface of the substrate, and the circuit layer is electrically connected between the first conducting posts and the driving circuit. The display panel as described in item 1 of the patent application scope further includes a plurality of first conductive material structures disposed on the upper surface of the substrate, and each of the first conductive material structures includes one of the first conductive patterns First conductive pattern, a second conductive A pattern and a connection pattern, the second conductive patterns respectively cover the second conductive posts, and the connection patterns are electrically connected between the first conductive patterns and the second conductive patterns, respectively. The display panel according to item 3 of the patent application scope, wherein the outer contour of each first projection of the conducting portion on the substrate and the outer contour of a second projection of each first conductive material structure on the substrate overlapping. The display panel as described in Item 1 of the patent application scope further includes a plurality of second conductive material structures, each of the second conductive material structures includes a third conductive pattern, and the third conductive patterns respectively cover the first Conducting column. The display panel according to item 5 of the patent application scope, wherein a bottom surface of each of the first conductive patterns contacts the top surface of the substrate or a top surface of the second conductive material structure. A display panel manufacturing method includes: forming a plurality of active elements on an upper surface of a substrate, the active elements are arranged in an array; forming a plurality of first conductive patterns on the upper surface of the substrate; and forming a through A plurality of through holes of the substrate; and forming a conductive structure, the conductive structure includes a circuit layer, a plurality of first conductive pillars and a plurality of conductive parts, the circuit layer is disposed on the lower surface of the substrate, the first conductive The pillars are respectively fitted with the through holes to penetrate the substrate, and the first conductive pillars are respectively coupled between the circuit layer and the active devices, wherein each conductive portion includes a first of the first conductive pillars Conducting column, first Two conductive pillars and a connection block, each of the first conductive pillars is electrically connected to the circuit layer, the second conductive pillars are electrically connected to the active devices, respectively, and the connection blocks are electrically connected to the Between the first conductive pillars and the second conductive pillars, wherein the first conductive patterns respectively cover the sidewalls of the first conductive pillars. The method for manufacturing a display panel as described in item 7 of the patent application scope, wherein when forming the first conductive patterns, a plurality of pixel electrodes are formed on the upper surface of the substrate, and the pixel electrodes are electrically To connect these active components. The method for manufacturing a display panel according to item 7 of the patent application scope, wherein after forming the through holes penetrating the substrate, a surface treatment film is formed, the surface treatment film covering the through holes of the substrate and The lower surface of the substrate.

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