CN111081140A

CN111081140A - Display panel and manufacturing method thereof

Info

Publication number: CN111081140A
Application number: CN202010013538.1A
Authority: CN
Inventors: 刘展睿; 梁育馨; 王脩华; 黄巧俐; 郑君丞
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-05-21
Filing date: 2020-01-07
Publication date: 2020-04-28
Anticipated expiration: 2040-01-07
Also published as: TW202043867A; CN111081140B; TWI696868B

Abstract

A display panel and a manufacturing method thereof are provided. The display panel comprises a substrate, a plurality of active elements, a conducting structure and a plurality of first conducting patterns. The substrate is provided with a plurality of through holes penetrating through the substrate. The active elements are arranged in an array and arranged on an upper surface of the substrate. The conducting structure comprises a circuit layer and a plurality of first conducting columns, wherein the circuit layer is arranged on a lower surface of the substrate. The first conductive columns are respectively embedded with the through holes and penetrate through the substrate, and the first conductive columns are respectively coupled between the circuit layer and the active element. The first conductive patterns are arranged on the upper surface of the substrate and respectively wrap the side walls of the first conductive columns.

Description

Display panel and manufacturing method thereof

Technical Field

The present disclosure relates to electronic devices and methods for fabricating the same, and particularly to a display panel and a method for fabricating the same.

Background

Generally, a display panel may have a display area and a non-display area around the display area. The non-display area may include a wiring area for routing wires and a driving circuit area for driving circuits, such as a source driving circuit or a gate driving circuit, for driving active devices in the display panel, so that the non-display area of the display panel cannot display images, which affects the design of the display panel.

Specifically, when the area of the non-display area is reduced, the display area occupies a larger area of the display panel, and correspondingly more pixels are disposed, so that the resolution of the display panel can be improved. When the area of the non-display area is reduced, the boundary of the display area is closer to the outer edge of the display panel, so that the narrow frame design can be realized. For a large display panel formed by splicing, a non-display area forms a splicing gap which cannot display an image, so that the discontinuity of the whole image is caused, and the display quality is influenced. Therefore, the existing display panel still needs to be improved.

Disclosure of Invention

In an embodiment of the present invention, a display panel is provided, which is configured to reduce the size of the display panel or reduce the area of a wiring region on a substrate.

An embodiment of the invention provides a display panel, which includes a substrate, a plurality of active devices, a conductive structure, and a plurality of first conductive patterns. The substrate is provided with a plurality of through holes penetrating through the substrate. The active elements are arranged in an array and are arranged on an upper surface of the substrate. The conducting structure comprises a circuit layer and a plurality of first conducting columns, wherein the circuit layer is arranged on a lower surface of the substrate. The first conducting columns are respectively embedded with the through holes and penetrate through the substrate, and the first conducting columns are respectively coupled between the circuit layer and the active elements. The first conductive patterns are arranged on the upper surface of the substrate and respectively coat the side walls of the first conductive columns.

An embodiment of the present invention provides a method for manufacturing a display panel, including forming a plurality of active devices on an upper surface of a substrate, forming a plurality of first conductive patterns on the upper surface of the substrate, forming a plurality of through holes penetrating through the substrate, and forming a conductive structure. The active elements are arranged in an array. The conducting structure comprises a circuit layer and a plurality of first conducting columns. The circuit layer is arranged on a lower surface of the substrate. The first conduction columns are respectively embedded with the through holes and penetrate through the substrate. The first conductive vias are respectively coupled between the circuit layer and the active devices. The first conductive patterns respectively cover the side walls of the first conductive vias.

In the display panel according to the embodiment of the invention, the through hole penetrates through the substrate, so that the element on the upper surface of the substrate can be coupled to the element on the lower surface of the substrate through the conduction structure embedded in the through hole, and thus, the size miniaturization can be realized, or the area of the wiring area on the substrate can be reduced, and the narrow frame design or the seamless splicing design can be realized. In addition, the display panel of the invention takes the conductive pattern of the conductive material structure or the surface treatment coating film of the substrate as a seed crystal layer which coats the conduction structure, thereby being beneficial to the formation of the conduction structure.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A and 1B are schematic cross-sectional views of a display panel according to an embodiment of the invention.

Fig. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a local area of the display panel shown in fig. 1A.

Fig. 3A and 3B are schematic cross-sectional views of a display panel according to an embodiment of the invention.

Fig. 4A and 4B are schematic cross-sectional views of a display panel according to an embodiment of the invention.

Fig. 5 is a schematic plan view of a display panel according to an embodiment of the invention.

Fig. 6 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Description of reference numerals:

10. 30, 40, 50, 60: display panel

100. 199, 600, 699, 500, 599a, 599 b: substrate

100B, 600B: lower surface

100T, 600T: upper surface of

100Va, 100Vb, 500V1 a-500V 22a, 500V1 b-500V 18b, 600V: through hole

102: surface treatment film

110a, 110b, 610a, 610 b: buffer layer

120a, 120b, 620a, 620 b: gate insulating layer

130. 630: interlayer dielectric layer

140: planarization layer

181C, 182C, 183C, 184C, 185C, 186C, 681C to 686C: connection pattern

181H1, 181H2, 182H, 183H1, 183H2, 184H, 181H1 ', 183H 1': opening of the container

181P1, 181P2, 182P, 183P1, 183P2, 184P, 185P, 186P, 181P1 ', 183P 1', 681P to 684P: conductive pattern

181S, 182S, 183S, 184S, 185S, 186S, 181S ', 183S', 681S, 682S, 683S, 684S, 685S, 686S: conductive material structure

190: conduction structure

190L, 650: line layer

190L1, 190L2 a-190L 5a, 190L2 b-190L 5b, 590L1 a-590L 22a, 590L1 b-590L 18 b: signal line

190P1a, 190P2a, 190P1b, 190P2b, 690P1a, 690P1 b: conduction column

190Pa, 190Pb, 690Pa, 690Pb, 690 Pc: conduction part

190Sa, 190Sb, 690Sa, 690Sb, 690 Sc: connection area

640: insulating layer

BDa, BDb: bonding region

CH1, CH 2: channel region

D1, D2: drain electrode

DP1a, DP1b, DP2a, DP2 b: drain region

G1, G2: grid electrode

H1-H3, H4-H6, H1': contact hole

IC: driving circuit

L1, L2: light emitting unit

LL: characteristic length

PE1, PE 2: pixel electrode

PE1a, PE1b, PE2 c: electrode pattern

S1, S2: source electrode

SE1, SE 2: semiconductor layer

SP1a, SP1b, SP2a, SP2 b: source region

T1, T2: active component

XX: intersection line

X, Y, Z: direction of rotation

Detailed Description

Directional phrases used in connection with embodiments, such as: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In the drawings, which illustrate general features of methods, structures, and/or materials used in certain exemplary embodiments. These drawings, however, should not be construed as limiting or restricting the scope or nature covered by these exemplary embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

In the embodiments, the same or similar elements will be denoted by the same or similar reference numerals, and the detailed description thereof will be omitted. Furthermore, the features of the different exemplary embodiments may be combined with each other without conflict and simple equivalent changes and modifications made in the present specification or claims may still fall within the scope of the present patent. In addition, the terms "first", "second", and the like in the description or the claims are only used for naming discrete (discrete) elements or distinguishing different embodiments or ranges, and are not used for limiting the upper limit or the lower limit of the number of elements, nor for limiting the manufacturing order or the arrangement order of the elements.

Fig. 1A and 1B are schematic cross-sectional views of a part of a display panel 10 according to an embodiment of the invention, wherein the cross-sections of fig. 1A and 1B intersect at an intersection line XX. Referring to fig. 1A and 1B, the display panel 10 may include

substrates

100 and 199, buffer layers 110a and 110B, Gate Insulators (GI) 120a and 120B, an inter-layer dielectric (ILD) 130, a Planarization Layer (PL) 140,

conductive material structures

181S, 182S, 183S, 184S, 185S, 186S, a conductive structure 190, a driving circuit IC, an active device T1, a light emitting unit L1, and a pixel electrode PE 1. However, the number of the elements of the present invention is not limited thereto, and may be adjusted according to different design considerations, that is, the display panel 10 may include one or more substrates, a buffer layer, a gate insulating layer, an interlayer dielectric layer, a planarization layer, a conductive material structure, a conductive structure, a driving circuit, an active device, a light emitting unit, and a pixel electrode.

The substrate 100 is suitable for carrying other components, and may have an upper surface 100T and a lower surface 100B opposite to each other, and a normal direction of the upper surface 100T and the lower surface 100B may be parallel to the direction Z. The substrate 100 may have a plurality of through holes (e.g., through holes 100Va, 100Vb) penetrating the substrate 100. The substrate 100 includes a surface treatment coating 102. The surface treatment coating film 102 covers the through holes 100Va and 100Vb of the substrate 100 and the lower surface 100B of the substrate 100. In this embodiment, the substrate 100 may be a flexible substrate, but the invention is not limited thereto, and in other embodiments, the substrate 100 may also be a rigid substrate. The feature length LL of the vias 100Va, 100Vb is between 5 micrometers (μm) and 50 μm.

The buffer layers 110a and 110b are disposed on the substrate 100 and may be inorganic thin films made of inorganic materials, and the material constituting the

buffer layers

110a and 110b may be generally an insulating material. The

gate insulating layers

120a and 120b are disposed on the

buffer layers

110a and 110b, and the material of the

gate insulating layers

120a and 120b is, for example, silicon oxide, silicon nitride, or other insulating materials. The interlayer dielectric layer 130 is disposed on the

gate insulating layers

120a and 120b, and a material of the interlayer dielectric layer 130 may include an inorganic material, an organic material, or a combination thereof. The planarization layer 140 is disposed on the interlayer dielectric layer 130, and the material of the planarization layer 140 may include various suitable organic materials.

The active devices (e.g., the active device T1) are disposed on the upper surface 100T of the substrate 100 and arranged in an array. In the present embodiment, the active device T1 may be a top gate thin film transistor (top gate TFT), for example. However, the present invention is not limited thereto, and in other embodiments, the thin film transistor may be designed as a bottom gate Thin Film Transistor (TFT) or other suitable thin film transistors. The active device T1 may include a semiconductor layer SE1, a source S1, a drain D1, and a gate G1. The semiconductor layer SE1 is disposed on the

buffer layers

110a and 110b, and the material of the semiconductor layer SE1 is, for example, polysilicon (e.g., Low Temperature Polysilicon (LTPS)), amorphous silicon (amorphous silicon), a metal Oxide semiconductor (e.g., Indium Gallium Zinc Oxide (IGZO)), or other semiconductor materials. The semiconductor layer SE1 may include source regions SP1a, SP1b, drain regions DP1a, DP1b, and a channel region CH 1. Portions of the source S1 and the drain D1 are disposed on the interlayer dielectric layer 130, and other portions of the source S1 and the drain D1 penetrate the

gate insulating layers

120a and 120b and the interlayer dielectric layer 130 and are in contact with the source regions SP1a and SP1b and the semiconductor layer SE1 of the drain regions DP1a and DP1b, respectively.

The conductive material structures 181S to 185S are generally made of a metal material or an alloy thereof, a nitride thereof, an oxide thereof, an oxynitride thereof, or other conductive materials based on conductivity. The conductive material structures 181S-185S are disposed on the upper surface 100T of the substrate 100. The conductive material structure 181S (which may also be referred to as a first conductive material structure) may include a conductive pattern 181P1 (which may also be referred to as a first conductive pattern), a conductive pattern 181P2 (which may also be referred to as a second conductive pattern), and a connection pattern 181C. The conductive material structure 182S (which may also be referred to as a second conductive material structure) may include a conductive pattern 182P (which may also be referred to as a third conductive pattern) and a connection pattern 182C. Similarly, the conductive material structure 183S includes conductive patterns 183P1, 183P2 and a connection pattern 183C. The

conductive material structures

184S, 185S, 186S may include

conductive patterns

184P, 185P, 186P and

connection patterns

184C, 185C, 186C, respectively.

In the present embodiment, the conductive material structure 181S is electrically connected to the conductive material structure 182S, and the conductive material structure 183S is electrically connected to the

conductive material structures

184S and 185S. The conductive patterns 181P 1-186P extend substantially along the direction Z. The bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the conductive material structure 182S, the bottom surface of the conductive pattern 181P2 of the conductive material structure 181S contacts the source S1 of the active device T1, and the connection pattern 181C of the conductive material structure 181S is electrically connected between the conductive pattern 181P1 and the conductive pattern 181P 2. The bottom surface of the conductive pattern 182P of the conductive material structure 182S contacts the upper surface 100T of the substrate 100, and the connection pattern 182C of the conductive material structure 182S is electrically connected to the conductive pattern 182P. Similarly, the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the top surface of the conductive material structure 184S, the bottom surface of the conductive pattern 183P2 of the conductive material structure 183S contacts the top surface of the conductive material structure 185S, and the connection pattern 183C of the conductive material structure 183S is electrically connected between the conductive pattern 183P1 and the conductive pattern 183P 2. The bottom surface of the conductive pattern 184P of the conductive material structure 184S contacts the upper surface 100T of the substrate 100, and the connection pattern 184C of the conductive material structure 184S is electrically connected to the conductive pattern 184P. The bottom surface of the conductive pattern 185P of the conductive material structure 185S contacts the gate G1 of the active device T1, and the connection pattern 185C of the conductive material structure 185S is electrically connected to the conductive pattern 185P. The bottom surface of the conductive pattern 186P of the conductive material structure 186S contacts the drain D1 of the active device T1, and the connection pattern 186C of the conductive material structure 186S is electrically connected to the conductive pattern 186P.

The

connection patterns

181C, 182C, 183C, 184C, 185C, 186C are used to connect the conductive patterns, and the projection shapes of the connection patterns along the direction Z on the substrate 100 can be adjusted according to different design considerations. The conductive patterns 181P1, 181P2, 182P, 183P1, 183P2, 184P have openings 181H1, 181H2, 182H, 183H1, 183H2, 184H, respectively, and have a substantially tubular hollow structure. The projection shapes of the conductive patterns 181P 1-184P along the direction Z on the substrate 100 can be adjusted according to different design considerations. In some embodiments, the inner contour and the outer contour of the projected shape are conformal (conformal), for example, the inner contour and the outer contour of the projected shape are both rectangular. In some embodiments, the inner contour and the outer contour of the projected shape may be concentric circles, but are not limited thereto. In the embodiment, the inner contours of the projected shapes of the conductive patterns 181P1, 182P are the projected contours of the openings 181H 1-182H, which can overlap and align with the through hole 100Va, in this case, the inner contours of the projected shapes of the conductive patterns 181P1, 182P are the same as the shape, area, size and/or position of the through hole 100Va, but the invention is not limited thereto. That is, the openings 181H 1-182H are connected to the through hole 100 Va. Similarly, the inner contour of the projected shape of the conductive patterns 183P1, 184P can be the projected contour of the openings 183H 1-184H, which overlaps and aligns with the through holes 100 Vb. That is, the openings 183H 1-184H are connected to the through holes 100 Vb. The outer contours of the projected shapes of the conductive patterns 181P1, 182P may overlap and align, and the outer contours of the projected shapes of the conductive patterns 183P1, 184P may overlap and align. On the other hand, in the present embodiment, the

conductive patterns

185P, 186P may be solid pillars, but the present invention is not limited thereto.

The material of the conductive structure 190 is generally a metal material or an alloy thereof, a nitride thereof, an oxide thereof, an oxynitride thereof, or other conductive materials based on conductivity. The conductive structure 190 may include a circuit layer 190L and conductive portions 190Pa and 190 Pb.

The conductive portion 190Pa may include a conductive via 190P1a (also referred to as a first conductive via), a conductive via 190P2a (also referred to as a second conductive via), and a connection region 190 Sa. Similarly, the conductive part 190Pb may include a conductive via 190P1b (also referred to as a first conductive via), a conductive via 190P2b (also referred to as a second conductive via), and a connection region 190 Sb. The conductive via 190P1a of the conductive part 190Pa and the conductive via 190P1b of the conductive part 190Pb are electrically connected to the circuit layer 190L, respectively. The conductive via 190P2a of the conductive portion 190Pa and the conductive via 190P2b of the conductive portion 190Pb are respectively coupled to the active device T1, wherein the conductive via 190P2a is electrically connected to the source S1 of the active device T1, and the conductive via 190P2b is coupled to the gate G1 of the active device T1. The connection regions 190Sa and 190Sb are provided on the upper surface 100T of the substrate 100. The connection region 190Sa is electrically connected between the conductive vias 190P1a, 190P2a, and the connection region 190Sb is electrically connected between the conductive vias 190P1b, 190P2 b.

The circuit layer 190L is disposed on the lower surface 100B of the substrate 100 and may include signal lines 190L1, 190L2 a-190L 5a, 190L 2B-190L 5B. The circuit layer 190L is coupled between a plurality of conductive vias (e.g., the conductive vias 190P1a, 190P1b) and the driving circuit IC. However, the number of the devices of the present invention is not limited thereto, and may be adjusted according to different design considerations, that is, the conductive structure 190 may include a plurality of conductive portions, and the circuit layer 190L may include a plurality of signal lines.

As can be seen from the above, the source S1 of the active device T1 on the upper surface 100T of the substrate 100 may be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through the conductive portion 190Pa, and coupled to the driving circuit IC on the lower surface 100B of the substrate 100 through the circuit layer 190L. The gate G1 of the active device T1 on the upper surface 100T of the substrate 100 may be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through a conductive portion 190Pb, and coupled to the driving circuit IC on the lower surface 100B of the substrate 100 through the circuit layer 190L. In this way, the space between the upper surface 100T and the lower surface 100B of the substrate 100 can be sufficiently utilized for wiring, and the size of the display panel 10 can be reduced, thereby achieving size miniaturization. In addition, signal lines (e.g., signal lines 190L1, 190L2a to 190L5a, 190L2B to 190L5B) in the circuit layer 190L are disposed on the lower surface 100B of the substrate 100, so that the area of a wiring region (i.e., a non-light-emitting region) on the upper surface 100T of the substrate 100 can be reduced. In this case, the display panel 10 may implement a narrow bezel design or a seamless tiling design.

The conductive material structures 181S to 185S may be made of a material different from that of the conductive structure 190, but the invention is not limited thereto, and the conductive material structures 181S to 185S may be made of the same material as that of the conductive structure 190 and may be formed at different time points. In the embodiment, the conductive via 190P1a is embedded in the through hole 100Va to penetrate through the substrate 100, and the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively coat the sidewall of the conductive via 190P1a of the conductive part 190Pa, so as to facilitate the formation of the conductive via 190P1 a. Similarly, the conductive via 190P1b is embedded in the through hole 100Va to penetrate through the substrate 100, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive pattern 184P of the conductive material structure 184S respectively coat the sidewall of the conductive via 190P1b of the conductive part 190Pb, thereby facilitating the formation of the conductive via 190P1 b. The conductive pattern 181P2 covers the sidewall of the conductive via 190P2a of the conductive portion 190Pa to facilitate formation of the conductive via 190P2a, and the conductive pattern 183P2 covers the sidewall of the conductive via 190P2b of the conductive portion 190Pb to facilitate formation of the conductive via 190P2 b.

The shapes of the conductive vias 190P1a, 190P2a of the conductive portion 190Pa, the connecting region 190Sa, the conductive vias 190P1b, 190P2b of the conductive portion 190Pb, and the projection of the connecting region 190Sb on the substrate 100 along the direction Z can be adjusted adaptively according to different design considerations. In the present embodiment, the conductive posts 190P1a and 190P2a of the conductive portion 190Pa and the conductive posts 190P1b and 190P2b of the conductive portion 190Pb are all solid posts, but the present invention is not limited thereto. Based on the plating characteristics, in some embodiments, the outer contour of the projection of the conducting portion 190Pa on the substrate 100 along the direction Z (also referred to as a first projection) overlaps, more specifically overlaps and aligns, the outer contour of the projection of the conductive material structure 181S on the substrate 100 along the direction Z (also referred to as a second projection), in which case, the shape, area, size and/or position of the first projection and the second projection are the same, but the invention is not limited thereto. In the embodiment, an outer contour of the conductive material structure 181S projected on the substrate 100 along the direction Z is an outer contour of the connection pattern 181C of the conductive material structure 181S projected on the substrate 100 along the direction Z, and an outer contour of the conducting portion 190Pa projected on the substrate 100 along the direction Z is an outer contour of the connection region 190Sa of the conducting portion 190Pa projected on the substrate 100 along the direction Z. As shown in fig. 1A, the outer contour of the projection of the connection region 190Sa of the via 190Pa on the substrate 100 along the direction Z overlaps and aligns with the outer contour of the projection of the connection pattern 181C of the conductive material structure 181S on the substrate 100 along the direction Z. Similarly, the outer contour of the projection of the conductive part 190Pb on the substrate 100 along the direction Z overlaps and aligns with the outer contour of the projection of the conductive material structure 183S on the substrate 100 along the direction Z.

The substrate 199 is suitable for carrying other devices, and may be a Chip On Film (COF) substrate, but the invention is not limited thereto. The driving circuit IC may be configured to provide driving signals to active devices (such as the active device T1) disposed on the bottom surface 100B of the substrate 100 and disposed on the substrate 199. The active device T1 can be electrically connected to the pixel electrode PE1 to transmit the pixel voltage to the pixel electrode PE 1. For conductivity, the material of the pixel electrode PE1 may include a metal material or an alloy, or the material of the pixel electrode PE1 may include a transparent metal oxide conductive material, such as, but not limited to, indium tin oxide. The pixel electrode PE1 may include electrode patterns PE1a, PE1 b. The electrode pattern PE1b of the pixel electrode PE1 is disposed between the connection pattern 186C of the conductive material structure 186S and the planarization layer 140. The connection pattern 186C of the conductive material structure 186S may be electrically connected to the light emitting unit L1, and the electrode pattern PE1a of the pixel electrode PE1 covers the sidewall of the conductive pattern 186P of the conductive material structure 186S. The Light emitting unit L1 may be a Light-emitting diode (LED), but the invention is not limited thereto.

To explain the technical content of the display panel 10 of the present embodiment in detail, the following describes a manufacturing method of the display panel 10 with reference to fig. 2A to 2D. Fig. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a local area of the display panel 10 shown in fig. 1A.

Referring to fig. 2A, a substrate 100 is provided. In some embodiments, the substrate 100 may be disposed on a carrier substrate (not shown). Then,

buffer layers

110a and 110b are formed globally on the substrate 100. Next, a semiconductor layer SE1 is formed on the

buffer layers

110a and 110b, wherein the method for forming the semiconductor layer SE1 may include performing one or more patterning steps after forming a material layer (not shown) on the buffer layer 110 b. The patterning step may include, after forming a photoresist material layer (not shown) on the material layer, patterning the photoresist material layer by performing an exposure and development process on the photoresist material layer using one or more masks (not shown), performing an etching process on the material layer using the patterned photoresist material layer (not shown) as a mask to complete patterning of the material layer, and removing the patterned photoresist material layer.

Next, the

gate insulating layers

120a and 120b are formed entirely over the semiconductor layer SE1 and the

buffer layers

110a and 110 b. A gate electrode G1 is then formed on the

gate insulating layers

120a, 120 b. The gate electrode G1 may be formed by a Physical Vapor Deposition (PVD) method or a chemical vapor deposition (cvd) method, and one or more patterning steps are performed after a material layer (not shown) is formed on the gate insulating layer 120 b. Then, an ion doping process is performed on the semiconductor layer SE1 by using the gate G1 as a mask to form source regions SP1a, SP1b, drain regions DP1a, DP1b, and a channel region CH 1.

An interlayer dielectric 130 is then formed globally over the gate G1. Then, the

buffer layers

110a and 110b, the

gate insulating layers

120a and 120b, and the interlayer dielectric layer 130 are patterned, for example, by performing one or more patterning steps, so as to form contact holes H1-H3 in the

buffer layers

110a and 110b, the

gate insulating layers

120a and 120b, and the interlayer dielectric layer 130. The contact holes H1-H3 respectively expose at least a portion of the substrate 100 and the semiconductor layer SE 1.

A conductive material structure 182S, a source S1 and a drain D1 are then formed on the ILD 130. As such, active devices (e.g., active device T1) can be formed on the upper surface 100T of the substrate 100. The conductive material structure 182S, the source S1, and the drain D1 are formed by filling the contact holes H1-H3, such that the conductive material structure 182S, the source S1, and the drain D1 respectively contact the substrate 100 and the semiconductor layer SE 1. In some embodiments, the conductive material structure 182S, the source S1, and the drain D1 may be formed together in a single process, and the method of forming the conductive material structure 182S, the source S1, and the drain D1 may include one or more patterning steps performed after a material layer (not shown) is formed over the ild 130. In other embodiments, the conductive material structure 182S, the source S1 and the drain D1 may be formed separately in different processes. In some embodiments, the

conductive material structures

184S and 185S of fig. 1B may also be formed together with the conductive material structure 182S, the source S1 and the drain D1 in the same process.

Referring to fig. 2B, a planarization layer 140 is globally formed on the ild layer 130, the conductive material structure 182S, the source S1 and the drain D1. The planarization layer 140 is then patterned, for example, by performing one or more patterning steps, to form contact holes H4-H6 in the planarization layer 140. The contact holes H4-H6 respectively expose at least a portion of the conductive material structure 182S, the source S1 and the drain D1. In some embodiments, the projection of contact hole H4 on substrate 100 along direction Z may overlap and align with the projection of contact hole H1 on substrate 100 along direction Z, in which case contact hole H4 and contact hole H1 are the same in shape, area, size and/or location, but the invention is not limited thereto.

Next, a conductive material structure 181S and a pixel electrode PE1 are formed on the planarization layer 140. The conductive material structure 181S and the pixel electrode PE1 are filled with the material forming the contact holes H4-H6, such that the conductive material structure 181S and the pixel electrode PE1 respectively contact the conductive material structure 182S, the source S1 and the drain D1. In some embodiments, the conductive material structure 181S and the pixel electrode PE1 may be formed together in the same process, that is, the pixel electrode PE1 is formed on the upper surface 100T of the substrate 100 when the conductive pattern 181P1 of the conductive material structure 181S is formed. The conductive material structure 181S and the pixel electrode PE1 may be formed by a physical vapor deposition method or a chemical vapor deposition method, and one or more patterning steps are performed after a material layer (not shown) is formed on the planarization layer 140. In other embodiments, the conductive material structure 181S and the pixel electrode PE1 may be formed separately in different processes. In some embodiments, the conductive material structure 183S in FIG. 1B can also be formed together with the conductive material structure 181S and the pixel electrode PE1 in the same process.

Referring to fig. 2C, a through hole 100Va penetrating the substrate 100 is formed on the substrate 100. In some embodiments, the via 100Vb in FIG. 1B can also be formed together with the via 100Va in the same process. The formation method of the via 100Va may include laser or etching (e.g., dry etching). The projected area of the through hole 100Va on the substrate 100 along the direction Z is smaller than the projected areas of the contact holes H1, H4 on the substrate 100 along the direction Z. In some embodiments, the carrier substrate is then removed from the substrate 100, i.e., a release process is performed. After a through hole 100Va penetrating the substrate 100 is formed in the substrate 100, a surface treatment coating film 102 is formed. In some embodiments, the surface treatment coating 102 may be formed using a surface metallization process. In some embodiments, the surface treatment coating 102 may be formed by opening the heterocyclic ring or the weaker bond of the substrate 100 through a physical treatment (e.g., plasma treatment) or a chemical treatment (e.g., alkali treatment) on the surface of the substrate 100, then performing metal ion exchange on the surface of the substrate 100, and then reducing the metal to the surface of the substrate 100. The surface treatment coating film 102 covers the through holes 100Va and 100Vb of the substrate 100 and the lower surface 100B of the substrate 100, and can be used as a seed layer (seed layer) to facilitate the formation of the conductive structure 190, or to enhance the bonding between the substrate 100 and the conductive vias 190P1a and 190P 1B.

Referring to fig. 2D, a conductive structure 190 and a conductive material structure 186S are formed. The conductive structure 190 and the conductive material structure 186S may be formed by a physical vapor deposition method or a chemical vapor deposition method, and one or more patterning steps are performed after a material layer (not shown) is formed. In this way, the line layer 190L of the conductive structure 190 may be patterned into the signal lines 190L1, 190L2a to 190L5a, and 190L2B to 190L5B shown in fig. 1B, and the conductive portion 190Pa of the conductive structure 190 may be patterned out of the connection region 190 Sa. In some embodiments, the conductive structure 190 and the conductive material structure 186S may be formed together in the same process. In other embodiments, the conductive structures 190 and the conductive material structures 186S may be formed separately in different processes. The material forming the conductive material structure 186S fills the contact hole H6, such that the conductive pattern 186P of the conductive material structure 186S contacts the drain D1.

In addition, the line layer 190L and the conductive portion (e.g., the conductive portion 190Pa and the conductive portion 190Pb shown in fig. 1B) of the conductive structure 190 may be integrally formed, that is, the line layer 190L and the conductive portion are formed in the same process. The material forming the conductive structure 190 is filled in the through hole 100Va, the opening 181H1 of the conductive pattern 181P1 and the opening 182H of the conductive pattern 182P, so that the conductive via 190P1a of the conductive portion 190Pa of the conductive structure 190 is embedded in the through hole 100Va, the openings 181H1 and 182H to penetrate through the substrate 100 and the film layer on the upper surface 100T of the substrate 100. The material forming the conductive structure 190 is filled in the opening 181H2 of the conductive pattern 181P2, so that the conductive via 190P2a of the conductive portion 190Pa of the conductive structure 190 contacts the source S1. The

conductive material structures

181S and 182S may serve as seed layers (seed layers) that facilitate the formation of the conductive vias 190P1a and 190P2a, or may improve the uniformity of the formation of the conductive vias 190P1a and 190P2a, or may enhance the bonding between the conductive vias 190P1a and 190P2a and the

buffer layers

110a and 110b, the

gate insulating layers

120a and 120b, the interlayer dielectric layer 130 and/or the planarization layer 140. The source S1 of the active device T1 on the upper surface 100T of the substrate 100 may be coupled to the circuit layer 190L on the lower surface 100B of the substrate 100 through a via 190 Pa.

Referring to fig. 1A and fig. 2D, after the conductive structure 190 is formed, a light emitting unit L1 is formed on the conductive material structure 186S. The driving circuit IC and the substrate 199 are disposed on the lower surface 100B of the substrate 100 and are bonded to the circuit layer 190L of the conductive structure 190. In this way, the display panel 10 can be completed.

In fig. 1A and 1B, the conductive pattern 181P1 of the conductive material structure 181S and the conductive pattern 182P of the conductive material structure 182S respectively cover the sidewall of the conductive via 190P1A of the conductive part 190Pa, and the conductive pattern 183P1 of the conductive material structure 183S and the conductive pattern 184P of the conductive material structure 184S respectively cover the sidewall of the conductive via 190P1B of the conductive part 190 Pb. However, the present invention is not limited thereto, and the conductive material structure may be selectively arranged according to different design considerations. For example, referring to fig. 3A and 3B, fig. 3A and 3B are respectively schematic cross-sectional views of a part of a display panel 30 according to an embodiment of the invention. The display panel 30 of the present embodiment is similar to the display panel 10 of the embodiment shown in fig. 1A and 1B, except that the display panel 30 does not include the

conductive material structures

182S and 184S. In this case, the bottom surface of the conductive pattern 181P1 of the conductive material structure 181S contacts the top surface of the interlayer dielectric layer 130, and the bottom surface of the conductive pattern 183P1 of the conductive material structure 183S contacts the top surface of the interlayer dielectric layer 130. The conductive pattern 181P1 and the surface treatment coating film 102 of the conductive material structure 181S cover part of the sidewall of the via 190P1a of the via 190Pa, and part of the sidewall of the via 190P1a is not in contact with the conductive material. The conductive pattern 183P1 of the conductive material structure 183S and the surface treatment coating film 102 cover part of the sidewall of the via 190P1b of the via 190Pb, and part of the sidewall of the via 190P1b is not in contact with the conductive material. In some embodiments, the

buffer layers

110a and 110b, the

gate insulating layers

120a and 120b, the contact hole H1 ' formed in the interlayer dielectric layer 130, and the opening 181H1 of the conductive pattern 181P1 are connected to the via 100Va, and the projections of the contact hole H1 ', the opening 181H1, and the via 100Va on the substrate 100 along the direction Z are overlapped and aligned, in which case, the shapes, areas, sizes, and/or positions of the contact hole H1 ', the opening 181H1, and the via 100Va are the same, but the invention is not limited thereto.

Referring to fig. 4A and 4B, fig. 4A and 4B are respectively schematic cross-sectional views of a part of a display panel 40 according to an embodiment of the invention. The display panel 40 of the present embodiment is similar to the display panel 30 of the embodiment shown in fig. 3A and 3B, except that the display panel 40 does not include the

conductive material structures

182S and 184S, the bottom surface of the conductive pattern 181P1 'of the conductive material structure 181S' in the display panel 40 contacts the upper surface 100T of the substrate 100, and the bottom surface of the conductive pattern 183P1 'of the conductive material structure 183S' contacts the upper surface 100T of the substrate 100. The conductive pattern 181P1 'and the surface treatment coating 102 of the conductive material structure 181S' completely cover the side wall of the via 190P1a of the via 190Pa, and the conductive pattern 183P1 'and the surface treatment coating 102 of the conductive material structure 183S' completely cover the side wall of the via 190P1b of the via 190 Pb. In addition, the opening 181H1 'of the conductive pattern 181P 1' is connected to the through hole 100Va, and the opening 183H1 'of the conductive pattern 183P 1' is connected to the through hole 100 Vb.

The through holes (e.g., the through holes 100Va, 100Vb) in the substrate 100 may be disposed in the substrate 100 according to different design considerations. For example, referring to fig. 5, fig. 5 is a schematic plan view of a display panel 50 according to an embodiment of the invention. As shown in fig. 5, the display panel 50 may include

substrates

500, 599a, 599b and signal lines 590L1 a-590L 22a, 590L1 b-590L 18b with a conductive structure. The display panel 50 of FIG. 5 can be applied to the display panels 10 to 40 of FIGS. 1A to 4B, and is used as an embodiment of the display panels 10 to 40 of FIGS. 1A to 4B. Therefore, the substrate 500 may correspond to the substrate 100, the

substrates

599a and 599b may correspond to the substrate 199, and the signal lines 590L1a to 590L22a and 590L1b to 590L18b may correspond to the signal lines 190L1 to 190L5b, respectively. For convenience of explanation, the display panel 50 of fig. 5 mainly shows one side of the lower surface of the substrate 500, and elements on the upper surface of the substrate 500 are not shown in fig. 5.

As shown in FIG. 5, the substrate 500 may have through holes 500V1 a-500V 22a, 500V1 b-500V 18b penetrating through the substrate 500. In FIG. 5, the through holes 500V1 a-500V 22a, 500V1 b-500V 18b are respectively arranged along a rectangular path, but the invention is not limited thereto, and the arrangement of the through holes can be adjusted according to different design considerations, such as along paths with other shapes, or in an array, or irregularly arranged. In addition, the substrate 500 may have a display region and a non-display region. In some embodiments, the through holes 500V1 a-500V 22a, 500V1 b-500V 18b can be distributed in the display area. In other embodiments, the vias 500V1 a-500V 22a, 500V1 b-500V 18b may be distributed in the non-display area, and the two rectangular paths corresponding to the vias 500V1 a-500V 22a, 500V1 b-500V 18b surround the two display areas of the substrate 500 respectively. In other embodiments, a portion of the vias 500V1 a-500V 22a, 500V1 b-500V 18b may be distributed in the non-display area, and another portion of the vias 500V1 a-500V 22a, 500V1 b-500V 18b may be distributed in the non-display area.

As shown in fig. 5, one end of each of the signal lines 590L1 a-590L 22a, 590L1 b-590L 18b of the conducting structure of the display panel 50 is respectively connected to the through holes 500V1 a-500V 22a, 500V1 b-500V 18b, and the other end of each of the signal lines 590L1 a-590L 22a, 590L1 b-590L 18b is respectively connected to the bonding regions BDa, BDb. In some embodiments, substrate 100 is bonded to

substrates

599a, 599b via bonding regions BDa, BDb, and in some embodiments, the traces of substrate 100 are coupled to driver circuits on

substrates

599a, 599b via bonding regions BDa, BDb, respectively.

Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a portion of a display panel 60 according to an embodiment of the invention. The display panel 60 of the present embodiment has a similar structure to the display panel 10 of the embodiment shown in fig. 1A and 1B, except that the buffer layers 110a and 110B, the gate insulating layers 120a and 120B, the interlayer dielectric layer 130, the planarization layer 140, the driving circuit IC, the active device T1, the light emitting unit L1, and the pixel electrode PE1 are included in the display panel 60, the

substrate

600, 699, the buffer layers 610a and 610B, the gate insulating layers 620a and 620B, the interlayer dielectric layer 630, the insulating layer 640, the circuit layer 650, the

conductive material structures

681S, 682S, 683S, 684S, 685S, 686S, the conducting portions 690Pa, Pb 690, 690Pc, the active device T2, the light emitting unit L2, and the pixel electrode PE 2.

The active device T2 may include a semiconductor layer SE2, a source S2, a drain D2, and a gate G2. The semiconductor layer SE2 may include source regions SP2a, SP2b, drain regions DP2a, DP2b, and a channel region CH 2. The

conductive material structures

681S, 682S, 684S-686S are disposed on the top surface 600T of the substrate 600, and the conductive material structure 683S is disposed on the bottom surface 600B of the substrate 600. The conductive patterns 681P-684P of the conductive material structures 681S-684S are connected to the connection patterns 681C-684C of the conductive material structures 681S-684S, respectively; similarly, the conductive patterns (not shown) of the conductive material structures 685S and 686S are connected to the

connection patterns

685C and 686C of the conductive material structures 685S and 686S, respectively. Connection regions 690Sa, 690Sb of the conduction portions 690Pa, 690Pb are connected to conduction pillars 690P1a, 690P1b of the conduction portions 690Pa, 690Pb, respectively, and connection regions 690Sc of the conduction portions 690Pc are connected to conduction pillars (not shown) of the conduction portions 690Pc, respectively.

The conductive via 690P1a of the conductive portion 690Pa is embedded in the through hole 600V to penetrate through the substrate 600, and the conductive pattern 681P1 of the conductive material structure 681S, the conductive pattern 682P of the conductive material structure 682S, and the conductive pattern 683P of the conductive material structure 683S respectively coat the sidewall of the conductive via 690P1a of the conductive portion 690Pa, thereby facilitating the formation of the conductive via 690P1 a. The conductive pattern 684P of the conductive material structure 684S covers the sidewall of the conductive via 690P1b of the conductive part 690Pb to facilitate formation of the conductive via 690P1b, and the conductive pattern (not shown) of the conductive material structure 685S covers the sidewall of the conductive via (not shown) of the conductive part 690Pc to facilitate formation of the conductive via.

The light emitting unit L2 on the upper surface 600T of the substrate 600 may be coupled to the source S2 of the active device T2 on the lower surface 600B of the substrate 600 through a conducting portion 690 Pa. In this way, the space between the upper surface 600T and the lower surface 600B of the substrate 600 can be sufficiently utilized for wiring, and the size of the display panel 60 can be reduced, thereby achieving size miniaturization.

In summary, the display panel of the present invention has the through hole penetrating through the substrate, so that the device on the upper surface of the substrate can be coupled to the device on the lower surface of the substrate through the conductive structure or the conductive portion embedded in the through hole, thereby achieving size miniaturization, or reducing the area of the wiring region (i.e., the non-light-emitting region) on the substrate, and achieving a narrow frame design or a seamless splicing design. In addition, the display panel of the invention uses the conductive pattern of the conductive material structure or the surface treatment coating film of the substrate as a seed crystal layer, and the seed crystal layer coats the conduction structure or the conduction part, thereby being beneficial to forming the conduction structure or the conduction part.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display panel, comprising:

a substrate having a plurality of through holes penetrating through the substrate;

a plurality of active elements arranged in an array and arranged on an upper surface of the substrate;

a conductive structure, comprising:

a circuit layer disposed on a lower surface of the substrate; and

a plurality of first conduction columns, wherein the first conduction columns are respectively embedded with the through holes and penetrate through the substrate, and the first conduction columns are respectively coupled between the circuit layer and the active elements; and

the plurality of first conductive patterns are arranged on the upper surface of the substrate and respectively wrap the side walls of the first conductive columns.

2. The display panel of claim 1, further comprising a driving circuit disposed on the lower surface of the substrate, wherein the circuit layer is electrically connected between the first conductive vias and the driving circuit.

3. The display panel of claim 1, wherein the conductive structure further comprises a plurality of conductive portions, each of the conductive portions comprises a first conductive via, a second conductive via and a connecting region of the first conductive vias, each of the first conductive vias is electrically connected to the circuit layer, the second conductive vias are respectively electrically connected to the active devices, and the connecting regions are respectively electrically connected between the first conductive vias and the second conductive vias.

4. The display panel of claim 3, further comprising a plurality of first conductive material structures disposed on the top surface of the substrate, each of the first conductive material structures including a first conductive pattern, a second conductive pattern and a connecting pattern of the first conductive patterns, the second conductive patterns respectively covering the second conductive vias, and the connecting patterns respectively electrically connected between the first conductive patterns and the second conductive patterns.

5. The display panel of claim 4, wherein an outline of a first projection of each conductive via on the substrate overlaps with an outline of a second projection of each first conductive material structure on the substrate.

6. The display panel of claim 1, further comprising a plurality of second conductive material structures, each of the second conductive material structures comprising a third conductive pattern, the third conductive patterns respectively covering the first conductive vias.

7. The display panel of claim 6, wherein a bottom surface of each of the first conductive patterns contacts the top surface of the substrate or a top surface of the second conductive material structure.

8. A display panel manufacturing method comprises the following steps:

forming a plurality of active elements on an upper surface of a substrate, the active elements being arranged in an array;

forming a plurality of first conductive patterns on the upper surface of the substrate; and

forming a plurality of through holes penetrating through the substrate; and

and forming a conducting structure, wherein the conducting structure comprises a circuit layer and a plurality of first conducting columns, the circuit layer is arranged on the lower surface of the substrate, the first conducting columns are respectively embedded with the through holes and penetrate through the substrate, the first conducting columns are respectively coupled between the circuit layer and the active elements, and the first conducting patterns respectively coat the side walls of the first conducting columns.

9. The method according to claim 8, wherein a plurality of pixel electrodes are formed on the upper surface of the substrate when the first conductive patterns are formed, the pixel electrodes being electrically connected to the active devices, respectively.

10. The method according to claim 8, wherein a surface treatment coating is formed after the through holes penetrating the substrate are formed, the surface treatment coating covering the through holes of the substrate and the lower surface of the substrate.