KR100927363B1 - 패턴 형성 방법, 회로 기판 및 다층 기판 - Google Patents
패턴 형성 방법, 회로 기판 및 다층 기판 Download PDFInfo
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- KR100927363B1 KR100927363B1 KR1020070120654A KR20070120654A KR100927363B1 KR 100927363 B1 KR100927363 B1 KR 100927363B1 KR 1020070120654 A KR1020070120654 A KR 1020070120654A KR 20070120654 A KR20070120654 A KR 20070120654A KR 100927363 B1 KR100927363 B1 KR 100927363B1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
- H05K3/125—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J3/00—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed
- B41J3/28—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed for printing downwardly on flat surfaces, e.g. of books, drawings, boxes, envelopes, e.g. flat-bed ink-jet printers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/013—Inkjet printing, e.g. for printing insulating material or resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Coating Apparatus (AREA)
Abstract
Description
Claims (10)
- 기능 재료를 포함하는 기능액을 기체(基體)를 향하여 토출하고, 상기 기체에 패턴을 형성하는 패턴 형성 방법으로서,상기 기체의 표면 온도를 토출 시의 기능액의 온도 이상 또한 기능액에 포함되는 액체 조성의 비점(沸點) 미만의 온도로 되도록 기체를 가열하는 제 1 공정과,상기 기체를 가열한 상태에서, 상기 기능액의 액적을 상기 기체에 토출시켜 패턴을 형성하는 제 2 공정으로 이루어지고,상기 제 2 공정에서, 상기 기체에 착탄한 앞서의 액적의 일부분에 겹치도록 액적을 토출할 때, 상기 앞서 착탄한 액적의 외경이 변화하지 않게 된 후에, 토출시키는 것을 특징으로 하는 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 공정은 상기 기체의 표면 온도가 상기 기체에 착탄한 액적의 중앙부에 비해 외주부(外周部)에서의 고형분 농도가 빠르게 포화 농도에 이르는 온도로 되도록, 상기 기체를 가열하는 것을 특징으로 하는 패턴 형성 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 제 2 공정에서 형성되는 패턴은, 적어도, 착탄한 인접하는 액적끼리의 일부분이 겹치도록 액적을 토출시켜 형성하는 것을 특징으로 하는 패턴 형성 방법.
- 삭제
- 제 1 항에 있어서,상기 제 2 공정은 상기 표면 온도에 대한 착탄한 액적의 외경이 변화하지 않게 될 때까지의 시간을 상기 액적의 토출 간격 시간으로 하여, 상기 토출 간격 시간 이상으로 액적을 토출하도록 한 것을 특징으로 하는 패턴 형성 방법.
- 제 1 항에 있어서,상기 기체는 세라믹 입자와 수지로 구성되고,상기 기능액은 금속 입자를 포함하는 액체인 것을 특징으로 하는 패턴 형성 방법.
- 제 1 항에 있어서,상기 기능액에 포함되는 액체 조성의 비점은 상기 액체 조성 중 가장 비점이 낮은 액체의 비점인 것을 특징으로 하는 패턴 형성 방법.
- 제 1 항에 있어서,상기 기능액에 포함되는 액체 조성의 비점은 상기 액체 조성 중에서, 돌비(突沸)하여 패턴 형성에 영향을 주는 농도인 것 중에서 가장 비점이 낮은 액체의 비점인 것을 특징으로 하는 패턴 형성 방법.
- 회로 소자를 실장하는 동시에 그 실장한 회로 소자에 대하여 전기적으로 접속된 배선이 형성된 회로 기판에 있어서,상기 배선은 제 1 항에 기재된 패턴 형성 방법으로 형성한 것을 특징으로 하는 회로 기판.
- 제 1 항에 기재된 패턴 형성 방법으로 형성한 회로 기판으로 구성되는 것을 특징으로 하는 다층 기판.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006321257A JP4367481B2 (ja) | 2006-11-29 | 2006-11-29 | パターン形成方法 |
JPJP-P-2006-00321257 | 2006-11-29 |
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KR20080048939A KR20080048939A (ko) | 2008-06-03 |
KR100927363B1 true KR100927363B1 (ko) | 2009-11-19 |
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KR1020070120654A KR100927363B1 (ko) | 2006-11-29 | 2007-11-26 | 패턴 형성 방법, 회로 기판 및 다층 기판 |
Country Status (4)
Country | Link |
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US (1) | US20080122898A1 (ko) |
JP (1) | JP4367481B2 (ko) |
KR (1) | KR100927363B1 (ko) |
CN (1) | CN101193500B (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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DE112013001892T5 (de) * | 2012-04-04 | 2014-12-24 | Ngk Spark Plug Co., Ltd. | Verfahren zum Ausbilden einer Struktur, Bauelement und Verfahren zum Herstellen eines Bauelementes |
JP2014185358A (ja) * | 2013-03-22 | 2014-10-02 | M&M Research Inst | レーザを用いる焼結体膜形成方法及び焼結体膜形成装置 |
CN105291588A (zh) * | 2015-11-19 | 2016-02-03 | 江苏汉印机电科技股份有限公司 | 双工作平台的高速印刷线路板字符喷印机及其运行方法 |
Citations (1)
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JP2003133692A (ja) * | 2001-10-29 | 2003-05-09 | Seiko Epson Corp | 膜パターンの形成方法および形成装置、ならびにこれにより得られる膜構造体、電気光学装置、電子機器、および非接触型カード媒体 |
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TW535025B (en) * | 1998-12-03 | 2003-06-01 | Hitachi Ltd | Liquid crystal display device |
US6501527B1 (en) * | 1999-07-29 | 2002-12-31 | Canon Kabushiki Kaisha | Liquid crystal elemental device, production process thereof and spacer-bearing substrate |
JP2002019260A (ja) * | 2000-07-04 | 2002-01-23 | Seiko Epson Corp | 記録方法 |
JP4048979B2 (ja) * | 2003-02-28 | 2008-02-20 | セイコーエプソン株式会社 | ノズル孔の画像認識方法およびこれを用いた液滴吐出ヘッドの位置補正方法、ノズル孔の検査方法、ノズル孔の画像認識装置およびこれを備えた液滴吐出装置 |
JP2005081335A (ja) * | 2003-09-11 | 2005-03-31 | Seiko Epson Corp | パターン形成方法、導電性薄膜、電気光学装置、電子機器 |
JP4654627B2 (ja) * | 2004-07-26 | 2011-03-23 | セイコーエプソン株式会社 | 化学吸着膜の形成方法、及び化学吸着膜 |
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2006
- 2006-11-29 JP JP2006321257A patent/JP4367481B2/ja active Active
-
2007
- 2007-10-31 US US11/930,918 patent/US20080122898A1/en not_active Abandoned
- 2007-11-26 KR KR1020070120654A patent/KR100927363B1/ko active IP Right Grant
- 2007-11-29 CN CN200710196625.XA patent/CN101193500B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003133692A (ja) * | 2001-10-29 | 2003-05-09 | Seiko Epson Corp | 膜パターンの形成方法および形成装置、ならびにこれにより得られる膜構造体、電気光学装置、電子機器、および非接触型カード媒体 |
Also Published As
Publication number | Publication date |
---|---|
KR20080048939A (ko) | 2008-06-03 |
CN101193500A (zh) | 2008-06-04 |
US20080122898A1 (en) | 2008-05-29 |
JP2008135599A (ja) | 2008-06-12 |
JP4367481B2 (ja) | 2009-11-18 |
CN101193500B (zh) | 2011-03-16 |
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