KR100874640B1 - LCD and its driving method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for improving display quality by preventing direct current afterimage and flicker.

The liquid crystal display includes: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; A polarity control signal in which logic is periodically inverted and a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period by inverting the logic in units of one frame period. Control circuit; Invert the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal and shift the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines. A data driving circuit; And a gate driving circuit supplying the scan pulses to the gate lines.

Description

Liquid Crystal Display and Driving Method

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

5 is a view for explaining a method of driving a liquid crystal display device according to an embodiment of the present invention;

FIG. 6 is a waveform diagram showing an effect of preventing direct current afterimage of the liquid crystal display shown in FIG. 5; FIG.

7 is a view illustrating a polar pattern of data voltage supplied to a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a waveform diagram showing an experimental result of data voltages as shown in FIG. 7.

FIG. 9 is an optical waveform diagram showing an experimental result of a liquid crystal display panel to which data voltages as shown in FIG. 7 are supplied.

10 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 11 is a block diagram showing in detail the data driving circuit shown in FIG. 10; FIG.

12 is a circuit diagram showing in detail the digital-to-analog converter shown in FIG.

FIG. 13 is a waveform diagram showing a polarity control signal and a horizontal output switching signal for controlling the digital-to-analog converter shown in FIG.

14 is a flowchart illustrating a method of driving a liquid crystal display according to another embodiment of the present invention.

15 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 16 is a view illustrating a polar pattern of data voltage supplied to a liquid crystal display according to another exemplary embodiment of the present invention. FIG.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101, 151: timing controller

103, 153: data driving circuit 104: gate driving circuit

105: system 106: line memory

111: shift register 112: data register

113, 114: latch 115: digital-to-analog converter

116: charge share circuit 117: output circuit

121: P-decoder 122: N-decoder

123a to 123d: multiplexer 124a, 124b: horizontal polarity switching circuit

151: image analysis circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality by preventing direct current afterimage and flicker.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One such example is a case in which data voltages of an interlace type are supplied to a liquid crystal display. Interlaced data (hereinafter referred to as "interlaced data") includes only the odd line data voltages to be displayed on the liquid crystal cells of the odd horizontal lines in the odd frame period, and is displayed on the liquid crystal cells of the even horizontal lines in the even frame period. Only the data voltage to be included is included.

2 is a waveform diagram illustrating an example of interlace data supplied to a liquid crystal cell Clc. It is assumed that the liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is any one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, since the high positive data voltage is supplied only to the liquid crystal cell Clc arranged on the odd horizontal line during the odd frame period, the positive data voltage is negatively divided like the waveform in the box during the four frame periods. It is predominant compared to that of the direct current afterimage. Figure 3 is an image showing the experimental results of the DC afterimage resulting from the interlace data. When the original image as shown in the left image of FIG. 3 is supplied to the liquid crystal display panel in an interlaced manner for a predetermined time, the amplitude of the data voltage whose polarity changes in units of frame periods varies in the odd frame and the even frame, resulting in the original image as shown in the left image. After the image is supplied with a data voltage of intermediate gradation, that is, 127 gradations, to all the liquid crystal cells Clc of the liquid crystal display panel, a direct current afterimage in which a pattern of the original image is faint appears as shown in the right image.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, the voltage of the same polarity is applied to the liquid crystal cell Clc according to the correlation between the scrolling speed and the scrolling speed. Accumulation may occur repeatedly, resulting in a DC afterimage. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC afterimage appearing when moving the diagonal pattern and the character pattern at a constant speed.

In a liquid crystal display device, not only the display quality of a moving image is deteriorated by the afterimage of DC, but also the display quality is deteriorated by a flicker phenomenon in which the luminance difference is periodically observed by the naked eye. Therefore, in order to improve the display quality of the liquid crystal display device, it is necessary to solve the DC afterimage and to prevent the flicker phenomenon.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which are designed to solve the problems of the prior art and to improve display quality by preventing direct current afterimage and flicker.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse; A polarity control signal in which logic is periodically inverted and a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period by inverting the logic in units of one frame period. Control circuit; Invert the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal and shift the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines. A data driving circuit; And a gate driving circuit supplying the scan pulses to the gate lines.
The data voltage polarity in the row direction is shifted by one dot from " +--+ " to " + +--"

The polarity control signal is inverted logic in units of one horizontal period or two horizontal periods.

During the Nth frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the odd rows in columns 4i (i is an integer greater than or equal to 0) +1 and columns 4i + 4, and columns 4i + 2 and 4i are provided. A negative data voltage is supplied to the liquid crystal cells arranged in the odd row in a +3 column, and a negative data voltage is supplied to the liquid crystal cells arranged in an even row in the fourth i + 1 column and the fourth i + 4 column. The data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth row and the fourth row.

During the N + 1th frame period, the data voltages of the positive polarity are supplied to the liquid crystal cells arranged in the odd rows in the fourth i + 1 column and the fourth i + 2 column, and the fourth i + 3 column and the fourth electrode are provided. The negative data voltages are supplied to the liquid crystal cells arranged in the odd rows in columns 4i + 4, and the liquid crystal cells arranged in the even rows in the fourth i + 1 columns and the fourth i + 2 columns are provided in the odd rows. The data voltage of negative polarity is supplied, and the data voltage of positive polarity is supplied to the liquid crystal cells arranged in the even row in the fourth row and the fourth row.

During the N + 2th frame period, the negative data voltages are supplied to the liquid crystal cells arranged in the odd rows in the 4i + 1 columns and the 4i + 4 columns, and the 4i + 2 columns and the The positive data voltages are supplied to the liquid crystal cells arranged in the odd rows in column 4i + 3, and the positive electrodes are provided in the liquid crystal cells arranged in the even rows in columns 4i + 1 and 4i + 4. The negative data voltage is supplied, and the negative data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth row and the fourth row.

During the N + 3th frame period, the negative data voltage is supplied to the liquid crystal cells arranged in the odd row in the fourth i + 1 column and the fourth i + 2 column, and the fourth i + 3 column and the The positive data voltages are supplied to the liquid crystal cells arranged in the radix row in the fourth i + 4 column, and the liquid crystal cells arranged in the even row in the fourth i + 1 column and the fourth i + 2 column are provided in the fourth row. The positive data voltage is supplied, and the negative data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth and fourth columns.

The polarity of the data voltage supplied to the first liquid crystal cell during the Nth frame period and the N + 1th frame period is maintained at the same polarity and is supplied to the second liquid crystal cell adjacent in the row direction with the first liquid crystal cell. The polarity of the data voltage is inverted at the same time as the start of the N + 1th frame period.

The polarity of the data voltage supplied to the second liquid crystal cell is maintained at the same polarity during the N + 1th frame period and the N + 2th frame period, and the polarity of the data voltage supplied to the first liquid crystal cell is Inverted at the same time as the start of the N + 2th frame period.

During the Nth frame period, positive data voltages are applied to liquid crystal cells arranged in rows 4j (positive integer) + 1 and 4j + 2 in columns 4i + 1 (i is a positive integer) and 4i + 4. Is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 2 and 4i + 3 columns, and the 4i + 1 and 4i are supplied. The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows in a +4 column, and the fourth j + 3 and fourth in the fourth i + 2 and fourth i + 3 columns. The positive data voltages are supplied to the liquid crystal cells arranged in the 4j + 4 rows.

During the N + 1th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns, and the fourth i The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the +3 and 4i + 4 columns, and the The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 3 and fourth i + 4 columns. The data voltages of the positive polarity are supplied to the liquid crystal cells disposed in the.

During the N + 2th frame period, the negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 2 and 4i + 3 columns, and the columns of the 4i + 1 and 4i + 4 columns are supplied. The positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 2 and fourth i + 3 columns. The negative data voltages are supplied to the arranged liquid crystal cells.

During the N + 3th frame period, the negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns. The positive data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 3 and 4i + 4 columns, and the 4i + 1 and 4i + 2 columns are provided. The positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 3 and fourth i + 4 columns. The negative data voltages are supplied to the arranged liquid crystal cells.

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses, and having a plurality of liquid crystal cells; An image analysis circuit for analyzing digital video data of the input image; In addition to generating a polarity control signal in which logic is inverted periodically, shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period when the image determination result of the image analysis circuit is interlaced. A control circuit for generating a horizontal output switching signal for the circuit; A data driving circuit for inverting the polarity of the data voltage in units of the horizontal period in response to the polarity control signal and shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines; in; And a gate driving circuit supplying the scan pulses to the gate lines.

A method of driving a liquid crystal display according to an embodiment of the present invention includes the steps of: generating a polarity control signal whose logic is inverted periodically; Generating a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in one frame period; Inverting the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal, shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to the data lines. Supplying; And supplying the scan pulse to the gate lines.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes analyzing digital video data of an input image; Generating a polarity control signal in which logic is inverted periodically; Generating a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period when the image determination result of the input image is interlaced; Inverting the polarity of the data voltage in units of the horizontal period in response to the polarity control signal and shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines; And supplying the scan pulse to the gate lines.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 16.

Referring to FIG. 5, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention inverts the polarity of the data voltage charged in the liquid crystal cell in units of two frame periods and supplies the adjacent liquid crystal cells in the horizontal direction. The polarity inversion periods of the data voltages to be offset are shifted.

The polarities of the data voltages supplied to the liquid crystal cells (first liquid crystal cell group) in the left column during the Nth (N is a positive integer) frame period and the N + 1 frame period are maintained at either polarity and the liquid crystal cells in the right column The polarities of the data voltages supplied to the second liquid crystal cell group are reversed from negative polarity (or positive polarity) to positive polarity (or negative polarity). The polarities of the data voltages supplied to the liquid crystal cells (first liquid crystal cell group) in the right column during the N + 1th frame period and the N + 2 frame period are maintained at either polarity and the liquid crystal cells in the left column (second liquid crystal cell group). The polarities of the data voltages supplied to () are inverted from negative (or positive) to positive (or negative). Further, the polarities of the data voltages supplied to the liquid crystal cells (first liquid crystal cell group) in the left column during the N + 2th frame period and the N + 3 frame period are maintained at either polarity, and the liquid crystal cells (second column) in the right column are maintained. The polarities of the data voltages supplied to the liquid crystal cell group are reversed from negative polarity (or positive polarity) to positive polarity (or negative polarity). Accordingly, there are liquid crystal cells (second liquid crystal cell group) in which the polarity of the data voltage is inverted once around the liquid crystal cells (first liquid crystal cell group) in which the polarity of the data voltage is maintained for two frame periods.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention provides a first liquid crystal in which a data voltage having the same polarity is supplied to a liquid crystal cell for two frame periods to prevent direct current afterimage, and the polarity of the data voltage is maintained for two frame periods. Flickering is prevented by inverting the polarity of the data voltage supplied to the second liquid crystal cell group present around the cell group once. Referring to FIG. 6, the effects of no direct-current afterimage appearing when the data voltage supplied to the liquid crystal cell is inverted every two frame periods will be described.

Referring to FIG. 6, it is assumed that a high data voltage is supplied to the liquid crystal cell during the odd frame period and a relatively low data voltage is supplied during the even frame period, and the polarities of the data voltages change every two frame periods. Then, like the waveforms in the box, the positive data voltages supplied to the liquid crystal cell during the Nth frame period and the N + 1th frame period and the negative polarity supplied to the same liquid crystal cell during the N + 2 and N + 3th frame periods. The data voltages are neutralized so that voltages of polarized polarities are not accumulated in the liquid crystal cell. Accordingly, the liquid crystal display of the present invention does not appear to have a DC afterimage when interlace data is generated in which a high voltage of a specific polarity is generated during one of the odd frame and the even frame.

However, when all of the liquid crystal cells are inverted at the same time in two frame periods as shown in FIG. 6, flicker may appear in two frame periods. If the flicker shortens the period of change in brightness, the observer does not feel the flicker. Therefore, in the method of driving the liquid crystal display according to the exemplary embodiment of the present invention, the polarity of the data voltage supplied to other liquid crystal cells existing around the liquid crystal cell charged with the data voltage of the same polarity for two frame periods is determined by one frame period. Inverting the signal to increase the spatial frequency of the display screen so that the viewer hardly feels flicker.

FIG. 7 is a diagram illustrating polarities of data voltages supplied to 8x7 liquid crystal cells during Nth through Nth + 3th frame periods.

During the Nth frame period, the liquid crystal cells arranged in radix rows R1, R3, R5, and R7 in columns 4i (i are integers greater than or equal to 0) +1 and 4i + 4 (C1, C4, C5, and C8). Are supplied with positive data voltages and are arranged in radix rows R1, R3, R5, and R7 in columns 4i + 2 and 4i + 3, C2, C3, C6, and C7. Is supplied with a negative data voltage. During the Nth frame period, a negative data voltage is applied to liquid crystal cells arranged in even rows R2, R4, and R6 in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8). Is supplied, and a positive data voltage is supplied to the liquid crystal cells formed in the even rows R2, R4, and R6 in the 4i + 2 and 4i + 3 columns C2, C3, C6, and C7. . The first group of liquid crystal cells for preventing DC afterimage during the N-th frame period includes liquid crystal cells arranged on even vertical lines, and the second group of liquid crystal cells for preventing flicker includes liquid crystal cells arranged on an even vertical line. .

During the N + 1th frame period, positive polarity (+) is applied to the liquid crystal cells arranged in the radix rows R1, R3, R5, and R7 in the columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6). ) Is supplied with a negative polarity (-) to the liquid crystal cells arranged in the radix rows R1, R3, R5, and R7 in the 4i + 3 and 4i + 4 columns C3, C4, C6, and C7. Is supplied with the data voltage. During the N + 1th frame period, the liquid crystal cells arranged in the even rows R2, R4, and R6 in the 4i + 1 and 4i + 2 columns C1, C2, C5, and C6 have a negative polarity (-). The data voltages are supplied, and the positive data voltages are applied to the liquid crystal cells arranged in the even rows R2, R4, and R6 in the 4i + 3 and 4i + 4 columns C3, C4, C6, and C7. Is supplied. The first liquid crystal cell group for preventing direct current afterimage during the N + 1 frame period includes liquid crystal cells arranged on an even vertical line, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells disposed on an even vertical line. Include.

During the N + 2th frame period, the liquid crystal cells arranged in the odd rows R1, R3, R5, and R7 in the 4i + 1 and 4i + 4 columns C1, C4, C5, and C8 have negative polarity (−). ) Is supplied, and the positive polarity (+) is applied to the liquid crystal cells arranged in the radix rows R1, R3, R5, and R7 in the 4i + 2 and 4i + 3 columns C2, C3, C6, and C7. Is supplied with the data voltage. During the N + 2th frame period, the liquid crystal cells arranged in the even rows R2, R4, and R6 in the 4i + 1 and 4i + 4 columns C1, C4, C5, and C8 have positive polarity (+). The data voltages are supplied, and the negative data voltages are applied to the liquid crystal cells formed in the even rows R2, R4, and R6 in the 4i + 2 and 4i + 3 columns C2, C3, C6, and C7. Supplied. The first liquid crystal cell group for preventing direct current afterimage during the N + 2 frame period includes liquid crystal cells arranged in even vertical lines, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells arranged in an even vertical line. Include.

During the N + 3th frame period, the liquid crystal cells arranged in the odd rows R1, R3, R5, and R7 in the 4i + 1 and 4i + 2 columns C1, C2, C5, and C6 have a negative polarity (−). ) Is supplied, and positive polarity (+) is applied to the liquid crystal cells arranged in the odd rows R1, R3, R5, and R7 in the 4i + 3 and 4i + 4 columns C3, C4, C6, and C7. Is supplied with the data voltage. During the N + 3th frame period, the liquid crystal cells arranged in the even rows R2, R4, and R6 in the 4i + 1 and 4i + 2 columns C1, C2, C5, and C6 have positive polarity (+). Data voltages are supplied, and negative data voltages are applied to liquid crystal cells arranged in even rows R2, R4, and R6 in the 4i + 3 and 4i + 4 columns C3, C4, C6, and C7. Is supplied. The first liquid crystal cell group for preventing direct current afterimage during the N + 3 frame period includes liquid crystal cells arranged on an even vertical line, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells disposed on an even vertical line. Include.

FIG. 8 illustrates an experimental result of supplying a data voltage of 127 gray levels to a liquid crystal display panel in the same polar pattern as in FIG. 7 and measuring a voltage waveform of the liquid crystal display panel. In this experiment, the data frequency is 30 Hz. One of the left and right neighboring liquid crystal cells has the same polarity of the data voltage during two frame periods, and the other has the polarity reversed in units of one frame period. Therefore, the spatial frequency including these liquid crystal cells is 60Hz and these results are confirmed on the experimental result screen of FIG. 8. In addition, as a result of measuring the optical waveform by installing an optical sensor on the liquid crystal display panel in this experiment, the optical waveform was also measured at 60 Hz due to the spatial frequency including the liquid crystal cells adjacent to the left and right as shown in FIG.

10 to 12 show a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 103, and a gate driving circuit 104.

In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The m data lines D1 to Dm and the n gate lines G1 to Gn cross the lower glass substrate of the liquid crystal display panel 100. The liquid crystal display panel 100 includes m × n liquid crystal cells Clc arranged in a matrix form by the cross structure of the data lines D1 to Dm and the n gate lines G1 to Gn. As described above, the liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group driven at different data voltage frequencies. The lower glass substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and A storage capacitor Cst or the like is formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. Polarizing plates having optical axes orthogonal to each other are attached to the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 100 in contact with the liquid crystal.

The timing controller 101 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable, clock signal (CLK), and the like. Generate control signals for controlling the operation timing of the signal. These control signals include a gate timing control signal such as a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. In addition, the control signals include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL2), and And a horizontal output switching signal HO. The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit 104 and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated at a pulse width corresponding to the ON period of the TFT. do. The gate output enable signal GOE indicates the output of the gate driving circuit 104. The source start pulse SSP indicates a start pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs the latching operation of data in the data driving circuit 103 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. The polarity control signal POL2 indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The logic control signal POL is inverted in one horizontal period cycle as shown in FIG. 7 or inverted in two horizontal period cycles as shown in FIG. The horizontal output switching signal HO is a control signal for inverting the polarity of the data voltage in units of two liquid crystal cells adjacent to each other in the pixel row as shown in FIG. 7.

In addition, the timing controller 101 separates the input digital video data RGB into the odd pixel data RGBodd and the even pixel data RGBeven in order to lower the transmission frequency of the digital video data, and the data RGBodd and RGBeven. Is supplied to the data driving circuit 103 through the six data buses.

The data driving circuit 103 latches the digital video data RGBodd and RGBeven under the control of the timing controller 101 and converts the digital video data into analog positive / negative gamma compensation voltages and the polarity control signal POL2. The data voltages having the selected polarity are supplied to the data lines D1 to Dm according to the horizontal output switching signal HO. The data driving circuit 103 selects the polarity of the data voltage to be supplied to the liquid crystal cells arranged along the column direction in response to the polarity control signal POL2. In addition, the data driving circuit 103 selects the polarity of the data voltage to be supplied to the liquid crystal cells arranged along the row direction according to the horizontal output switching signal HO. During the Nth and Nth + 2th frame periods, the horizontal output switching signal HO is generated in high logic H, and in response to the horizontal output switching signal HO: H, the data driving circuit 103 is shown in FIG. As described above, the polarities of the data voltages supplied to the four liquid crystal cells arranged along the row direction are selected as "+--+" or "-+ +-". During the N + 1th and Nth + 3th frame periods, the horizontal output signal H0 is generated in the low logic L, and the data driving circuit 103 responds to the horizontal output signal HO: L in FIG. 7. As described above, the polarities of the data voltages supplied to the four liquid crystal cells arranged along the row direction are selected as "+ +--" or "--+ +".

The gate driving circuit 104 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. Comprising a plurality of gate drive integrated circuits comprising a sequentially output scan pulses having a pulse width of approximately one horizontal period.

The liquid crystal display according to the first embodiment of the present invention further includes a system 105 for supplying digital video data RGB and timing signals Vsync, Hsync, DE, and CLK to the timing controller 101.

The system 105 extracts video data from a broadcast signal or an image source input from an external device, including a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and converts the video data into digital. Supply to timing controller 101. The interlace broadcast signal received by the system 106 is stored in the line memory 106 and then output. The video data of the interlace broadcast signal exists only in the odd line in the odd frame period and only in the even line in the even frame period. Accordingly, when the system 105 receives the interlace broadcast signal, the system 105 generates even line data of the odd frame period and odd line line data of the even frame as an average value or black data value of valid data stored in the line memory 106. The system 105 supplies timing signals Vsync, Hsync, DE, CLK and power to the timing controller 101 together with the digital video data.

11 and 12 are circuit diagrams showing the data driving circuit 103 in detail.

11 and 12, the data driving circuit 103 includes a plurality of integrated circuits (ICs) for driving k data lines D1 to Dk (k is an integer smaller than m), respectively. Each of the integrated circuits includes a shift register 111, a data register 112, a first latch 113, a second latch 114, a digital-to-analog converter (hereinafter referred to as a “DAC”) 115, and a charge. A share circuit 116 and an output circuit 117 are included.

The shift register 111 shifts the source start pulse SSP from the timing controller 101 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register 111 shifts the source start pulse SSP to transfer the carry signal CAR to the shift register 111 of the next integrated circuit. The data register 112 temporarily stores odd digital video data RGBodd and even digital video data RGBeven separated by the timing controller 101, and stores the stored data RGBodd and RGBeven in the first latch 113. Supply. The first latch 113 samples the digital video data RGBeven and RGBodd from the data register 112 in response to a sampling signal sequentially input from the shift register 111 and the data RGBeven and RGBodd. Latches and outputs the latched data simultaneously. The second latch 114 latches data input from the first latch 113 and then simultaneously latches data with the second latch 114 of other integrated circuits during the low logic period of the source output enable signal SOE. Output them.

The DAC 115 is a P-decoder (PDEC) 121 supplied with a positive gamma reference voltage GH and an N-decoder (NDEC) 122 supplied with a negative gamma reference voltage GL as shown in FIG. 12. , Multiplexers 123a to 173d for selecting the output of the P-decoder 121 and the output of the N-decoder 122 in response to the polarity control signal POL2, and the multiplexer 123a in response to the horizontal output switching signal HO. And horizontal polarity switching circuits 124a and 124b for inverting the logic of the selection control signal supplied to the control terminal of the first through 123d. The P-decoder 121 decodes the digital video data input from the second latch 114 and outputs a positive gamma compensation voltage corresponding to the gray value of the data, and the N-decoder 122 uses the second latch ( 114 decodes the digital video data inputted from the digital video data, and outputs a negative gamma compensation voltage corresponding to the grayscale value of the data.

The multiplexers 123a to 123d) are the 4i + 1 multiplexers 123a and 4i + that output data voltages to output channels connected to the 4i + 1 data lines D1, D5, D9 ... Dm-3. 4th i + 2 multiplexer 123b and 4i + 3 data lines D3, D7, D11 which output data voltages to the output channels connected to the data lines D2, D6, D10 ... Dm-2. Data to an output channel connected to a fourth i + 3 multiplexer 123c for outputting a data voltage to an output channel connected to Dm-1) and a fourth i + 4 data line (D4, D8, D12 ... Dm); And a fourth i + 4 multiplexer 123d for outputting a voltage. The fourth i + 1 multiplexer 123a selects either the positive data voltage or the negative data voltage in response to the non-inverting logic value of the polarity control signal POL2. The fourth i + 2 multiplexer 123b includes a positive data voltage and a negative data voltage in response to an inversion logic value of the polarity control signal POL2 in which the logic value is selectively inverted by the first horizontal polarity switching circuit 124a. Select either one. The fourth i + 3 multiplexer 123c selects one of a positive data voltage and a negative data voltage in response to an inversion logic value of the polarity control signal POL2. The fourth i + 4 multiplexer 123d receives the positive data voltage and the negative data voltage in response to the non-inverting logic value of the polarity control signal POL2 whose logic value is selectively inverted by the second horizontal polarity switching circuit 124b. Select either one.

The horizontal polarity switching circuits 124a and 124b include a first horizontal polarity switching circuit 124a for selectively inverting the polarity control signal POL2 supplied to the inversion control terminal of the fourth i + 2 multiplexer 123b and a fourth i +. A second horizontal polarity switching circuit 124b for selectively inverting the polarity control signal POL2 supplied to the non-inverting control terminal of the fourth multiplexer 123d is provided.

The first horizontal polarity switching circuit 124a is an inversion control terminal of the first and second switch elements to which the polarity control signal POL2 is supplied in parallel, and the second switch element S2 and the 4i + 2 multiplexer 123b. And a first inverter 125a connected therebetween. The first horizontal polarity switching circuit 124a is connected to the inversion control terminal of the fourth i + 2 multiplexer 123b for the Nth and N + 2th frame periods in response to the horizontal output switching signal HO of the high logic H. While the logic of the supplied polarity control signal POL2 is maintained as it is, the polarity control signal POL2 supplied to the inversion control terminal of the fourth i + 2 multiplexer 123b during the N + 1 and N + 3 frame periods is maintained. Invert logic

The first horizontal polarity switching circuit 124a includes the first and second switch elements S1 and S2 to which the polarity control signal POL2 is supplied in parallel, the second switch element S2 and the fourth i + 2 multiplexer 123b. A first inverter 125a connected between the inversion control terminals of The first switch element S1 is turned on in response to the high logic H of the horizontal output switching signal HO to supply the polarity control signal POL2 to the inversion control terminal of the fourth i + 2 multiplexer 123b. . The second switch element S2 is turned on in response to the low logic H of the horizontal output switching signal HO to supply the polarity control signal POL2 to the first inverter 125a so as to supply the polarity control signal POL2 to the first inverter 125a. The inverted polarity control signal POL2 is supplied to the inversion control terminal. Accordingly, the first horizontal polarity switching circuit 124a inverts the control terminal of the fourth i + 2 multiplexer 123b for the Nth and N + 2th frame periods in response to the horizontal output switching signal HO of the high logic H. While maintaining the logic of the polarity control signal POL2 supplied to the polarity, the polarity control signal POL2 supplied to the inversion control terminal of the fourth i + 2 multiplexer 123b during the N + 1 and N + 3 frame periods is maintained. Invert the logic of

The second horizontal polarity switching circuit 124b includes the third and fourth switch elements S3 and S4 to which the polarity control signal POL2 is supplied in parallel, the fourth switch element S4 and the fourth i + 4 multiplexer 123d. And a second inverter 125b connected between the non-inverting control terminals. The third switch element S3 is turned on in response to the high logic H of the horizontal output switching signal HO to supply the polarity control signal POL2 to the non-inverting control terminal of the fourth i + 4 multiplexer 123d. do. The fourth switch element S4 is turned on in response to the low logic H of the horizontal output switching signal HO to supply the polarity control signal POL2 to the second inverter 125b to supply the fourth i + 4 multiplexer ( The inverted polarity control signal POL2 is supplied to the non-inverting control terminal of 123d). Accordingly, the second horizontal polarity switching circuit 124b controls the non-inverting of the fourth i + 4 multiplexer 123d for the Nth and N + 2th frame periods in response to the horizontal output switching signal HO of the high logic H. While maintaining the logic of the polarity control signal POL2 supplied to the terminal as it is, the fourth i + 4 during the N + 1 and N + 3 frame periods in response to the horizontal output switching signal HO of the low logic H. The logic of the polarity control signal POL2 supplied to the inversion control terminal of the multiplexer 123d is inverted.

FIG. 13 is a waveform diagram showing a polarity control signal POL2 and a horizontal output switching signal HO.

7 and 13, the logic of the polarity control signal POL2 is inverted in units of one horizontal period, and the logic of the horizontal output switching signal HO is inverted in units of one frame period. Therefore, as shown in FIG. 7, the liquid crystal cells are driven in a vertical 1 dot inversion method V1dot in the column direction and are driven in a horizontal 2 dot inversion method H2dot in the row direction. Here, the polarity of the data voltage is shifted in the row direction every frame by the horizontal output switching signal.

14 is a flowchart illustrating a driving method of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 14, a method of driving a liquid crystal display according to an exemplary embodiment of the present invention analyzes input data and determines whether the input data is data capable of generating a DC residual image such as interlace data or scroll data. (S1, S2)

In operation S2, when the current input data is determined to be a data capable of displaying a DC residual image, the present invention provides the polarity of adjacent liquid crystal cells to the left and right of the liquid crystal cells in which the polarity of the data voltage is reversed in units of two frame periods within two frame periods. Enable the horizontal output switching signal HO to be inverted by one frame period in step S3.

In the step S2, if it is determined that the current input data is the data of which no direct current residual image appears, the present invention displays the horizontal output switching signal HO in order to reverse the polarity of the data voltage charged in all liquid crystal cells every frame period. (S4)

15 illustrates a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 15, a liquid crystal display according to another exemplary embodiment of the present invention may include a system 105, a liquid crystal display panel 100, an image analysis circuit 152, a timing controller 151, a data driving circuit 153, And a gate driving circuit 104. In this embodiment, since the system 105, the liquid crystal display panel 100, and the gate driving circuit 104 are substantially the same as the above-described embodiments, the same reference numerals will be used and detailed description thereof will be omitted.

The image analysis circuit 152 determines whether DC residual image generation is possible with respect to the digital video data of the currently input image. The image analysis circuit 152 compares data between neighboring lines in one frame image and determines the currently input data as interlace data when the data between the lines is larger than a predetermined threshold. In addition, the image analysis circuit 152 compares the data of each pixel on a frame-by-frame basis to detect a moving image in the display image and a moving speed of the image, and if the moving image moves at a preset speed, the moving image is included. The frame data is determined to be scroll data. As a result of the image analysis, the image analysis circuit 152 supplies a signal indicating the interlace data or the scroll data to the timing controller 151.

The timing controller 151 receives a timing signal such as a vertical / horizontal synchronization signal (Vsync, Hsync), a data enable (Data Enable), a clock signal (CLK), and the like, and the data driving circuit 153 and the gate driving circuit 104. Generate control signals for controlling the operation timing of the signal. Among the data timing control signals, the polarity control signal POL2 indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The logic of the polarity control signal POL2 is inverted in one horizontal period period as shown in FIG. The horizontal output switching signal HO is generated from the timing controller 151 when data that may present a current DC residual image is input as a result of the analysis of the image analysis circuit 152 and neighbors in the pixel row as shown in FIGS. 7 and 13. The polarity of the data voltage is inverted in units of two liquid crystal cells, and the polarity of the data voltage is shifted by one dot in the row direction in units of one frame period.

The data driving circuit 153 latches the digital video data RGBodd and RGBeven under the control of the timing controller 151 and converts the digital video data into analog positive / negative gamma compensation voltages. When data that may cause a DC residual image is input, the data driving circuit 153 has a polarity in the horizontal 2 dots and the vertical 1 dots as shown in FIG. 7 according to the polarity control signal POL2 and the horizontal output switching signal HO. The changing data voltages are supplied to the data lines D1 to Dm. When data in which no DC residual image appears does not appear, the data driving circuit 153 determines the polarities of the data voltages only by the polarity control signal POL2.

FIG. 16 is a diagram illustrating polarities of data voltages supplied to 8x7 liquid crystal cells during an Nth to N + 3th frame periods as polarity patterns of data voltages supplied to a liquid crystal display according to another exemplary embodiment of the present invention. to be.

During the Nth frame period, the fourth j (j is an integer of 0 or more) +1 and the fourth j + 2 rows R1, R2, R5, in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8. The liquid crystal cells arranged in R6 are supplied with a positive data voltage, and in the 4i + 2 and 4i + 3 columns C2, C3, C6, and C7, the fourth j + 1 and the fourth j + 2 are respectively. The liquid crystal cells arranged in the rows R1, R2, R5, and R6 are supplied with a negative data voltage. During the Nth frame period, the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8 are included in the liquid crystal cells. A negative data voltage is supplied to the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 2 and fourth i + 3 columns C2, C3, C6, and C7. The arranged liquid crystal cells are supplied with a positive data voltage. The first group of liquid crystal cells for preventing DC afterimage during the N-th frame period includes liquid crystal cells arranged on even vertical lines, and the second group of liquid crystal cells for preventing flicker includes liquid crystal cells arranged on an even vertical line. .

During the N + 1th frame period, rows 4j + 1 and 4j + 2 are arranged in rows 4j + 1 and 4j + 2 in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6). The liquid crystal cells are supplied with a positive data voltage, and are arranged in the fourth j + 1 and fourth j + 2 rows R1 and R2 in columns 4i + 3 and 4i + 4 (C3, C4, C6, and C7). The data voltages of the negative polarity (-) are supplied to the liquid crystal cells disposed in the R5 and R6. Liquid crystal cells arranged in rows 4j + 3 and 4j + 4 (R3, R4, and R7) in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6) during the N + 1th frame period. Field is supplied with a negative data voltage, and the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 3 and fourth i + 4 columns C3, C4, C6, and C7. The liquid crystal cells disposed in the C1 are supplied with a positive data voltage. The first liquid crystal cell group for preventing direct current afterimage during the N + 1 frame period includes liquid crystal cells arranged on an even vertical line, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells disposed on an even vertical line. Include.

During the N + 2th frame period, the fourth j + 1 and fourth j + 2 rows R1, R2, R5 and R6 are arranged in the fourth i + 1 and fourth i + 4 columns C1, C4, C5 and C8. The liquid crystal cells are supplied with a negative data voltage, and are arranged in the fourth j + 1 and fourth j + 2 rows R1 and R2 in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7). The data voltages of the positive polarity (+) are supplied to the liquid crystal cells disposed in the R5 and R6. Liquid crystal cells arranged in rows 4j + 3 and 4j + 4 (R3, R4, and R7) in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8) during the N + 2th frame period. Field is supplied with a positive data voltage, and the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 2 and fourth i + 3 columns C2, C3, C6, and C7. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. The first liquid crystal cell group for preventing direct current afterimage during the N + 2 frame period includes liquid crystal cells arranged in even vertical lines, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells arranged in an even vertical line. Include.

During the N + 3th frame period, rows 4j + 1 and 4j + 2 are arranged in rows 4j + 1 and 4j + 2 in the 4i + 1 and 4i + 2 columns C1, C2, C5, and C6. The liquid crystal cells are supplied with a negative data voltage, and the fourth j + 1 and fourth j + 2 rows R1 and R2 are arranged in columns 4i + 3 and 4i + 4 (C3, C4, C6, and C7). The data voltages of the positive polarity (+) are supplied to the liquid crystal cells disposed in the R5 and R6. Liquid crystal cells arranged in rows 4j + 3 and 4j + 4 (R3, R4, and R7) in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6) during the N + 3th frame period. Field is supplied with a positive data voltage, and the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 3 and fourth i + 4 columns C3, C4, C6, and C7. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. The first liquid crystal cell group for preventing direct current afterimage during the N + 3 frame period includes liquid crystal cells arranged on an even vertical line, and the second liquid crystal cell group for preventing flicker includes liquid crystal cells disposed on an even vertical line. Include.

The polarity of the data voltage of FIG. 16 is controlled by the polarity control signal POL2 in which logic is inverted in units of two horizontal periods and the horizontal output switching signal HO in which polarity is inverted in units of one frame period as shown in FIG.

As described above, the liquid crystal display device and the driving method thereof according to the embodiment of the present invention invert the polarity of the data voltage supplied to the liquid crystal cells in units of two frame periods, and the data voltage in a horizontal two dot and vertical two dot manner. The polarity of is controlled and the polarity of the data voltage is shifted in the row direction by one frame period. As a result, the data voltage supplied to the liquid crystal cell is inverted in units of two frame periods to prevent direct current afterimage, and the liquid crystal cells around the liquid crystal cell are inverted in units of one frame period so that the spatial frequency of the data voltage on the display screen is increased. Since it is faster, flicker can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; A polarity control signal in which logic is periodically inverted and a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period by inverting the logic in units of one frame period. Control circuit; Invert the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal and shift the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines. A data driving circuit; And A gate driving circuit for supplying the scan pulses to the gate lines; The data voltage polarity in the row direction is shifted by one dot from " +--+ " to " + +--" during the N + 1th frame period for the Nth (N is positive integer) frame period. LCD display device. The method of claim 1, The polarity control signal, A liquid crystal display, characterized in that the logic is reversed in units of one horizontal period or two horizontal periods. The method of claim 1, During the Nth frame period, positive data voltages are supplied to the liquid crystal cells arranged in the odd rows in columns 4i (i is an integer greater than or equal to 0) +1 and columns 4i + 4, and columns 4i + 2 and 4th are provided. Negative data voltages are supplied to the liquid crystal cells arranged in the odd rows in 4i + 3 columns, and negative polarities are applied to the liquid crystal cells arranged in the even rows in the 4i + 1 columns and the 4i + 4 columns. The data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth row and the fourth row; During the N + 1th frame period, the data voltages of the positive polarity are supplied to the liquid crystal cells arranged in the odd rows in the 4i + 1 columns and the 4i + 2 columns, and the 4i + 3 columns and the The negative data voltages are supplied to the liquid crystal cells arranged in the radix row in the 4i + 4 column, and the liquid crystal cells arranged in the even row in the 4i + 1 column and the 4i + 2 column. The negative data voltage is supplied, and the positive data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth and third columns. During the N + 2th frame period, the negative data voltages are supplied to the liquid crystal cells arranged in the odd rows in the 4i + 1 columns and the 4i + 4 columns, and the 4i + 2 columns and the The positive data voltages are supplied to the liquid crystal cells arranged in the odd rows in column 4i + 3, and the positive electrodes are provided in the liquid crystal cells arranged in the even rows in columns 4i + 1 and 4i + 4. A negative data voltage is supplied and the negative data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth row and the fourth row; During the N + 3th frame period, the negative data voltage is supplied to the liquid crystal cells arranged in the odd row in the fourth i + 1 column and the fourth i + 2 column, and the fourth i + 3 column and the The positive data voltages are supplied to the liquid crystal cells arranged in the radix row in the fourth i + 4 column, and the liquid crystal cells arranged in the even row in the fourth i + 1 column and the fourth i + 2 column are provided in the fourth row. The positive data voltage is supplied, and the negative data voltage is supplied to the liquid crystal cells arranged in the even row in the fourth and fourth columns. The method of claim 3, wherein Polarities of the data voltages supplied to the first liquid crystal cell during the Nth frame period and the Nth + 1th frame period are maintained at the same polarity; And the polarity of the data voltage supplied to the second liquid crystal cell adjacent in the row direction to the first liquid crystal cell is inverted at the same time as the start of the N + 1 frame period. The method of claim 4, wherein Polarities of the data voltages supplied to the second liquid crystal cell during the N + 1th frame period and the N + 2th frame period are maintained at the same polarity; And the polarity of the data voltage supplied to the first liquid crystal cell is inverted at the same time as the start of the N + 2th frame period. The method of claim 1, During the Nth frame period, positive electrodes are included in liquid crystal cells arranged in rows 4j (j is a positive integer) +1 and 4j + 2 in columns 4i (i is a positive integer) +1 and 4i + 4. A negative data voltage is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 2 and 4i + 3 columns, and the 4i + 1 And the data voltages of the negative polarity are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows in the fourth i + 4 columns, and the fourth j + in the fourth i + 2 and fourth i + 3 columns. The data voltages of the positive polarity are supplied to the liquid crystal cells arranged in the third and fourth j + 4 rows. During the N + 1th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns, and the fourth i The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the +3 and 4i + 4 columns, and the The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 3 and fourth i + 4 columns. The data voltages of the positive polarity are supplied to the liquid crystal cells disposed in the During the N + 2th frame period, the negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 2 and 4i + 3 columns, and the columns of the 4i + 1 and 4i + 4 columns are supplied. The positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 2 and fourth i + 3 columns. Arranged liquid crystal cells are supplied with the negative data voltage, During the N + 3th frame period, the negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns, The positive data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 3 and 4i + 4 columns, and the 4i + 1 and 4i + 2 columns are provided. The positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j + 4 rows are provided in the fourth i + 3 and fourth i + 4 columns. And a negative data voltage supplied to the arranged liquid crystal cells. The method of claim 6, Polarities of the data voltages supplied to the first liquid crystal cell during the Nth frame period and the Nth + 1th frame period are maintained at the same polarity; And the polarity of the data voltage supplied to the second liquid crystal cell adjacent in the row direction to the first liquid crystal cell is inverted at the same time as the start of the N + 1 frame period. The method of claim 7, wherein Polarities of the data voltages supplied to the second liquid crystal cell during the N + 1th frame period and the N + 2th frame period are maintained at the same polarity; And the polarity of the data voltage supplied to the first liquid crystal cell is inverted at the same time as the start of the N + 2 frame period. A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; An image analysis circuit for analyzing digital video data of the input image; In addition to generating a polarity control signal in which logic is periodically inverted, the logic is reversed in units of one frame period when the interlaced data is input as a result of the image determination of the image analysis circuit. A control circuit for generating a horizontal output switching signal for shifting along the row direction of the liquid crystal cells; A data driving circuit for inverting the polarity of the data voltage in units of one horizontal period in response to the polarity control signal and shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines; ; And A gate driving circuit for supplying the scan pulses to the gate lines; The data voltage polarity in the row direction is shifted by one dot from " +--+ " to " + +--" during the N + 1th frame period for the Nth (N is positive integer) frame period. LCD display device. The method of claim 9, The polarity control signal, A liquid crystal display, characterized in that the logic is reversed in units of one horizontal period or two horizontal periods. A driving method of a liquid crystal display device comprising a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse and having a plurality of liquid crystal cells, Generating a polarity control signal in which logic is inverted periodically; Generating a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period by inverting logic in units of one frame period; Inverting the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signal, shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to the data lines. Supplying; And Supplying the scan pulse to the gate lines; The data voltage polarity in the row direction is shifted by one dot from " +--+ " to " + +--" during the N + 1th frame period for the Nth (N is positive integer) frame period. Driving method of liquid crystal display device. The method of claim 11, The polarity control signal, A driving method of a liquid crystal display device, characterized in that logic is reversed in units of one horizontal period or two horizontal periods. A driving method of a liquid crystal display device comprising a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse and having a plurality of liquid crystal cells, Analyzing digital video data of the input image; Generating a polarity control signal in which logic is inverted periodically; When the interlaced data is input as a result of the image determination of the input image, the logic is inverted in units of one frame period to shift a horizontal output switching signal for shifting the polarity of the data voltage along the row direction of the liquid crystal cells in units of one frame period. Generating; Inverting the polarity of the data voltage in units of one horizontal period in response to the polarity control signal and shifting the polarity of the data voltage in the row direction in response to the horizontal output switching signal to supply the data lines; And Supplying the scan pulse to the gate lines; The data voltage polarity in the row direction is shifted by one dot from " +--+ " to " + +--" during the N + 1th frame period for the Nth (N is positive integer) frame period. Driving method of liquid crystal display device. The method of claim 13, The polarity control signal, A driving method of a liquid crystal display device, characterized in that logic is reversed in units of one horizontal period or two horizontal periods.

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