KR100894642B1 - Liquid Crystal Display and Driving Method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for improving display quality by preventing direct current afterimage and flicker.

The liquid crystal display device includes: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses, and having first and second liquid crystal cell groups; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And a polarity control circuit that generates the polarity control signal differently in units of frame periods and controls the data voltage frequencies of the first and second liquid crystal cell groups differently by controlling the polarity inversion periods of the polarity control signals differently in a plurality of frame periods. It is provided.

Description

Liquid Crystal Display and Driving Method

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

5 is a flowchart for explaining a method of driving a liquid crystal display device according to a first embodiment of the present invention;

FIG. 6 is a view illustrating a polarity change of data voltages charged in a first and a second liquid crystal cell group. FIG.

7 is a waveform diagram illustrating an example of a data voltage charged in a first liquid crystal cell group.

8A to 8E illustrate polar patterns of data voltages supplied to first and second liquid crystal cell groups during 20 frame periods.

FIG. 9 is a waveform diagram illustrating an AC value and a DC offset value of a data voltage measured in a liquid crystal display panel to which data voltages having a polar pattern as shown in FIGS. 8A to 8E are supplied.

10 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 11 is a block diagram showing in detail the data driving circuit shown in FIG. 10; FIG.

12 is a circuit diagram showing in detail the digital-to-analog converter shown in FIG.

FIG. 13 is a block diagram illustrating in detail a POL logic circuit shown in FIG. 10; FIG.

14 is a block diagram showing in detail the POL generation circuit shown in FIG.

15 is a flowchart for explaining a method of driving a liquid crystal display according to a second embodiment of the present invention.

16 is a block diagram illustrating a liquid crystal display according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101: timing controller

102, 162: POL logic circuit 103: data driving circuit

104: gate driving circuit 105: system

106: line memory 111: shift register

112: data register 113, 114: latch

115: digital to analog converter 116: charge-sharing circuit

117: output circuit 121: P-decoder

122: N-decoder 123, 134: multiplexer

131: frame counter 132: line counter

133, 141, 142, 143: POL generating circuit 144, 145: inverter

161: image analysis circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality by preventing direct current afterimage and flicker.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One example of such an example is when interlace data voltages are supplied to a liquid crystal display. The interlace method generates a data voltage to be supplied to the liquid crystal cells of the odd horizontal line during the odd frame period, and generates a data voltage to be supplied to the liquid crystal cells of the even horizontal line during the even frame period.

2 is a waveform diagram illustrating an example of an interlaced data voltage supplied to a liquid crystal cell Clc. The liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is any one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, if the high positive data voltage is supplied only to the liquid crystal cell Clc arranged in the odd horizontal line during the odd frame period, the positive data voltage is applied to the negative data voltage like the waveform in the box during the four frame periods. It is predominant compared to that of the direct current afterimage. 3 is an image showing the experimental results of the DC afterimage. When the original image as shown in the left image of FIG. 3 is supplied to the liquid crystal display panel in an interlaced manner for a predetermined time, the amplitude of the data voltage whose polarity changes in units of frame periods varies in the odd frame and the even frame, resulting in the original image as shown in the left image. When a data voltage of an intermediate gray level, for example, 127 gray levels, is supplied to all the liquid crystal cells Clc of the liquid crystal display panel after the image, a direct current afterimage having a faint pattern of the original image appears as shown in the right image.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, voltages of the same polarity are repeatedly accumulated in the liquid crystal cell Clc according to the correlation of the scroll speed and the size of the scrolled picture. Direct afterimage may appear. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC afterimage appearing when moving the diagonal pattern and the character pattern at a constant speed.

In a liquid crystal display device, not only the moving image display quality is degraded by the afterimage of DC, but also the moving image display quality is degraded by the flicker phenomenon which periodically experiences a luminance difference with the naked eye. Therefore, in order to improve the moving image display quality of the liquid crystal display device, it is necessary to solve the DC afterimage and to prevent the flicker phenomenon.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which are designed to solve the problems of the prior art and to improve display quality by preventing direct current afterimage and flicker.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention is a liquid crystal having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse and having first and second liquid crystal cell groups. Display panel; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And a polarity control circuit that generates the polarity control signal differently in units of frame periods and controls the data voltage frequencies of the first and second liquid crystal cell groups differently by controlling the polarity inversion periods of the polarity control signals differently in a plurality of frame periods. It is provided.
The polarity control signal may include a first polarity control signal inverting logic in two horizontal periods to invert the polarity of the data voltage in two horizontal line periods of the liquid crystal display panel; And a second polarity control signal for inverting logic in one horizontal period and inverting the polarity of the data voltage in one horizontal line period of the liquid crystal display panel.

The polarity control circuit controls the data voltage frequency to be supplied to the first liquid crystal cell group lower than the data voltage frequency to be supplied to the second liquid crystal cell group.

The data voltage frequency to be supplied to the first liquid crystal cell group is 1/2 of the frequency of the data voltage to be supplied to the second liquid crystal cell group.

delete

The first polarity control signal may include: a firsta polarity control signal generated in a fourth i + 1 frame period except for a fifth i (i is an integer of 0 or more) frame period; A first b polarity control signal generated in a fourth i + 2 frame period except the fifth i frame period and having a phase difference of approximately one horizontal period with respect to the first a polarity control signal; A first c polarity control signal generated in a fourth i + 3 frame period except the fifth i frame period and generated out of phase with respect to the first a polarity control signal; And a first d polarity control signal generated in a fourth i + 4 frame period except the fifth i frame period and generated out of phase with respect to the first b polarity control signal.

The second polarity control signal is generated in the fifth frame period.

The polarity control circuit sequentially outputs the first to first polarity control signals and the second polarity control signal in frame period units.

The polarity control circuit includes a frame counter for counting a gate start pulse to generate frame count information indicating a frame number; A line counter for counting a source output enable signal to generate line count information indicating the number of display lines of the liquid crystal display panel; A polarity control signal generation circuit configured to generate the first to first polarity control signals and the second polarity control signal based on the frame count information and the line count information; And a multiplexer for sequentially selecting the first to first polarity control signals and the second polarity control signal in response to the frame count information.

The polarity control circuit may include a first inverter for inverting the firsta polarity control signal to generate the firstc polarity control signal and supply the firstc polarity control signal to the multiplexer; And a second inverter configured to invert the first b polarity control signal to generate the first d polarity control signal and to supply the first d polarity control signal to the multiplexer.

The liquid crystal display further comprises an image analysis circuit for analyzing the digital video data of the input image and controlling the output of the polarity control circuit according to the analysis result.

The image analysis circuit analyzes the digital video data of the input image and determines that the luminance difference of the data to be displayed on each of the horizontal lines adjacent to the liquid crystal display panel is greater than or equal to a preset threshold in units of frame periods. The polarity control circuit is controlled so that the polarity control signal and the second polarity control signal are sequentially output.

The image analysis circuit compares the digital video data of the input image in units of frame periods and determines that an image moving at a predetermined moving speed is included in the digital video data of the input image in units of frame periods. The polarity control circuit is controlled to sequentially output a 1d polarity control signal and the second polarity control signal.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention generates a polarity control signal differently in units of frame periods so as to control different data voltage frequencies to be supplied to the first and second liquid crystal cell groups coexisting in the liquid crystal display panel. Differently controlling a polarity inversion period of the polarity control signal at a frame period period; Supplying a data voltage to data lines of the liquid crystal display panel in response to the polarity control signal; And supplying scan pulses to gate lines of the liquid crystal display panel.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 16.

5 and 6, a method of driving a liquid crystal display according to a first exemplary embodiment of the present invention is provided in the liquid crystal display panel within two frame periods for N (N is a positive integer of 2 or more) frame periods. The first liquid crystal cell group is supplied with a data voltage whose polarity is inverted every two frame periods, and the second liquid crystal cell group is supplied with a data voltage whose polarity is inverted every one frame period. (S1) Each of the first and second liquid crystal cell groups Liquid crystal cells Clc.

In the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention, a data voltage having a polarity pattern different from that of the polarity pattern which determines the polarity of the data voltage during the N frame periods described above is applied during the N + 1 frame periods. And the second liquid crystal cell group. (S2) Hereinafter, the polarity pattern for controlling the polarity of the data voltage during the N + 1th frame period is referred to as an "non-regular polarity pattern". The non-regulated polarity pattern uses a polarization pattern different from the polarity pattern of the data voltage supplied to the liquid crystal cells Clc of the first and second liquid crystal cell groups during the N frame periods before the N + 1 frame period. The polar pattern of the cell Clc is made irregular.

In the driving method of the liquid crystal display according to the first embodiment of the present invention, the afterimage prevention is prevented by using the first liquid crystal cell group, and the flicker phenomenon is prevented by using the first liquid crystal cell group. The prevention effect of DC afterimage due to the first liquid crystal cell group will be described with reference to FIG. 7.

Referring to FIG. 7, a high data voltage is supplied to any liquid crystal cell Clc included in the first liquid crystal cell group during a odd frame period, a relatively low data voltage is supplied during an even frame period, and the data voltages are supplied in a two frame period. Assume that the polarity changes with a period. Then, the positive data voltages supplied to the liquid crystal cell Clc during the first and second frame periods and the negative data voltages supplied to the liquid crystal cell Clc during the third and fourth frame periods are neutralized to form a liquid crystal cell ( The voltage of polarized polarity in Clc) is not accumulated. Therefore, in the liquid crystal display device of the present invention, the DC residual image remains even in the data voltage, for example, the data voltage of the interlaced image, to which the first liquid crystal cell group is applied with a high voltage having a predominant polarity in either odd frame or even frame as shown in FIG. Does not appear

On the other hand, the first liquid crystal cell group can prevent a DC afterimage, but flicker may occur because data voltages having the same polarity are supplied to the liquid crystal cell Clc in two frame periods. The liquid crystal cells Clc of the second liquid crystal cell group are applied with a data voltage whose polarity is inverted in one frame period in which flicker is hardly felt by the naked eye, thereby minimizing the flicker phenomenon caused by the first liquid crystal cell group. This is because the human eye is sensitive to change, and when the first liquid crystal cell group and the second liquid crystal cell group with different driving frequencies coexist, the driving frequency of the second liquid crystal cell group with high driving frequency is driven. Because it recognizes the frequency.

8A to 8E illustrate examples of polar patterns of data voltages supplied to the liquid crystal display panel when 'N' is 4 in FIGS. 5 and 6.

8A to 8E, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention repeats the polarity pattern of the data voltage every 20 frame periods.

Except for the fifth i (i is a positive integer) frame period, in each of the 4i + 1 to 4i + 4 frame periods, the liquid crystal cells Clc of the first and second liquid crystal cell groups have logic in units of two horizontal periods. The polarity is inverted every two horizontal periods in the vertical direction by the inverted first polarity control signals POL1a to POL1d, and the data voltage has a polarity pattern in which polarities of neighboring data voltages in the horizontal direction are opposite to each other. Charge them. The first polarity control signals POL1a generated in the fourth i + 1 to fourth i + 4 frame periods are basically generated in the form of a vertical two dot inversion in which logic is inverted in two horizontal period periods.

In the fifth i (i is a positive integer greater than or equal to zero), the liquid crystal cells Clc of the first and second liquid crystal cell groups charge data voltages having different polarities with a non-regular polarity pattern in the form of one dot inversion. . That is, during the fifth i frame period, the liquid crystal cells Clc of the first and second liquid crystal cell groups are polarized in a vertical period in the horizontal direction by the second polarity control signal POL2 whose logic is inverted in units of one horizontal period. This inverts and charges the data voltages having the polarity pattern in which the polarities of the neighboring data voltages in the horizontal direction are inverted. The first polarity control signals POL1a to POL1d are replaced with the second polarity control signal POL2 in the fifth i frame period.

First and second frame periods, fourth and fifth frame periods, ninth and tenth frame periods, eleventh and twelfth frame periods, fourteenth and fifteenth frame periods, sixteenth and seventeenth frame periods, and nineteenth frame periods. And in each of the twentieth frame periods, some of the liquid crystal cells Clc of the first and second liquid crystal cell groups maintain their positions in the next frame period, and others move their positions to other horizontal lines in the next frame period. In contrast, the second to fourth frame periods, the seventh to ninth frame periods, the tenth and eleventh frame periods, the twelfth to fourteenth frame periods, the fifteenth and sixteenth frame periods, and the seventeenth to nineteenth frame periods. In each of the liquid crystal cells Clc of the first and second liquid crystal cell groups, positions do not overlap between the previous frame and the next frame period.

The first polarity control signal POL1a generated in the fourth i + 1 frame period and the firstc polarity control signal POL1c generated during the fourth i + 3 frame period are generated as waveforms of an inverse phase with each other. The first-b polarity control signal POL1b generated in the fourth i + 2 frame period and the first-d polarity control signal POL1d generated in the fourth i + 4 frame period are generated as waveforms of inverse phase with each other. The phase difference between the first polarity control signal POL1a and the first b polarity control signal POL1b is equal to one horizontal period, and the firstc polarity control signal POL1c and the first polarity control signal POL1d are also equal to one horizontal period. There is a phase difference.

8A to 8B, the polarities of the data voltages supplied to the liquid crystal cells Clc of the first liquid crystal cell group are inverted in units of two frame periods. On the other hand, the data voltage supplied to the liquid crystal cells Clc of the second liquid crystal cell group is inverted in polarity in units of one frame period while the voltage polarity of the first liquid crystal cell group remains the same for two frame periods.

Since the liquid crystal cells Clc of the first liquid crystal cell group have a relatively long polarity change period, they may make flicker visible when spatially concentrated. Accordingly, in the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIGS. 8A to 8E, the polarities of the data voltages are not maintained so that the liquid crystal cells Clc of the first liquid crystal cell group are continuous for three or more horizontal lines in each frame period. To control.

In addition, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention is a frame period in which the position of the horizontal line in which the liquid crystal cells Clc of the first liquid crystal cell group exist as shown in FIGS. 8A to 8E is maximum. Control less than Since the liquid crystal cells Clc of the first liquid crystal cell group have a relatively long polarity change period, when their positions are the same for three or more frame periods, wave noise may be caused by causing a luminance difference with other horizontal lines.

FIG. 9 shows an experimental result of supplying a data voltage of 127 gradations to the specimen liquid crystal display panel in the same polar pattern as FIGS. 8A to 8E and measuring the voltage waveform of the liquid crystal display panel. In this experiment, the second liquid crystal cell group of the specimen liquid crystal display panel is supplied with a data voltage of 60 Hz frequency and the first liquid crystal cell group is supplied with a data voltage of 30 Hz frequency, but the 60 Hz frequency with high frequency prevails, so that the measurement is performed on the specimen liquid crystal display panel. The frequency of the data voltage is measured at 60 Hz. The AC voltage value AC of the data voltage, that is, the amplitude was 30.35 mV, and the DC offset value DC between the center of the AC voltage and the ground voltage GND was measured to be 1.389V. In addition, in this experiment, the optical waveform was measured by installing an optical sensor on the specimen liquid crystal display panel. As a result, the optical waveform of the specimen liquid crystal display panel was also measured at 60 Hz due to the predominant frequency of the second liquid crystal cell group. This is because the optical waveform measured in the specimen liquid crystal display panel is determined by the light conversion period of the second liquid crystal cell group having a faster frequency than the first liquid crystal cell having a slow frequency.

10 to 14 show a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a POL logic circuit 102, a data driving circuit 103, and a gate driving circuit. 104 is provided.

In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The liquid crystal display panel 100 includes m × n liquid crystal cells Clc in which m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix by a cross structure. Include. As described above, the liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group driven at different data voltage frequencies.

The lower glass substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. Meanwhile, the common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS). In the horizontal electric field driving method as in the mode, the pixel electrode 1 is formed on the lower glass substrate. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 101 receives a timing signal such as a vertical / horizontal synchronization signal (Vsync, Hsync), a data enable (Data Enable), a clock signal (CLK), and the like, and the data driving circuit 104 and the gate driving circuit 104. And control signals for controlling the operation timing of the POL logic circuit 102. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). , A source sampling clock (SSC), a source output enable signal (SOE), and a reference polarity control signal (Polarity: POL). The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit and is a timing control signal for sequentially shifting the gate start pulse GSP, and is generated with a pulse width corresponding to the ON period of the TFT. The gate output signal GOE indicates the output of the gate driving circuit 104. The source start pulse SSP indicates the start pixel on one horizontal line in which the data control signal DDC is to be displayed. The source sampling clock SSC instructs the latching operation of data in the data driving circuit 103 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. The reference polarity control signal Polar (POL) indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The reference polarity control signal POL is generated as either a polarity control signal of one dot inversion in which logic is inverted in one horizontal period or a polarity control signal of two dot inversion in which logic is inverted in two horizontal periods.

The POL logic circuit 102 receives the gate start pulse GSP, the source output enable signal SOE, and the reference polarity control signal POL, and includes 4i + 1 to 4i + 4 frames except for the fifth frame period. The first polarity control signal POL1 is generated during the period and the second polarity control signal POL2 is generated during the fifth i frame period. The first polarity control signal POL1 includes the first polarity control signal POL1a generated in the fourth i + 1 frame period, the first polarity control signal POL1b generated in the fourth i + 2 frame period, and the fourth i + 3 frame. 1c polarity control signal POL1c generated during the period, and 1d polarity control signal POL1d generated during the 4i + 4 frame period. In addition, the POL logic circuit 102 may optionally transmit the reference polarity control signal POL to the data driving circuit 103 as it is for all frame periods.

The data driving circuit 103 latches the digital video data RGB under the control of the timing controller 101 and analog-responses the digital video data in response to the polarity control signal POL / POL1 / POL2 from the timing controller 101. It converts into a positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and supplies the data voltage to the data lines D1 to Dm.

The gate driving circuit 104 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. Comprising a plurality of gate drive integrated circuits comprising a sequentially output scan pulses having a pulse width of approximately one horizontal period.

The timing controller 101 and the POL logic circuit 102 may be integrated into one chip.

The liquid crystal display according to the first embodiment of the present invention further includes a system 105 for supplying digital video data RGB and timing signals Vsync, Hsync, DE, and CLK to the timing controller 101.

The system 105 extracts video data from a broadcast signal or an image source input from an external device, including a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and converts the video data into digital. Supply to timing controller 101. The interlace broadcast signal received by the system 106 is stored in the line memory and then output. The video data of the interlace broadcast signal exists only in the odd line in the odd frame period and only in the even line in the even frame period. Accordingly, when the system 105 receives the interlace broadcast signal, the system 105 generates even line data of the odd frame period and odd line line data of the even frame as an average value or black data value of valid data stored in the line memory 106. The system 105 supplies timing signals Vsync, Hsync, DE, CLK and power to the timing controller 101 together with the digital video data.

11 and 12 are circuit diagrams showing the data driving circuit 103 in detail.

11 and 12, the data driving circuit 103 includes a plurality of integrated circuits (ICs) for driving k data lines D1 to Dk (k is an integer smaller than m), respectively. Each of the integrated circuits includes a shift register 111, a data register 112, a first latch 113, a second latch 114, a digital-to-analog converter (hereinafter referred to as a “DAC”) 115, and a charge. A share circuit 116 and an output circuit 117 are included.

The shift register 111 shifts the source start pulse SSP from the timing controller 101 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register 111 shifts the source start pulse SSP to transfer the carry signal CAR to the shift register 111 of the next integrated circuit. The data register 112 temporarily stores odd digital video data RGBodd and even digital video data RGBeven separated by the timing controller 101, and stores the stored data RGBodd and RGBeven in the first latch 113. Supply. The first latch 113 samples the digital video data RGBeven and RGBodd from the data register 112 in response to a sampling signal sequentially input from the shift register 111, and the data latches RGBeven and RGBodd. ) Is latched by one horizontal line, and then data for one horizontal line is output at the same time. The second latch 114 latches one horizontal line of data input from the first latch 113 and then second latch 114 of other integrated circuits during the low logic period of the source output enable signal SOE. And latched digital video data at the same time. The DAC 115 is a P-decoder (PDEC) 121 supplied with a positive gamma reference voltage GH and an N-decoder (NDEC) 122 supplied with a negative gamma reference voltage GL as shown in FIG. 12. And a multiplexer 123 for selecting the output of the P-decoder 121 and the output of the N-decoder 122 in response to the polarity control signals POL / POL1 / POL2. The P-decoder 121 decodes the digital video data input from the second latch 114 and outputs a positive gamma compensation voltage corresponding to the gray value of the data, and the N-decoder 122 uses the second latch ( 114 decodes the digital video data inputted from the digital video data, and outputs a negative gamma compensation voltage corresponding to the grayscale value of the data. The multiplexer 123 alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal POL / POL1 / POL2 and outputs the selected positive / negative gamma compensation voltage as an analog data voltage. do. The charge share circuit 116 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE to output an average value of the neighboring data voltages, or the output of the source output enable signal SOE. The common voltage Vcom is supplied to the data output channels during the high logic period to reduce the sudden change of the positive data voltage and the negative data voltage. The output circuit 117 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

13 and 14 are circuit diagrams illustrating the POL logic circuit 102 in detail.

13 and 14, the POL logic circuit 102 includes a frame counter 131, a line counter 132, a POL generation circuit 133, and a multiplexer 134.

The frame counter 131 is a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 in response to the gate start pulse GSP, which is generated once during one frame period and coincided with the start of one frame period. Outputs information Fcnt. The frame count information Fcnt is generated as 5-bit information so that each of the 20 frame periods can be identified assuming that a polar pattern of the data voltage as shown in FIGS. 8A to 8E is generated.

The line counter 132 is line count information Lcnt indicating a horizontal line to be displayed on the liquid crystal display panel 100 in response to a source output enable signal SOE indicating a time point at which data voltages are supplied to each horizontal line. Outputs The line count information Fcnt is two-bit information because the polarity of the data voltage displayed on the liquid crystal display panel 100 is inverted in one or two horizontal line periods as shown in the polarity pattern of the data voltage as shown in FIGS. 8A to 8E. Is caused by.

As a timing signal supplied to the frame counter 131 and the line counter 132, a clock generated from the internal oscillator of the timing controller 101 may be used. However, since the clock has a high frequency, the timing controller 101 and the POL logic circuit may be used. It is possible to increase electromagnetic interference (EMI) between the 102. According to the present invention, the operation of the frame counter 131 and the line counter 132 operates the gate start pulse GSP and the source output enable signal SOE having a smaller frequency than the clock generated by the internal oscillator of the timing controller 101. The increase in EMI between the timing controller 101 and the POL logic circuit 102 can be reduced by using the timing signal.

The POL generating circuit 133 includes a first POL generating circuit 141, a second POL generating circuit 142, a third POL generating circuit 143, and first and second inverters 144 and 145. The first POL generation circuit 141 generates the first a polarity control signal POL1a whose polarity is inverted in units of two horizontal periods based on the line counter information Lcnt. The first inverter 144 inverts the first a polarity control signal POL1a to generate the first c polarity control signal POL1c. The second POL generating circuit 142 has a polarity inverted in units of two horizontal periods based on the line counter information Lcnt, and has a first b polarity control having a phase difference of approximately one horizontal period with respect to the first a polarity control signal POL1a. Generate signal POL1b. The second inverter 145 inverts the first b polarity control signal POL1b to generate the first d polarity control signal POL1d. The third POL generation circuit 143 generates the second polarity control signal POL1b whose polarity is inverted in units of one horizontal period based on the line counter information Lcnt. Each of the first to third POL generation circuits 141, 142, and 143 inverts the polarity of the polarity control signals POL1a to POL1d and POL2 at frame period periods in response to the frame counter information Fcnt.

The multiplexer 134 selects the polarity control signals POL1 and POL2 from the POL generation circuit 133 corresponding to each frame period as shown in Figs. 8A to 8E in response to the frame counter information Fcnt. The multiplexer 134 may output the reference polarity control signal POL in every frame period by a separate option pin selected by the set maker. The option pin is connected to the option control terminal of the multiplexer 134 and is selectively connected to the base voltage or the power supply voltage Vcc by an operator of the set maker to fix the output of the multiplexer 134 to the reference polarity control signal POL. .

15 is a flowchart for explaining a method of driving a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 15, in the driving method of the liquid crystal display according to the second exemplary embodiment of the present invention, input data is analyzed to determine whether the input data is data in which a DC residual image may appear, such as interlace data or scroll data. (S1, S2)

In operation S2, when it is determined that the current input data is data that may cause a DC residual image, the second embodiment of the present invention has a polarity in the period of two frame periods in the first liquid crystal cell group existing in the liquid crystal display panel for N frame periods. The inverted data voltage is supplied and the second liquid crystal cell group is supplied with the data voltage whose polarity is inverted in one frame period. (S3) Next, the second embodiment of the present invention provides an "irregular polarity pattern" during the 5i frame period. To control the polarity of the data voltage.
The data voltage is supplied to the first and second liquid crystal cell groups in the "non-regulated polarity pattern" of the polarity pattern different from the polarity pattern which determines the polarity of the data voltage during the above-mentioned N frame periods (S4). According to the second embodiment of the present invention, when the input data is determined to be data capable of generating a DC residual image such as interlaced data or scroll data, the data voltage driving frequency of the first liquid crystal cell group is converted into the data of the second liquid crystal cell group within two frame periods. Control lower than the voltage drive frequency.

In operation S2, when it is determined that the data currently input is data in which the DC residual image does not appear, the second embodiment of the present invention generates the reference polarity control signal POL in all frame periods, thereby generating data of the first and second liquid crystal cell groups. The voltage driving frequency is equally controlled (S5).

16 shows a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 16, the liquid crystal display according to the second exemplary embodiment of the present invention includes a system 105, a liquid crystal display panel 100, an image analysis circuit 161, a timing controller 101, and a POL logic circuit 162. , A data driving circuit 103, and a gate driving circuit 104. In this embodiment, the system 105, the liquid crystal display panel 100, the timing controller 101, the data driving circuit 103 and the gate driving circuit 104 are substantially the same as those of the first embodiment described above, and therefore the same reference numerals. And the detailed description thereof will be omitted.

The image analysis circuit 161 determines whether DC residual image generation is possible with respect to the digital video data of the currently input image. The image analysis circuit 161 compares data between neighboring lines in one frame image and determines the currently input data as interlace data when the data between the lines is larger than a preset threshold. In addition, the image analysis circuit 161 compares the data of each pixel on a frame-by-frame basis to detect a moving image in the display image and a moving speed of the image, and if the moving image moves at a predetermined speed, the moving image is moved. The included frame data is determined as scroll data. As a result of the image analysis, the image analysis circuit 161 generates the selection signal SEL2 indicating the interlace data and the scroll data, and controls the POL logic circuit 162 using the selection signal SEL2.

In response to the first logic value of the selection signal SEL2 from the image analysis circuit 161, the POL logic circuit 162 outputs the first polarity control signals POL1a to POL1d to the fourth i + 1 to th to FIG. 13. It occurs sequentially during the 4i + 4 frame periods, and sequentially generates the second polarity control signal POL2 during the 5i frame periods. When data other than interlace data and scroll data are input, the POL logic circuit 162 keeps the reference polarity control signal POL in all frame periods intact in response to the second logic value of the selection signal SEL2. 103).

The timing controller 101, the image analysis circuit 161, and the POL logic circuit 162 may be integrated in one chip.

As described above, the liquid crystal display device and the driving method thereof according to the present invention control the driving frequency of the data voltage supplied to the first liquid crystal cell group of the liquid crystal display panel to be low to prevent direct current afterimage and to be supplied to the second liquid crystal cell group. The display frequency can be improved by preventing the flicker by controlling the driving frequency of the data voltage high.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (22)

A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having first and second liquid crystal cell groups; A data driving circuit supplying the data voltages to the data lines in response to a polarity control signal; A gate driving circuit supplying the scan pulses to the gate lines; And The polarity control signal is generated differently in units of frame periods, and the polarity inversion periods of the polarity control signals are controlled differently in a plurality of frame period periods to control data voltage frequencies of the first and second liquid crystal cell groups differently within two frame periods. Equipped with a polarity control circuit, The polarity control signal, A first polarity control signal for inverting logic in two horizontal periods to invert the polarity of the data voltage in two horizontal line periods of the liquid crystal display panel; And And a second polarity control signal for inverting logic in one horizontal period, thereby inverting the polarity of the data voltage in one horizontal line period of the liquid crystal display panel. The method of claim 1, The polarity control circuit, And controlling the data voltage frequency to be supplied to the first liquid crystal cell group to be lower than the data voltage frequency to be supplied to the second liquid crystal cell group within two frame periods. The method of claim 2, And a data voltage frequency to be supplied to the first liquid crystal cell group within two frame periods is 1/2 of a frequency of the data voltage to be supplied to the second liquid crystal cell group. delete The method of claim 1, The first polarity control signal, A first a polarity control signal generated in a fourth i + 1 frame period except for a fifth i (i is an integer greater than or equal to 0) frame period; A first b polarity control signal generated in a fourth i + 2 frame period except the fifth i frame period and having a phase difference equal to one horizontal period with respect to the first a polarity control signal; A first c polarity control signal generated in a fourth i + 3 frame period except the fifth i frame period and generated out of phase with respect to the first a polarity control signal; And And a first polarity control signal generated in a fourth i + 4 frame period except the fifth i frame period and generated out of phase with respect to the first b polarity control signal. The method of claim 5, wherein The second polarity control signal, And a liquid crystal display during the fifth frame period. The method of claim 5, wherein The polarity control circuit, And the first polarity control signal and the second polarity control signal are sequentially output in frame period units. The method of claim 7, wherein The polarity control circuit, A frame counter for counting the gate start pulses to generate frame count information indicating the number of frames; A line counter for counting a source output enable signal to generate line count information indicating the number of display lines of the liquid crystal display panel; A polarity control signal generation circuit configured to generate the first to first polarity control signals and the second polarity control signal based on the frame count information and the line count information; And And a multiplexer for sequentially selecting the first to first polarity control signals and the second polarity control signal in response to the frame count information. The method of claim 8, The polarity control circuit, A first inverter configured to invert the first a polarity control signal to generate the first c polarity control signal and to supply the first c polarity control signal to the multiplexer; And And a second inverter configured to invert the first b polarity control signal to generate the first d polarity control signal and to supply the first d polarity control signal to the multiplexer. The method of claim 6, And an image analysis circuit for analyzing digital video data of an input image and controlling the output of the polarity control circuit according to the analysis result. The method of claim 10, The image analysis circuit, When the digital video data of the input image is analyzed and it is determined that the luminance difference of the data to be displayed on each of the adjacent horizontal lines in the liquid crystal display panel is equal to or greater than a preset threshold, the first to first polarity control signals in frame period units, and And controlling the polarity control circuit so that the second polarity control signal is sequentially output. The method of claim 10, The image analysis circuit, When the digital video data of the input image is compared in the frame period unit and it is determined that the image moving at a predetermined moving speed is included in the digital video data of the input image unit, the first to first polarity control signals in the frame period unit. And controlling the polarity control circuit to sequentially output the second polarity control signal. A polarity control signal is generated differently in units of frame periods so as to control different data voltage frequencies to be supplied to the first and second liquid crystal cell groups coexisting in the liquid crystal display panel within two frame periods, and the polarity of the polarity control signal in a plurality of frame periods. Controlling the reversal period differently; Supplying a data voltage to data lines of the liquid crystal display panel in response to the polarity control signal; And Supplying a scan pulse to gate lines of the liquid crystal display panel; The polarity control signal, A first polarity control signal for inverting logic in two horizontal periods to invert the polarity of the data voltage in two horizontal line periods of the liquid crystal display panel; And And a second polarity control signal for inverting logic in one horizontal period and inverting the polarity of the data voltage in one horizontal line period of the liquid crystal display panel. The method of claim 13, And a data voltage frequency to be supplied to the first liquid crystal cell group within two frame periods is lower than a frequency of the data voltage to be supplied to the second liquid crystal cell group. The method of claim 14, And a data voltage frequency to be supplied to the first liquid crystal cell group within two frame periods is 1/2 of a data voltage frequency to be supplied to the second liquid crystal cell group. delete The method of claim 13, The first polarity control signal, A first a polarity control signal generated in a fourth i + 1 frame period except for a fifth i (i is an integer greater than or equal to 0) frame period; A first b polarity control signal generated in a fourth i + 2 frame period except the fifth i frame period and having a phase difference equal to one horizontal period with respect to the first a polarity control signal; A first c polarity control signal generated in a fourth i + 3 frame period except the fifth i frame period and generated out of phase with respect to the first a polarity control signal; And And a first polarity control signal generated in a fourth i + 4 frame period except the fifth i frame period and generated out of phase with respect to the first b polarity control signal. The method of claim 17, The second polarity control signal, And a driving method generated in the fifth i frame period. The method of claim 18, Generating the polarity control signal differently in units of frame periods and differently controlling the polarity inversion periods of the polarity control signal in a plurality of frame period periods, And the first polarity control signal and the second polarity control signal are sequentially output in units of the frame period. The method of claim 18, And analyzing the digital video data of the input image and controlling the polarity control signal according to the analysis result. The method of claim 20, Controlling the polarity control signal, When the digital video data of the input image is analyzed and it is determined that the luminance difference of the data to be displayed on each of the adjacent horizontal lines in the liquid crystal display panel is equal to or greater than a preset threshold, the first to first polarity control signals in frame period units, and And a second polarity control signal is sequentially output. The method of claim 20, Controlling the polarity control signal, When the digital video data of the input image is compared in the frame period unit and it is determined that the image moving at a predetermined moving speed is included in the digital video data of the input image unit, the first to first polarity control signals in the frame period unit. And sequentially outputting the second polarity control signal.

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