TWI613633B - Driver and pixel unit for display device - Google Patents

Abstract

A display device including a data driver, a gate driver, and a plurality of Paint the prime column. The data driver is configured to output a plurality of display data groups, each of the display data groups includes a plurality of display data signals, each of the display data signals having different frequencies. The gate driver is used to output a plurality of gate driving signals. Each pixel column includes a plurality of pixel units, each of the pixel units is electrically coupled to the data driver and the gate driver, and the plurality of pixel units of the same pixel column receive the same gate driving signal, at least two The pixel array receives the same gate driving signal, and each pixel unit determines whether to receive one of the display data groups according to the received gate driving signal.

Description

Driver and pixel unit applied to display device

The present invention relates to a display device, and more particularly to a display device that can transmit display data to a pixel unit at different frequencies.

A conventional display device, such as a liquid crystal display device, includes a display panel having a plurality of columns of pixels. When the liquid crystal display device is to be displayed, the pixels are charged by display data column by column, so that the liquid crystal display device can be Display the data for display. However, in recent years, due to the improved resolution of the liquid crystal display device, more columns of pixels need to be driven in the display time of one frame, resulting in less time for pixel charging, and more columns of pixels are relatively increased. The load effect, and the pixel is also likely to be charged to the target voltage value within the time due to the influence of the load effect, and the display error is also caused.

In order to solve the above drawbacks, the present invention provides a driver and a pixel unit applied to a display device, the display device including a data driver, a gate driver, and a plurality of pixel columns. The data driver is configured to output a plurality of display data groups, each of the display data groups includes a plurality of display data signals, each of the display data signals having different frequencies. The gate driver is used to output a plurality of gate driving signals. Each pixel column includes a plurality of pixel units, each pixel unit is electrically coupled to the data driver and the gate driver, and the plurality of pixel units of the same pixel column receive the same The gate driving signal receives at least two pixels of the same gate driving signal, and each pixel unit determines whether to receive one of the display data groups according to the received gate driving signal.

In other embodiments, each pixel unit includes a band pass filtering unit, a rectifying unit, a first transistor, a second transistor, and a first capacitor. The band pass filtering unit is a display data signal for receiving the display data group and outputting one of the above. The rectifying unit is electrically coupled to the band pass filtering unit, and the rectifying unit is configured to receive the display data signal and output the rectified rectified display data signal. The first transistor has a first end, a control end and a second end. The first end of the first transistor is electrically coupled to the rectifying unit and configured to receive the rectified display data signal, and the control end of the first transistor receives one of the first transistors. Gate drive signal. The second transistor has a first end, a control end and a second end, the first end of the second transistor is electrically coupled to the second end of the first transistor, and the control end of the second transistor receives the other end The gate drive signal, the second end of the second transistor is for receiving a low voltage. The first capacitor has a first end and a second end. The first end of the first capacitor is electrically coupled to the second end of the first transistor, and the second end of the first capacitor receives the common voltage.

In summary, since the pixel unit of the present invention has a band pass filtering unit, the display data group can be filtered to obtain a specific display data signal, so the data driver can output a plurality of display data including a plurality of display data signals in a single output. In the signal group, different pixel units can receive corresponding display data signals at the same time, that is, the display device of the present invention can write multiple columns of pixels into the display data signal at the same time, thereby increasing the single pixel unit. The charging time allows each pixel unit to have enough time to charge, effectively improving the lack of display data errors due to insufficient charging time.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

100‧‧‧ display device

110‧‧‧Data Drive

120‧‧‧gate driver

130, 130-1, 130-N, 130-N+1, 130-M‧‧‧

140, 140-1, 140-2, 140-P-1, 140-P‧‧‧

150, 150a, 150b‧‧‧ pixel units

151‧‧‧Bandpass Filter Unit

152‧‧‧Rectifier unit

T1, T2, T3, T4, T5, T6, C _TFT , R _TFT ‧‧‧O crystal

C1‧‧‧first capacitor

C2‧‧‧second capacitor

C3‧‧‧ third capacitor

R‧‧‧impedance unit

R _L ‧‧‧resistive components

L‧‧‧Inductance unit

G, G _N , G _N-1 , G ₁ ‧‧ ‧ gate drive signal

VSS‧‧‧low voltage

VCOM‧‧‧Common voltage

D _g ‧‧‧Display data set

D _S , D _S1 , D _S2 , D _S3 ‧‧‧ Display data signals

D _RS , D _RS1 , D _RS2 ‧‧‧ rectified display data signal

dB‧‧‧frequency response value

F, f ₁ , f ₂ , f ₃ ‧‧‧ frequencies

1 is a schematic view of an embodiment of a display device of the present invention.

2A is a schematic view of an embodiment of a pixel unit of the present invention.

2B is a schematic diagram of an embodiment of displaying a data signal according to the present invention.

FIG. 3A is a schematic diagram of an embodiment of a pixel unit configuration of the present invention.

FIG. 3B is a schematic diagram of a signal timing embodiment of the present invention.

4A is a schematic diagram of an embodiment of a band pass filtering unit of the present invention.

4B is a schematic view of a first embodiment of an inductor unit according to the present invention.

4C is a schematic view of the second embodiment of the inductor unit of the present invention.

FIG. 5A is a schematic diagram of Embodiment 1 of a rectifying unit of the present invention.

FIG. 5B is a schematic diagram of Embodiment 2 of the rectifying unit of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an embodiment of a display device 100 according to the present invention. The display device 110 is, for example, a liquid crystal display device. The display device 100 includes a data driver 110, a gate driver 120, a plurality of pixel columns 130, and a plurality of pixel rows 140, such as the pixel columns 130-1~130-N and the pixel columns 130-N as shown in FIG. +1~130-M, where N is a positive integer greater than 1, M is a positive integer greater than N+1, and multiple pixel rows 140 are as shown in Figure 1 for pixel rows 140-1, 140-2~140- P-1 and 140-P, P is a positive integer greater than 1, wherein the plurality of pixel columns 130 and the plurality of pixel rows 140 are vertically aligned with each other. However, the present invention is not limited thereto, and the pixel units 150 may be arranged in other array shapes according to different requirements, such as the pixel rows 130 of two adjacent rows being misaligned with each other, or the pixel columns 130 and the pixel rows 140 are alternately arranged. And interlaced with each other to form an obtuse angle or an acute angle arrangement. In this embodiment, each pixel column 130 and each pixel row 140 respectively include a plurality of pixel units 150. In other words, the plurality of pixel units 150 may form a plurality of pixel columns 130 and a plurality of pixel rows 140. The data driver 110 is electrically coupled to the plurality of pixel units 150 through the plurality of data lines DL, wherein the data driver 110 is configured to output a plurality of display data sets D _g to the electrically coupled pixel units 150, each display The data group D _g includes a plurality of display data signals D _S , and each of the display data signals D _S is a sine wave signal having a different frequency, and the plurality of display data signals D _{S of the} same display data group D _g are orthogonal to each other. The gate driver 120 is electrically coupled to the plurality of pixel units 150 through the plurality of gate lines GL. The gate driver 120 is configured to output a plurality of gate driving signals G and a plurality of pictures of the same pixel array 130. The pixel unit 150 receives the same gate driving signal G, and at least two pixel rows 130 receive the same gate driving signal G. Further, in this example, the adjacent two columns of pixel columns 130 receive different gates. The driving signal G, wherein each pixel unit 150 determines whether to receive one of the display data groups D _g to display the data signal D _S according to the corresponding gate driving signal G.

Please refer to FIG. 2A. FIG. 2A is a schematic diagram of an embodiment of a pixel unit 150 of the present invention. The pixel unit 150 includes a band pass filtering unit 151, a rectifying unit 152, a transistor T1, a transistor T2, and a first capacitor C1. Band-pass filtering unit 151 is electrically coupled to the rectifying unit 152, the band pass filtering unit 151 to display the received data set D _g of the above-described band pass filtering unit 151 according to the setting information displayed on its band filter group D _g, The display data signal D _S whose signal frequency falls in the frequency band of the band pass filtering unit 151 will be output by the band pass filtering unit 151, wherein a plurality of pixels located in different pixel columns 130 but electrically coupled to the same data line DL The units 150 have different frequency bands from each other, so the plurality of pixel units 150 that receive the same display data set D _g and are located in different pixel columns 130 can filter out different display data signals D _S according to their frequency bands.

Please refer to FIG. 2B. FIG. 2B is a schematic diagram showing an embodiment of the data set D _g . The horizontal axis is the frequency F and the vertical axis is the frequency response value dB. As shown in FIG. 2B, a display data set D _g may include a display data signal D _{S1 of} different frequencies, a display data signal D _{S2 ,} and a display data signal D _S3 . The display data signal D _S1 has a frequency f ₁ and a display data signal D _{S2 .} With frequency f ₂ , the display data signal D _S3 has a frequency f ₃ . After the plurality of pixel units 150 of the same pixel row 140 receive the display data group D _g shown in FIG. 2B, the band pass filtering unit 151 of each pixel unit 150 can filter and receive the corresponding display according to its individual frequency bands. The data signal D _S , for example, the band pass filtering unit 151 can output the display data signal D _S1 according to the frequency band of the display data signal D _S2 and the display data signal D _S3 .

Referring to FIG. 2A again, in the embodiment of FIG. 2A, the rectifying unit 152 is configured to receive the display data signal D _S output by the band pass filtering unit 151, and the rectifying unit 152 rectifies the display data signal D _S and outputs the rectified display. The data signal D _RS , and the rectifying unit 152 is electrically coupled to the transistor T1. In detail, the rectifying unit 152 can convert the display data signal D _{S in the} form of a sine wave signal into a rectified display data signal D _{RS in the} form of a voltage signal, so as to facilitate the transmission of the voltage signal to the subsequent pixel circuit. The transistor T1 has a first end, a control end and a second end. The first end is electrically coupled to the rectifying unit 152 for receiving the rectified display data signal D _RS , and the control end receives the gate driving signal G. For example, the Nth gate driving signal G _N in the multi-level gate driving signal G in FIG. 1 is accepted. The transistor T2 has a first end, a control end and a second end, wherein the first end is electrically coupled to the second end of the transistor T1, and the control end of the transistor T2 receives the gate drive signal different from the transistor T1. For example, to receive the N-1th gate drive signal G _N-1 , the second end of the transistor T2 is used to receive the low voltage VSS, for example, the ground. The first capacitor C1 has a first end and a second end. The first end of the first capacitor C1 is electrically coupled to the second end of the transistor T1, and the second end of the first capacitor C1 receives a common voltage VCOM. The first capacitor C1 may be composed of a storage capacitor and a liquid crystal capacitor of the display device 100.

The operation method of the display device 100 of the present invention will be further described below with reference to FIG. 3A and FIG. 3B. FIG. 3A is the pixel row 140-1 of FIG. 1 and is disposed in the pixel column 130-N and the pixel column 130-M. The schematic diagram of the pixel unit 150a and the pixel unit 150b, and FIG. 3B is a schematic diagram of the signal timing embodiment of FIG. 3A. In addition, in this embodiment, the display data group D _g received by the pixel unit 150a and the pixel unit 150b includes the display data signal D _{S1 of} different frequencies and the display data signal D _S2 , but is not limited thereto. In the first time period T _{ime1 of} FIG. 3B, the N- _1th gate drive signal G _N-1 is an enable voltage level, and the Nth gate drive signal G _N is a disable voltage level. In the example, the enable voltage level is, for example, a logic high level, and the disable voltage level is, for example, a logic low level. During the first time period T _ime1 , the pixel unit 150a and the transistor T2 of the pixel unit 150b are turned on by the N- _1th gate driving signal G _{N-1 ,} and the first end of the transistor T2 is thus maintained at a low level. voltage VSS, the pixel unit 150a and a pixel unit transistor T1 150b because the first N-level gate drive signals G _N and closed. In the second time period _{Time2 of} FIG. 3B, the Nth gate driving signal G _N is an enable voltage level, and the N- _1th gate driving signal G _N-1 is a disable voltage level, and the pixel unit The transistor T1 of the 150a and the pixel unit 150b is turned on by the Nth gate driving signal G _N , and the pixel T2 of the pixel unit 150a and the pixel unit 150b is driven by the N-1th gate driving signal G _{N-1 .} And closed. _T ime2 second period, the pixel units 150a and 150b of pixel units by respective band pass filtering unit 151 to the display data set D _g filtering pixel unit 150a of the band-pass filtering unit 151 because of its frequency band and Setting and outputting only the corresponding display data signal D _S1 to the rectifying unit 152, the band pass filtering unit 151 of the pixel unit 150b outputs only the corresponding display data signal D _S2 to the rectifying unit 152 due to the setting of the frequency band thereof, the pixel unit The rectifying unit 152 of the 150a and the pixel unit 150b outputs the rectified display data signal D _RS1 and the rectified display data signal D _RS2 to the pixel unit 150a and the pixel unit 150b corresponding to the received display data signal D _S1 and the display data signal D _S2 . The transistor T1 is simultaneously turned on by the pixel unit 150a and the transistor T1 of the pixel unit 150b, so that the rectified display data signal D _RS1 and the rectified display data signal D _{RS2 are} simultaneously stored in the pixel unit 150a and the pixel unit 150b. The first capacitor C1 completes charging of the pixel unit 150a and the pixel unit 150b. Therefore, in this embodiment, since the two columns of pixel units 150 can be charged at the same time, in the case where the frame display time is the same, the number of times of charging in this embodiment is half of the column-by-column charging, so a single time The charging time can be significantly increased to twice the column-by-column charging.

Please refer to FIG. 4A. FIG. 4A is a schematic diagram of an embodiment of a band pass filtering unit 151 of a pixel unit 140. The band pass filtering unit 151 includes an impedance unit R, a second capacitor C2, and an inductance unit L. The impedance unit R has a first end and a second end. The first end of the impedance unit R is used to receive the display data set D _g output by the data driver 110. The impedance unit R can be implemented by a resistor or other impedance element. The second capacitor C2 has a first end and a second end. The first end of the second capacitor C2 is electrically coupled to the second end of the impedance unit R and the rectifying unit 152, and the second end of the second capacitor C2 receives the low voltage VSS. . The inductor unit L has a first end and a second end. The first end of the inductor unit L is electrically coupled to the second end of the impedance unit R and the rectifying unit 152, and the second end of the inductor unit L receives the low voltage VSS.

Please refer to FIG. 4B. FIG. 4B is a schematic diagram of Embodiment 1 of the inductor unit L of the pixel unit 150. The inductor unit L can include a third capacitor C3 and a resistive element R _L . The third capacitor C3 has a first end and a second end. The first end of the third capacitor C3 is electrically coupled to the second end of the impedance unit R. The resistive element R _L has a first end and a second end. The first end of the resistive element R _L is electrically coupled to the second end of the third capacitor C3, and the second end of the resistive element R _L is electrically connected to the low voltage VSS. Coupling. Please refer to FIG. 4C. FIG. 4C is a schematic diagram of Embodiment 2 of the inductor unit L of the pixel unit 150. The inductor unit L includes a transistor C _TFT and a transistor R _TFT . The transistor C _TFT has a first end, a control end, and a second end. The first end and the second end of the transistor C _TFT are electrically coupled to the rectifying unit 152. The control end of the transistor C _TFT is electrically coupled to the second end of the impedance unit R. The transistor R _TFT has a first end, a control end and a second end. The first end of the transistor R _TFT is electrically coupled to the first end and the second end of the transistor C _TFT , and the control end of the transistor R _TFT is The control terminal of the transistor T1 is electrically coupled, and the second terminal of the transistor R _TFT receives the low voltage VSS.

Please refer to FIG. 5A. FIG. 5A is a schematic diagram of a first embodiment of a rectifying unit 152 of a pixel unit 150. The rectifying unit 152 includes a transistor T3 having a first end, a control end and a second end, and the first end of the transistor T3. The second end of the transistor T3 is electrically coupled to the first end of the transistor T1. The second end of the transistor T3 is electrically coupled to the first end of the transistor T1. Please refer to FIG. 5B. FIG. 5B is a schematic diagram of Embodiment 2 of the rectifying unit 152 of the pixel unit 150. The rectifying unit 152 includes the foregoing transistor T3, and further includes a transistor T4, a transistor T5, and a transistor T6. The transistor T4 has a first end, a control end and a second end, and the first end of the transistor T4 and the first end of the transistor T3 One end is electrically coupled, and the control end of the transistor T4 is electrically coupled to the second end of the transistor T4 and receives the common voltage VCOM. The transistor T5 has a first end, a control end and a second end. The first end of the transistor T5 and the control end are electrically coupled to each other and receive a common voltage VCOM, and the second end of the transistor T5 receives the low voltage VSS. The transistor T6 has a first end, a control end and a second end. The first end of the transistor T6 is electrically coupled to the first end of the transistor T1, and the control end and the second end of the transistor T6 are electrically coupled to each other. And receive low voltage VSS.

In summary, since the pixel unit 150 of the present invention can filter the display data group D _g to obtain a specific display data signal D _S , the data driver 110 can output a plurality of display data signals D _S in a single output. Displaying the data signal group D _g , the different pixel units 150 can be driven at the same time and individually receive the corresponding display data signal D _S by the same display data signal group D _g , that is, the display device 100 of the present invention can be At the same time, the multi-column pixel unit 150 is simultaneously written into the display data signal D _S , so that the charging time of the single pixel unit 150 can be increased, so that each pixel unit 40 has sufficient time for charging, thereby effectively improving the charging time. Insufficient results in the display of data errors.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

100‧‧‧ display device

110‧‧‧Data Drive

120‧‧‧gate driver

130, 130-1, 130-N, 130-N+1, 130-M‧‧‧

140, 140-1, 140-2, 140-P-1, 140-P‧‧‧

150‧‧‧ pixel unit

DL‧‧‧ data line

GL‧‧‧ gate line

G, G ₁ , G _N ‧‧ ‧ gate drive signal

D _g ‧‧‧Display data set

Claims (9)

A driver and a pixel unit for a display device, comprising: a data driver for outputting a plurality of display data groups, each of the display data groups comprising a plurality of display data signals, each of the display data signals having different Frequency; a gate driver for outputting a plurality of gate driving signals; and a plurality of pixel columns, each of the pixel columns including a plurality of pixel units, each of the pixel units and the data driver and The gate driver is electrically coupled, and the pixel units of the same pixel array receive the same gate driving signal, and at least two of the pixel columns receive the same gate driving signal, and each pixel unit receives the same The gate drive signal and one of the frequencies determines whether one of the display data sets of the display data set is received. The driver and pixel unit of claim 1, wherein the display data signal is a sine wave signal. The driver and pixel unit of claim 1, wherein the display data signals of the same display data group are orthogonal to each other. The driver and pixel unit of claim 1, wherein each of the pixel units comprises: a band pass filtering unit, configured to receive the display data group and output one of the display data signals; a rectifying unit, and The band pass filter unit is electrically coupled to receive the display data signal and output a rectified display data signal; a first transistor having a first end, a control end and a second end, the first The first end of the transistor is electrically coupled to the rectifying unit for receiving the rectified display data signal, and the control end of the first transistor receives one of the gate driving signals; a second transistor having a first end, a control end and a second end, the first end of the second transistor being electrically coupled to the second end of the first transistor, the first The control terminal of the second transistor receives the other of the gate drive signals, the second end of the second transistor is configured to receive a low voltage, and the first capacitor has a first end and a second The first end of the first capacitor is electrically coupled to the second end of the first transistor, and the second end of the first capacitor receives a common voltage. The driver and pixel unit of claim 4, wherein the band pass filtering unit comprises: an impedance unit having a first end and a second end, the first end of the impedance unit is configured to receive the a data set; a second capacitor having a first end and a second end, the first end of the second capacitor being electrically coupled to the second end of the impedance unit and the rectifying unit, the first The second end of the second capacitor receives the low voltage; and an inductive unit having a first end and a second end, the first end of the inductive unit being electrically coupled to the second end of the impedance unit The second end of the inductive unit receives the low voltage. The driver and the pixel unit of claim 5, wherein the inductor unit comprises: a third capacitor having a first end and a second end, the first end of the third capacitor and the impedance unit The second end is electrically coupled to the second end of the third capacitor, and the first end of the resistive element is electrically coupled to the second end of the third capacitor, The second end of the resistive element is electrically coupled to the low voltage. The driver and pixel unit of claim 5, wherein the inductance unit comprises: a third transistor having a first end, a control end and a second end, the first end and the second end of the third transistor being electrically coupled to the rectifying unit, the third electric The control end of the crystal is electrically coupled to the second end of the impedance unit; and a fourth transistor having a first end, a control end, and a second end, the fourth end of the fourth transistor One end of the third transistor is electrically coupled to the first end and the second end of the third transistor, and the control end of the fourth transistor is electrically coupled to the control end of the first transistor, the fourth The second end of the transistor receives the low voltage. The driver and the pixel unit of claim 4, wherein the rectifying unit comprises a third transistor, the third transistor having a first end, a control end and a second end, the third transistor The first end is electrically coupled to the second end of the impedance unit and the control end of the third transistor, the second end of the third transistor and the first end of the first transistor Electrically coupled. The driver and the pixel unit of claim 4, wherein the rectifying unit comprises: a third transistor having a first end, a control end and a second end, the third transistor One end and the control end are electrically coupled to each other, the second end of the third transistor is electrically coupled to the first end of the first transistor; and a fourth transistor having a first end a first end of the fourth transistor is electrically coupled to the first end of the third transistor, the control end of the fourth transistor and the fourth The second ends of the crystals are electrically coupled to each other and receive the common voltage; a fifth transistor having a first end, a control end, and a second end, the first end of the fifth transistor and The control terminals are electrically coupled to each other and receive the common voltage, and the second end of the fifth transistor receives the low voltage; a sixth transistor having a first end, a control end, and a second end, the first end of the sixth transistor being electrically coupled to the first end of the first transistor, the first The control terminal of the six transistor and the second terminal are electrically coupled to each other and receive the low voltage.