CN107644604B - Display device - Google Patents

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CN107644604B
CN107644604B CN201610580827.3A CN201610580827A CN107644604B CN 107644604 B CN107644604 B CN 107644604B CN 201610580827 A CN201610580827 A CN 201610580827A CN 107644604 B CN107644604 B CN 107644604B
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stage
signal
shift register
potential
clock
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CN107644604A (en
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简廷宪
高宏成
林松君
詹建廷
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Hannstar Display Corp
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Hannstar Display Corp
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Abstract

The invention discloses a display device, which is provided with a display area and a peripheral area. There are a plurality of first gate lines and second gate lines arranged alternately in the display area. In the peripheral region, there are a plurality of first shift register circuits and a plurality of second shift register circuits. Each first shift register circuit is used for generating and providing a first scanning signal to a corresponding first gate line according to at least one clock signal, and each second shift register circuit is used for generating and providing a second scanning signal to a corresponding second gate line according to at least one clock signal. For the first shift register circuit and the second shift register circuit of the same stage, the high-potential duration of the first scan signal is the same as the high-potential duration of the second scan signal, and the difference between the first scan signal and the second scan signal is 1/4 clock cycles. The display device at least has the advantages of high resolution, narrow frame, high display quality, low manufacturing cost and the like.

Description

Display device
Technical Field
The present invention relates to a display device, and more particularly, to a display device driven by bilateral scanning.
Background
With the continuous progress of electronic technology, various portable electronic products, such as smart phones and GPS navigation devices, have been developed. These portable electronic products generally have a display device, and the image display of the display device needs to be controlled by a driving circuit, and the arrangement of the driving circuit leads to the increase of the size of the display device. How to design a display device with high display quality and being beneficial to the lightness and thinness of portable electronic products has been one of the targets addressed by the related technical personnel in the field.
Disclosure of Invention
The present invention is directed to a display device having at least advantages of high resolution, narrow frame, high display quality, and low manufacturing cost.
According to the above object of the present invention, a display device having a display area and a peripheral area and comprising a plurality of pixel units, N first gate lines and N second gate lines, a first driving circuit and a second driving circuit is provided. The pixel units are arranged in the display area and are arranged into a plurality of pixel columns and a plurality of pixel rows. The N first gate lines and the N second gate lines are alternately arranged in the display area, wherein the pixel rows (rows) are coupled to one of the first gate lines and one of the second gate lines. The first driving circuit is disposed in the peripheral region and includes 1 st to 4 th clock signal lines and 1 st to nth shift register circuits. The 1 st to 4 th clock signal lines are respectively used for providing 1 st to 4 th clock signals, and the first shift register circuits are respectively used for generating and providing 1 st to Nth first scanning signals to the first gate lines according to at least one clock signal in the 1 st to 4 th clock signals. The second driving circuit is disposed in the peripheral region and includes 5 th to 8 th clock signal lines and 1 st to N th second shift register circuits. The 5 th to 8 th clock signal lines are respectively used for providing 5 th to 8 th clock signals, and the second shift register circuits are respectively used for generating and providing 1 st to Nth second scanning signals to the second gate lines according to at least one clock signal in the 5 th to 8 th clock signals. The clock cycle lengths of the 1 st to 8 th clock signals are the same, and the (j +4) th clock signal of the 1 st to 8 th clock signals differs from the j th clock signal of the 1 st to 8 th clock signals by 1/4 clock cycles, the high potential duration of the i-th stage first scan signal of the first scan signals is the same as the high potential duration of the i-th stage second scan signal of the second scan signals, the i-th stage first scan signal of the first scan signals differs from the i-th stage second scan signal of the second scan signals by 1/4 clock cycles, where N is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 1 and less than or equal to 4, and i is any one positive integer selected from 1 to N.
According to an embodiment of the present invention, the display area is non-rectangular.
According to another embodiment of the present invention, the ith stage of the first shift register circuit or the ith stage of the second shift register circuit includes a precharge unit and an output unit. The pre-charging unit is coupled to the first node and is used for outputting a control signal from the first node. The output unit is used for receiving a control signal and outputting an ith-level first scanning signal in the first scanning signals or an ith-level second scanning signal in the second scanning signals through a second node.
According to another embodiment of the present invention, the control signal of the i-th stage first shift register circuit is changed from the first potential to the second potential at a 1 st time point, from the second potential to the third potential at a 3 rd time point, from the third potential to the fourth potential at a 5 th time point, and from the fourth potential to the first potential at a 7 th time point, wherein a potential value of the third potential is greater than a potential value of the second potential and a potential value of the fourth potential, and the potential values of the second potential and the fourth potential are both greater than the potential value of the first potential. The control signal of the i-th stage of the second shift register circuit is changed from the first potential to the second potential at the 2 nd time point, from the second potential to the third potential at the 4 th time point, from the third potential to the fourth potential at the 6 th time point, and from the fourth potential to the first potential at the 8 th time point. An (m +1) th time point of the 1 st to 8 th time points lags an m time point of the 1 st to 8 th time points by 1/4 clock cycles, m being any positive integer selected from 1, 3, 5 and 7.
According to still another embodiment of the present invention, a potential value of the above-mentioned second potential is equal to a potential value of the above-mentioned fourth potential.
According to another embodiment of the present invention, the i-th scan signal is switched from a low potential to a high potential at the 3 rd time point and from a high potential to a low potential at the 5 th time point, and the i-th scan signal is switched from a low potential to a high potential at the 4 th time point and from a high potential to a low potential at the 6 th time point.
According to another embodiment of the present invention, the time difference between the 5 th time point and the 7 th time point is at least 1/2 clock cycles, and the time difference between the 6 th time point and the 8 th time point is at least 1/2 clock cycles.
According to another embodiment of the present invention, the time difference between the 1 st time point and the 7 th time point is at least 3/2 clock cycles, and the time difference between the 2 nd time point and the 8 th time point is at least 3/2 clock cycles.
According to another embodiment of the present invention, the first driving circuit and the second driving circuit are respectively disposed at two opposite sides of the display area.
According to another embodiment of the present invention, each of the pixel units includes at least one thin film transistor, the first driving circuit and the second driving circuit include a plurality of thin film transistors, and the thin film transistors of the first driving circuit and the second driving circuit and the thin film transistors of the pixel units are commonly disposed on a substrate.
According to another embodiment of the present invention, the thin film transistors of the first driving circuit and the second driving circuit and the thin film transistor of the pixel unit are amorphous silicon thin film transistors.
According to another embodiment of the present invention, the high durations of the 1 st to 8 th clock signals in one clock cycle are 1/2 clock cycles, the (k +1) th clock signal among the 1 st to 4 th clock signals differs from the k-th clock signal by 1/2 clock cycles, and the (k +5) th clock signal among the 5 th to 8 th clock signals differs from the (k +4) th clock signal by 1/2 clock cycles, wherein k is a positive integer greater than or equal to 1 and less than or equal to 3.
According to another embodiment of the present invention, the high-potential durations of the i-th scan signal of the 1-th to N-th scan signals and the i-th scan signal of the 1-th to N-th scan signals are 1/2 clock cycles, respectively, and the high-potential period of the i-th scan signal overlap 1/4 clock cycles in time sequence.
According to another embodiment of the present invention, the pre-charge unit is configured to receive a first input signal and a second input signal, the output unit receives a fourth input signal, and the i-th stage of the first shift register circuit or the i-th stage of the second shift register circuit further includes a first pull-down unit and a second pull-down unit. The first pull-down unit is coupled to the first node and is used for receiving a third input signal. The second pull-down unit is coupled to the second node and configured to receive a fifth input signal. The fourth input signal and the fifth input signal of the i-th stage first shift register circuit are two of the 1 st to 4 th clock signals, respectively, and the third input signal is an (i +2) th stage first scan signal or a first reset signal among the first scan signals. The fourth input signal and the fifth input signal of the i-th stage second shift register circuit are two of the 5 th to 8 th clock signals, respectively, and the third input signal is an (i +2) th stage second scan signal or a second reset signal among the second scan signals.
According to yet another embodiment of the present invention, N is a positive integer less than or equal to N and is a multiple of 4. When i is (n-3), the fourth input signal of the i-th stage first shift register circuit is the 1 st clock signal, and the fourth input signal of the i-th stage second shift register circuit is the 5 th clock signal. When i is (n-2), the fourth input signal of the i-th stage first shift register circuit is the 2 nd clock signal, and the fourth input signal of the i-th stage second shift register circuit is the 6 th clock signal. When i is (n-1), the fourth input signal of the i-th stage first shift register circuit is the 3 rd clock signal, and the fourth input signal of the i-th stage second shift register circuit is the 7 th clock signal. When i is n, the fourth input signal of the i-th stage first shift register circuit is the 4 th clock signal, and the fourth input signal of the i-th stage second shift register circuit is the 8 th clock signal.
According to another embodiment of the present invention, when i is 1, the first input signal and the second input signal of the i-th stage first shift register circuit are both the first start signal, and the first input signal and the second input signal of the i-th stage second shift register circuit are both the second start signal. When i is 2, the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) -th stage first scan signal and a first start signal among the first scan signals, and the first input signal and the second input signal of the i-th stage second shift register circuit are respectively an (i-1) -th stage second scan signal and a second start signal among the second scan signals. When i is any positive integer from 3 to N, the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) th stage first scan signal and an (i-2) th stage first scan signal of the first scan signals, and the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) th stage second scan signal and an (i-2) th stage second scan signal of the second scan signals.
According to another embodiment of the present invention, the precharge unit includes a first transistor and a second transistor. The first terminal and the third terminal of the first transistor are used for receiving the first input signal. The first terminal and the third terminal of the second transistor are used for receiving the second input signal. The first pull-down unit includes a third transistor. The third terminal of the third transistor is used for receiving the third input signal, and the first terminal of the third transistor is coupled to the first node. The output unit includes a fourth transistor and a capacitor. The third terminal of the fourth transistor is coupled to the first node, the first terminal of the fourth transistor is configured to receive the fourth input signal, and the second terminal of the fourth transistor is coupled to the second node. The capacitor is coupled to the third terminal and the second terminal of the fourth transistor.
Compared with the prior art, the invention has the following beneficial effects: the display device of the invention at least has the advantages of high resolution, narrow frame, high display quality, low manufacturing cost and the like.
Drawings
For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention;
FIGS. 2A and 2B are schematic diagrams of a pixel cell in the display area of FIG. 1 according to some embodiments;
FIG. 3 is a schematic diagram illustrating the coupling relationship between the elements, gate lines and data lines in the pixel unit in the display area of FIG. 1;
FIG. 4 is a schematic diagram of a display device according to another embodiment of the present invention;
FIG. 5 is a diagram of a conventional display device having a non-rectangular display area;
FIG. 6 is a diagram of a first driving circuit and a second driving circuit according to an embodiment of the invention;
FIGS. 7A and 7B are block diagrams of shift register circuits according to some embodiments of the present invention;
FIGS. 8A and 8B are equivalent circuit diagrams of shift register circuits according to some embodiments of the present invention;
and
fig. 9A to 9C are timing diagrams of the first driving circuit and the second driving circuit of fig. 6 in one frame period.
Detailed Description
Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.
Fig. 1 is a schematic diagram of a display device 100 according to an embodiment of the invention. The display device 100 may be various types of liquid crystal display panels such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, an FFS (fringe-field switching) type, or a VA (vertical alignment) type, or an OLED (organic light emitting diode) display panel, but is not limited thereto. The display device 100 has a display area 110, and the display area 110 has a plurality of pixels, which are commonly used for displaying images. The source driver circuit 122 and the gate driver circuits 124A, 124B are located at opposite sides of the display region 110 (i.e., in the peripheral region 120). The source driving circuit 122 is used for converting the image data into a source driving signal and transmitting the source driving signal to the pixels in the display region 110. The gate driving circuits 124A and 124B are used for generating gate driving signals and transmitting the gate driving signals to the pixels in the display area 110. The pixels in the display region 110 are driven by the source driving signal and the gate driving signal to collectively display an image.
Fig. 2A is a schematic diagram of a pixel unit in the display area 110 of fig. 1. As shown in fig. 2A, a plurality of pixel units P (1,1) to P (M, N) are disposed in the display region 110, and the pixel units P are arranged in N pixel rows (row) R (1) to R (N) and M pixel columns (columns) C (1) to C (M). In addition, the display region 110 is also provided with a plurality of first gate lines GA (1) to GA (n), a plurality of second gate lines GB (1) to GB (n), and a plurality of data lines D (1) to D (l). The embodiment shown in fig. 2A adopts a dual gate design, that is, each of the pixel rows R (1) -R (n) is correspondingly coupled to one of the first gate lines GA (1) -GA (n) and one of the second gate lines GB (1) -GB (n), wherein two adjacent pixel units in the same pixel row are respectively coupled to the first gate line and the second gate line corresponding to the pixel row, and two adjacent pixel columns C (1) -C (m) are coupled to one of the data lines D (1) -D (l). As shown in fig. 2A, the pixel row r (i) is coupled to the first gate line ga (i) and the second gate line gb (i), the pixel columns C (j-1) and C (j) are coupled to the data line D (j/2), and the pixel units P (j-1, i) and P (j, i) in the pixel row r (i) are respectively coupled to the first gate line ga (i) and the second gate line gb (i), wherein i is a positive integer less than or equal to N, and j is an even number greater than or equal to 2 and less than or equal to M. In other embodiments, as shown in fig. 2B, the pixel units P (j-1, i) and P (j, i) in the pixel row r (i) are respectively coupled to the second gate line gb (i) and the first gate line ga (i).
Fig. 3 is a schematic diagram illustrating the coupling relationship between the elements in the pixel units P (1,1) -P (M, N) in the display area 110 and the first gate lines GA (1) -GA (N), the second gate lines GB (1) -GB (N), and the data lines D (1) -D (l), according to some embodiments of the present invention, which corresponds to the arrangement of the pixel units in fig. 2B. Each of the pixel units P (1,1) -P (M, N) includes a thin film transistor T and a pixel electrode PE coupled to the thin film transistor T, wherein a gate G of the thin film transistor T is coupled to one of the first gate lines GA (1) -GA (N) or one of the second gate lines GB (1) -GB (N), a source S of the thin film transistor T is coupled to one of the data lines D (1) -D (l), and a drain D of the thin film transistor T is coupled to the pixel electrode PE. As shown in fig. 3, if j is an odd number, the gate G and the source S of the tft T in the pixel unit P (j, i) are respectively coupled to the second gate line gb (i) and the data line D ((j + 1)/2); if j is an even number, the gate G and the source S of the tft T in the pixel unit P (j, i) are respectively coupled to the first gate line ga (i) and the data line D (j/2). Taking the pixel unit P (1, N) as an example, the gate G and the source S of the thin film transistor T in the pixel unit P (1, N) are respectively coupled to the second gate line gb (N) and the data line D (1). Similarly, in other embodiments corresponding to the pixel unit arrangement shown in fig. 2A, if j is an odd number, the gate G and the source S of the tft T in the pixel unit P (j, i) are respectively coupled to the first gate line ga (i) and the data line D ((j + 1)/2); if j is an even number, the gate G and the source S of the tft T in the pixel unit P (j, i) are respectively coupled to the second gate line gb (i) and the data line D (j/2).
Referring to fig. 4, fig. 4 is a schematic view of a display device 200 according to another embodiment of the invention. As shown in fig. 4, the display device 200 has a display region 210 and a peripheral region 220, wherein the display region 210 has a plurality of pixel units P, a source driving circuit 222 is located at a bottom side outside the display region 210 (i.e., located in the peripheral region 220), and gate driving circuits 224A and 224B are respectively located at left and right sides outside the display region 210 (i.e., located in the peripheral region 220). The pixel units P in the display region 210 are arranged in N rows of pixel columns and M columns of pixel rows, the gate lines GA (1) -GA (N) and GB (1) -GB (N) are electrically connected to the gate driving circuits 224A and 224B, respectively, and the data lines D (1) -D (L) are electrically connected to the source driving circuit 222, where L is equal to M/2. The difference between fig. 4 and fig. 1 is that the display area 110 of fig. 1 is rectangular, and the display area 210 of fig. 4 is non-rectangular (or referred to as a special shape). In the embodiment of FIG. 4, the shape of the display area 210 is circular, while in other embodiments, the shape of the non-rectangular display area may be oval, triangular, heart-shaped, or other irregular shapes, but the shape of the non-rectangular display area of the present invention is not limited thereto. The number of pixel units in each pixel row and each pixel column may be changed according to the shape of the display region 210. Similar to fig. 2A, fig. 2B and fig. 3, the pixel unit configuration of the embodiment of fig. 4 also adopts a dual gate design, and the related description thereof please refer to the description of fig. 2A, fig. 2B and fig. 3, which is not repeated herein.
It should be noted that the present invention is particularly advantageous for display devices that employ a dual gate design in non-rectangular display areas. Referring to fig. 4 and 5, fig. 5 is a schematic diagram of a conventional display device 300 having a non-rectangular display area. The display device 300 has a display region 310 and a peripheral region 320, wherein the display region 310 has a plurality of pixel units P, the source driving circuit 322 is located at a bottom side outside the display region 310 (i.e. located in the peripheral region 320), and the gate driving circuits 324A and 324B are respectively located at two opposite sides outside the display region 310 (i.e. located in the peripheral region 320). The pixel units P in the display region 310 are arranged in N rows of pixel columns and M columns of pixel rows, the gate lines GL (1) -GL (N) are electrically connected to the gate driving circuits 324A and 324B, and the data lines DL (1) -DL (M) are electrically connected to the source driving circuit 322. The difference between fig. 5 and fig. 4 is that the coupling manner of the pixel units, the gate lines and the data lines in fig. 5 is well known, each pixel column and each pixel row are respectively coupled to a gate line and a data line (for example, the first row of pixel units is coupled to the gate line GL (1), the second row of pixel units is coupled to the gate line GL (2) …, etc., and the first row of pixel units is coupled to the data line DL (1), the second row of pixel units is coupled to the data line DL (2) …, etc.), and fig. 4 adopts a dual-gate design, that is, adjacent pixel rows share a data line (for example, the first row of pixel units is coupled to the second row of pixel units and the data line D (1), the third row of pixel units is coupled to the fourth row of pixel units and the data line D (2) …, etc.), and each pixel column is coupled to two gate lines (for example, the first row of pixel units is coupled to the gate line GA, the second row of pixel cells are coupled to gate lines GA (2) and GB (2) …, etc.), so for display devices 200 and 300 having the same number of pixel cells, the same number of pixel rows, and the same number of pixel columns, the number of data lines in the embodiment of fig. 5 is twice as many as the number of data lines in the embodiment of fig. 4, and the number of gate lines in the embodiment of fig. 4 is twice as many as the number of gate lines in the embodiment of fig. 5. As shown in fig. 5, since the number of data lines in the embodiment of fig. 5 is twice as large as that in the embodiment of fig. 4, in order to extend the data lines DL (1) -DL (m) to the source driving circuit 322 and electrically connect the source driving circuit 322, the pitch (pitch) of the data lines DL (1) -DL (m) in the peripheral region 320 needs to be reduced so that the area of the frame (border) in fig. 5 is the same as that in the embodiment of fig. 4, i.e., the width (width) of the data lines in the peripheral region 320 and/or the pitch (spacing) of the adjacent data lines need to be reduced, which may cause the data lines DL (1) -DL (m) in the peripheral region 320 to be easily opened or shorted, thereby reducing the yield and reliability of the display device 300.
In addition, since the pitch of the data lines is related to the process and the capability of the machine and has a limit, when the resolution of the panel increases, the number of the data lines increases, the frame area needs to be increased to accommodate more data lines, or the data lines in the peripheral region 320 need to be processed by multiple layers of metal to reduce the pitch of the data lines, thereby resulting in that the requirement of a narrow frame cannot be achieved or the manufacturing cost increases. In contrast to the embodiment of fig. 4 of the present invention, the number of data lines in the embodiment of fig. 4 is only half of the number of data lines in the embodiment of fig. 5. Therefore, compared with the conventional display device with a non-rectangular display area, the display device with the narrow frame and the non-rectangular display area can be manufactured at lower cost.
Fig. 6 is a diagram of a first driving circuit 400A and a second driving circuit 400B according to an embodiment of the invention. The first driving circuit 400A and the second driving circuit 400B are suitable for the display device 100 of fig. 1, the display device 200 of fig. 4, or other similar display devices. The following description will be given taking the display device 100 used in fig. 1 as an example. The first driving circuit 400A and the second driving circuit 400B are the gate driving circuits 124A and 124B of fig. 1, respectively, wherein the first driving circuit 400A includes clock signal lines L1-L4, a start signal line SL1, a reset signal line RL1, and first shift register circuits 410A (1) -410A (N) from level 1 to level N, and the second driving circuit 400B includes clock signal lines L5-L8, a start signal line SL2, a reset signal line RL2, and second shift register circuits 410B (1) -410B (N) from level 1 to level N, where N is a positive integer greater than or equal to 6. In some embodiments, N is a complex multiple of 4.
The clock signal lines L1-L8 are used for providing clock signals C1-C8 to the corresponding first shift register circuits 410A (1) -410A (N) or second shift register circuits 410B (1) -410B (N). For example, for the first shift register circuits 410A (1) -410A (N), the clock signal lines L1 and L3 are coupled to the first shift register circuit 410A (1) at the 1 st stage, the clock signal lines L2 and L4 are coupled to the first shift register circuit 410A (2) at the 2 nd stage 410A (2) …, the clock signal lines L3 and L1 are coupled to the first shift register circuit 410A (N-1) at the (N-1) th stage, and the clock signal lines L4 and L2 are coupled to the first shift register circuit 410A (N) at the N th stage. Similarly, for the second shift register circuits 410B (1) -410B (N), the clock signal lines L5 and L7 are coupled to the second shift register circuit 410B (1) at stage 1, the clock signal lines L6 and L8 are coupled to the second shift register circuit 410B (2) at stage 2, the clock signal lines L7 and L5 are coupled to the second shift register circuit 410B (N-1) at stage (N-1), and the clock signal lines L8 and L6 are coupled to the second shift register circuit 410B (N) at stage N.
In addition, the start signal line SL1 provides the start signal STV1 to the 1 st, 2 nd, 4 th to N th stages of the first shift register circuits 410A (1), 410A (2), 410A (4) -410A (N), the start signal line SL2 provides the start signal STV2 to the 1 st, 2 nd, 4 th to N th stages of the second shift register circuits 410B (1), 410B (2), 410B (4) -410B (N), the reset signal line RL1 provides the reset signal RST1 to the (N-1) th, N th stages of the first shift register circuits 410A (N-1), 410A (N), and the reset signal line RL2 provides the reset signal 2 to the (N-RST) th, N th stages of the second shift register circuits 410B (N-1), 410B (N), (N).
The 1 st to nth stage first shift register circuits 410A (1) to 410A (N) are respectively configured to generate the 1 st to nth stage first scan signals SA (1) to SA (N) and output the 1 st to nth stage first scan signals SA (1) to SA (N) to the first gate lines GA (1) to GA (N), and the 1 st to nth stage second shift register circuits 410B (1) to 410B (N) are respectively configured to generate the 1 st to nth stage second scan signals SB (1) to SB (N) and output the 1 st to nth stage second scan signals SB (1) to SB (N) to the second gate lines GB (1) to GB (N). The 1 st stage first shift register circuit 410A (1) further outputs a 1 st stage first scan signal SA (1) to the 2 nd and 3 rd stage first shift register circuits 410A (2) and 410A (3), the 2 nd stage first shift register circuit 410A (2) further outputs a 2 nd stage first scan signal SA (2) to the 3 rd and 4 th stage first shift register circuits 410A (3) and 410A (4), the (N-1) th stage first shift register circuit 410A (N-1) further outputs a (N-1) th stage first scan signal SA (N-1) to a (N-3), a N-stage first shift register circuit 410A (N-3), 410A (N), the N-th stage first shift register circuit 410A (N) further outputs a N-th stage first scan signal SA (N) to the (N-2) th stage first shift register circuit 410A (N-2), the ith stage of the first shift register circuit 410A (i) also outputs the ith stage of the first scan signal sa (i) to the (i-2), (i +1), (i +2) stages of the first shift register circuits 410A (i-2), 410A (i +1), 410A (i +2), where i is a positive integer greater than or equal to 3 and less than or equal to (N-2). For example, the 3 rd stage first shift register circuit 410A (3) further outputs the 3 rd stage first scan signal SA (3) to the 1 st, 4 th, and 5 th stage first shift register circuits 410A (1), 410A (4), and 410A (5).
Similarly, the 1 st stage second shift register circuit 410B (1) further outputs the 1 st stage second scan signal SB (1) to the 2 nd and 3 rd stage second shift register circuits 410B (2) and 410B (3), the 2 nd stage second shift register circuit 410B (2) further outputs the 2 nd stage second scan signal SB (2) to the 3 rd and 4 th stage second shift register circuits 410B (3) and 410B (4), the (N-1) th stage second shift register circuit 410B (N-1) further outputs the (N-1) th stage second scan signal SB (N-1) to the (N-3) th stage second shift register circuits 410B (N-3) and 410B (N), the N th stage second shift register circuit 410B (N) further outputs the N th stage second scan signal SB (N) to the (N-2) th stage second shift register circuit 410B (N-2), the ith stage of the second shift register circuit 410B (i) also outputs the ith stage of the second scan signal sb (i) to the (i-2), (i +1), (i +2) stages of the second shift register circuits 410B (i-2), 410B (i +1), 410B (i +2), where i is a positive integer greater than or equal to 3 and less than or equal to (N-2).
FIG. 7A is a block diagram of a shift register circuit 500A according to some embodiments of the present invention. For example, the block diagram of the shift register circuit 500A can correspond to any one of the stages 1-3 of the first shift register circuits 410A (1) -410A (3) and the stages 1-3 of the second shift register circuits 410B (1) -410B (3) in FIG. 6. The shift register circuit 500A includes a precharge unit 510A, a first pull-down unit 520A, an output unit 530A, and a second pull-down unit 540A. The precharge unit 510A receives input signals IN 1-IN 2 and outputs a control signal CTRL from the node X1. The first pull-down unit 520A is coupled to the pre-charge unit 510A, and is used for receiving the input signal IN3 and pulling down the potential of the node X1. The output unit 530A is coupled to the precharge unit 510A, and receives the control signal CTRL and the input signal IN4, and outputs the scan signal OUT from the node X2. The second pull-down unit 540A is coupled to the first pull-down unit 520A and the output unit 530A, and is used for receiving the input signal IN5 and resetting the scan signal OUT.
Referring next to FIG. 7B, FIG. 7B is a block diagram illustrating a shift register circuit 500B according to some embodiments of the present invention. For example, the block diagram of the shift register circuit 500B can correspond to any one of the 4 th to N th stages of the first shift register circuits 410A (4) -410A (N) and the 4 th to N th stages of the second shift register circuits 410B (4) -410B (N) of FIG. 6. The shift register circuit 500B includes a precharge unit 510B, a first pull-down unit 520B, an output unit 530B, and a second pull-down unit 540B. The difference between the shift register circuit 500B of FIG. 7B and the shift register circuit 500A of FIG. 7A is that the first pull-down cell 520B of the shift register circuit 500B receives the input signal IN6 IN addition to the input signal IN 3. The rest of the circuit is similar to the shift register circuit 500A, and is not described herein again.
FIG. 8A is an equivalent circuit diagram of a shift register circuit 600A according to some embodiments of the present invention. The shift register circuit 600A is one embodiment of the shift register circuit 500A, and may be any one of the 1 st to 3 rd stages of first shift register circuits 410A (1) to 410A (3) and the 1 st to 3 rd stages of second shift register circuits 410B (1) to 410B (3). The shift register circuit 600A includes a pre-charge unit 610A, a first pull-down unit 620A, an output unit 630A, and a second pull-down unit 640A, which correspond to the pre-charge unit 510A, the first pull-down unit 520A, the output unit 530A, and the second pull-down unit 540A of the shift register circuit 500A, respectively.
The precharge unit 610A includes transistors T1, T2. The first terminal and the third terminal of the transistor T1 are coupled together and receive the input signal IN1, and the second terminal of the transistor T1 is coupled to the node X1. The third terminal and the first terminal of the transistor T2 receive the input signal IN2, and the second terminal of the transistor T2 is coupled to the node X1. In this specification, the first terminal and the second terminal of the transistor are respectively a drain and a source or respectively a source and a drain, which are determined according to voltages of the first terminal and the second terminal when the transistor operates, and the third terminal of the transistor is a gate of the transistor.
The first pull-down unit 620A includes a transistor T3. The third terminal of the transistor T3 receives the input signal IN3, the first terminal of the transistor T3 receives the reference potential Vss, and the second terminal of the transistor T3 is coupled to the node X1.
The output unit 630A includes a capacitance Cx and transistors T4, T5. The first and second terminals of the capacitor Cx are coupled to the node X1 and the node X2, respectively. The third terminal of the transistor T4 is coupled to the node X1, the first terminal of the transistor T4 receives the input signal IN4, and the second terminal of the transistor T4 is coupled to the node X2. The third terminal and the second terminal of the transistor T5 are coupled to the node X2, and the first terminal of the transistor T5 receives the input signal IN 4.
The second pull-down unit 640A includes a transistor T6. The third terminal of the transistor T3 receives the input signal IN5, the first terminal of the transistor T3 receives the reference potential Vss, and the second terminal of the transistor T3 is coupled to the node X2.
If the shift register circuit 600A is the 1 st stage first shift register circuit 410A (1), the input signals IN 1-IN 5 are the start signal STV1, the start signal STV1, the 3 rd stage first scan signal SA (3), the clock signal C1, and the clock signal C3, respectively. If the shift register circuit 600A is the 2 nd stage first shift register circuit 410A (2), the input signals IN 1-IN 5 are the 1 st stage first scan signal SA (1), the start signal STV1, the 4 th stage first scan signal SA (4), the clock signal C2, and the clock signal C4, respectively. If the shift register circuit 600A is the 3 rd stage first shift register circuit 410A (3), the input signals IN 1-IN 5 are the 2 nd stage first scan signal SA (2), the 1 st stage first scan signal SA (1), the 5 th stage first scan signal SA (5), the clock signal C3 and the clock signal C1, respectively.
Similarly, if the shift register circuit 600A is the second shift register circuit 410B (1) of the 1 st stage, the input signals IN 1-IN 5 are the start signal STV2, the start signal STV2, the second scan signal SB (3) of the 3 rd stage, the clock signal C5 and the clock signal C7, respectively. If the shift register circuit 600A is the second shift register circuit 410B (2) of the 2 nd stage, the input signals IN 1-IN 5 are the second scan signal SB (1) of the 1 st stage, the start signal STV2, the second scan signal SB (4) of the 4 th stage, the clock signal C6 and the clock signal C8, respectively. If the shift register circuit 600A is the 3 rd stage second shift register circuit 410B (3), the input signals IN 1-IN 5 are the 2 nd stage second scan signal SB (2), the 1 st stage second scan signal SB (1), the 5 th stage second scan signal SB (5), the clock signal C7 and the clock signal C5, respectively.
FIG. 8B is an equivalent circuit diagram of the shift register circuit 600B according to some embodiments of the present invention. The shift register circuit 600B is one embodiment of the shift register circuit 500B, and may be any one of the 4 th to N th stages of the first shift register circuits 410A (4) to 410A (N) and the 4 th to N th stages of the second shift register circuits 410B (4) to 410B (N). The shift register circuit 600B includes a pre-charge unit 610B, a first pull-down unit 620B, an output unit 630B, and a second pull-down unit 640B, which respectively correspond to the pre-charge unit 510B, the first pull-down unit 520B, the output unit 530B, and the second pull-down unit 540B of the shift register circuit 500B. The precharge unit 610B, the output unit 630B, and the second pull-down unit 640B are respectively the same as the precharge unit 610A, the output unit 630A, and the second pull-down unit 640A of fig. 8A, and thus are not described herein again.
The first pull-down unit 620A includes transistors T3, T7. The third terminal of the transistor T3 receives the input signal IN3, the first terminal of the transistor T3 receives the reference potential Vss, and the second terminal of the transistor T3 is coupled to the node X1. The third terminal of the transistor T7 receives the input signal IN6, the first terminal of the transistor T7 receives the reference potential Vss, and the second terminal of the transistor T7 is coupled to the node X1.
If the shift register circuit 600B is the ith stage first shift register circuit 410a (i) and i is a positive integer greater than or equal to 4 and less than or equal to (N-2), the input signals IN 1-IN 3, IN6 are the (i-1) th stage first scan signal SA (i-1), the (i-2) th stage first scan signal SA (i-2), the (i +2) th stage first scan signal SA (i +2), and the start signal STV1, respectively. For the 4 th to (N-2) th stage first shift register circuits 410A (4) to 410A (N-2), the input signal IN4 is the cycle order of the clock signals C4, C1, C2, C3, respectively (that is, for the 4 th to (N-2) th stage first shift register circuits 410A (4) to 410A (N-2), the input signal IN4 is C4, C1, C2, C3, C4, C1, C2, C3 …, respectively), and the input signal IN5 is the cycle order of the clock signals C2, C3, C4, C1, respectively. If the shift register circuit 600A is the (N-1) th stage first shift register circuit 410A (N-1), the input signals IN 1-IN 6 are the (N-2) th stage first scan signal SA (N-2), the (N-3) th stage first scan signal SA (N-3), the reset signal RST1, the clock signal C3, the clock signal C1, and the start signal STV1, respectively. If the shift register circuit 600A is the Nth stage first shift register circuit 410A (N), the input signals IN 1-IN 6 are the (N-1) th stage first scan signal SA (N-1), the (N-2) th stage first scan signal SA (N-2), the reset signal RST1, the clock signal C4, the clock signal C2 and the start signal STV1, respectively.
Similarly, if the shift register circuit 600B is the ith stage of the second shift register circuit 410B (i) and i is a positive integer greater than or equal to 4 and less than or equal to (N-2), the input signals IN 1-IN 3, IN6 are the (i-1) th stage of the second scan signal SB (i-1), the (i-2) th stage of the second scan signal SB (i-2), the (i +2) th stage of the second scan signal SB (i +2), and the start signal STV2, respectively. For the 4 th to (N-2) th stages of the second shift register circuits 410B (4) -410B (N-2), the input signal IN4 is a cyclic sequence of the clock signals C8, C5, C6, C7, respectively, and the input signal IN5 is a cyclic sequence of the clock signals C6, C7, C8, C5, respectively. If the shift register circuit 600A is the (N-1) th stage second shift register circuit 410B (N-1), the input signals IN 1-IN 6 are the (N-2) th stage second scan signal SB (N-2), the (N-3) th stage second scan signal SB (N-3), the reset signal RST2, the clock signal C7, the clock signal C5, and the start signal STV2, respectively. If the shift register circuit 600A is the Nth stage second shift register circuit 410B (N), the input signals IN 1-IN 6 are the (N-1) th stage second scan signal SB (N-1), the (N-2) th stage second scan signal SB (N-2), the reset signal RST2, the clock signal C8, the clock signal C6 and the start signal STV2, respectively.
In some embodiments, the display devices 100 and 200 of the present invention are System On Glass (SOG) display devices, that is, the gate driver circuits 124A and 124B (or the gate driver circuits 224A and 224B) are fabricated on a substrate (not shown) of the display device 100 (or the display device 200). Thus, the electronic components (e.g., the transistors T1-T7 and/or the capacitor Cx in fig. 8A and 8B) in the gate driver circuits 124A and 124B (or the gate driver circuits 224A and 224B) and the electronic components (e.g., the first gate lines GA (1) -GA (n), the second gate lines GB (1) -GB (n), the data lines D (1) -D (m), and/or the transistors T in the pixel units P) in the display area 110 (or the display area 210) can be fabricated by the same process.
In addition, the transistors T1 to T7 in fig. 8A and 8B are not limited to Low Temperature Polysilicon (LTPS) thin film transistors. For example, the transistors T1 to T7 in fig. 8A and 8B may be amorphous silicon (amorphous silicon) thin film transistors to reduce the production cost.
Fig. 9A to 9C are timing diagrams of the first driving circuit 400A and the second driving circuit 400B of fig. 6 in one frame period. In fig. 9A to 9C, the difference between each time point and the next time point is 1/4 clock cycles (hereinafter, denoted by H time) of the clock signals C1 to C8. As shown in FIG. 9A, the period of each of the clock signals C1-C8 is the same. In the present embodiment, the clock cycles of the clock signals C1-C8 are 4H times. The high and low durations are 1/2 clock cycles (i.e., 2H times, respectively) for each complete clock cycle. The clock signals C1-C4 sequentially shift backward for 2H times, the clock signals C5-C8 sequentially shift backward for 2H times, and the clock signal C5 lags the clock signal C1 by one H time (i.e., 1/4 clock cycles). The start signals STV1 and STV2 are respectively at the time point t0、t1Rise from low potential to high potential and respectively at time point t2、t3From a high potential to a low potential. The clock signals C1-C4 are sequentially at the time point t2、t4、t6、t8Goes high and the clock signals C5-C8 are sequentially at the time point t3、t5、t7、t9Raising to a high potential. Reset signals STV1 and STV2At a point in time t2N+4、t2N+5Rise from low potential to high potential and respectively at time point t2N+6、t2N+7From a high potential to a low potential.
At a point in time t0At this time, the control signal CTRL of the 1 st stage first shift register circuit 410A (1) and the control signal CTRL of the 2 nd stage first shift register circuit 410A (2) are raised from the first potential V1 to the second potential V2 under the influence of the start signal STV1 being raised to the high potential. In the present embodiment, the first potential V1 corresponds to the reference potential Vss in fig. 8A and 8B.
At a point in time t1At this time, the control signal CTRL of the 1 st stage of the second shift register circuit 410B (1) and the control signal CTRL of the 2 nd stage of the second shift register circuit 410B (2) are raised from the first potential V1 to the second potential V2 under the influence of the start signal STV2 being raised to the high potential.
At a point in time t2At this time, the control signal CTRL of the 1 st stage first shift register circuit 410A (1) is raised from the second potential V2 to the third potential V3 by the effect of the clock signal C1 rising to the high potential and the coupling effect of the capacitor Cx, and the 1 st stage first scan signal SA (1) output therefrom is raised from the low potential to the high potential. The control signal CTRL of the 2 nd stage first shift register circuit 410A (2) is maintained at the second potential V2. In addition, the control signal CTRL of the 3 rd stage first shift register circuit 410A (3) rises from the first potential V1 to the second potential V2 under the influence of the 1 st stage first scan signal SA (1) rising to the high potential.
At a point in time t3At this time, the control signal CTRL of the 1 st stage second shift register circuit 410B (1) is raised from the second potential V2 to the third potential V3 by the effect of the clock signal C5 rising to the high potential and the coupling effect of the capacitor Cx, and the output 1 st stage second scan signal SB (1) rises from the low potential to the high potential. The control signal CTRL of the second shift register circuit 410B (2) of stage 2 is maintained at the second potential V2. In addition, the control signal CTRL of the 3 rd stage second shift register circuit 410B (3) rises from the first potential V1 to the second potential V2 under the influence of the 1 st stage second scan signal SB (1) rising to the high potential.
At a point in time t4At this time, the control signal CTRL of the 1 st stage first shift register circuit 410A (1) is receivedThe clock signal C1 falls from the third potential V3 to the fourth potential V4 due to the effect of the falling to the low potential and the coupling effect of the capacitor Cx, and the output stage 1 first scan signal SA (1) falls from the high potential to the low potential. It should be noted that, in the present embodiment, the potential value of the fourth potential V4 is equal to the potential value of the second potential V2, but the present invention is not limited thereto, and in other embodiments, the potential value of the fourth potential V4 may be greater than the first potential V1 and not equal to the second potential V2. The control signal CTRL of the 2 nd stage first shift register circuit 410A (2) rises from the second potential V2 to the third potential V3 due to the rising of the clock signal C2 and the coupling effect of the capacitor Cx, and the output 2 nd stage first scan signal SA (2) rises from the low potential to the high potential. The control signal CTRL of the 3 rd stage first shift register circuit 410A (3) is maintained at the second potential V2. In addition, the control signal CTRL of the 4 th stage of the first shift register circuit 410A (4) rises from the first potential V1 to the second potential V2 under the influence of the 2 nd stage of the first scan signal SA (2) rising to the high potential.
At a point in time t5At this time, the control signal CTRL of the 1 st stage second shift register circuit 410B (1) is driven by the clock signal C5 to fall to the low level and the coupling effect of the capacitor Cx to fall from the third voltage V3 to the fourth voltage V4, and the output 1 st stage second scan signal SB (1) falls from the high voltage to the low voltage. The control signal CTRL of the second shift register circuit 410B (2) of the 2 nd stage rises from the second potential V2 to the third potential V3 due to the rising of the clock signal C6 and the coupling effect of the capacitor Cx, and the second scan signal SB (2) of the 2 nd stage output therefrom rises from the low potential to the high potential. The control signal CTRL of the 3 rd stage second shift register circuit 410B (3) is maintained at the second potential V2. In addition, the control signal CTRL of the 4 th stage of the second shift register circuit 410B (4) rises from the first potential V1 to the second potential V2 under the influence of the 2 nd stage of the second scan signal SB (2) rising to the high potential.
At a point in time t6At this time, the 1 st stage first scan signal SA (1) output from the 1 st stage first shift register circuit 410A (1) is reset by the clock signal C3 rising to the high level. The control signal CTRL of the 2 nd stage first shift register circuit 410A (2) is lowered by the clock signal C2The third potential V3 drops to the fourth potential V4 in response to the coupling of the capacitor Cx, and the output 2 nd stage first scan signal SA (2) drops from high to low. The control signal CTRL of the 3 rd stage first shift register circuit 410A (3) is raised from the second potential V2 to the third potential V3 by the effect of the clock signal C3 rising to the high potential and the coupling effect of the capacitor Cx, and the 3 rd stage first scan signal SA (3) output therefrom is raised from the low potential to the high potential. The control signal CTRL of the 4 th-stage first shift register circuit 410A (4) is maintained at the second potential V2. In addition, the control signal CTRL of the 1 st stage first shift register circuit 410A (1) is raised to the high level by the 3 rd stage first scan signal SA (3) and falls from the fourth level V4 to the first level V1.
At a point in time t7At this time, the 1 st stage second scan signal SB (1) output from the 1 st stage second shift register circuit 410B (1) is reset by the rising of the clock signal C7. The control signal CTRL of the second shift register circuit 410B (2) of the 2 nd stage is influenced by the clock signal C6 falling to the low level and the coupling effect of the capacitor Cx to fall from the third potential V3 to the fourth potential V4, and the second scan signal SB (2) of the 2 nd stage output therefrom falls from the high potential to the low potential. The control signal CTRL of the 3 rd stage second shift register circuit 410B (3) is raised from the second potential V2 to the third potential V3 by the effect of the clock signal C7 rising to the high potential and the coupling effect of the capacitor Cx, and the 3 rd stage second scan signal SB (3) output therefrom is raised from the low potential to the high potential. The control signal CTRL of the 4 th-stage second shift register circuit 410B (4) is maintained at the second potential V2. In addition, the control signal CTRL of the 1 st stage second shift register circuit 410B (1) is driven by the 3 rd stage second scan signal SB (3) rising to the high level to fall from the fourth level V4 to the first level V1.
At a point in time t8At this time, the 2 nd stage first scan signal SA (2) outputted from the 2 nd stage first shift register circuit 410A (2) is reset by the clock signal C4 rising to the high level. The control signal CTRL of the 3 rd stage first shift register circuit 410A (3) is driven by the clock signal C3 to fall to the low level and the coupling effect of the capacitor Cx to fall from the third voltage V3 to the fourth voltage V4, and the output 3 rd stage first scan signal SA (3) falls from the high voltage level to the low voltage level. Stage 4The control signal CTRL of the first shift register circuit 410A (4) rises from the second potential V2 to the third potential V3 due to the rising of the clock signal C4 and the coupling effect of the capacitor Cx, and the output 4 th-stage first scan signal SA (4) rises from the low potential to the high potential. The control signal CTRL of the 5 th stage first shift register circuit 410A (5) is maintained at the second potential V2. In addition, the control signal CTRL of the 2 nd stage first shift register circuit 410A (1) is raised to the high level by the 4 th stage first scan signal SA (4) and falls from the fourth level V4 to the first level V1.
At a point in time t9At this time, the 2 nd stage second scan signal SB (2) output from the 2 nd stage second shift register circuit 410B (2) is reset by the rising of the clock signal C8. The control signal CTRL of the second shift register circuit 410B (3) of the 3 rd stage is influenced by the clock signal C7 falling to the low level and the coupling effect of the capacitor Cx to fall from the third voltage V3 to the fourth voltage V4, and the second scan signal SB (3) of the 3 rd stage output therefrom falls from the high voltage to the low voltage. The control signal CTRL of the 4 th stage second shift register circuit 410B (4) is raised from the second potential V2 to the third potential V3 by the effect of the clock signal C8 rising to the high potential and the coupling effect of the capacitor Cx, and the 4 th stage second scan signal SB (4) output therefrom is raised from the low potential to the high potential. The control signal CTRL of the second shift register circuit 410B (5) of stage 5 is maintained at the second potential V2. In addition, the control signal CTRL of the second shift register circuit 410B (2) of the 2 nd stage is driven by the second scan signal SB (4) of the 4 th stage to rise to the first potential V1 from the fourth potential V4.
As shown in fig. 9A to 9C, the control signal CTRL of the i-th stage of the first shift register circuit 410A (i) is the control signal CTRL of the (i-1) th stage of the first shift register circuit 410A (i-1) waveform shifted backward for 2H times, and the first scan signal SA (i) of the i-th stage of the first shift register circuit 410A (i) is the first scan signal SA (i-1) of the (i-1) th stage of the first shift register circuit 410A (i-1) waveform shifted backward for 2H times, where i is a positive integer greater than or equal to 3 and less than or equal to (N-2).
Similarly, the control signal CTRL of the i-th stage of the second shift register circuit 410B (i) is obtained by shifting the waveform of the control signal CTRL of the (i-1) -th stage of the second shift register circuit 410B (i-1) backward by 2H times, and the second scan signal SB (i) of the i-th stage of the second shift register circuit 410B (i) is obtained by shifting the waveform of the first scan signal SB (i-1) of the (i-1) -th stage of the second shift register circuit 410B (i-1) backward by 2H times, where i is a positive integer greater than or equal to 3 and less than or equal to (N-2).
At a point in time t(2N-6)And the time point t(2N-4)At this time, the control signals CTRL of the (N-1) th stage of the first shift register circuit 410A (N-1) and the Nth stage of the first shift register circuit 410A (N) are respectively raised from the first voltage level V1 to the second voltage level V2. At a point in time t(2N-2)And the time point t(2N)At this time, the control signals CTRL of the (N-1) th stage of the first shift register circuit 410A (N-1) and the Nth stage of the first shift register circuit 410A (N) are respectively raised from the second voltage level V2 to the third voltage level V3. At a point in time t(2N)At this time, the control signal CTRL of the (N-1) -th stage of the first shift register circuit 410A (N-1) is decreased from the third voltage V3 to the fourth voltage V4.
Similarly, at the time point t(2N-5)And the time point t(2N-3)At this time, the control signals CTRL of the (N-1) th stage of the second shift register circuit 410B (N-1) and the Nth stage of the second shift register circuit 410B (N) are respectively raised from the first potential V1 to the second potential V2. At a point in time t(2N-1)And the time point t(2N+1)At this time, the control signals CTRL of the (N-1) th stage of the second shift register circuit 410B (N-1) and the Nth stage of the second shift register circuit 410B (N) are respectively raised from the second potential V2 to the third potential V3. At a point in time t(2N+1)At this time, the control signal CTRL of the (N-1) -th stage of the second shift register circuit 410B (N-1) is lowered from the third voltage V3 to the fourth voltage V4.
At a point in time t(2N+2)At this time, the control signal CTRL of the (N-1) -th stage of the first shift register circuit 410A (N-1) is maintained at the second voltage V2 because the reset signal RST1 is still at the low voltage level. The control signal CTRL of the nth stage of the first shift register circuit 410a (N) is driven by the clock signal C4 to fall to the low level and the coupling effect of the capacitor Cx to fall from the third voltage V3 to the fourth voltage V4, and the output nth stage of the first scan signal sa (N) falls from the high voltage to the low voltage.
At a point in time t(2N+3)Due to the reset signal RST2 is still at the low level, so the control signal CTRL of the (N-1) th stage of the second shift register circuit 410B (N-1) is maintained at the second voltage V2. The control signal CTRL of the nth stage of the second shift register circuit 410b (N) is driven by the clock signal C8 to fall to the low level and the coupling effect of the capacitor Cx to fall from the third voltage V3 to the fourth voltage V4, and the output nth stage of the second scan signal sb (N) falls from the high voltage to the low voltage.
At a point in time t(2N+4)At this time, the reset signal RST1 rises from the low level to the high level, so that the control signal CTRL of the (N-1) th stage of the first shift register circuit 410A (N-1) and the Nth stage of the first shift register circuit 410A (N) falls from the fourth level V4 to the first level V1.
At a point in time t(2N+5)At this time, the reset signal RST2 rises from the low level to the high level, so that the control signal CTRL of the (N-1) th stage of the second shift register circuit 410B (N-1) and the Nth stage of the second shift register circuit 410B (N) falls from the fourth level V4 to the first level V1.
As can be seen from the timing diagrams shown in fig. 9A to 9C, for the first shift register circuit 410A (1) of the 1 st stage and the second shift register circuit 410B (1) of the 1 st stage, the time point of the control signal CTRL rising from the first potential V1 to the second potential V2 is 1/2 clock cycles (i.e., 2H times) away from the time point of the control signal CTRL rising from the second potential V2 to the third potential V3, the time length of the control signal CTRL being maintained at the third potential V3 is 1/2 clock cycles (i.e., 2H times), and the time point of the control signal falling from the third potential V3 to the fourth potential V4 is 1/2 clock cycles (i.e., 2H times) away from the time point of the control signal falling from the fourth potential V4 to the first potential V1; for the (N-1) th stage first shift register circuit 410A (N-1) and the (N-1) th stage second shift register circuit 410B (N-1), the time point of the control signal CTRL rising from the first potential V1 to the second potential V2 is one clock cycle (i.e., 4H times) away from the time point of the control signal rising from the second potential V2 to the third potential V3, the time period of the control signal CTRL remaining at the third potential V3 is 1/2 clock cycles (i.e., 2H times), and the time point of the control signal falling from the third potential V3 to the fourth potential V4 is one clock cycle (i.e., 4H times) away from the time point of the control signal falling from the fourth potential V4 to the first potential V1; for the other first shift register circuits (e.g., 410A (2) -410A (N-2), 410A (N)), and second shift register circuits (e.g., 410B (2) -410B (N-2), 410B (N)), the time point at which the control signal CTRL rises from the first potential V1 to the second potential V2 is one clock cycle (i.e., 4H times) from the time point at which it rises from the second potential V2 to the third potential V3, the time length at which it is maintained at the third potential V3 is 1/2 clock cycles (i.e., 2H times), and the time point at which it falls from the third potential V3 to the fourth potential V4 is 1/2 clock cycles (i.e., 2H times) from the time point at which it falls from the fourth potential V4 to the first potential V1.
In addition, as shown in fig. 9C, although the high potential maintaining time of each of the first scan signals SA (1) to SA (n) and each of the second scan signals SB (1) to SB (n) is 2H times, the first half of the high potential maintaining time (1H time) of each of the first scan signals SA (1) to SA (n) and each of the second scan signals SB (1) to SB (n) is a precharge pixel unit, and the second half of the high potential maintaining time (1H time) is a data writing time of the pixel unit. For example, the high-level sustain time t of the first scanning signal SA (2)4～t6In, t5～t6The time interval (1H time) is the data writing time, and the high potential of the second scanning signal SB (2) is maintained for the time t5～t7In, t6～t7The time interval (1H time) is the data writing time.
As can be seen from the above description, the potential of the control signal CTRL is raised from the first potential V1 to the second potential V2 before each of the first scan signals SA (1) -SA (n) and each of the second scan signals SB (1) -SB (n) is raised from the low potential to the high potential, and is raised from the second potential V2 to the third potential V3 when the display area is scanned, instead of being directly raised from the first potential V1 to the third potential V3. In addition, when each of the first scan signals SA (1) -SA (n) and each of the second scan signals SB (1) -SB (n) decrease from high to low, the control signal CTRL decreases from the third voltage V3 to the fourth voltage V4, and then decreases from the fourth voltage V4 to the first voltage V1 after 1/2 clock cycles or 1 time period (i.e., 2H or 4H times), rather than directly decreasing from the third voltage V3 to the first voltage V1. Therefore, the operation time of the discharge circuits of the first shift register circuits 410A (1) -410A (n) and the second shift register circuits 410B (1) -410B (n) can be prolonged, so that the control signal CTRL is not easily interfered by other noise to cause the influence on the output waveforms of the first scan signals SA (1) -SA (n) and the second scan signals SB (1) -SB (n), thereby improving the display quality of the display device.
It should be noted that, although, for the first shift register circuit 410A (1) of the 1 st stage and the second shift register circuit 410B (1) of the 1 st stage, the time point of the control signal CTRL rising from the first voltage V1 to the second voltage V2 is 1/2 clock cycles (i.e. 2H times) from the time point of the control signal CTRL rising from the second voltage V2 to the third voltage V3, and the time point of the control signal CTRL rising from the first voltage V1 to the second voltage V2 of the first shift register circuit and the second shift register circuit of the other stages is 1 clock cycle (i.e. 4H times) from the time point of the control signal CTRL rising from the second voltage V4934 to the third voltage V3, those skilled in the art can adjust the first shift register circuit 410A (1) of the 1 st stage and the second shift register circuit 410B (1) of fig. 6, 8A, 8B, so that the time point of the control signal CTRL rising from the first voltage V5635 to the second voltage V2 is 1 to the second voltage V4625 The time points of the three potentials V3 are likewise 1 clock cycle apart (i.e. 4H times). For example, in addition to the start signals STV1 and STV2 provided by the start signal lines SL1 and SL2 in fig. 6, another start signal line SL1 ' and another start signal line SL2 ' may be additionally provided to provide start signals STV1 ' and STV2 ', respectively, wherein the high-potential maintaining time of the start signal STV1 ' is 2H times as the start signal STV1, but the time for the start signal STV1 ' to rise from the low potential to the high potential is 2H times earlier than the time for the start signal STV1 to rise from the low potential to the high potential, that is, the start signal STV1 ' shifts the waveform of the start signal STV1 by 2H times. Similarly, the high-potential hold time of the start signal STV2 'is 2H times as with the start signal STV2, but the time for the start signal STV 2' to rise from the low potential to the high potential is 2H times earlier than the start signal STV 2. Therefore, the input signal IN2 of the first shift register circuit 410A (1) of the 1 st stage is changed from the start signal STV1 to the start signal STV1 ', and the input signal IN2 of the second shift register circuit 410B (1) of the 1 st stage is changed from the start signal STV2 to the start signal STV 2', so that the time point when the control signal CTRL of the first shift register circuit 410A (1) of the 1 st stage and the second shift register circuit 410B (1) of the 1 st stage rises from the first potential V1 to the second potential V2 and the time point when the control signal CTRL rises from the second potential V2 to the third potential V3 of the other stages are also separated from each other by 1 clock cycle (i.e., 4H times).
Similarly, although the time point of the control signal CTRL from the third potential V3 to the fourth potential V4 is one clock cycle (i.e., 4H times) away from the time point of the control signal CTRL from the fourth potential V4 to the first potential V1, and the time point of the control signal CTRL from the third potential V3 to the fourth potential V4 is 1/2 clock cycles (i.e., 2H times) away from the time point of the control signal CTRL from the fourth potential V4 to the first potential V1 for the (N-1) th stage first shift register circuit 410A (N-1) and the (N-1) th shift register circuit 410B (N-1) in FIGS. 6, 8A, 8B for the (N-1) th stage first shift register circuit 410A (N-1) and the (N-1) th stage second shift register circuit 410B (N-1), so that the time point when the control signal CTRL thereof falls from the third potential V3 to the fourth potential V4 is 1/2 clock cycles (i.e., 2H time) away from the time point when the control signal CTRL thereof falls from the fourth potential V4 to the first potential V1. For example, in addition to the reset signals RST1 and RST2 provided by the reset signal lines RL1 and RL2 in fig. 6, another reset signal line RL1 'and another reset signal line RL 2' may be additionally provided to provide reset signals RST1 'and RST 2', respectively, wherein the high-hold time of the reset signal RST1 'is 2H times as the reset signal RST1, but the time of the reset signal RST 1' rising from low to high is 2H times earlier than the time of the reset signal STV1, i.e., at the time point t(2N+2)The reset signal RST 1' rises from low to high and is at time t(2N+4)The reset signal RST 1' goes from high to low. Similarly, the high-hold time of the reset signal RST2 'is 2H times as the reset signal RST2, but the reset signal RST 2' is earlier than the high-hold time RST2 by 2H times,i.e. at the point of time t(2N+3)The reset signal RST 1' rises from low to high and is at time t(2N+5)The reset signal RST 1' goes from high to low. Therefore, the input signal IN3 of the (N-1) -th stage first shift register circuit 410A (N-1) is changed from the reset signal RST1 to the reset signal RST1 ', and the input signal IN3 of the (N-1) -th stage second shift register circuit 410B (1) is changed from the reset signal RST2 to the reset signal RST 2', so that the time point of the control signal CTRL of the (N-1) -th stage first shift register circuit 410A (N-1) and the (N-1) -th stage second shift register circuit 410B (N-1) decreases from the third potential V3 to the fourth potential V4 and the time point of the control signal CTRL decreases from the fourth potential V4 to the first potential V1 are 1/2 clock cycles (i.e., 2H times) as the other stages of the first shift register circuit and the second shift register circuit.
Although the present invention has been described with reference to the above embodiments, it should be understood that the scope of the present invention is not limited to the above embodiments, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention.

Claims (16)

1. A display device having a display area and a peripheral area, the display device comprising:
the pixel units are arranged in the display area and are arranged into a plurality of pixel columns and a plurality of pixel rows;
n first gate lines and N second gate lines alternately arranged in the display area, wherein each pixel row is coupled to one of the N first gate lines and one of the N second gate lines;
a first driving circuit disposed in the peripheral region, the first driving circuit including 1 st to 4 th clock signal lines and 1 st to nth shift register circuits, the 1 st to 4 th clock signal lines being respectively configured to provide 1 st to 4 th clock signals, the 1 st to nth shift register circuits being respectively configured to generate and provide 1 st to nth scan signals to the first gate line according to at least one of the 1 st to 4 th clock signals, a control signal of an i-th shift register circuit of the 1 st to nth shift register circuits being changed from a first potential to a second potential at a 1 st time point, from the second potential to a third potential at a 3 rd time point, from the third potential to a fourth potential at a 5 th time point, and from the fourth potential to the first potential at a 7 th time point, wherein the third potential is greater than the second potential and the fourth potential, and the second potential and the fourth potential are greater than the first potential;
a second driving circuit disposed in the peripheral region, the second driving circuit including 5 th to 8 th clock signal lines and 1 st to nth second shift register circuits, the 5 th to 8 th clock signal lines being respectively configured to provide 5 th to 8 th clock signals, the 1 st to nth second shift register circuits being respectively configured to generate and provide 1 st to nth second scan signals to the second gate line according to at least one of the 5 th to 8 th clock signals, a control signal of an i-th second shift register circuit of the 1 st to nth second shift register circuits being changed from the first potential to the second potential at a 2 nd time point, from the second potential to the third potential at a 4 th time point, and from the third potential to the fourth potential at a 6 th time point, and transitioning from the fourth potential to the first potential at time 8;
wherein the clock cycle lengths of the 1 st to 8 th clock signals are the same, and a (j +4) th clock signal of the 1 st to 8 th clock signals is different from a j th clock signal of the 1 st to 8 th clock signals by 1/4 clock cycles, a high potential duration of an i-th stage first scan signal of the 1 st to N-th stage first scan signals is the same as a high potential duration of an i-th stage second scan signal of the 1 st to N-th stage second scan signals, the i-th stage first scan signal is different from the i-th stage second scan signal by 1/4 clock cycles, where N is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 1 and less than or equal to 4, and i is any one positive integer selected from 1 to N, a (m +1) th time point of the 1 st to 8 th time points lags by 1/4 th time point of one of the 1 st to 8 th time points A clock period, m is any positive integer selected from 1, 3, 5 and 7.
2. The display device of claim 1, wherein the display area is non-rectangular in shape.
3. The display device according to claim 1, wherein the i-th stage first shift register circuit or the i-th stage second shift register circuit includes:
a precharge unit coupled to a first node, for outputting a control signal of the ith-stage first shift register circuit or a control signal of the ith-stage second shift register circuit from the first node;
an output unit for receiving a control signal of the ith stage first shift register circuit and outputting the ith stage first scan signal from a second node; or the control signal of the ith-stage second shift register circuit is received, and the ith-stage second scanning signal is output by a second node.
4. The display device according to claim 1, wherein a potential value of the second potential is equal to a potential value of the fourth potential.
5. The display apparatus as claimed in claim 1, wherein the i-th scan signal is changed from a low potential to a high potential at the 3 rd time point and from a high potential to a low potential at the 5 th time point, and the i-th scan signal is changed from a low potential to a high potential at the 4 th time point and from a high potential to a low potential at the 6 th time point.
6. The display device of claim 1, wherein the time difference between the 5 th time point and the 7 th time point is at least 1/2 clock cycles, and the time difference between the 6 th time point and the 8 th time point is at least 1/2 clock cycles.
7. The display device of claim 1, wherein the time difference between the 1 st time point and the 7 th time point is at least 3/2 clock cycles, and the time difference between the 2 nd time point and the 8 th time point is at least 3/2 clock cycles.
8. The display device according to claim 1, wherein the first driver circuit and the second driver circuit are respectively disposed on opposite sides of the display area.
9. The display device according to claim 1, wherein each of the pixel units comprises at least one thin film transistor, the first driving circuit and the second driving circuit respectively comprise a plurality of thin film transistors, and the thin film transistors of the first driving circuit and the second driving circuit and the thin film transistors of the pixel units are commonly disposed on a substrate.
10. The display device according to claim 9, wherein the thin film transistors of the first driver circuit and the second driver circuit and the thin film transistor of the pixel unit are amorphous silicon thin film transistors.
11. The display device according to claim 1, wherein the high potential durations of the 1 st to 8 th clock signals in one clock cycle are 1/2 clock cycles, respectively, a (k +1) th clock signal among the 1 st to 4 th clock signals is different from a k-th clock signal by 1/2 clock cycles, and a (k +5) th clock signal among the 5 th to 8 th clock signals is different from the (k +4) th clock signal by 1/2 clock cycles, wherein k is a positive integer greater than or equal to 1 and less than or equal to 3.
12. The display device according to claim 1, wherein the high-potential durations of the i-th stage first scan signal and the i-th stage second scan signal are 1/2 clock cycles, respectively, and the high-potential period of the i-th stage first scan signal and the high-potential period of the i-th stage second scan signal overlap in timing by 1/4 clock cycles.
13. A display device having a display area and a peripheral area, the display device comprising:
the pixel units are arranged in the display area and are arranged into a plurality of pixel columns and a plurality of pixel rows;
n first gate lines and N second gate lines alternately arranged in the display area, wherein each pixel row is coupled to one of the N first gate lines and one of the N second gate lines;
a first driving circuit disposed in the peripheral region, the first driving circuit including 1 st to 4 th clock signal lines and 1 st to nth shift register circuits, the 1 st to 4 th clock signal lines being respectively configured to provide 1 st to 4 th clock signals, the 1 st to nth shift register circuits being respectively configured to generate and provide 1 st to nth first scan signals to the first gate lines according to at least one of the 1 st to 4 th clock signals;
a second driving circuit disposed in the peripheral region, the second driving circuit including 5 th to 8 th clock signal lines and 1 st to nth second shift register circuits, the 5 th to 8 th clock signal lines being respectively configured to provide 5 th to 8 th clock signals, the 1 st to nth second shift register circuits being respectively configured to generate and provide 1 st to nth second scan signals to the second gate lines according to at least one of the 5 th to 8 th clock signals;
wherein the clock cycle lengths of the 1 st to 8 th clock signals are the same, and a (j +4) th clock signal of the 1 st to 8 th clock signals is different from a j th clock signal of the 1 st to 8 th clock signals by 1/4 clock cycles, a high potential duration of an i-th stage first scan signal of the 1 st to N-th stage first scan signals is the same as a high potential duration of an i-th stage second scan signal of the 1 st to N-th stage second scan signals, the i-th stage first scan signal is different from the i-th stage second scan signal by 1/4 clock cycles, where N is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 1 and less than or equal to 4, and i is any one positive integer selected from 1 to N;
an ith stage first shift register circuit of the 1 st to nth stage first shift register circuits or an ith stage second shift register circuit of the 1 st to nth stage second shift register circuits includes:
a precharge unit coupled to a first node, for receiving a first input signal and a second input signal and outputting a control signal from the first node;
a first pull-down unit coupled to the first node and configured to receive a third input signal;
an output unit for receiving a fourth input signal and the control signal, and outputting the ith-level first scan signal or the ith-level second scan signal from a second node; and
a second pull-down unit coupled to the second node and configured to receive a fifth input signal;
wherein the fourth input signal and the fifth input signal of the i-th stage first shift register circuit are two of the 1 st to 4 th clock signals, respectively, and the third input signal is an (i +2) th stage first scan signal or a first reset signal among the 1 st to N-th stage first scan signals;
the fourth input signal and the fifth input signal of the ith-stage second shift register circuit are two of the 5 th to 8 th clock signals, respectively, and the third input signal is an (i +2) th-stage second scan signal or a second reset signal among the 1 st-nth-stage second scan signals.
14. The display device according to claim 13, wherein when i is (n-3), the fourth input signal of the first shift register circuit of the i-th stage is the 1 st clock signal, and the fourth input signal of the second shift register circuit of the i-th stage is the 5 th clock signal;
when i is (n-2), a fourth input signal of the ith-stage first shift register circuit is the 2 nd clock signal, and a fourth input signal of the ith-stage second shift register circuit is the 6 th clock signal;
when i is (n-1), a fourth input signal of the i-th stage first shift register circuit is the 3 rd clock signal, and a fourth input signal of the i-th stage second shift register circuit is the 7 th clock signal;
when i is n, a fourth input signal of the i-th stage first shift register circuit is the 4 th clock signal, and a fourth input signal of the i-th stage second shift register circuit is the 8 th clock signal;
wherein N is a positive integer less than or equal to N and is a multiple of 4.
15. The display device according to claim 13, wherein when i is 1, the first input signal and the second input signal of the first shift register circuit of the i-th stage are both first start signals, and the first input signal and the second input signal of the second shift register circuit of the i-th stage are both second start signals;
when i is 2, the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) -th stage first scan signal and the first start signal in the 1-th to N-th stage first scan signals, and the first input signal and the second input signal of the i-th stage second shift register circuit are respectively an (i-1) -th stage second scan signal and the second start signal in the 1-th to N-th stage second scan signals; and
when i is any positive integer from 3 to N, the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) th stage first scan signal and an (i-2) th stage first scan signal in the 1 st stage to the N-th stage first scan signals, and the first input signal and the second input signal of the i-th stage first shift register circuit are respectively an (i-1) th stage second scan signal and an (i-2) th stage second scan signal in the 1 st stage to the N-th stage second scan signals.
16. The display device according to claim 13, wherein the precharge unit includes a first transistor and a second transistor, the first terminal and the third terminal of the first transistor are used for receiving the first input signal, the first terminal and the third terminal of the second transistor are used for receiving the second input signal, the first pull-down unit comprises a third transistor, a third terminal of the third transistor is used for receiving the third input signal, a second terminal of the third transistor is coupled to the first node, the output unit includes a fourth transistor and a capacitor, a third terminal of the fourth transistor is coupled to the first node, a first terminal of the fourth transistor is configured to receive the fourth input signal, the second terminal of the fourth transistor is coupled to the second node, and the capacitor is coupled to a third terminal and a second terminal of the fourth transistor.
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