CN103943075A - Gate driving circuit and gate line driving method for display panel - Google Patents
Gate driving circuit and gate line driving method for display panel Download PDFInfo
- Publication number
- CN103943075A CN103943075A CN201310025023.3A CN201310025023A CN103943075A CN 103943075 A CN103943075 A CN 103943075A CN 201310025023 A CN201310025023 A CN 201310025023A CN 103943075 A CN103943075 A CN 103943075A
- Authority
- CN
- China
- Prior art keywords
- drive pattern
- scanning sequency
- those
- gate
- kenel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a gate driving circuit and a gate line driving method for a display panel. The gate driving circuit comprises a plurality of gate driving stages; the gate driving stages are integrated on the display panel and used for receiving a plurality of clock rate signals and initial signals; a plurality of scanning signals are generated according to the clock rate signals after the gate driving stages are started by the initial signals; according to the clock rate signals, the scanning signals drive a plurality of gate lines on the display panel respectively in a plurality of scanning sequences in the different frame periods; and at least two scanning sequences are different during the scanning sequences.
Description
Technical field
The invention relates to the gate line driving method of a kind of gate driver circuit and display panel.
Background technology
The display mode of liquid crystal display is to control by a gate drivers and one source pole driver.According to different designs, gate drivers mainly can divide into two kinds multi-form, comprise the capable driving of the array base palte being incorporated on display panel (Gate Driver on Array, GOA) form, and the form that is arranged on the outer grid drive chip (Gate Driver IC) of being made by external silicon of display panel.Utilize the capable Driving technique of array base palte, display panel is without external grid drive chip.Sequential control circuit if transmit required clock signal and voltage quasi position to the gate drivers on display panel, just can produce sweep signal and drive display panel.Fig. 1 illustrates traditional gate drivers in order to the signal schematic representation of driving grid line.
Refer to Fig. 1, gate drivers is used shift register (shift register) to control the opening sequence of grid output, it is by a start signal (start pulse, STV) after starting shift register, grid output channel can sequentially be carried out the action of Push And Release along with clock signal (CLK) to gate line, with sweep signal GO[1], GO[2], GO[3], GO[4] ... represent.When sweep signal is opened the pixel of connection, image document can be inputted by the source electrode of pixel.
In order to reduce liquid crystal display cost, with existing technology, the dot structure of liquid crystal display changes from bigrid (dual gate) structure.Double-grid structure is to utilize same source electrode output in operation, at a horizontal line, in the time, respectively odd number two pixels adjacent with even number are driven, the number of gates that so can save the source electrode number of half but must double, the liquid crystal display that is greater than number of gates for conventional source number of poles order can reach the effect reducing costs.
Yet, prior art is passed to the clock signal that is incorporated into the gate drivers on display panel and fixes during each frame (frame), therefore can only produce the sweep signal on suitable rank as shown in Figure 1, lack flexibility, have no idea to utilize identical circuit layout to produce the sweep signal of different scanning order, thereby also cannot solve the display brightness producing inhomogeneous (mura) defect on some special pixel layout.
Summary of the invention
The invention provides a kind of gate driver circuit being incorporated on display panel, two or more non-sweep signals of arranging along rank can be provided.
The invention provides a kind of gate line driving method of display panel, the method can provide two or more non-sweep signals of arranging along rank to drive display panel.
The invention provides a kind of gate driver circuit, comprise a plurality of gate drive stages.Described gate drive stage is to be integrated on display panel, in order to receive a plurality of clock signals and start signal.Gate drive stage produces a plurality of sweep signals according to clock signal after being started by start signal.According to clock signal, described sweep signal is driving a plurality of gate lines on display panel with a plurality of scanning sequencies respectively during different frame.At least two scanning sequency differences in described scanning sequency.
In an embodiment of the present invention, above-mentioned sweep signal is at least driving the gate line on display panel with the first scanning sequency and the second scanning sequency during different frame.The first scanning sequency is not identical with the second scanning sequency.
In an embodiment of the present invention, based on the first scanning sequency, the drive pattern of above-mentioned sweep signal be selected from Z-type state drive pattern, anti-Z-type state drive pattern, the anti-C of a C/ mix kenel drive pattern and the anti-C of the 2nd C/ mix kenel drive pattern one of them.
In an embodiment of the present invention, based on the second scanning sequency, the drive pattern of above-mentioned sweep signal is to be different from the corresponding drive pattern of the first scanning sequency among being selected from Z-type state drive pattern, anti-Z-type state drive pattern, the anti-C mixing kenel drive pattern of a C/ and the anti-C mixing of the 2nd C/ kenel drive pattern.
In an embodiment of the present invention, above-mentioned sweep signal is at least driving the gate line on display panel with the first scanning sequency, the second scanning sequency and the 3rd scanning sequency during different frame.At least both are not identical for the first scanning sequency, the second scanning sequency and the 3rd scanning sequency.
In an embodiment of the present invention, based on the first scanning sequency, the drive pattern of above-mentioned sweep signal be selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three one of them.
In an embodiment of the present invention, based on the second scanning sequency, the drive pattern of above-mentioned sweep signal is to be different from the corresponding drive pattern of the first scanning sequency among being selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three.
In an embodiment of the present invention, based on the 3rd scanning sequency, the drive pattern of above-mentioned sweep signal is to be different from the first scanning sequency and the corresponding drive pattern of the second scanning sequency among being selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three.
In an embodiment of the present invention, above-mentioned gate drive stage is divided into a plurality of grids and is driven group.Each grid drives group to comprise first grid driving stage and a plurality of second grid driving stage.After being started by start signal, first grid driving stage produces one of them sweep signal corresponding in the middle of sweep signal according to one of them clock signal in the middle of clock signal.Second grid driving stage according to clock signal with and the output of previous stage gate drive stage produce corresponding a plurality of sweep signals in the middle of sweep signal.
In an embodiment of the present invention, gate drive stage is divided into X grid and is driven group, and clock signal comprises Y clock signal, and Y=2X, and it is natural number that X is more than or equal to 2, X, Y.
The gate line driving method that the invention provides a kind of display panel, comprises the steps.Utilize a plurality of gate drive stages to receive a plurality of clock signals and start signal.Gate drive stage is to be integrated on this display panel.Utilize gate drive stage to produce a plurality of sweep signals according to clock signal and start signal.During different frame, sweep signal has a plurality of scanning sequencies.Utilize gate drive stage with sweep signal, driving a plurality of gate lines on display panel respectively during different frame.At least two scanning sequency differences in scanning sequency.
In an embodiment of the present invention, above-mentioned drives in the step of the gate line on display panel with sweep signal respectively during different frame, is at least with the first scanning sequency and the second scanning sequency, to carry out driving grid line.The first scanning sequency is not identical with the second scanning sequency.
In an embodiment of the present invention, above-mentioned drives in the step of the gate line on display panel with sweep signal respectively during different frame, is at least with the first scanning sequency, the second scanning sequency and the 3rd scanning sequency, to drive the gate line on display panel.At least both are not identical for the first scanning sequency, the second scanning sequency and the 3rd scanning sequency.
Based on above-mentioned, in exemplary embodiment of the present invention, the layout of gate driver circuit is identical, utilizes the clock signal that receives different sequential, can produce two or more non-sweep signals of arranging along rank.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates traditional gate drivers in order to the signal schematic representation of driving grid line;
Fig. 2 illustrates the schematic diagram of the image display of one embodiment of the invention;
Fig. 3 A to Fig. 3 D illustrates the schematic diagram of the different charging order of dot structure on the bigrid display panel of Fig. 2;
Fig. 4 illustrates the schematic diagram of the gate driver circuit internal circuit layout of one embodiment of the invention;
The gate driver circuit that Fig. 5 A and Fig. 6 A illustrate respectively Fig. 4 continuous two image duration each signal signal waveforms;
Fig. 5 B and Fig. 6 B illustrate respectively display panel upper part pixel in the schematic diagram of the charging order of continuous two image durations;
Fig. 7 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention;
Fig. 8 and Fig. 9 illustrate respectively the signal waveforms of gate driver circuit each signal between continuous two grid period of output of Fig. 7;
The anti-C of the 2nd C/ that Figure 10 illustrates sweep signal mixes kenel drive pattern;
Figure 11 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention;
Figure 12 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention;
Figure 13, Figure 14 A and Figure 15 A illustrate respectively the signal waveforms of gate driver circuit (gate output sequence) each signal between continuous three grid period of output of Figure 12;
Figure 14 B and Figure 15 B illustrate respectively the schematic diagram of the charging order of display panel upper part pixel between second and the 3rd grid period of output;
Figure 16 illustrates the flow chart of steps of the gate line driving method of one embodiment of the invention.
Description of reference numerals:
200: image display;
210,410,510,510 ', 610: gate driver circuit;
220: source electrode drive circuit;
230: display panel;
231,232: pixel;
410_1 to 410_N, 510_1 to 510_N, 610_1 to 610_N: gate drive stage;
GO[1] to GO[N]: sweep signal;
SO: source electrode output;
S800, S810, S820: the step of gate line driving method;
CLK, CLK1 to CLK8: clock signal;
STV: start signal.
Embodiment
Below propose a plurality of embodiment the present invention is described, yet the present invention is not limited only to illustrated a plurality of embodiment, and between embodiment, also allow suitable combination.
Fig. 2 illustrates the schematic diagram of the image display of one embodiment of the invention.Fig. 3 A to Fig. 3 D illustrates the schematic diagram of the different charging order of dot structure on the bigrid display panel of Fig. 2.Please refer to Fig. 2 and Fig. 3 A to Fig. 3 D, the image display 200 of this exemplary embodiment comprises gate driver circuit 210, source electrode drive circuit 220 and bigrid display panel 230.Gate driver circuit 210 is to be incorporated on bigrid display panel 230.Adjacent two pixels the 231, the 232nd of odd number and even number on bigrid display panel 230, are connected to same source electrode output SO, to form bigrid dot structure.Therefore, image display 200 is to utilize same source electrode output SO in operation, respectively odd number two pixels 231,232 adjacent with even number is driven, to obtain different charging orders at a horizontal line in the time.Fig. 3 A to Fig. 3 D illustrates the different charging order of dot structure on bigrid display panel 230, and by a left side, the right side is sequentially Z-type state charging order, anti-Z-type state charging order, the anti-C charging order of C/ and anti-C/C charging order.In this exemplary embodiment, gate driver circuit 210 utilizes the sweep signal with different driving pattern to drive display panel 230, and the charging order that its dot structure can be corresponding charges.Especially exemplified by a plurality of different exemplary embodiment, this technical characterictic is described below.
Fig. 4 illustrates the schematic diagram of the gate driver circuit internal circuit layout of one embodiment of the invention.Please refer to Fig. 4, the gate driver circuit 410 of this exemplary embodiment comprises a plurality of gate drive stage 410_1 to 410_N.Gate drive stage 410_1 to 410_N is integrated on a display panel, in order to receive a plurality of clock signal CLK1 to CLK4 and start signal STV.Gate drive stage 410_1 to 410_N produces a plurality of sweep signal GO[1 according to received clock signal CLK1 to CLK4 after being started by start signal STV] to GO[N].In this example, each gate drive stage for example comprises that a shift register is carried out and produces sweep signal GO[1] to GO[N] operation.
Particularly, the gate drive stage 410_1 to 410_N of this exemplary embodiment roughly can divide into two grids and drive group, and each grid drives group to comprise a first grid driving stage and a plurality of second grid driving stage.In this example, first grid drive group comprise first grid driving stage 410_1 and second grid driving stage 410_3 ..., 410_N-1, second grid drive group comprise first grid driving stage 410_2 and second grid driving stage 410_4 ..., 410_N, N is even number herein.At first grid, drive in group, first grid driving stage 410_1 is in order to receive start signal STV, and clock signal CLK1 postpones start signal STV, to produce corresponding sweep signal GO[1].In addition, at first grid, drive in group, second grid driving stage 410_3 ..., 410_N-1 according to clock signal CLK1 to CLK4 with and the output of previous stage gate drive stage produce sweep signal GO[2] to GO[N].For example, gate drive stage 410_3 postpones according to clock signal CLK3 the sweep signal GO[1 that gate drive stage 410_1 produces], to produce sweep signal GO[3].First grid drives the signal producing method of other gate drive stages of group to work as and can by that analogy, not repeat them here.
Similarly, at second grid, drive in group, gate drive stage 410_2 is in order to receive start signal STV, and postpones start signal STV according to clock signal CLK2, to produce corresponding sweep signal GO[2].In addition, at second grid, drive in group, gate drive stage 410_4 postpones according to clock signal CLK4 the sweep signal GO[2 that gate drive stage 410_2 produces], to produce sweep signal GO[4].Second grid drives the signal producing method of other gate drive stages of group to work as and can by that analogy, not repeat them here.
In summary, in this exemplary embodiment, each grid drives group to comprise a first grid driving stage and a plurality of second grid driving stage.After being started by start signal STV, first grid driving stage for example, produces one of them sweep signal corresponding in the middle of sweep signal (for example sweep signal GO[1]) according to one of them clock signal in the middle of clock signal (clock signal CLK1).Second grid driving stage according to clock signal CLK1 to CLK4 with and the output of previous stage gate drive stage produce corresponding a plurality of sweep signal GO[2 in the middle of sweep signal] to GO[N].In addition, in this exemplary embodiment, sweep signal GO[1] to GO[N] during different frame, with a plurality of different scanning sequencies, driving a plurality of gate lines on display panel respectively.
Particularly, the gate driver circuit that Fig. 5 A and Fig. 6 A illustrate respectively Fig. 4 continuous two image duration each signal signal waveforms.Fig. 5 B and Fig. 6 B illustrate respectively display panel upper part pixel in the schematic diagram of the charging order of continuous two image durations.For the purpose of brief description, Fig. 5 A and Fig. 6 A be the signal waveform of four gate drive stage 410_1 to 410_4 of illustration only, but its quantity is not in order to limit the present invention.
Refer to Fig. 5 A, Fig. 5 A definition sweep signal GO[1] to GO[4] Z-type state drive pattern, its first scanning sequency of opening gate line is: GO[1] → GO[2] → GO[3] → GO[4].Within n image duration, gate drive stage 410_1 to 410_4 reaches Z-type state pixel charging order as shown in Figure 5 B according to start signal STV and clock signal CLK1 to CLK4, so reaches the effect of space average.Show after average or space average of image elapsed time, can promote display quality of image.
Refer to Fig. 6 A and Fig. 6 B, based on same mechanism and identical effect, gate line also can be for changing anti-Z-type state drive pattern, now sweep signal GO[1 at the opening sequence of n+1 image duration] to GO[4] second scanning sequency of opening gate line is: GO[2] → GO[1] → GO[4] → GO[3].Based on this second scanning sequency, gate drive stage 410_1 to 410_4 can drive panel pixel to reach anti-Z-type state pixel charging order as shown in Figure 6B.
From another viewpoint, the clock signal CLK1 to CLK4 of comparison diagram 5A and Fig. 6 A, it can distinguish two groups of clock signals, and for example clock signal CLK1 and CLK2 can divide into one group, and clock signal CLK3 and CLK4 can divide into another group.Within n image duration, clock signal CLK1 to CLK4 is sequentially passed to gate drive stage 410_1 to 410_4.Within n+1 image duration, compared to n image duration, clock signal CLK1 and CLK2 are passed to the sequential of gate drive stage and exchange each other, and the sequential that clock signal CLK3 and CLK4 are passed to gate drive stage is also to exchange each other.Therefore the sweep signal GO[1, producing during different frame] to GO[4] also corresponding clock signal CLK1 to CLK4 there is identical temporal characteristics.
In this exemplary embodiment, in n+2 and subsequent image duration, gate drive stage 410_1 to 410_N can the first scanning sequency or the second scanning sequency drive the gate line on display panel, the present invention is not limited.That is to say, the sweep signal 410_1 to 410_N of this exemplary embodiment is driving a plurality of gate lines on display panel with a plurality of scanning sequencies respectively during different frame, at least two scanning sequency differences in wherein said scanning sequency.Therefore, in this exemplary embodiment, gate driver circuit 410 utilizes the sweep signal GO[1 with different driving pattern] to GO[N] driving display panel, the charging order that its dot structure can be corresponding charges.
In addition, in this exemplary embodiment, gate drive stage is to divide into two grids to drive group, and these two grids drive group according to four clock signal CLK1 to CLK4, can produce the sweep signal 410_1 to 410_N of a plurality of different scanning sequencies.
Fig. 7 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention.Please refer to Fig. 4 and Fig. 7, the gate driver circuit 510 of this exemplary embodiment is similar to the gate driver circuit 410 of Fig. 4, but main difference is for example between the two, the gate drive stage 510_1 to 510_N of this exemplary embodiment divides into four grids to drive group.First grid drive group comprise gate drive stage 510_1,510_5 ..., 510_N-3 (not shown), second grid drive group comprise gate drive stage 510_2,510_6 ..., 510_N-2 (not shown), the 3rd grid drive group comprise gate drive stage 510_3,510_7 ..., 510_N-1, the 4th grid drive group comprise gate drive stage 510_4,510_8 ..., 510_N, N is greater than 84 multiple herein.
Fig. 8 and Fig. 9 illustrate respectively the signal waveforms of gate driver circuit (gate output sequence) each signal between continuous two grid period of output of Fig. 7.For the purpose of brief description, Fig. 8 and Fig. 9 be the signal waveform of eight gate drive stage 510_1 to 510_8 of illustration only, but its quantity is not in order to limit the present invention.
Refer to Fig. 8, gate drive stage 510_1 to 510_8 receives the clock signal CLK1 to CLK8 along rank between first grid period of output, therefore, according to these a little clock signals, gate drive stage 510_1 to 510_8 also can produce the sweep signal GO[1 along rank] to GO[8] drive display panel, the charging order of its pixel as shown in Figure 3A, is the pixel charging order of Z-type state.Therefore, between first grid period of output, sweep signal GO[1] to GO[8] first scanning sequency of opening gate line is: GO[1] → GO[2] → GO[3] → GO[4] → GO[5] → GO[6] → GO[7] → GO[8].
Then, between second grid period of output, refer to Fig. 9, Fig. 9 defines sweep signal GO[1] to GO[8] the anti-C of a C/ mix kenel drive pattern, i.e. anti-C shape and C shape mixed mode, second scanning sequency of its unlatching gate line is:
GO[1]→GO[2]→GO[4]→GO[3]→GO[5]→GO[6]→GO[8]→GO[7]。Between second grid period of output, the anti-C of a C/ that gate drive stage 510_1 to 510_8 reaches as shown in Figure 3 C according to start signal STV and clock signal CLK1 to CLK8 mixes the pixel charging order of kenel.From another viewpoint, the clock signal CLK1 to CLK8 of comparison diagram 8 and Fig. 9, between first grid period of output, clock signal CLK1 to CLK8 is sequentially passed to gate drive stage 510_1 to 510_8.Between second grid period of output, compared between first grid period of output, clock signal CLK3 and CLK4 are passed to the sequential of gate drive stage and exchange each other, and the sequential that clock signal CLK7 and CLK8 are passed to gate drive stage is also to exchange each other.Therefore the sweep signal GO[1, producing between different grid period of output] to GO[8] also corresponding clock signal CLK1 to CLK8 there is identical temporal characteristics.
Afterwards, between the 3rd and subsequent grid period of output, gate drive stage 510_1 to 510_N can the first scanning sequency or the second scanning sequency drive the gate line on display panel, the present invention is not limited.
In another exemplary embodiment, second scanning sequency of opening gate line can be also: GO[2] → GO[1] → GO[3] → GO[4] → GO[6] → GO[5] → GO[7] → GO[8], as shown in figure 10.Refer to Figure 10, Figure 10 defines sweep signal GO[1] to GO[8] the anti-C of the 2nd C/ mix kenel drive pattern, i.e. C shape and anti-C shape mixed mode.In this example, the pixel charging order on display panel as shown in Figure 3 D.
Therefore, in this exemplary embodiment, based on the second scanning sequency, sweep signal GO[1] to GO[N] drive pattern can be that the anti-C of a C/ mixes kenel drive pattern or the anti-C of the 2nd C/ mixes kenel drive pattern.Or in another exemplary embodiment, the anti-C of the 2nd C/ mixes kenel drive pattern and also can be used as sweep signal GO[1] to GO[N] the 3rd scanning sequency, to carry out driving grid line between the 3rd or grid period of output thereafter.
In this exemplary embodiment, gate drive stage 510_1 to 510_N divides into four grids to drive group, therefore, by adjusting the sequential that is passed to gate drive stage of eight clock signal CLK1 to CLK8, can produce the drive pattern of 24 kinds of different kenels.Therefore, gate drive stage 510_1 to 510_N can be between different grid period of output, by selecting two in the middle of the drive pattern of these 24 kinds of kenels to carry out driving grid line to a plurality of, to improve the display quality of panel.
Figure 11 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention.Please refer to Fig. 7 and Figure 11, the gate driver circuit 510 ' of this exemplary embodiment is similar to the gate driver circuit 510 of Fig. 7, but main difference is for example between the two, the first and the 3rd grid of this exemplary embodiment drives group to be arranged at a side of display panel 230, and second drives group to be arranged at the opposite side of the relative first and the 3rd grid driving group on display panel 230 with the 4th grid.
In addition, the gate line driving method of this exemplary embodiment is similar to the revealer of Fig. 7 institute, therefore can in the narration of Fig. 8 to Figure 10 embodiment, obtain enough teachings, suggestion and implementation, therefore repeats no more.
In summary, in above-mentioned exemplary embodiment, described sweep signal is at least driving the gate line on display panel with the first scanning sequency and the second scanning sequency during different frame.Based on described the first scanning sequency, the drive pattern of sweep signal be selected from Z-type state drive pattern, anti-Z-type state drive pattern, the anti-C of a C/ mix kenel drive pattern and the anti-C of the 2nd C/ mix kenel drive pattern one of them.Based on described the second scanning sequency, the drive pattern of sweep signal is to be different from the corresponding drive pattern of the first scanning sequency among being selected from Z-type state drive pattern, anti-Z-type state drive pattern, the anti-C mixing kenel drive pattern of a C/ and the anti-C mixing of the 2nd C/ kenel drive pattern.
In other exemplary embodiment, described sweep signal also can at least drive the gate line on display panel with the first scanning sequency, the second scanning sequency and the 3rd scanning sequency during different frame.Wherein, at least both are not identical for the first scanning sequency, the second scanning sequency and the 3rd scanning sequency, are described as follows.
Figure 12 illustrates the schematic diagram of the gate driver circuit internal circuit layout of another embodiment of the present invention.Please refer to Fig. 4 and Figure 12, the gate driver circuit 610 of this exemplary embodiment is similar to the gate driver circuit 410 of Fig. 4, but main difference is for example between the two, the gate drive stage 610_1 to 610_N of this exemplary embodiment divides into three grids to drive group.First grid drive group comprise gate drive stage 610_1,610_4 ..., 610_N-2 (not shown), second grid drive group comprise gate drive stage 610_2,610_5 ..., 610_N-1, the 3rd grid drive group comprise gate drive stage 610_3,610_6 ..., 610_N, N is greater than 63 multiple herein.
Figure 13, Figure 14 A and Figure 15 A illustrate respectively the signal waveforms of gate driver circuit (gate output sequence) each signal between continuous three grid period of output of Figure 12.Figure 14 B and Figure 15 B illustrate respectively the schematic diagram of the charging order of display panel upper part pixel between second and the 3rd grid period of output.For the purpose of brief description, Figure 13, Figure 14 A and Figure 15 A be the signal waveform of six gate drive stage 610_1 to 610_6 of illustration only, but its quantity is not in order to limit the present invention.
Refer to Figure 13, gate drive stage 610_1 to 610_6 receives the clock signal CLK1 to CLK6 along rank between first grid period of output, therefore, according to these a little clock signals, gate drive stage 610_1 to 610_6 also can produce the sweep signal GO[1 along rank] to GO[6] drive display panel, the charging order of its pixel as shown in Figure 3A, is the pixel charging order of Z-type state.Therefore, between first grid period of output, sweep signal GO[1] to GO[6] first scanning sequency of opening gate line is: GO[1] → GO[2] → GO[3] → GO[4] → GO[5] → GO[6].
Then, between second grid period of output, refer to Figure 14 A, Figure 14 A definition sweep signal GO[1] to GO[6] y kenel drive pattern, its second scanning sequency of opening gate line is: GO[1] → GO[3] → GO[2] → GO[4] → GO[6] → GO[5].Between second grid period of output, gate drive stage 610_1 to 610_6 reaches the pixel charging order of y kenel as shown in Figure 14B according to start signal STV and clock signal CLK1 to CLK6.From another viewpoint, compare the clock signal CLK1 to CLK6 of Figure 13 and Figure 14 A, between first grid period of output, clock signal CLK1 to CLK6 is sequentially passed to gate drive stage 610_1 to 610_6.Between second grid period of output, compared between first grid period of output, clock signal CLK2 and CLK3 are passed to the sequential of gate drive stage and exchange each other, and the sequential that clock signal CLK5 and CLK6 are passed to gate drive stage is also to exchange each other.Therefore the sweep signal GO[1, producing between different grid period of output] to GO[6] also corresponding clock signal CLK1 to CLK6 there is identical temporal characteristics.
Afterwards, between the 3rd grid period of output, refer to Figure 15 A, Figure 15 A definition sweep signal GO[1] to GO[6] anti-y kenel drive pattern, its 3rd scanning sequency of opening gate line is: GO[2] → GO[1] → GO[3] → GO[5] → GO[4] → GO[6].Between the 3rd grid period of output, gate drive stage 610_1 to 610_6 reaches the pixel charging order of the anti-y kenel as shown in Figure 15 B according to start signal STV and clock signal CLK1 to CLK6.From another viewpoint, compare the clock signal CLK1 to CLK6 of Figure 13 and Figure 15 A, between first grid period of output, clock signal CLK1 to CLK6 is sequentially passed to gate drive stage 610_1 to 610_6.Between the 3rd grid period of output, compared between first grid period of output, clock signal CLK1 and CLK2 are passed to the sequential of gate drive stage and exchange each other, and the sequential that clock signal CLK4 and CLK5 are passed to gate drive stage is also to exchange each other.Therefore the sweep signal GO[1, producing between different grid period of output] to GO[6] also corresponding clock signal CLK1 to CLK6 there is identical temporal characteristics.
Finally, between the 4th and subsequent grid period of output, gate drive stage 610_1 to 610_N can the first scanning sequency, the second scanning sequency or the 3rd scanning sequency drive the gate line on display panel, and the present invention is not limited.
In this exemplary embodiment, gate drive stage 610_1 to 610_N divides into three grids to drive group, therefore, by adjusting the sequential that is passed to gate drive stage of six clock signal CLK1 to CLK6, can produce the drive pattern of 6 kinds of different kenels.Therefore, gate drive stage 610_1 to 610_N can be between different grid period of output, by selecting two in the middle of the drive pattern of these 6 kinds of kenels to carry out driving grid line to a plurality of, to improve the display quality of panel.
In summary, in above-mentioned exemplary embodiment, described sweep signal is at least driving the gate line on display panel with the first scanning sequency, the second scanning sequency and the 3rd scanning sequency during different frame.At least both are not identical for the first scanning sequency, the second scanning sequency and the 3rd scanning sequency.Based on described the first scanning sequency, the drive pattern of sweep signal be selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three one of them.Based on described the second scanning sequency, the drive pattern of sweep signal is to be different from the corresponding drive pattern of the first scanning sequency among being selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three.Based on described the 3rd scanning sequency, the drive pattern of sweep signal is to be different from the first scanning sequency and the corresponding drive pattern of the second scanning sequency among being selected from Z-type state drive pattern, y kenel drive pattern and anti-y kenel drive pattern three.
In addition, in this exemplary embodiment, although gate driver circuit between continuous three grid period of output all the sweep signal with different scanning order drive the gate line on display panel, the present invention is not limited to this.As long as driving the gate line on display panel with the sweep signal of different scanning order between continuous two grid period of output is technical scheme according to the invention, between the 3rd grid period of output thereafter, identical or not identical between the grid period of output that the scanning sequency of sweep signal can be continuous with the first two.
Figure 16 illustrates the flow chart of steps of the gate line driving method of one embodiment of the invention.Referring to Fig. 4 and Figure 16, the gate line driving method of this exemplary embodiment comprises the steps.First, in step S800, utilize a plurality of gate drive stage 410_1 to 410_N to receive a plurality of clock signal CLK1 to CLK4 and start signal STV.Gate drive stage 410_1 to 410_N is integrated on display panel 230, forms GOA configuration.Then,, in step S810, utilize gate drive stage 410_1 to 410_N to produce a plurality of sweep signal GO[1 according to clock signal CLK1 to CLK4 and start signal STV] to GO[N].In this example, during different frame, sweep signal GO[1] to GO[N] and there is different scanning sequencies, as shown in Fig. 5 A and 6A.Afterwards, in step S820, utilize gate drive stage 410_1 to 410_N during different frame respectively with sweep signal GO[1] to GO[N]] drive a plurality of gate lines on display panel 230.At least two scanning sequency differences in described scanning sequency.
In addition, the gate line driving method of embodiments of the invention can be obtained enough explanations, suggestion and implementation in the narration of Fig. 1 to Figure 15 B embodiment, therefore repeats no more.
In sum, in exemplary embodiment of the present invention, be arranged at the clock signal that gate driver circuit utilization on display panel receives different sequential, can produce two or more non-sweep signals of arranging along rank, so can reach the effect of space average.Show after average or space average of image elapsed time, can promote display quality of image.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (18)
1. a gate driver circuit, is characterized in that, comprising:
A plurality of gate drive stages, are integrated on a display panel, and in order to receive a plurality of clock signals and a start signal, those gate drive stages produce a plurality of sweep signals according to those clock signals after being started by this start signal,
Wherein, according to those clock signals, those sweep signals are driving a plurality of gate lines on this display panel with a plurality of scanning sequencies respectively during different frame, wherein at least two scanning sequency differences in those scanning sequencies.
2. gate driver circuit according to claim 1, it is characterized in that, those sweep signals are at least driving those gate lines on this display panel with one first scanning sequency and one second scanning sequency during those different frames, and wherein this first scanning sequency is not identical with this second scanning sequency.
3. gate driver circuit according to claim 2, it is characterized in that, based on this first scanning sequency, the drive pattern of those sweep signals be selected from a Z-type state drive pattern, an anti-Z-type state drive pattern, the anti-C of one the one C/ mix kenel drive pattern and the anti-C of one the 2nd C/ mix kenel drive pattern one of them.
4. gate driver circuit according to claim 3, it is characterized in that, based on this second scanning sequency, the drive pattern of those sweep signals is to be different from the corresponding drive pattern of this first scanning sequency among being selected from this Z-type state drive pattern, this anti-Z-type state drive pattern, the anti-C mixing kenel drive pattern of a C/ and the anti-C mixing of the 2nd C/ kenel drive pattern.
5. gate driver circuit according to claim 1, it is characterized in that, those sweep signals are at least driving those gate lines on this display panel with one first scanning sequency, one second scanning sequency and one the 3rd scanning sequency during those different frames, and wherein at least both are not identical for this first scanning sequency, this second scanning sequency and the 3rd scanning sequency.
6. gate driver circuit according to claim 5, is characterized in that, based on this first scanning sequency, the drive pattern of those sweep signals be selected from a Z-type state drive pattern, a y kenel drive pattern and an anti-y kenel drive pattern three one of them.
7. gate driver circuit according to claim 6, it is characterized in that, based on this second scanning sequency, the drive pattern of those sweep signals is to be different from the corresponding drive pattern of this first scanning sequency among being selected from this Z-type state drive pattern, this y kenel drive pattern and this anti-y kenel drive pattern three.
8. gate driver circuit according to claim 7, it is characterized in that, based on the 3rd scanning sequency, the drive pattern of those sweep signals is to be different from this first scanning sequency and the corresponding drive pattern of this second scanning sequency among being selected from this Z-type state drive pattern, this y kenel drive pattern and this anti-y kenel drive pattern three.
9. gate driver circuit according to claim 1, it is characterized in that, those gate drive stages are divided into a plurality of grids and are driven group, each grid drives group to comprise a first grid driving stage and a plurality of second grid driving stage, after being started by this start signal, this first grid driving stage produces one of them corresponding sweep signal in the middle of those sweep signals according to one of them clock signal in the middle of those clock signals, those second grid driving stages according to those clock signals with and the output of previous stage gate drive stage produce corresponding a plurality of sweep signals in the middle of those sweep signals.
10. gate driver circuit according to claim 9, is characterized in that, those gate drive stages are divided into X grid and driven group, and those clock signals comprise Y clock signal, and Y=2X, and it is natural number that X is more than or equal to 2, X, Y.
The gate line driving method of 11. 1 kinds of display panels, is characterized in that, comprising:
Utilize a plurality of gate drive stages to receive a plurality of clock signals and a start signal, wherein those gate drive stages are to be integrated on this display panel;
Utilize those gate drive stages to produce a plurality of sweep signals according to those clock signals and this start signal, wherein, during different frame, those sweep signals have a plurality of scanning sequencies; And
Utilize those gate drive stages with those sweep signals, driving a plurality of gate lines on this display panel respectively during those different frames, wherein at least two scanning sequency differences in those scanning sequencies.
12. gate line driving methods according to claim 11, it is characterized in that, during those different frames, with those sweep signals, drive in the step of those gate lines on this display panel respectively, be at least with one first scanning sequency and one second scanning sequency, to drive those gate lines, wherein this first scanning sequency is not identical with this second scanning sequency.
13. gate line driving methods according to claim 12, it is characterized in that, based on this first scanning sequency, the drive pattern of those sweep signals be selected from a Z-type state drive pattern, an anti-Z-type state drive pattern, the anti-C of one the one C/ mix kenel drive pattern and the anti-C of one the 2nd C/ mix kenel drive pattern one of them.
14. gate line driving methods according to claim 13, it is characterized in that, based on this second scanning sequency, the drive pattern of those sweep signals is to be different from the corresponding drive pattern of this first scanning sequency among being selected from this Z-type state drive pattern, this anti-Z-type state drive pattern, the anti-C mixing kenel drive pattern of a C/ and the anti-C mixing of the 2nd C/ kenel drive pattern.
15. gate line driving methods according to claim 11, it is characterized in that, during those different frames, with those sweep signals, drive in the step of those gate lines on this display panel respectively, be at least with one first scanning sequency, one second scanning sequency and one the 3rd scanning sequency, to drive those gate lines on this display panel, wherein at least both are not identical for this first scanning sequency, this second scanning sequency and the 3rd scanning sequency.
16. gate line driving methods according to claim 15, it is characterized in that, based on this first scanning sequency, the drive pattern of those sweep signals be selected from a Z-type state drive pattern, a y kenel drive pattern and an anti-y kenel drive pattern three one of them.
17. gate line driving methods according to claim 16, it is characterized in that, based on this second scanning sequency, the drive pattern of those sweep signals is to be different from the corresponding drive pattern of this first scanning sequency among being selected from this Z-type state drive pattern, this y kenel drive pattern and this anti-y kenel drive pattern three.
18. gate line driving methods according to claim 17, it is characterized in that, based on the 3rd scanning sequency, the drive pattern of those sweep signals is to be different from this first scanning sequency and the corresponding drive pattern of this second scanning sequency among being selected from this Z-type state drive pattern, this y kenel drive pattern and this anti-y kenel drive pattern three.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310025023.3A CN103943075A (en) | 2013-01-23 | 2013-01-23 | Gate driving circuit and gate line driving method for display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310025023.3A CN103943075A (en) | 2013-01-23 | 2013-01-23 | Gate driving circuit and gate line driving method for display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103943075A true CN103943075A (en) | 2014-07-23 |
Family
ID=51190712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310025023.3A Pending CN103943075A (en) | 2013-01-23 | 2013-01-23 | Gate driving circuit and gate line driving method for display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103943075A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| CN105739750A (en) * | 2014-12-26 | 2016-07-06 | 乐金显示有限公司 | Touch display device and the method for driving the same |
| CN106293289A (en) * | 2015-05-27 | 2017-01-04 | 联咏科技股份有限公司 | Display drive apparatus and the driving method of touch-control display panel |
| CN107507600A (en) * | 2017-10-18 | 2017-12-22 | 京东方科技集团股份有限公司 | Display device, image element circuit and its driving method, drive device |
| CN107644604A (en) * | 2016-07-22 | 2018-01-30 | 瀚宇彩晶股份有限公司 | Display device |
| CN110660369A (en) * | 2019-09-06 | 2020-01-07 | 北京集创北方科技股份有限公司 | Display driving method, source electrode driving circuit, driving chip and display device |
| CN115985223A (en) * | 2023-03-21 | 2023-04-18 | 惠科股份有限公司 | Display device and driving method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556770A (en) * | 2008-04-10 | 2009-10-14 | 联咏科技股份有限公司 | Method and device for driving liquid crystal display to lower power supply noises |
| CN101777301A (en) * | 2010-01-15 | 2010-07-14 | 友达光电股份有限公司 | Grid electrode driving circuit |
| CN101923839A (en) * | 2009-06-12 | 2010-12-22 | 瑞萨电子株式会社 | Displaying panel driving method, gate drivers and display device |
| CN201716499U (en) * | 2010-05-19 | 2011-01-19 | 深圳华映显示科技有限公司 | Display device |
| CN102074218A (en) * | 2011-02-25 | 2011-05-25 | 福建华映显示科技有限公司 | Liquid crystal display system capable of improving non-uniform brightness of liquid crystal display panel |
| CN102436792A (en) * | 2011-11-18 | 2012-05-02 | 友达光电股份有限公司 | Driving method applied to display panel |
| CN102737591A (en) * | 2011-04-12 | 2012-10-17 | 联咏科技股份有限公司 | Gate driver of dual-gate display and frame control method thereof |
-
2013
- 2013-01-23 CN CN201310025023.3A patent/CN103943075A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556770A (en) * | 2008-04-10 | 2009-10-14 | 联咏科技股份有限公司 | Method and device for driving liquid crystal display to lower power supply noises |
| CN101923839A (en) * | 2009-06-12 | 2010-12-22 | 瑞萨电子株式会社 | Displaying panel driving method, gate drivers and display device |
| CN101777301A (en) * | 2010-01-15 | 2010-07-14 | 友达光电股份有限公司 | Grid electrode driving circuit |
| CN201716499U (en) * | 2010-05-19 | 2011-01-19 | 深圳华映显示科技有限公司 | Display device |
| CN102074218A (en) * | 2011-02-25 | 2011-05-25 | 福建华映显示科技有限公司 | Liquid crystal display system capable of improving non-uniform brightness of liquid crystal display panel |
| CN102737591A (en) * | 2011-04-12 | 2012-10-17 | 联咏科技股份有限公司 | Gate driver of dual-gate display and frame control method thereof |
| CN102436792A (en) * | 2011-11-18 | 2012-05-02 | 友达光电股份有限公司 | Driving method applied to display panel |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700358A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | GIP (Gate In Panel) type LCD (Liquid Crystal Display) device |
| US10140938B2 (en) | 2013-12-31 | 2018-11-27 | Boe Technology Group Co., Ltd. | GIP type liquid crystal display device |
| CN105739750A (en) * | 2014-12-26 | 2016-07-06 | 乐金显示有限公司 | Touch display device and the method for driving the same |
| CN105739750B (en) * | 2014-12-26 | 2019-07-26 | 乐金显示有限公司 | Touch panel display device and its driving method |
| US9983720B2 (en) | 2014-12-26 | 2018-05-29 | Lg Display Co., Ltd. | Touchscreen display device and method of driving the same |
| CN106293289B (en) * | 2015-05-27 | 2019-05-07 | 联咏科技股份有限公司 | The driving method of display drive apparatus and touch-control display panel |
| CN106293289A (en) * | 2015-05-27 | 2017-01-04 | 联咏科技股份有限公司 | Display drive apparatus and the driving method of touch-control display panel |
| CN107644604A (en) * | 2016-07-22 | 2018-01-30 | 瀚宇彩晶股份有限公司 | Display device |
| WO2019076121A1 (en) * | 2017-10-18 | 2019-04-25 | 京东方科技集团股份有限公司 | Display device, pixel circuit, and drive method and drive device therefor |
| CN107507600A (en) * | 2017-10-18 | 2017-12-22 | 京东方科技集团股份有限公司 | Display device, image element circuit and its driving method, drive device |
| CN107507600B (en) * | 2017-10-18 | 2020-03-06 | 京东方科技集团股份有限公司 | Display device, pixel circuit, driving method thereof and driving device |
| US11393420B2 (en) | 2017-10-18 | 2022-07-19 | Hefei Boe Optoelectronics Technology Co., Ltd. | Display device, pixel circuit and its driving method and driving device |
| CN110660369A (en) * | 2019-09-06 | 2020-01-07 | 北京集创北方科技股份有限公司 | Display driving method, source electrode driving circuit, driving chip and display device |
| CN110660369B (en) * | 2019-09-06 | 2022-05-20 | 北京集创北方科技股份有限公司 | Display driving method, source electrode driving circuit, driving chip and display device |
| CN115985223A (en) * | 2023-03-21 | 2023-04-18 | 惠科股份有限公司 | Display device and driving method thereof |
| CN115985223B (en) * | 2023-03-21 | 2023-08-25 | 惠科股份有限公司 | Display device and driving method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103943075A (en) | Gate driving circuit and gate line driving method for display panel | |
| TWI483230B (en) | Gate diver on array and method for driving gate lines of display panel | |
| CN107767832B (en) | Liquid crystal display panel and grid drive circuit | |
| US9437166B2 (en) | Bi-directional driving scan driver | |
| EP3327715B1 (en) | Display device | |
| CN101295481B (en) | Gate driving circuit and liquid crystal display having the same | |
| US8686990B2 (en) | Scanning signal line drive circuit and display device equipped with same | |
| US20100315403A1 (en) | Display device, method for driving the display device, and scan signal line driving circuit | |
| TWI415055B (en) | Pixel array and driving method thereof and flat panel display | |
| CN1407536A (en) | Liquid crystal display device and its driving method | |
| WO2015007052A1 (en) | Goa circuit, array substrate, display apparatus, and driving method | |
| TWI453724B (en) | Liquid crystal display which can compensate gate voltages and method thereof | |
| CN102778798B (en) | Liquid crystal display panel and display driving method | |
| JP2004252092A (en) | Display device and driving method therefor | |
| CN106157873A (en) | A kind of gate drive apparatus, driving method and display floater | |
| CN101083066A (en) | Display apparatus, device for driving the same and method of driving the same | |
| CN103474039A (en) | Grid line driving method, grid driving circuit and display device | |
| CN102214428B (en) | Gate driving circuit and driving method therefor | |
| GB2527470A (en) | Liquid crystal panel and drive method thereof | |
| JP2004334104A (en) | Data driver and electrooptical apparatus | |
| CN102376281A (en) | Driving module and driving method | |
| KR20080044397A (en) | A liquid crystal display device | |
| CN102103294A (en) | Gate drive circuit and relevant liquid crystal display | |
| TWI242312B (en) | Signal circuit, display apparatus including same, and method for driving data line | |
| KR102104976B1 (en) | Display Device For Low Refresh Rate Driving And Driving Method Of The Same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140723 |
|
| WD01 | Invention patent application deemed withdrawn after publication |